From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=chasel.chiu@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 39FE5211E2F1B for ; Mon, 1 Apr 2019 19:29:01 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Apr 2019 19:29:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,298,1549958400"; d="scan'208";a="157335243" Received: from pgsmsx103.gar.corp.intel.com ([10.221.44.82]) by fmsmga002.fm.intel.com with ESMTP; 01 Apr 2019 19:29:00 -0700 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.237]) by PGSMSX103.gar.corp.intel.com ([169.254.2.210]) with mapi id 14.03.0415.000; Tue, 2 Apr 2019 10:28:59 +0800 From: "Chiu, Chasel" To: "Kubacki, Michael A" , "edk2-devel@lists.01.org" CC: "Desimone, Nathaniel L" , "Gao, Liming" , "Kinney, Michael D" Thread-Topic: [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI Thread-Index: AQHU6PK8eBQMwUwse0yRVZS5CT0L/qYoIgJA Date: Tue, 2 Apr 2019 02:28:58 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC502A446E@PGSMSX111.gar.corp.intel.com> References: <20190402012323.25504-1-michael.a.kubacki@intel.com> <20190402012323.25504-2-michael.a.kubacki@intel.com> In-Reply-To: <20190402012323.25504-2-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWEzYmQwY2UtOWI5ZC00MjQxLThjM2YtNWRlOTRjMjJjYzVhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiYk5OZGd4bndpTURTTnpaS2c5SzhYeGJRMHUwMzYrK3hTaUl4UVMwbWwxbHpOM0dhZnpJN3hcL1prTlh2dWViVlUifQ== x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.205] MIME-Version: 1.0 Subject: Re: [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSiliconPkg: Add SPI write support in PEI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 Apr 2019 02:29:02 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Michael, Please see below inline. Thanks! Chasel > -----Original Message----- > From: Kubacki, Michael A > Sent: Tuesday, April 2, 2019 9:23 AM > To: edk2-devel@lists.01.org > Cc: Desimone, Nathaniel L ; Chiu, Chasel > ; Gao, Liming ; Kinney, Mich= ael > D > Subject: [edk2-platforms/devel-MinPlatform][PATCH v3 1/3] KabylakeSilicon= Pkg: > Add SPI write support in PEI >=20 > Adds a new library PeiSpiLib to perform the initialization necessary to p= erform > SPI write cycles in PEI. After initialization, it installs an instance of= the > PCH_SPI_PPI. >=20 > Cc: Nate DeSimone > Cc: Chasel Chiu > Cc: Liming Gao > Cc: Michael D Kinney > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Michael Kubacki > --- > Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc | 3 +- > .../Pch/Library/PeiSpiLib/PeiSpiLib.inf | 50 +++++ > .../Pch/Include/Library/SpiLib.h | 32 +++ > .../Pch/Library/PeiSpiLib/PeiSpiLib.c | 221 +++++++++++++++= ++++++ > .../LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c | 5 +- > 5 files changed, 307 insertions(+), 4 deletions(-) create mode 100644 > Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf > create mode 100644 > Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h > create mode 100644 > Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c >=20 > diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc > b/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc > index b81a736486..bb95ce3888 100644 > --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc > +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc > @@ -1,7 +1,7 @@ > ## @file > # Component description file for the SkyLake SiPkg PEI libraries. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved.
> # > # This program and the accompanying materials are licensed and made avai= lable > under # the terms and conditions of the BSD License which accompanies th= is > distribution. > @@ -30,6 +30,7 @@ > !endif >=20 > ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiResetSystemLib/P > eiResetSystemLib.inf >=20 > PchResetLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchResetLib/PeiPchR > esetLib.inf > + SpiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiSpiLib/PeiSpiLib.inf >=20 > # > # Cpu > diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSp= iLib.inf > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf > new file mode 100644 > index 0000000000..9240b6ef06 > --- /dev/null > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.i > +++ nf > @@ -0,0 +1,50 @@ > +## @file > +# Component description file for PEI PCH SPI Initialization # # > +Copyright (c) 2019, Intel Corporation. All rights reserved.
# # > +This program and the accompanying materials are licensed and made > +available under # the terms and conditions of the BSD License which > accompanies this distribution. > +# The full text of the license may be found at # > +http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010017 > + BASE_NAME =3D PeiSpiLib > + FILE_GUID =3D 4998447D-7948-448F-AB75-96E24E18FF23 > + VERSION_STRING =3D 1.0 > + MODULE_TYPE =3D PEIM > + LIBRARY_CLASS =3D SpiLib|PEIM PEI_CORE > + # > + # The following information is for reference only and not required by = the build > tools. > + # > + # VALID_ARCHITECTURES =3D IA32 X64 IPF > + # > + > +[LibraryClasses] > + DebugLib > + MemoryAllocationLib > + PcdLib > + PchCycleDecodingLib > + PchSpiCommonLib > + PciSegmentLib > + PeiServicesLib > + PeiServicesTablePointerLib > + > +[Packages] > + MdePkg/MdePkg.dec > + KabylakeSiliconPkg/SiPkg.dec > + > +[Sources] > + PeiSpiLib.c > + > +[Pcd] > + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES > + > +[Ppis] > + gPchSpiPpiGuid ## PRODUCES > diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.= h > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h > new file mode 100644 > index 0000000000..6af66f8869 > --- /dev/null > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiLib.h > @@ -0,0 +1,32 @@ > +/** @file > + Library to initialize SPI services for future SPI accesses. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
This > +program and the accompanying materials are licensed and made available > +under the terms and conditions of the BSD License that accompanies this > distribution. > +The full text of the license may be found at > +http://opensource.org/licenses/bsd-license.php. > + > +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS > OR IMPLIED. > + > +**/ > + > +#ifndef _SPI_LIB_H_ > +#define _SPI_LIB_H_ > + > +/** > + Initializes SPI for access from future services. > + > + @retval EFI_SUCCESS The SPI service was initialized successful= ly. > + @retval EFI_OUT_OF_RESOUCES Insufficient memory available to allocate > structures required for initialization. > + @retval Others An error occurred initializing SPI service= s. > + > +**/ > +EFI_STATUS > +EFIAPI > +SpiServiceInit ( > + VOID > + ); > + > +#endif > diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSp= iLib.c > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c > new file mode 100644 > index 0000000000..954317cd40 > --- /dev/null > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c > @@ -0,0 +1,221 @@ > +/** @file > + PCH SPI PEI Library implements the SPI Host Controller Interface. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
This > +program and the accompanying materials are licensed and made available > +under the terms and conditions of the BSD License that accompanies this > distribution. > +The full text of the license may be found at > +http://opensource.org/licenses/bsd-license.php. > + > +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS > OR IMPLIED. > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include #include > +#include #include > + #include #include > + > + > +typedef struct { > + EFI_PEI_PPI_DESCRIPTOR PpiDescriptor; > + SPI_INSTANCE SpiInstance; > +} PEI_SPI_INSTANCE; > + > +/** > + Initializes the SPI BAR0 value to a default value and enables memory s= pace > decoding. > + > + The SPI BAR0 will be assigned later in PCI enumeration. > + > +**/ > +VOID > +InitSpiBar0 ( > + VOID > + ) > +{ > + UINT64 PchSpiBase; > + PchSpiBase =3D PCI_SEGMENT_LIB_ADDRESS ( > + 0, > + 0, > + PCI_DEVICE_NUMBER_PCH_SPI, > + PCI_FUNCTION_NUMBER_PCH_SPI, > + 0 > + ); > + PciSegmentWrite32 (PchSpiBase + R_PCH_SPI_BAR0, > +PCH_SPI_BASE_ADDRESS); > + PciSegmentOr32 (PchSpiBase + PCI_COMMAND_OFFSET, > +EFI_PCI_COMMAND_MEMORY_SPACE); } > + > +/** > + Initializes SPI for access from future services. > + > + @retval EFI_SUCCESS The SPI service was initialized successful= ly. > + @retval EFI_OUT_OF_RESOUCES Insufficient memory available to allocate > structures required for initialization. > + @retval Others An error occurred initializing SPI service= s. > + > +**/ > +EFI_STATUS > +EFIAPI > +SpiServiceInit ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + PEI_SPI_INSTANCE *PeiSpiInstance; > + SPI_INSTANCE *SpiInstance; > + PCH_SPI_PPI *SpiPpi; > + UINT16 AcpiBase; > + > + AcpiBase =3D 0; > + > + Status =3D PeiServicesLocatePpi ( > + &gPchSpiPpiGuid, > + 0, > + NULL, > + (VOID **) &SpiPpi > + ); > + > + if (Status !=3D EFI_SUCCESS) { Would you please add comments to explain why we must initialize ACPI BASE a= s part of the SpiServiceInit()? > + PchAcpiBaseGet (&AcpiBase); > + if (AcpiBase =3D=3D 0) { > + PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress)); > + } > + > + // > + // Prior to PCI enumeration, initialize SPI BAR0 to a default value > + // and also enable memory space decoding for SPI > + // > + InitSpiBar0 (); > + > + PeiSpiInstance =3D (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof > (PEI_SPI_INSTANCE)); > + if (NULL =3D=3D PeiSpiInstance) { > + return EFI_OUT_OF_RESOURCES; > + } > + > + SpiInstance =3D &(PeiSpiInstance->SpiInstance); > + SpiProtocolConstructor (SpiInstance); > + > + PeiSpiInstance->PpiDescriptor.Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; > + PeiSpiInstance->PpiDescriptor.Guid =3D &gPchSpiPpiGuid; > + PeiSpiInstance->PpiDescriptor.Ppi =3D &(SpiInstance->SpiProtocol); > + > + Status =3D PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor); > + } > + return Status; > +} > + > +/** > + Acquires the PCH SPI BAR0 MMIO address. > + > + @param[in] SpiInstance Pointer to SpiInstance to initialize > + > + @retval UINTN The SPIO BAR0 MMIO address > + > +**/ > +UINTN > +AcquireSpiBar0 ( > + IN SPI_INSTANCE *SpiInstance > + ) > +{ > + return MmioRead32 (SpiInstance->PchSpiBase + R_PCH_SPI_BAR0) & > +~(B_PCH_SPI_BAR0_MASK); } > + > +/** > + Release the PCH SPI BAR0 MMIO address. > + > + @param[in] SpiInstance Pointer to SpiInstance to initialize > + > + @retval None > +**/ > +VOID > +ReleaseSpiBar0 ( > + IN SPI_INSTANCE *SpiInstance > + ) > +{ > + return; > +} > + > +/** > + Disables BIOS Write Protect > + > + @retval EFI_SUCCESS BIOS Write Protect was disabled succes= sfully > + > +**/ > +EFI_STATUS > +EFIAPI > +DisableBiosWriteProtect ( > + VOID > + ) > +{ > + UINT64 SpiBaseAddress; > + > + SpiBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( > + 0, > + 0, > + PCI_DEVICE_NUMBER_PCH_SPI, > + PCI_FUNCTION_NUMBER_PCH_SPI, > + 0 > + ); > + // > + // Clear EISS bit to allow for SPI use // > + PciSegmentAnd8 (SpiBaseAddress + R_PCH_SPI_BC, (UINT8) > + ~B_PCH_SPI_BC_EISS); > + > + // > + // Write clear BC_SYNC_SS prior to change WPD from 0 to 1. > + // > + PciSegmentOr8 ( > + SpiBaseAddress + R_PCH_SPI_BC + 1, > + (B_PCH_SPI_BC_SYNC_SS >> 8) > + ); > + > + // > + // Set BIOSWE bit (SPI PCI Offset DCh [0]) =3D 1b // Enable the acces= s > + to the BIOS space for both read and write cycles // > + PciSegmentOr8 ( > + SpiBaseAddress + R_PCH_SPI_BC, > + B_PCH_SPI_BC_WPD > + ); > + > + ASSERT ((PciSegmentRead8 (SpiBaseAddress + R_PCH_SPI_BC) & > + B_PCH_SPI_BC_EISS) !=3D 0); > + > + return EFI_SUCCESS; > +} > + > +/** > + Enables BIOS Write Protect > + > +**/ > +VOID > +EFIAPI > +EnableBiosWriteProtect ( > + VOID > + ) > +{ > + UINT64 SpiBaseAddress; > + > + SpiBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( > + 0, > + 0, > + PCI_DEVICE_NUMBER_PCH_SPI, > + PCI_FUNCTION_NUMBER_PCH_SPI, > + 0 > + ); > + > + // > + // Disable the access to the BIOS space for write cycles > + // > + PciSegmentAnd8 ( > + SpiBaseAddress + R_PCH_SPI_BC, > + (UINT8) (~B_PCH_SPI_BC_WPD) > + ); > +} > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib= / > SpiCommon.c > b/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib= / > SpiCommon.c > index 46184d4994..0b708d4aad 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiCommonLib= / > SpiCommon.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/LibraryPrivate/BasePchSpiComm > +++ onLib/SpiCommon.c > @@ -1,7 +1,7 @@ > /** @file > PCH SPI Common Driver implements the SPI Host Controller Compatibility > Interface. >=20 > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> This program and the accompanying materials are licensed and made availa= ble > under the terms and conditions of the BSD License that accompanies this > distribution. > The full text of the license may be found at @@ -760,9 +760,8 @@ SendSpi= Cmd > ( > Status =3D EFI_SUCCESS; > SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This); > SpiBaseAddress =3D SpiInstance->PchSpiBase; > - PchSpiBar0 =3D AcquireSpiBar0 (SpiInstance); > - SpiBaseAddress =3D SpiInstance->PchSpiBase; > ABase =3D SpiInstance->PchAcpiBase; > + PchSpiBar0 =3D AcquireSpiBar0 (SpiInstance); >=20 > // > // Disable SMIs to make sure normal mode flash access is not interrupt= ed by an > SMI > -- > 2.16.2.windows.1