From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: chasel.chiu@intel.com) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by groups.io with SMTP; Wed, 22 May 2019 17:16:03 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 May 2019 17:16:02 -0700 X-ExtLoop1: 1 Received: from kmsmsx151.gar.corp.intel.com ([172.21.73.86]) by orsmga001.jf.intel.com with ESMTP; 22 May 2019 17:16:00 -0700 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.3]) by KMSMSX151.gar.corp.intel.com ([169.254.10.117]) with mapi id 14.03.0415.000; Thu, 23 May 2019 08:15:59 +0800 From: "Chiu, Chasel" To: "Desimone, Nathaniel L" , "Agyeman, Prince" , "devel@edk2.groups.io" CC: "Kubacki, Michael A" , "Kinney, Michael D" , "Gao, Liming" , "Sinha, Ankit" Subject: Re: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 build support Thread-Topic: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 build support Thread-Index: AQHVD4J5QiWtuhP31EaECCyVliKEyaZ2/z6AgADbDmA= Date: Thu, 23 May 2019 00:15:59 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC503253CD@PGSMSX111.gar.corp.intel.com> References: <0396bf25fe843dcf9f798eb6608cec6c381bcc51.1558406058.git.prince.agyeman@intel.com> <02A34F284D1DA44BB705E61F7180EF0AAEB47B4A@ORSMSX114.amr.corp.intel.com> In-Reply-To: <02A34F284D1DA44BB705E61F7180EF0AAEB47B4A@ORSMSX114.amr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZDdkMjJkNDUtZWZlMy00ZjkyLWE1NzEtZDZmNjRjNDU0MGVhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiZDNpSUpSMUM3OHZYKzBUQnJVWE1LaW5KeTIwRjlBaWhPVFk3NktpYlZzSVFqSTBBNWJvYlwva1JiSGdsNCtybFUifQ== x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.205] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: Desimone, Nathaniel L > Sent: Thursday, May 23, 2019 3:12 AM > To: Agyeman, Prince ; devel@edk2.groups.io > Cc: Chiu, Chasel ; Kubacki, Michael A > ; Kinney, Michael D > ; Gao, Liming ; Sinha, > Ankit > Subject: RE: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 > build support >=20 > Reviewed-by: Nate DeSimone >=20 > -----Original Message----- > From: Agyeman, Prince > Sent: Monday, May 20, 2019 8:08 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Agyeman, Prince > ; Kubacki, Michael A > ; Kinney, Michael D > ; Desimone, Nathaniel L > ; Gao, Liming ; Sin= ha, > Ankit > Subject: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 build > support >=20 > From: Prince Agyeman >=20 > Fixes: > * Replacing .asm and .S with nasm in SecFspWrapperPlatformSecLib for > cross-platform build support > * Modified RuleInclude.fdf > * Modified python files to be OS independent >=20 > Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm v= ersion > 2.11.08 >=20 > Cc: Michael Kubacki > Cc: Michael D Kinney > Cc: Nate DeSimone > Cc: Liming Gao > Cc: Ankit Sinha >=20 > Signed-off-by: Prince Agyeman > --- > .../Ia32/PeiCoreEntry.S | 117 ------- > .../Ia32/{PeiCoreEntry.asm =3D> PeiCoreEntry.nasm} | 46 +-- > .../SecFspWrapperPlatformSecLib/Ia32/SecEntry.S | 342 ---------------= ------ > .../Ia32/{SecEntry.asm =3D> SecEntry.nasm} | 132 ++++---- > .../SecFspWrapperPlatformSecLib/Ia32/Stack.S | 67 ---- > .../Ia32/{Stack.asm =3D> Stack.nasm} | 39 ++- > .../SecFspWrapperPlatformSecLib.inf | 12 +- > .../MinPlatformPkg/Include/Fdf/RuleInclude.fdf | 6 +- > .../Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py | 2 +- > .../MinPlatformPkg/Tools/PatchFv/PatchBinFv.py | 8 +- > .../MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py | 15 +- > Platform/Intel/build_bios.py | 28 +- > 12 files changed, 143 insertions(+), 671 deletions(-) delete mode 10064= 4 > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS > ecLib/Ia32/PeiCoreEntry.S > rename > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS > ecLib/Ia32/{PeiCoreEntry.asm =3D> PeiCoreEntry.nasm} (66%) delete mode > 100644 > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS > ecLib/Ia32/SecEntry.S > rename > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS > ecLib/Ia32/{SecEntry.asm =3D> SecEntry.nasm} (72%) delete mode 100644 > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS > ecLib/Ia32/Stack.S > rename > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS > ecLib/Ia32/{Stack.asm =3D> Stack.nasm} (59%) >=20 > diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/PeiCoreEntry.S > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/PeiCoreEntry.S > deleted file mode 100644 > index 8c8356f..0000000 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/PeiCoreEntry.S > +++ /dev/null > @@ -1,117 +0,0 @@ > -## @file > -# Find and call SecStartup > -# > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
-# > SPDX-License-Identifier: BSD-2-Clause-Patent -# -## > - > -ASM_GLOBAL ASM_PFX(CallPeiCoreEntryPoint) > -ASM_PFX(CallPeiCoreEntryPoint): > - # > - # Obtain the hob list pointer > - # > - movl 0x4(%esp), %eax > - # > - # Obtain the stack information > - # ECX: start of range > - # EDX: end of range > - # > - movl 0x8(%esp), %ecx > - movl 0xC(%esp), %edx > - > - # > - # Platform init > - # > - pushal > - pushl %edx > - pushl %ecx > - pushl %eax > - call ASM_PFX(PlatformInit) > - popl %eax > - popl %eax > - popl %eax > - popal > - > - # > - # Set stack top pointer > - # > - movl %edx, %esp > - > - # > - # Push the hob list pointer > - # > - pushl %eax > - > - # > - # Save the value > - # ECX: start of range > - # EDX: end of range > - # > - movl %esp, %ebp > - pushl %ecx > - pushl %edx > - > - # > - # Push processor count to stack first, then BIST status (AP then BSP) > - # > - movl $1, %eax > - cpuid > - shr $16, %ebx > - andl $0x000000FF, %ebx > - cmp $1, %bl > - jae PushProcessorCount > - > - # > - # Some processors report 0 logical processors. Effectively 0 =3D 1. > - # So we fix up the processor count > - # > - inc %ebx > - > -PushProcessorCount: > - pushl %ebx > - > - # > - # We need to implement a long-term solution for BIST capture. For now= , we > just copy BSP BIST > - # for all processor threads > - # > - xorl %ecx, %ecx > - movb %bl, %cl > -PushBist: > - movd %mm0, %eax > - pushl %eax > - loop PushBist > - > - # Save Time-Stamp Counter > - movd %mm5, %eax > - pushl %eax > - > - movd %mm6, %eax > - pushl %eax > - > - # > - # Pass entry point of the PEI core > - # > - movl $0xFFFFFFE0, %edi > - pushl %ds:(%edi) > - > - # > - # Pass BFV into the PEI Core > - # > - movl $0xFFFFFFFC, %edi > - pushl %ds:(%edi) > - > - # > - # Pass stack size into the PEI Core > - # > - movl -4(%ebp), %ecx > - movl -8(%ebp), %edx > - pushl %ecx # RamBase > - > - subl %ecx, %edx > - pushl %edx # RamSize > - > - # > - # Pass Control into the PEI Core > - # > - call ASM_PFX(SecStartup) > diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/PeiCoreEntry.asm > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/PeiCoreEntry.nasm > similarity index 66% > rename from > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS > ecLib/Ia32/PeiCoreEntry.asm > rename to > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS > ecLib/Ia32/PeiCoreEntry.nasm > index c854067..5c5b788 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/PeiCoreEntry.asm > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/Ia32/PeiCoreEntry.nasm > @@ -1,21 +1,25 @@ > -;; @file > -; Find and call SecStartup > +;---------------------------------------------------------------------- > +-------- > ; > -; Copyright (c) 2017, Intel Corporation. All rights reserved.
> +; Copyright (c) 2019, Intel Corporation. All rights reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; -;; > - > +; Module Name: > +; > +; PeiCoreEntry.nasm > +; > +; Abstract: > +; > +; Find and call SecStartup > +; > +;---------------------------------------------------------------------- > +-------- >=20 > -.686p > -.xmm > -.model flat, c > -.code > +SECTION .text >=20 > -EXTRN SecStartup:NEAR > -EXTRN PlatformInit:NEAR > +extern ASM_PFX(SecStartup) > +extern ASM_PFX(PlatformInit) >=20 > -CallPeiCoreEntryPoint PROC PUBLIC > +global ASM_PFX(CallPeiCoreEntryPoint) > +ASM_PFX(CallPeiCoreEntryPoint): > ; > ; Obtain the hob list pointer > ; > @@ -26,7 +30,7 @@ CallPeiCoreEntryPoint PROC PUBLIC > ; EDX: end of range > ; > mov ecx, [esp+8] > - mov edx, [esp+0Ch] > + mov edx, [esp+0xC] >=20 > ; > ; Platform init > @@ -35,7 +39,7 @@ CallPeiCoreEntryPoint PROC PUBLIC > push edx > push ecx > push eax > - call PlatformInit > + call ASM_PFX(PlatformInit) > pop eax > pop eax > pop eax > @@ -66,7 +70,7 @@ CallPeiCoreEntryPoint PROC PUBLIC > mov eax, 1 > cpuid > shr ebx, 16 > - and ebx, 0000000FFh > + and ebx, 0xFF > cmp bl, 1 > jae PushProcessorCount >=20 > @@ -100,14 +104,14 @@ PushBist: > ; > ; Pass entry point of the PEI core > ; > - mov edi, 0FFFFFFE0h > - push DWORD PTR ds:[edi] > + mov edi, 0xFFFFFFE0 > + push DWORD [edi] >=20 > ; > ; Pass BFV into the PEI Core > ; > - mov edi, 0FFFFFFFCh > - push DWORD PTR ds:[edi] > + mov edi, 0xFFFFFFFC > + push DWORD [edi] >=20 > ; > ; Pass stack size into the PEI Core > @@ -122,7 +126,5 @@ PushBist: > ; > ; Pass Control into the PEI Core > ; > - call SecStartup > -CallPeiCoreEntryPoint ENDP > + call ASM_PFX(SecStartup) >=20 > -END > diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/SecEntry.S > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/SecEntry.S > deleted file mode 100644 > index 63c420a..0000000 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/SecEntry.S > +++ /dev/null > @@ -1,342 +0,0 @@ > -## @file > -# This is the code that goes from real-mode to protected mode. > -# It consumes the reset vector, calls TempRamInit API from FSP binary. > -# > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
-# > SPDX-License-Identifier: BSD-2-Clause-Patent -# -## > - > -#include "Fsp.h" > - > -ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFsptBaseAddress) > -ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize) > - > -ASM_GLOBAL ASM_PFX(_TEXT_REALMODE) > -ASM_PFX(_TEXT_REALMODE): > -#-----------------------------------------------------------------------= ----- > -# > -# Procedure: _ModuleEntryPoint > -# > -# Input: None > -# > -# Output: None > -# > -# Destroys: Assume all registers > -# > -# Description: > -# > -# Transition to non-paged flat-model protected mode from a > -# hard-coded GDT that provides exactly two descriptors. > -# This is a bare bones transition to protected mode only > -# used for a while in PEI and possibly DXE. > -# > -# After enabling protected mode, a far jump is executed to > -# transfer to PEI using the newly loaded GDT. > -# > -# Return: None > -# > -# MMX Usage: > -# MM0 =3D BIST State > -# MM5 =3D Save time-stamp counter value high32bit > -# MM6 =3D Save time-stamp counter value low32bit. > -# > -#-----------------------------------------------------------------------= ----- > - > -ASM_GLOBAL ASM_PFX(_ModuleEntryPoint) > -ASM_PFX(_ModuleEntryPoint): > - fninit # clear any pending Floating poi= nt exceptions > - # > - # Store the BIST value in mm0 > - # > - movd %eax, %mm0 > - cli > - > - # > - # Check INIT# is asserted by port 0xCF9 > - # > - mov $0x0CF9, %dx > - in %dx, %al > - cmp $0x04, %al > - jnz NotWarmStart > - > - # > - # @note Issue warm reset, since if CPU only reset is issued not all MS= Rs are > restored to their defaults > - # > - movw $0x0CF9, %dx > - movb $0x06, %al > - out %al, %dx > - > - # > - # Save time-stamp counter value > - # rdtsc load 64bit time-stamp counter to EDX:EAX > - # > - rdtsc > - movd %edx, %mm5 > - movd %ecx, %mm6 > - > - # > - # Load the GDT table in GdtDesc > - # > - movl $GdtDesc, %esi > - .byte 0x66 > - lgdt %cs:(%si) > - > - # > - # Transition to 16 bit protected mode > - # > - movl %cr0, %eax # Get control register 0 > - orl $0x00000003, %eax # Set PE bit (bit #0) & MP bit (bit= #1) > - movl %eax, %cr0 # Activate protected mode > - > - movl %cr4, %eax # Get control register 4 > - orl $0x00000600, %eax # Set OSFXSR bit (bit #9) & OSXMMEX= CPT > bit (bit #10) > - movl %eax, %cr4 > - > - # > - # Now we're in 16 bit protected mode > - # Set up the selectors for 32 bit protected mode entry > - # > - mov $SYS_DATA_SEL, %ax > - mov %ax, %ds > - mov %ax, %es > - mov %ax, %fs > - mov %ax, %gs > - mov %ax, %ss > - > - # > - # Transition to Flat 32 bit protected mode > - # The jump to a far pointer causes the transition to 32 bit mode > - # > - movl $ProtectedModeEntryLinearAddress, %esi > - jmp *%cs:(%si) > - > -ASM_GLOBAL ASM_PFX(_TEXT_PROTECTED_MODE) > -ASM_PFX(_TEXT_PROTECTED_MODE): > - > -#-----------------------------------------------------------------------= ----- > -# > -# Procedure: ProtectedModeEntryPoint > -# > -# Input: None > -# > -# Output: None > -# > -# Destroys: Assume all registers > -# > -# Description: > -# > -# This function handles: > -# Call two basic APIs from FSP binary > -# Initializes stack with some early data (BIST, PEI entry, etc) > -# > -# Return: None > -# > -#-----------------------------------------------------------------------= ----- > - > -ASM_GLOBAL ASM_PFX(ProtectedModeEntryPoint) > -ASM_PFX(ProtectedModeEntryPoint): > - > - # Find the fsp info header > - movl PcdGet32(PcdFsptBaseAddress), %edi > - > - movl FVH_SIGINATURE_OFFSET(%edi), %eax > - cmp $FVH_SIGINATURE_VALID_VALUE, %eax > - jnz FspHeaderNotFound > - > - xorl %eax, %eax > - movw FVH_EXTHEADER_OFFSET_OFFSET(%edi), %ax > - cmp $0x00, %ax > - jnz FspFvExtHeaderExist > - > - xorl %eax, %eax > - movw FVH_HEADER_LENGTH_OFFSET(%edi), %ax # Bypass Fv Header > - addl %eax, %edi > - jmp FspCheckFfsHeader > - > -FspFvExtHeaderExist: > - addl %eax, %edi > - movl FVH_EXTHEADER_SIZE_OFFSET(%edi), %eax # Bypass Ext Fv Header > - addl %eax, %edi > - > - # Round up to 8 byte alignment > - movl %edi, %eax > - andb $0x07, %al > - jz FspCheckFfsHeader > - > - and $0xFFFFFFF8, %edi > - add $0x08, %edi > - > -FspCheckFfsHeader: > - # Check the ffs guid > - movl (%edi), %eax > - cmp $FSP_HEADER_GUID_DWORD1, %eax > - jnz FspHeaderNotFound > - > - movl 0x4(%edi), %eax > - cmp $FSP_HEADER_GUID_DWORD2, %eax > - jnz FspHeaderNotFound > - > - movl 0x08(%edi), %eax > - cmp $FSP_HEADER_GUID_DWORD3, %eax > - jnz FspHeaderNotFound > - > - movl 0x0c(%edi), %eax > - cmp $FSP_HEADER_GUID_DWORD4, %eax > - jnz FspHeaderNotFound > - > - add $FFS_HEADER_SIZE_VALUE, %edi # Bypass the ffs header > - > - # Check the section type as raw section > - movb SECTION_HEADER_TYPE_OFFSET(%edi), %al > - cmp $0x19, %al > - jnz FspHeaderNotFound > - > - addl $RAW_SECTION_HEADER_SIZE_VALUE, %edi # Bypass the section > header > - jmp FspHeaderFound > - > -FspHeaderNotFound: > - jmp . > - > -FspHeaderFound: > - # Get the fsp TempRamInit Api address > - movl FSP_HEADER_IMAGEBASE_OFFSET(%edi), %eax > - addl FSP_HEADER_TEMPRAMINIT_OFFSET(%edi), %eax > - > - # Setup the hardcode stack > - movl $TempRamInitStack, %esp > - > - # Call the fsp TempRamInit Api > - jmp *%eax > - > -TempRamInitDone: > - cmp $0x8000000E, %eax #Check if EFI_NOT_FOUND returned. Error code > for Microcode Update not found. > - je CallSecFspInit #If microcode not found, don't hang, but cont= inue. > - > - cmp $0x0, %eax > - jnz FspApiFailed > - > - # ECX: start of range > - # EDX: end of range > -CallSecFspInit: > - subl PcdGet32 (PcdFspTemporaryRamSize), %edx # TemporaryRam for FSP > - xorl %eax, %eax > - movl %edx, %esp > - > - # Align the stack at DWORD > - addl $3, %esp > - andl $0xFFFFFFFC, %esp > - > - pushl %edx > - pushl %ecx > - pushl %eax # zero - no hob list yet > - call ASM_PFX(CallPeiCoreEntryPoint) > - > -FspApiFailed: > - jmp . > - > -.align 0x10 > -TempRamInitStack: > - .long TempRamInitDone > - .long FsptUpdDataPtr > - > -# > -# ROM-based Global-Descriptor Table for the Tiano PEI Phase -# -.align 0= x10 > - > -# > -# GDT[0]: 0x00: Null entry, never used. > -# > -.equ NULL_SEL, . - GdtBase # Selector [0] > -GdtBase: > -BootGdtTable: > - .long 0 > - .long 0 > - > -# > -# Linear data segment descriptor > -# > -.equ LINEAR_SEL, . - GdtBase # Selector [0x8] > - .word 0xFFFF # limit 0xFFFFF > - .word 0 # base 0 > - .byte 0 > - .byte 0x92 # present, ring 0, data, expa= nd-up, > writable > - .byte 0xCF # page-granular, 32-bit > - .byte 0 > - > -# > -# Linear code segment descriptor > -# > -.equ LINEAR_CODE_SEL, . - GdtBase # Selector [0x10] > - .word 0xFFFF # limit 0xFFFFF > - .word 0 # base 0 > - .byte 0 > - .byte 0x9B # present, ring 0, data, expa= nd-up, > not-writable > - .byte 0xCF # page-granular, 32-bit > - .byte 0 > -# > -# System data segment descriptor > -# > -.equ SYS_DATA_SEL, . - GdtBase # Selector [0x18] > - .word 0xFFFF # limit 0xFFFFF > - .word 0 # base 0 > - .byte 0 > - .byte 0x93 # present, ring 0, data, expa= nd-up, > not-writable > - .byte 0xCF # page-granular, 32-bit > - .byte 0 > - > -# > -# System code segment descriptor > -# > -.equ SYS_CODE_SEL, . - GdtBase # Selector [0x20] > - .word 0xFFFF # limit 0xFFFFF > - .word 0 # base 0 > - .byte 0 > - .byte 0x9A # present, ring 0, data, expa= nd-up, > writable > - .byte 0xCF # page-granular, 32-bit > - .byte 0 > -# > -# Spare segment descriptor > -# > -.equ SYS16_CODE_SEL, . - GdtBase # Selector [0x28] > - .word 0xFFFF # limit 0xFFFFF > - .word 0 # base 0 > - .byte 0x0E # Changed from F000 to E000. > - .byte 0x9B # present, ring 0, code, expa= nd-up, > writable > - .byte 0x00 # byte-granular, 16-bit > - .byte 0 > -# > -# Spare segment descriptor > -# > -.equ SYS16_DATA_SEL, . - GdtBase # Selector [0x30] > - .word 0xFFFF # limit 0xFFFF > - .word 0 # base 0 > - .byte 0 > - .byte 0x93 # present, ring 0, data, expa= nd-up, > not-writable > - .byte 0x00 # byte-granular, 16-bit > - .byte 0 > - > -# > -# Spare segment descriptor > -# > -.equ SPARE5_SEL, . - GdtBase # Selector [0x38] > - .word 0 # limit 0 > - .word 0 # base 0 > - .byte 0 > - .byte 0 # present, ring 0, data, expa= nd-up, writable > - .byte 0 # page-granular, 32-bit > - .byte 0 > -.equ GDT_SIZE, . - BootGdtTable # Size, in bytes > - > -# > -# GDT Descriptor > -# > -GdtDesc: # GDT descriptor > - .word GDT_SIZE - 1 # GDT limit > - .long BootGdtTable # GDT base address > - > -ASM_PFX(ProtectedModeEntryLinearAddress): > -ProtectedModeEntryLinearOffset: > - .long ProtectedModeEntryPoint # Offset of our 32 bit code > - .word LINEAR_CODE_SEL > diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/SecEntry.asm > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/SecEntry.nasm > similarity index 72% > rename from > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS > ecLib/Ia32/SecEntry.asm > rename to > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS > ecLib/Ia32/SecEntry.nasm > index 2886a37..7f6d771 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/SecEntry.asm > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/Ia32/SecEntry.nasm > @@ -1,28 +1,28 @@ > -;; @file > -; This is the code that goes from real-mode to protected mode. > -; It consumes the reset vector, calls TempRamInit API from FSP binary. > +;---------------------------------------------------------------------- > +-------- > ; > -; Copyright (c) 2017, Intel Corporation. All rights reserved.
> +; Copyright (c) 2019, Intel Corporation. All rights reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent > +; Module Name: > ; > -;; > +; SecEntry.nasm > +; > +; Abstract: > +; > +; This is the code that goes from real-mode to protected mode. > +; It consumes the reset vector, calls TempRamInit API from FSP binary. > +; > +;---------------------------------------------------------------------- > +-------- >=20 > #include "Fsp.h" >=20 > -.686p > -.xmm > -.model small, c > - > -EXTRN CallPeiCoreEntryPoint:NEAR > -EXTRN BoardBeforeTempRamInit:NEAR > -EXTRN FsptUpdDataPtr:FAR > +SECTION .text >=20 > +extern ASM_PFX(CallPeiCoreEntryPoint) > +extern ASM_PFX(FsptUpdDataPtr) > +extern ASM_PFX(BoardBeforeTempRamInit) > ; Pcds > -EXTRN PcdGet32 (PcdFsptBaseAddress):DWORD > -EXTRN PcdGet32(PcdFspTemporaryRamSize):DWORD > - > -_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE' > - ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE > +extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize)) > +extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress)) >=20 > ;-----------------------------------------------------------------------= ----- > ; > @@ -53,8 +53,10 @@ _TEXT_REALMODE SEGMENT PARA PUBLIC USE16 > 'CODE' > ; > ;-----------------------------------------------------------------------= ----- >=20 > +BITS 16 > align 4 > -_ModuleEntryPoint PROC NEAR C PUBLIC > +global ASM_PFX(_ModuleEntryPoint) > +ASM_PFX(_ModuleEntryPoint): > fninit ; clear any pending Floating poi= nt exceptions > ; > ; Store the BIST value in mm0 > @@ -70,6 +72,7 @@ _ModuleEntryPoint PROC NEAR C PUBLIC > cmp al, 04h > jnz NotWarmStart >=20 > + > ; > ; @note Issue warm reset, since if CPU only reset is issued not all MS= Rs are > restored to their defaults > ; > @@ -78,7 +81,6 @@ _ModuleEntryPoint PROC NEAR C PUBLIC > out dx, al >=20 > NotWarmStart: > - > ; > ; Save time-stamp counter value > ; rdtsc load 64bit time-stamp counter to EDX:EAX @@ -90,9 +92,9 @@ > NotWarmStart: > ; > ; Load the GDT table in GdtDesc > ; > - mov esi, OFFSET GdtDesc > + mov esi, GdtDesc > DB 66h > - lgdt fword ptr cs:[si] > + lgdt [cs:si] >=20 > ; > ; Transition to 16 bit protected mode @@ -120,14 +122,8 @@ NotWarmStar= t: > ; Transition to Flat 32 bit protected mode > ; The jump to a far pointer causes the transition to 32 bit mode > ; > - mov esi, offset ProtectedModeEntryLinearAddress > - jmp fword ptr cs:[si] > - > -_ModuleEntryPoint ENDP > -_TEXT_REALMODE ENDS > - > -_TEXT_PROTECTED_MODE SEGMENT PARA PUBLIC USE32 'CODE' > - ASSUME CS:_TEXT_PROTECTED_MODE, > DS:_TEXT_PROTECTED_MODE > + mov esi, ProtectedModeEntryLinearAddress > + jmp dword far [cs:si] >=20 > ;-----------------------------------------------------------------------= ----- > ; > @@ -149,69 +145,69 @@ _TEXT_PROTECTED_MODE SEGMENT PARA > PUBLIC USE32 'CODE' > ; > ;-----------------------------------------------------------------------= ----- >=20 > +BITS 32 > align 4 > -ProtectedModeEntryPoint PROC NEAR PUBLIC > - > - ; > - ; Early board hooks > - ; > - mov esp, BoardBeforeTempRamInitRet > - jmp BoardBeforeTempRamInit > +ProtectedModeEntryPoint: > + ; > + ; Early board hooks > + ; > + mov esp, BoardBeforeTempRamInitRet > + jmp ASM_PFX(BoardBeforeTempRamInit) >=20 > BoardBeforeTempRamInitRet: >=20 > ; Find the fsp info header > - mov edi, PcdGet32 (PcdFsptBaseAddress) > + mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))] >=20 > - mov eax, dword ptr [edi + FVH_SIGINATURE_OFFSET] > + mov eax, dword [edi + FVH_SIGINATURE_OFFSET] > cmp eax, FVH_SIGINATURE_VALID_VALUE > jnz FspHeaderNotFound >=20 > xor eax, eax > - mov ax, word ptr [edi + FVH_EXTHEADER_OFFSET_OFFSET] > + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET] > cmp ax, 0 > jnz FspFvExtHeaderExist >=20 > xor eax, eax > - mov ax, word ptr [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv > Header > + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header > add edi, eax > jmp FspCheckFfsHeader >=20 > FspFvExtHeaderExist: > add edi, eax > - mov eax, dword ptr [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv > Header > + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv > + Header > add edi, eax >=20 > ; Round up to 8 byte alignment > mov eax, edi > and al, 07h > - jz FspCheckFfsHeader > + jz FspCheckFfsHeader >=20 > and edi, 0FFFFFFF8h > add edi, 08h >=20 > FspCheckFfsHeader: > ; Check the ffs guid > - mov eax, dword ptr [edi] > + mov eax, dword [edi] > cmp eax, FSP_HEADER_GUID_DWORD1 > - jnz FspHeaderNotFound > + jnz FspHeaderNotFound >=20 > - mov eax, dword ptr [edi + 4] > + mov eax, dword [edi + 4] > cmp eax, FSP_HEADER_GUID_DWORD2 > - jnz FspHeaderNotFound > + jnz FspHeaderNotFound >=20 > - mov eax, dword ptr [edi + 8] > + mov eax, dword [edi + 8] > cmp eax, FSP_HEADER_GUID_DWORD3 > - jnz FspHeaderNotFound > + jnz FspHeaderNotFound >=20 > - mov eax, dword ptr [edi + 0Ch] > + mov eax, dword [edi + 0Ch] > cmp eax, FSP_HEADER_GUID_DWORD4 > - jnz FspHeaderNotFound > + jnz FspHeaderNotFound >=20 > add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header >=20 > ; Check the section type as raw section > - mov al, byte ptr [edi + SECTION_HEADER_TYPE_OFFSET] > + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET] > cmp al, 019h > jnz FspHeaderNotFound >=20 > @@ -223,11 +219,11 @@ FspHeaderNotFound: >=20 > FspHeaderFound: > ; Get the fsp TempRamInit Api address > - mov eax, dword ptr [edi + FSP_HEADER_IMAGEBASE_OFFSET] > - add eax, dword ptr [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] > + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] add eax, dword > + [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] >=20 > ; Setup the hardcode stack > - mov esp, OFFSET TempRamInitStack > + mov esp, TempRamInitStack >=20 > ; Call the fsp TempRamInit Api > jmp eax > @@ -242,7 +238,7 @@ TempRamInitDone: > ; ECX: start of range > ; EDX: end of range > CallSecFspInit: > - sub edx, PcdGet32 (PcdFspTemporaryRamSize) ; TemporaryRam for FSP > + sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; > TemporaryRam for FSP > xor eax, eax > mov esp, edx >=20 > @@ -253,30 +249,29 @@ CallSecFspInit: > push edx > push ecx > push eax ; zero - no hob list yet > - call CallPeiCoreEntryPoint > + call ASM_PFX(CallPeiCoreEntryPoint) >=20 > FspApiFailed: > jmp $ >=20 > align 10h > TempRamInitStack: > - DD OFFSET TempRamInitDone > - DD OFFSET FsptUpdDataPtr ; TempRamInitParams > - > -ProtectedModeEntryPoint ENDP > + DD TempRamInitDone > + DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams >=20 > ; > ; ROM-based Global-Descriptor Table for the Tiano PEI Phase ; align 16 > -PUBLIC BootGdtTable > +global ASM_PFX(BootGdtTable) >=20 > ; > ; GDT[0]: 0x00: Null entry, never used. > ; > NULL_SEL EQU $ - GDT_BASE ; Selector [0] > GDT_BASE: > -BootGdtTable DD 0 > +ASM_PFX(BootGdtTable): > + DD 0 > DD 0 > ; > ; Linear data segment descriptor > @@ -350,20 +345,17 @@ SPARE5_SEL EQU $ - GDT_BASE ; Selector > [0x38] > DB 0 ; present, ring 0, data, expand-= up, writable > DB 0 ; page-granular, 32-bit > DB 0 > -GDT_SIZE EQU $ - BootGdtTable ; Size, in bytes > +GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes >=20 > ; > ; GDT Descriptor > ; > GdtDesc: ; GDT descriptor > DW GDT_SIZE - 1 ; GDT limit > - DD OFFSET BootGdtTable ; GDT base address > + DD GDT_BASE ; GDT base address >=20 >=20 > -ProtectedModeEntryLinearAddress LABEL FWORD > -ProtectedModeEntryLinearOffset LABEL DWORD > - DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code > +ProtectedModeEntryLinearAddress: > +ProtectedModeEntryLinear: > + DD ProtectedModeEntryPoint ; Offset of our 32 bit code > DW LINEAR_CODE_SEL > - > -_TEXT_PROTECTED_MODE ENDS > -END > diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/Stack.S > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/Stack.S > deleted file mode 100644 > index 9953daa..0000000 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/Stack.S > +++ /dev/null > @@ -1,67 +0,0 @@ > -## @file > -# Switch the stack from temporary memory to permenent memory. > -# > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
-# > SPDX-License-Identifier: BSD-2-Clause-Patent -# -## > - > -#-----------------------------------------------------------------------= ------- > -# VOID > -# EFIAPI > -# SecSwitchStack ( > -# UINT32 TemporaryMemoryBase, > -# UINT32 PermanentMemoryBase > -# ) > -#-----------------------------------------------------------------------= ------- > -ASM_GLOBAL ASM_PFX (SecSwitchStack) > -ASM_PFX(SecSwitchStack): > - # > - # Save standard registers so they can be used to change stack > - # > - pushl %eax > - pushl %ebx > - pushl %ecx > - pushl %edx > - > - # > - # !!CAUTION!! this function address's is pushed into stack after > - # migration of whole temporary memory, so need save it to permanent > - # memory at first! > - # > - movl 20(%esp), %ebx # Save the first parameter > - movl 24(%esp), %ecx # Save the second parameter > - > - # > - # Save this function's return address into permanent memory at first= . > - # Then, Fixup the esp point to permanent memory > - # > - movl %esp, %eax > - subl %ebx, %eax > - addl %ecx, %eax > - movl 0(%esp), %edx # copy pushed register's value to perma= nent > memory > - movl %edx, 0(%eax) > - movl 4(%esp), %edx > - movl %edx, 4(%eax) > - movl 8(%esp), %edx > - movl %edx, 8(%eax) > - movl 12(%esp), %edx > - movl %edx, 12(%eax) > - movl 16(%esp), %edx # Update this function's return address = into > permanent memory > - movl %edx, 16(%eax) > - movl %eax, %esp # From now, esp is pointed to permanent > memory > - > - # > - # Fixup the ebp point to permanent memory > - # > - movl %ebp, %eax > - subl %ebx, %eax > - addl %ecx, %eax > - movl %eax, %ebp # From now, ebp is pointed to permanent > memory > - > - popl %edx > - popl %ecx > - popl %ebx > - popl %eax > - ret > - > diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/Stack.asm > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/Stack.nasm > similarity index 59% > rename from > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS > ecLib/Ia32/Stack.asm > rename to > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS > ecLib/Ia32/Stack.nasm > index 1830240..47db32d 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32/Stack.asm > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/Ia32/Stack.nasm > @@ -1,14 +1,14 @@ > -;; @file > -; Switch the stack from temporary memory to permenent memory. > +;---------------------------------------------------------------------- > +-------- > ; > -; Copyright (c) 2017, Intel Corporation. All rights reserved.
> +; Copyright (c) 2019, Intel Corporation. All rights reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent > +; Abstract: > +; > +; Switch the stack from temporary memory to permanent memory. > ; > -;; > +;---------------------------------------------------------------------- > +-------- >=20 > - .586p > - .model flat,C > - .code > + SECTION .text >=20 > ;-----------------------------------------------------------------------= ------- > ; VOID > @@ -18,7 +18,8 @@ > ; UINT32 PermanentMemoryBase > ; ); > ;-----------------------------------------------------------------------= ------- > -SecSwitchStack PROC > +global ASM_PFX(SecSwitchStack) > +ASM_PFX(SecSwitchStack): > ; > ; Save three register: eax, ebx, ecx > ; > @@ -43,16 +44,16 @@ SecSwitchStack PROC > mov eax, esp > sub eax, ebx > add eax, ecx > - mov edx, dword ptr [esp] ; copy pushed register's value to > permanent memory > - mov dword ptr [eax], edx > - mov edx, dword ptr [esp + 4] > - mov dword ptr [eax + 4], edx > - mov edx, dword ptr [esp + 8] > - mov dword ptr [eax + 8], edx > - mov edx, dword ptr [esp + 12] > - mov dword ptr [eax + 12], edx > - mov edx, dword ptr [esp + 16] ; Update this function's return a= ddress > into permanent memory > - mov dword ptr [eax + 16], edx > + mov edx, dword [esp] ; copy pushed register's value to per= manent > memory > + mov dword [eax], edx > + mov edx, dword [esp + 4] > + mov dword [eax + 4], edx > + mov edx, dword [esp + 8] > + mov dword [eax + 8], edx > + mov edx, dword [esp + 12] > + mov dword [eax + 12], edx > + mov edx, dword [esp + 16] ; Update this function's return addre= ss into > permanent memory > + mov dword [eax + 16], edx > mov esp, eax ; From now, esp is pointed to per= manent > memory >=20 > ; > @@ -68,6 +69,4 @@ SecSwitchStack PROC > pop ebx > pop eax > ret > -SecSwitchStack ENDP >=20 > - END > diff --git > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/SecFspWrapperPlatformSecLib.inf > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/SecFspWrapperPlatformSecLib.inf > index 6f2c95a..5d77e9e 100644 > --- > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/SecFspWrapperPlatformSecLib.inf > +++ > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat > +++ formSecLib/SecFspWrapperPlatformSecLib.inf > @@ -1,10 +1,11 @@ > ## @file > # Provide FSP wrapper platform sec related function. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # > +# > ## >=20 >=20 > ################################################################ > ################ > @@ -42,13 +43,10 @@ > PlatformInit.c >=20 > [Sources.IA32] > - Ia32/SecEntry.asm > - Ia32/PeiCoreEntry.asm > - Ia32/Stack.asm > + Ia32/SecEntry.nasm > + Ia32/PeiCoreEntry.nasm > + Ia32/Stack.nasm > Ia32/Fsp.h > - Ia32/SecEntry.S > - Ia32/PeiCoreEntry.S > - Ia32/Stack.S >=20 >=20 > ################################################################ > ################ > # > diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf > b/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf > index c4c4315..a1a8964 100644 > --- a/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf > +++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf > @@ -1,7 +1,7 @@ > ## @file > # FDF file of Platform. > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +25,7 @@ >=20 > [Rule.Common.PEI_CORE] > FILE PEI_CORE =3D $(NAMED_GUID) { > - PE32 PE32 Align =3D 32 $(INF_OUTPUT)/$(MODULE_NAME).= efi > + PE32 PE32 Align =3D 64 $(INF_OUTPUT)/$(MODULE_NAME).= efi > UI STRING=3D"$(MODULE_NAME)" Optional > VERSION STRING=3D"$(INF_VERSION)" Optional > BUILD_NUM=3D$(BUILD_NUMBER) > } > @@ -40,7 +40,7 @@ > [Rule.Common.PEIM] > FILE PEIM =3D $(NAMED_GUID) { > PEI_DEPEX PEI_DEPEX Optional > $(INF_OUTPUT)/$(MODULE_NAME).depex > - PE32 PE32 Align =3D 32 $(INF_OUTPUT)/$(MODULE_NAME).= efi > + PE32 PE32 Align =3D 64 $(INF_OUTPUT)/$(MODULE_NAME).= efi > UI STRING=3D"$(MODULE_NAME)" Optional > VERSION STRING=3D"$(INF_VERSION)" Optional > BUILD_NUM=3D$(BUILD_NUMBER) > } > diff --git > a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddr > ess.py > b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddr > ess.py > index 496b977..167a0e0 100644 > --- > a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddr > ess.py > +++ > b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAd > +++ dress.py > @@ -76,7 +76,7 @@ file.close() > pythontool =3D 'python' > if 'PYTHON_HOME' in os.environ: > pythontool =3D os.environ['PYTHON_HOME'] + os.sep + 'python' > -Process =3D subprocess.Popen(pythontool + " " + splitFspBinPath + " info= -f" + > fspBinFilePath, stdout=3Dsubprocess.PIPE) > +Process =3D subprocess.Popen([pythontool, splitFspBinPath, > +"info","-f",fspBinFilePath], stdout=3Dsubprocess.PIPE) > Output =3D Process.communicate()[0] > FsptInfo =3D Output.rsplit("FSP_M", 1); > for line in FsptInfo[1].split("\n"): > diff --git a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py > b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py > index 5b49b6b..b98c951 100644 > --- a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py > +++ b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py > @@ -1,6 +1,6 @@ > ## @ PatchBinFv.py > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved.
> # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -107,7 +107,7 @= @ > class FileChecker: > return >=20 > def ProcessFvInf(self, fvName): > - sourceFileName =3D > os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf") > + sourceFileName =3D > + os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf") > print "\nprocessing - " + sourceFileName > fileGuid =3D self.GetInfFileGuid (sourceFileName) > print "FV NAME GUID - " + fileGuid @@ -137,7 +137,7 @@ class > FileChecker: > self.PrintPcdList(self.InfPcdList) >=20 > def PatchFv(self, fvName): > - sourceFileName =3D > os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".fv") > + sourceFileName =3D > + os.path.join(self.sourceRoot,fvName,self.target,fvName+".Fv") > print "patching - " + sourceFileName >=20 > try : > @@ -161,7 +161,7 @@ class FileChecker: > print " [" + hex(offset) + "] " + > binascii.hexlify(data[offset:offset+2]) + " <=3D " + binascii.hexlify(h) > data[offset:offset+2] =3D h > elif (cmp (pcd[4], "UINT32") =3D=3D 0): > - l =3D struct.pack("L", int(pcd[3],16)) > + l =3D struct.pack("I", int(pcd[3],16)) > print " [" + hex(offset) + "] " + > binascii.hexlify(data[offset:offset+4]) + " <=3D " + binascii.hexlify(l) > data[offset:offset+4] =3D l > elif (cmp (pcd[4], "UINT64") =3D=3D 0): > diff --git a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py > b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py > index 321f7c5..149630e 100644 > --- a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py > +++ b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py > @@ -1,9 +1,8 @@ > ## @ PatchBinFv.py > # > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > +reserved.
> # SPDX-License-Identifier: BSD-2-Clause-Patent # -## >=20 > import os > import re > @@ -541,7 +540,7 @@ class FileChecker: > print "PCD: " + pcd[0] + "|" + pcd[3] + " <=3D=3D " + pcd[1] + "= (" + pcd[2] + ")" >=20 > def RebaseFv(self, fvName, rebasePcd): > - sourceFileName =3D > os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".fv") > + sourceFileName =3D > + os.path.join(self.sourceRoot,fvName,self.target,fvName+".Fv") > print "rebasing(FV) - " + sourceFileName >=20 > try : > @@ -617,7 +616,7 @@ class FileChecker: > if not line: > break >=20 > - newline =3D line[:-1] > + newline =3D line[:-1].replace('\r','') >=20 > if (cmp (newline, TargetPkg) =3D=3D 0): > FoundPkg =3D True > @@ -645,7 +644,7 @@ class FileChecker: > def GetOldFvBase (self, fvName, PcdName): > ParseBase =3D False > Value =3D "" > - fileName =3D > os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf") > + fileName =3D > + os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf") > try : > file =3D open(fileName) > except Exception: > @@ -657,7 +656,7 @@ class FileChecker: > if not line: > break >=20 > - newline =3D line[:-1] > + newline =3D line[:-1].replace('\r','') >=20 > if cmp (newline, "") =3D=3D 0: > continue > @@ -681,7 +680,7 @@ class FileChecker: > return Value >=20 > def SetNewFvBase (self, fvName, PcdName, OldFvBase, NewFvBase): > - fileName =3D > os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf") > + fileName =3D > + os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf") > print "update - " + fileName > try : > file =3D open(fileName, "r") > @@ -698,7 +697,7 @@ class FileChecker: > if not line: > break >=20 > - newline =3D line[:-1] > + newline =3D line[:-1].strip() >=20 > if cmp (newline, "") =3D=3D 0: > continue > diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py = index > a4ea093..9effefc 100644 > --- a/Platform/Intel/build_bios.py > +++ b/Platform/Intel/build_bios.py > @@ -135,12 +135,16 @@ def pre_build(build_config, build_type=3D"DEBUG", > silent=3DFalse, toolchain=3DNone): >=20 > # get the python path > if os.environ.get("PYTHON_HOME") is None: > - config["PYTHON_HOME"] =3D None > if os.environ.get("PYTHONPATH") is not None: > config["PYTHON_HOME"] =3D os.environ.get("PYTHONPATH") > else: > - print("PYTHONPATH environment variable is not found") > - sys.exit(1) > + config["PYTHON_HOME"] =3D os.path.dirname(sys.executable) > + config["PYTHONPATH"] =3D config["PYTHON_HOME"] > + > + if config.get("PYTHON_HOME") is None or \ > + not os.path.exists(config.get("PYTHON_HOME")): > + print("PYTHON_HOME environment variable is not found") > + sys.exit(1) >=20 > # if python is installed, disable the binary base tools. > # python is installed if this code is running :) @@ -151,18 +155,18 = @@ def > pre_build(build_config, build_type=3D"DEBUG", silent=3DFalse, toolchain= =3DNone): > # Run edk setup and update config > if os.name =3D=3D 'nt': > edk2_setup_cmd =3D [os.path.join(config["EFI_SOURCE"], "edksetup= "), > - "Rebuild"] > + "Rebuild"] >=20 > if config.get("EDK_SETUP_OPTION") and \ > - config["EDK_SETUP_OPTION"] !=3D " ": > + config["EDK_SETUP_OPTION"] !=3D " ": > edk2_setup_cmd.append(config["EDK_SETUP_OPTION"]) >=20 > _, _, result, return_code =3D execute_script(edk2_setup_cmd, > - config, > - collect_env=3DTrue, > - shell=3DTrue) > + config, > + collect_env=3DTrue, > + shell=3DTrue) > if return_code =3D=3D 0 and result is not None and isinstance(re= sult, > - dict): > + dict): > config.update(result) >=20 > # nmake BaseTools source > @@ -355,7 +359,11 @@ def build(config): > command.append("-D") > command.append("MAX_SOCKET=3D" + config["MAX_SOCKET"]) >=20 > - _, _, _, exit_code =3D execute_script(command, config) > + shell =3D True > + if os.name =3D=3D "posix": > + shell =3D False > + > + _, _, _, exit_code =3D execute_script(command, config, shell=3Dshell= ) > if exit_code !=3D 0: > build_failed(config) >=20 > -- > 2.7.4