From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: chasel.chiu@intel.com) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by groups.io with SMTP; Wed, 05 Jun 2019 23:18:56 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jun 2019 23:18:55 -0700 X-ExtLoop1: 1 Received: from pgsmsx113.gar.corp.intel.com ([10.108.55.202]) by orsmga004.jf.intel.com with ESMTP; 05 Jun 2019 23:18:54 -0700 Received: from pgsmsx110.gar.corp.intel.com (10.221.44.111) by pgsmsx113.gar.corp.intel.com (10.108.55.202) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 6 Jun 2019 14:05:57 +0800 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.51]) by PGSMSX110.gar.corp.intel.com ([169.254.13.11]) with mapi id 14.03.0415.000; Thu, 6 Jun 2019 14:05:57 +0800 From: "Chiu, Chasel" To: "Desimone, Nathaniel L" , "devel@edk2.groups.io" CC: "Kubacki, Michael A" , "Chaganty, Rangasai V" Subject: Re: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: FSP 2.1 SEC handling. Thread-Topic: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: FSP 2.1 SEC handling. Thread-Index: AQHVF6ZFwi5IkdNkkEORzbEeC+ZdnKaM+wqAgAExMWA= Date: Thu, 6 Jun 2019 06:05:56 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC50340223@PGSMSX111.gar.corp.intel.com> References: <20190531114251.12024-1-chasel.chiu@intel.com> <20190531114251.12024-2-chasel.chiu@intel.com> <02A34F284D1DA44BB705E61F7180EF0AAEBD257D@ORSMSX114.amr.corp.intel.com> In-Reply-To: <02A34F284D1DA44BB705E61F7180EF0AAEBD257D@ORSMSX114.amr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTJjMGRjN2EtZTMzMS00N2I4LTkyMGYtYTI3ZmU5OWJjMmZmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoicTV0SCs2RFNZdFY5cHlLaTJob04rTFdxSXlIZndQNGRcL1JlaVVKRjk1Z1wvT3kwZ3NJc0dJenRKd3F1RDdwWkVjIn0= x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.206] MIME-Version: 1.0 Return-Path: chasel.chiu@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Yes. I will add TempRamExitPpi.h to IntelFsp2Pkg in separate review later. Bugzilla filed: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1883 Thanks! Chasel > -----Original Message----- > From: Desimone, Nathaniel L > Sent: Thursday, June 6, 2019 3:53 AM > To: devel@edk2.groups.io; Chiu, Chasel > Cc: Kubacki, Michael A ; Chaganty, Rangasai= V > > Subject: RE: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: FSP 2.1 SEC ha= ndling. >=20 > Hi Chasel, >=20 > FSP_TEMP_RAM_EXIT_PPI is defined by the FSP 2.1 specification. The defin= ition > for it should not go in KabyLakeSiliconPkg, it should be placed in > IntelFsp2Pkg/Include/Ppi. >=20 > Thanks, > Nate >=20 > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Chiu, > Chasel > Sent: Friday, May 31, 2019 4:43 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Kubacki, Michael A > ; Chaganty, Rangasai V > > Subject: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: FSP 2.1 SEC handli= ng. >=20 > From: "Chasel, Chiu" >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1865 >=20 > To support FSP Dispatch mode, PlatformSecLib should consume > FSP_TEMP_RAM_EXIT_PPI to disable temporary memory. This patch added the > definition of this FSP_TEMP_RAM_EXIT_PPI. >=20 > Test: API mode no impact and can still booted. >=20 > Cc: Nate DeSimone > Cc: Michael A Kubacki > Cc: Sai Chaganty > Signed-off-by: Chasel Chiu > --- > Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi.h | 50 > ++++++++++++++++++++++++++++++++++++++++++++++++++ > Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 2 ++ > 2 files changed, 52 insertions(+) >=20 > diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi= .h > b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi.h > new file mode 100644 > index 0000000000..9e728a5d4d > --- /dev/null > +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/TempRamExitPpi.h > @@ -0,0 +1,50 @@ > +/** @file > + This file defines the Silicon Temp Ram Exit PPI which implements the > + required programming steps for disabling temporary memory. > + > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _FSP_TEMP_RAM_EXIT_PPI_H_ > +#define _FSP_TEMP_RAM_EXIT_PPI_H_ > + > +/// > +/// Global ID for the FSP_TEMP_RAM_EXIT_PPI. > +/// > +#define FSP_TEMP_RAM_EXIT_GUID \ > + { \ > + 0xbc1cfbdb, 0x7e50, 0x42be, { 0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, > +0xb0, 0x52 } \ > + } > + > +// > +// Forward declaration for the FSP_TEMP_RAM_EXIT_PPI. > +// > +typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI; > + > +/** > + Silicon function for disabling temporary memory. > + @param[in] TempRamExitParamPtr - Pointer to the TempRamExit parameter= s > structure. > + This structure is normally defined i= n the Integration > + Guide. If it is not defined in the I= ntegration Guide, > + pass NULL. > + @retval EFI_SUCCESS - Execution was completed successfully= . > + @retval Status - Error status reported by sub-functio= ns if > implemented. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *FSP_TEMP_RAM_EXIT) ( > + IN VOID *TempRamExitParamPtr > + ); > + > +/// > +/// This PPI provides function to disable temporary memory. > +/// > +struct _FSP_TEMP_RAM_EXIT_PPI { > + FSP_TEMP_RAM_EXIT TempRamExit; > +}; > + > +extern EFI_GUID gFspTempRamExitPpiGuid; > + > +#endif // _FSP_TEMP_RAM_EXIT_PPI_H_ > diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > index a613079dd4..874cbee7a7 100644 > --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > @@ -347,6 +347,8 @@ gPeiTpmInitializationDonePpiGuid =3D {0xa030d115, > 0x54dd, 0x447b, { 0x90, 0x64, 0x ## gSiPolicyPpiGuid =3D {0xaebffa01= , 0x7edc, > 0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}} > gSiPreMemPolicyPpiGuid =3D {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x9= 7, 0xc1, > 0x89, 0xd0, 0xab, 0x8d}} > +gFspTempRamExitPpiGuid =3D {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x8= 7, > 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}} > + > ## > ## SystemAgent > ## > -- > 2.19.1.windows.1 >=20 >=20 >=20