From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: chasel.chiu@intel.com) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by groups.io with SMTP; Mon, 10 Jun 2019 22:13:14 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jun 2019 22:13:13 -0700 X-ExtLoop1: 1 Received: from pgsmsx102.gar.corp.intel.com ([10.221.44.80]) by fmsmga005.fm.intel.com with ESMTP; 10 Jun 2019 22:13:12 -0700 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.51]) by PGSMSX102.gar.corp.intel.com ([169.254.6.79]) with mapi id 14.03.0415.000; Tue, 11 Jun 2019 13:13:11 +0800 From: "Chiu, Chasel" To: "Ni, Ray" , "devel@edk2.groups.io" , "Desimone, Nathaniel L" CC: "Kubacki, Michael A" , "Chaganty, Rangasai V" Subject: Re: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI. Thread-Topic: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI. Thread-Index: AQHVGiv9fPPlsaEfCU2frj8WoMZMbKaN3j4AgAddPQCAAJuRMA== Date: Tue, 11 Jun 2019 05:13:10 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC50342BAF@PGSMSX111.gar.corp.intel.com> References: <20190603164658.4668-1-chasel.chiu@intel.com> <20190603164658.4668-2-chasel.chiu@intel.com> <02A34F284D1DA44BB705E61F7180EF0AAEBD5DA3@ORSMSX114.amr.corp.intel.com> <734D49CCEBEEF84792F5B80ED585239D5C19FDDC@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <734D49CCEBEEF84792F5B80ED585239D5C19FDDC@SHSMSX104.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYThjNDEzOWMtM2Y0ZC00NWRlLWI3YTYtZjFmNDdhZDBhZDM2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiSG9yM2tiMndsMnlJZEl5MEsxc3B4REN4MjJOOXB5emh4eHhsTE5ZTG5OK0JxUzdLcW50TmNRdjRuYmRSZnRlRyJ9 x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.205] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Ray, Please see my reply below inline. Thanks! Chasel > -----Original Message----- > From: Ni, Ray > Sent: Tuesday, June 11, 2019 10:11 AM > To: devel@edk2.groups.io; Desimone, Nathaniel L > ; Chiu, Chasel > Cc: Kubacki, Michael A ; Chaganty, Rangasai= V > > Subject: RE: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support > DefaultPolicyInit PPI. >=20 > Chasel, > Where is the code that produces DefaultPolicyInit PPI? > Is the code public available? Only DefaultPolicyInit PPI definition public, no producer code in Kabylake= SiliconPkg. The producer code of DefaultPolicyInit PPI is inside FSP binary so it can = produce different ConfigBlock structures from different FSP binary, and Con= figBlocks in KabylakeSiliconPkg is only for boot loader to fill UPD buffer = in API mode, it is not used in Dispatch mode. >=20 > And in general, I think the patch consists of several changes: > 1. change version compare from "=3D=3D" to ">=3D" to support FSP be used= in newer > board. > 2. Add definition of SiDefaultPolicyPpi > 3. Update non-FSP version of PeiSiliconPolicyInitLib to consume the > SiDefaultPolicyPpi > 4. Update config block for GFX > 5. Add SiXXXInstallPolicyReadyPpi > 6. maybe more.... >=20 > Can you please try to separate the changes to small patches? Yes. I will follow this suggestion next time working on big change. >=20 > Regarding to the changes in > KabylakeSiliconPkg\Library\PeiSiPolicyLib\PeiSiPolicyLibPreMem.c: > There are two APIs: SiPreMemInstallPolicyPpi and > SiPreMemInstallPolicyReadyPpi. >=20 > When FSP runs in API mode, the calling flow is as below: > FspWrapperPeim::PeiMemoryDiscoveredNotify > --> MinPlatformPkg/../PeiFspWrapperPlatformLib::UpdateFspsUpdData > --> KabylakeSiliconPkg/.../SiliconPolicyInitPostMem > --> KabylakeSiliconPkg/.../PeiSiPolicyLib::SiCreateConfigBlocks > --> KabylakeSiliconPkg/.../PeiSiPolicyLib::SiInstallPolicyPpi >=20 > Do you think that it's possible to update > KabylakeSiliconPkg/.../SiliconPolicyInitPostMem() to > call SiDefaultPolicyInitPpi->PeiPolicyInit()? To align the behavior when= FSP runs > in dispatch mode. The actual policy initialization flows are aligned between API mode and Di= spatch mode: SiliconPolicyPeiPostMem.efi: SiliconPolicyInitPostMem () -> SiliconPolic= yUpdatePostMem () -> SiliconPolicyDonePostMem (). Only the library instances are different: FSP Wrapper running in Dispatch mode: \Silicon\Intel\KabylakeSiliconPkg\= Library\PeiSiliconPolicyInitLib\PeiPolicyInit.c (Initialize ConfigBlocks po= licy) FSP Wrapper running in API mode: \Silicon\Intel\KabylakeSiliconPkg\Libra= ry\PeiSiliconPolicyInitLibFsp\PeiFspPolicyInitLib.c (Initialize ConfigBlock= s policy first and then fill into UPD buffer) Also when running API mode the PPI produced by FSP binary - "SiDefaultPoli= cyInitPpi->PeiPolicyInit()" cannot be seen by boot loader as they are runni= ng with different PeiCore stacks. >=20 > Thanks, > Ray >=20 > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of Nate > > DeSimone > > Sent: Thursday, June 6, 2019 5:44 PM > > To: Chiu, Chasel ; devel@edk2.groups.io > > Cc: Kubacki, Michael A ; Chaganty, Rangas= ai V > > > > Subject: Re: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support > > DefaultPolicyInit PPI. > > > > Reviewed-by: Nate DeSimone > > > > -----Original Message----- > > From: Chiu, Chasel > > Sent: Monday, June 3, 2019 9:47 AM > > To: devel@edk2.groups.io > > Cc: Chiu, Chasel ; Kubacki, Michael A > > ; Chaganty, Rangasai V > > ; Desimone, Nathaniel L > > > > Subject: [PATCH 1/2] KabylakeSiliconPkg: Support DefaultPolicyInit PPI= . > > > > From: "Chasel, Chiu" > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1870 > > > > FSP in dispatch mode will produce DefaultPolicyInit PPI for boot loade= r to > > consume and install policy with default settings built-in by FSP. > > Boot loader then may patch policy with per-board settings and then ins= tall > > PolicyReady PPI to start silicon initialization (policy consumer code) > > > > Since different version FSP has different version policy structure, th= e policy > > revision check code has been extended to support newer revision policy= and > > the policy structure boot loader consuming has been aligned with the s= ame > > structure inside FSP. > > (FSP will maintain policy structure backward > > compatibility) > > > > Also removed microcode location searching code from silicon scope beca= use > > silicon code should not access hard-coded flash region unconditionally= . > > This should be done by platform/boot loader side. > > > > Cc: Michael A Kubacki > > Cc: Sai Chaganty > > Cc: Nate DeSimone > > Signed-off-by: Chasel Chiu > > --- > > > > Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol= icyLi > > b.c | 133 > +++++++---------------------------------------- > > ----------------------------------------------------------------------= ---------------- > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLi= b.c > > | 53 ++++++++++++++++++++++++++++++++++++++++++++++++----- > > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib= PreMem > > .c | 50 > > ++++++++++++++++++++++++++++++++++++++++++++++---- > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPoli= cyInit.c > > | 32 +++++++++++++++++++++++++------- > > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo= licyInitPr > > eMem.c | 39 > +++++++++++++++++++++++++++------- > > ----- > > > > Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicy= Lib. > > c | 6 +++--- > > > > Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/Dx= eSa > > PolicyLib.c | 4 ++-- > > > > Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Sa= Print > > Policy.c | 14 +++++++= ------- > > Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > > | 4 +++- > > > > Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol= icyLi > > brary.h | 4 +--- > > Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > > | 32 ++++++++++++++++++++++++++++---- > > > > Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicyI= nit.h > > | 36 ++++++++++++++++++++++++++++++++++++ > > Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.h > > | 36 ++++++++++++++++++++++++++++++++++++ > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLi= b.inf > > | 8 +++++--- > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPoli= cyInit.h > > | 4 +++- > > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPo= stMemSi > > liconPolicyInitLib.inf | 75 > > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > +++++++++++++++++ > > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/{PeiS= iliconPoli > > cyInitLib.inf =3D> PeiPreMemSiliconPolicyInitLib.inf} | 11 ++++++++--= - > > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/Pe= iSiliconP > > olicyInitLibFsp.inf | 5 +++-- > > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/Pe= iSiliconP > > olicyInitLibFspAml.inf | 1 + > > Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > > | 4 ++++ > > > > Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graph= ics > > PeiConfig.h | 16 +++++= +++++++++-- > > > > Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Pe= iSaP > > olicyLib.inf | 3 ++- > > 22 files changed, 384 insertions(+), 186 deletions(-) > > > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuP= olicy > > Lib.c > > b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuP= olicy > > Lib.c > > index cb7f379e0f..eb83cd4918 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuP= olicy > > Lib.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/Pei= Cp > > +++ uPolicyLib.c > > @@ -1,7 +1,7 @@ > > /** @file > > This file is PeiCpuPolicy library. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -13,128 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #include #include > > > > -#ifndef FSP_FLAG > > -/** > > - Get the next microcode patch pointer. > > - > > - @param[in, out] MicrocodeData - Input is a pointer to the last micr= ocode > > patch address found, > > - and output points to the next patch= address found. > > - > > - @retval EFI_SUCCESS - Patch found. > > - @retval EFI_NOT_FOUND - Patch not found. > > -**/ > > -EFI_STATUS > > -EFIAPI > > -RetrieveMicrocode ( > > - IN OUT CPU_MICROCODE_HEADER **MicrocodeData > > - ) > > -{ > > - UINTN MicrocodeStart; > > - UINTN MicrocodeEnd; > > - UINTN TotalSize; > > - > > - if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) =3D=3D 0) || (FixedPcd= Get32 > > (PcdFlashMicrocodeFvSize) =3D=3D 0)) { > > - return EFI_NOT_FOUND; > > - } > > - > > - /// > > - /// Microcode binary in SEC > > - /// > > - MicrocodeStart =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) = + > > - ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 > > (PcdFlashMicrocodeFvBase))->HeaderLength + > > - sizeof (EFI_FFS_FILE_HEADER); > > - > > - MicrocodeEnd =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + > > (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize); > > - > > - if (*MicrocodeData =3D=3D NULL) { > > - *MicrocodeData =3D (CPU_MICROCODE_HEADER *) (UINTN) > > MicrocodeStart; > > - } else { > > - if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) > > MicrocodeStart) { > > - DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart > > \n")); > > - return EFI_NOT_FOUND; > > - } > > - > > - TotalSize =3D (UINTN) ((*MicrocodeData)->TotalSize); > > - if (TotalSize =3D=3D 0) { > > - TotalSize =3D 2048; > > - } > > - > > - *MicrocodeData =3D (CPU_MICROCODE_HEADER *) > > ((UINTN)*MicrocodeData + TotalSize); > > - if (*MicrocodeData >=3D (CPU_MICROCODE_HEADER *) (UINTN) > > (MicrocodeEnd) || (*MicrocodeData)->TotalSize =3D=3D (UINT32) -1) { > > - DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >=3D MicrocodeEn= d > > \n")); > > - return EFI_NOT_FOUND; > > - } > > - } > > - return EFI_SUCCESS; > > -} > > - > > -/** > > - Get the microcode patch pointer. > > - > > - @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or N= ULL > > if not found. > > -**/ > > -EFI_PHYSICAL_ADDRESS > > -PlatformCpuLocateMicrocodePatch ( > > - VOID > > - ) > > -{ > > - EFI_STATUS Status; > > - CPU_MICROCODE_HEADER *MicrocodeData; > > - EFI_CPUID_REGISTER Cpuid; > > - UINT32 UcodeRevision; > > - UINTN MicrocodeBufferSize; > > - VOID *MicrocodeBuffer =3D NULL; > > - > > - AsmCpuid ( > > - CPUID_VERSION_INFO, > > - &Cpuid.RegEax, > > - &Cpuid.RegEbx, > > - &Cpuid.RegEcx, > > - &Cpuid.RegEdx > > - ); > > - > > - UcodeRevision =3D GetCpuUcodeRevision (); > > - MicrocodeData =3D NULL; > > - while (TRUE) { > > - /// > > - /// Find the next patch address > > - /// > > - Status =3D RetrieveMicrocode (&MicrocodeData); > > - DEBUG ((DEBUG_INFO, "MicrocodeData =3D %x\n", MicrocodeData)); > > - > > - if (Status !=3D EFI_SUCCESS) { > > - break; > > - } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, > > &UcodeRevision)) { > > - break; > > - } > > - } > > - > > - if (EFI_ERROR (Status)) { > > - return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; > > - } > > - > > - /// > > - /// Check that microcode patch size is <=3D 128K max size, > > - /// then copy the patch from FV to temp buffer for faster access. > > - /// > > - MicrocodeBufferSize =3D (UINTN) MicrocodeData->TotalSize; > > - > > - if (MicrocodeBufferSize <=3D MAX_MICROCODE_PATCH_SIZE) { > > - MicrocodeBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES > > (MicrocodeBufferSize)); > > - if (MicrocodeBuffer !=3D NULL) { > > - DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); > > - CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); > > - > > - return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; > > - } else { > > - DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for > > Microcode Patch.\n")); > > - } > > - } else { > > - DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max > > allowed size of 128K.\n")); > > - } > > - return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; -} -#endif > > > > /** > > Load Config block default > > @@ -158,9 +36,12 @@ LoadCpuConfigDefault ( > > CpuConfig->AesEnable =3D CPU_FEATURE_ENABLE; > > CpuConfig->EnableRsr =3D CPU_FEATURE_ENABLE; > > CpuConfig->SmmbaseSwSmiNumber =3D (UINTN) PcdGet8 > > (PcdSmmbaseSwSmi); > > -#ifndef FSP_FLAG > > - CpuConfig->MicrocodePatchAddress =3D PlatformCpuLocateMicrocodePatc= h > > (); -#endif > > + // > > + // This function is shared by both non-FSP and FSP scenarios and al= ways > > executed unconditionally. > > + // Since FSP/silicon code should not unconditionally access any > > + hardcoding flash regions (that region might not be accessible // in > > unknown platforms), the microcode location searching code should be > > moved to outside silicon code scope. > > + // > > + CpuConfig->MicrocodePatchAddress =3D 0; > > } > > > > > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyL= ib.c > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyL= ib.c > > index 813b868fcf..c3a8bbf539 100644 > > --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPol= icyLib.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPol= ic > > +++ yLib.c > > @@ -2,7 +2,7 @@ > > This file is PeiSiPolicyLib library creates default settings of RC > > Policy and installs RC Policy PPI. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -196,8 +196,6 @@ DumpSiPolicy ( > > > > /** > > SiInstallPolicyPpi installs SiPolicyPpi. > > - While installed, RC assumes the Policy is ready and finalized. So p= lease > > update and override > > - any setting before calling this function. > > > > @param[in] SiPolicyPpi The pointer to Silicon Policy PPI in= stance > > > > @@ -226,11 +224,56 @@ SiInstallPolicyPpi ( > > Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (V= OID *) > > &SiConfig); > > ASSERT_EFI_ERROR (Status); > > > > + // > > + // Install Silicon Policy PPI > > + // > > + Status =3D PeiServicesInstallPpi (SiPolicyPpiDesc); > > + ASSERT_EFI_ERROR (Status); > > + return Status; > > +} > > + > > +/** > > + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. > > + While installed, RC assumes the Policy is ready and finalized. So > > +please update and override > > + any setting before calling this function. > > + > > + @retval EFI_SUCCESS The policy is installed. > > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buf= fer > > +**/ > > +EFI_STATUS > > +EFIAPI > > +SiInstallPolicyReadyPpi ( > > + VOID > > + ) > > +{ > > + EFI_STATUS Status; > > + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPpiDesc; > > + SI_POLICY_PPI *SiPolicy; > > + > > + SiPolicyPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (si= zeof > > + (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyPpiDesc =3D=3D NULL) { > > + ASSERT (FALSE); > > + return EFI_OUT_OF_RESOURCES; > > + } > > + > > + SiPolicyPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | > > + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; > > + SiPolicyPpiDesc->Guid =3D &gSiPolicyReadyPpiGuid; > > + SiPolicyPpiDesc->Ppi =3D NULL; > > + > > + SiPolicy =3D NULL; > > + Status =3D PeiServicesLocatePpi ( > > + &gSiPolicyPpiGuid, > > + 0, > > + NULL, > > + (VOID **)&SiPolicy > > + ); > > + ASSERT_EFI_ERROR(Status); > > + > > DEBUG ((DEBUG_INFO, "Dump Silicon Policy update by Platform...\n"))= ; > > - DumpSiPolicy (SiPolicyPpi); > > + DumpSiPolicy (SiPolicy); > > > > // > > - // Install Silicon Policy PPI > > + // Install Silicon Policy Ready PPI > > // > > Status =3D PeiServicesInstallPpi (SiPolicyPpiDesc); > > ASSERT_EFI_ERROR (Status); > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyL= ibPreMe > > m.c > > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib= PreMe > > m.c > > index e0d83cb467..e6506a0445 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyL= ibPreMe > > m.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPol= ic > > +++ yLibPreMem.c > > @@ -2,7 +2,7 @@ > > This file is PeiSiPolicyLib library creates default settings of RC > > Policy and installs RC Policy PPI. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -69,8 +69,6 @@ SiCreatePreMemConfigBlocks ( > > > > /** > > SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. > > - While installed, RC assumes the Policy is ready and finalized. So p= lease > > update and override > > - any setting before calling this function. > > > > @param[in] SiPreMemPolicyPpi The pointer to Silicon Policy PPI in= stance > > > > @@ -97,6 +95,50 @@ SiPreMemInstallPolicyPpi ( > > SiPolicyPreMemPpiDesc->Ppi =3D SiPolicyPreMemPpi; > > > > // > > + // Install Silicon Policy PPI > > + // > > + Status =3D PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); > > + ASSERT_EFI_ERROR (Status); > > + return Status; > > +} > > + > > +/** > > + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. > > + While installed, RC assumes the Policy is ready and finalized. So > > +please update and override > > + any setting before calling this function. > > + > > + @retval EFI_SUCCESS The policy is installed. > > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buf= fer > > +**/ > > +EFI_STATUS > > +EFIAPI > > +SiPreMemInstallPolicyReadyPpi ( > > + VOID > > + ) > > +{ > > + EFI_STATUS Status; > > + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPreMemPpiDesc; > > + SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi; > > + > > + SiPolicyPreMemPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPo= ol > > + (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyPreMemPpiDesc =3D=3D= NULL) { > > + ASSERT (FALSE); > > + return EFI_OUT_OF_RESOURCES; > > + } > > + > > + SiPolicyPreMemPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | > > + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; > > + SiPolicyPreMemPpiDesc->Guid =3D &gSiPreMemPolicyReadyPpiGuid; > > + SiPolicyPreMemPpiDesc->Ppi =3D NULL; > > + > > + Status =3D PeiServicesLocatePpi ( > > + &gSiPreMemPolicyPpiGuid, > > + 0, > > + NULL, > > + (VOID **)&SiPolicyPreMemPpi > > + ); > > + ASSERT_EFI_ERROR (Status); > > + > > + // > > // Print whole PCH_POLICY_PPI and serial out. > > // > > PchPreMemPrintPolicyPpi (SiPolicyPreMemPpi); @@ -114,7 +156,7 @@ > > SiPreMemInstallPolicyPpi ( > > CpuPreMemPrintPolicy (SiPolicyPreMemPpi); > > > > // > > - // Install Silicon Policy PPI > > + // Install PreMem Silicon Policy Ready PPI > > // > > Status =3D PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); > > ASSERT_EFI_ERROR (Status); > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/Pei= PolicyInit > > .c > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/Pei= PolicyInit > > .c > > index 0de415ad19..6cbc39c29e 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/Pei= PolicyInit > > .c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib= /P > > +++ eiPolicyInit.c > > @@ -1,7 +1,7 @@ > > /** @file > > This file is SampleCode for Intel PEI Platform Policy initializatio= n. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -35,19 +35,37 @@ SiliconPolicyInitPostMem ( > > IN OUT VOID *Policy > > ) > > { > > - EFI_STATUS Status; > > - SI_POLICY_PPI *SiPolicyPpi; > > + EFI_STATUS Status; > > + SI_POLICY_PPI *SiPolicyPpi; > > + PEI_SI_DEFAULT_POLICY_INIT_PPI *PeiSiDefaultPolicyInitPpi; > > > > DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pos= t- > > Memory...\n")); > > > > ASSERT (Policy =3D=3D NULL); > > > > // > > - // Call SiCreateConfigBlocks to initialize Silicon Policy structure > > - // and get all Intel default policy settings. > > + // Locate Policy init PPI to install default silicon policy > > // > > - Status =3D SiCreateConfigBlocks (&SiPolicyPpi); > > + Status =3D PeiServicesLocatePpi ( > > + &gSiDefaultPolicyInitPpiGuid, > > + 0, > > + NULL, > > + (VOID **) &PeiSiDefaultPolicyInitPpi > > + ); > > ASSERT_EFI_ERROR (Status); > > + if (PeiSiDefaultPolicyInitPpi !=3D NULL) { > > + Status =3D PeiSiDefaultPolicyInitPpi->PeiPolicyInit (); > > + ASSERT_EFI_ERROR (Status); > > + if (Status =3D=3D EFI_SUCCESS) { > > + Status =3D PeiServicesLocatePpi ( > > + &gSiPolicyPpiGuid, > > + 0, > > + NULL, > > + (VOID **) &SiPolicyPpi > > + ); > > + ASSERT_EFI_ERROR (Status); > > + } > > + } > > > > return SiPolicyPpi; > > } > > @@ -78,7 +96,7 @@ SiliconPolicyDonePostMem ( > > // While installed, RC assumes the Policy is ready and finalized. S= o please > > // update and override any setting before calling this function. > > // > > - Status =3D SiInstallPolicyPpi (SiPolicyPpi); > > + Status =3D SiInstallPolicyReadyPpi (); > > ASSERT_EFI_ERROR (Status); > > > > DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Post= - > > Memory\n")); diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/Pei= PolicyInit > > PreMem.c > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/Pei= PolicyInit > > PreMem.c > > index fd76b4fac3..8e138b1eb2 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/Pei= PolicyInit > > PreMem.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib= /P > > +++ eiPolicyInitPreMem.c > > @@ -1,7 +1,7 @@ > > /** @file > > This file is SampleCode for Intel PEI Platform Policy initializatio= n. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -35,20 +35,38 @@ SiliconPolicyInitPreMem ( > > IN OUT VOID *Policy > > ) > > { > > - EFI_STATUS Status; > > - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > > + EFI_STATUS Status; > > + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > > + PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI > > + *PeiPreMemSiDefaultPolicyInitPpi; > > > > DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre= - > > Memory...\n")); > > > > ASSERT (Policy =3D=3D NULL); > > + SiPreMemPolicyPpi =3D NULL; > > > > // > > - // Call SiCreatePreMemConfigBlocks to initialize platform policy st= ructure > > - // and get all intel default policy settings. > > + // Locate Policy init PPI to install default silicon policy > > // > > - Status =3D SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi); > > + Status =3D PeiServicesLocatePpi ( > > + &gSiPreMemDefaultPolicyInitPpiGuid, > > + 0, > > + NULL, > > + (VOID **) &PeiPreMemSiDefaultPolicyInitPpi > > + ); > > ASSERT_EFI_ERROR (Status); > > - > > + if (PeiPreMemSiDefaultPolicyInitPpi !=3D NULL) { > > + Status =3D PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit (= ); > > + ASSERT_EFI_ERROR (Status); > > + if (Status =3D=3D EFI_SUCCESS) { > > + Status =3D PeiServicesLocatePpi ( > > + &gSiPreMemPolicyPpiGuid, > > + 0, > > + NULL, > > + (VOID **) &SiPreMemPolicyPpi > > + ); > > + ASSERT_EFI_ERROR (Status); > > + } > > + } > > return SiPreMemPolicyPpi; > > } > > > > @@ -69,16 +87,13 @@ SiliconPolicyDonePreMem ( > > ) > > { > > EFI_STATUS Status; > > - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > > - > > - SiPreMemPolicyPpi =3D Policy; > > > > // > > - // Install SiPreMemPolicyPpi. > > + // Install Policy Ready PPI > > // While installed, RC assumes the Policy is ready and finalized. S= o please > > // update and override any setting before calling this function. > > // > > - Status =3D SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi); > > + Status =3D SiPreMemInstallPolicyReadyPpi (); > > ASSERT_EFI_ERROR (Status); > > > > DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre- > > Memory\n")); diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePoli= cyLi > > b.c > > b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePoli= cyLi > > b.c > > index 31c7d59d1d..803de0999e 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePoli= cyLi > > b.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMe= Po > > +++ licyLib.c > > @@ -1,7 +1,7 @@ > > /** @file > > This file is PeiMePolicy library. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -97,7 +97,7 @@ PrintMePeiPreMemConfig ( > > DEBUG_CODE_BEGIN (); > > DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_PREMEM_CONFIG = -- > > ---------------\n")); > > DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", > > MePeiPreMemConfig->Header.Revision)); > > - ASSERT (MePeiPreMemConfig->Header.Revision =3D=3D > > ME_PEI_PREMEM_CONFIG_REVISION); > > + ASSERT (MePeiPreMemConfig->Header.Revision >=3D > > + ME_PEI_PREMEM_CONFIG_REVISION); > > > > DEBUG ((DEBUG_INFO, " HeciTimeouts : 0x%x\n", > > MePeiPreMemConfig->HeciTimeouts)); > > DEBUG ((DEBUG_INFO, " DidInitStat : 0x%x\n", > > MePeiPreMemConfig->DidInitStat)); > > @@ -129,7 +129,7 @@ PrintMePeiConfig ( > > DEBUG_CODE_BEGIN (); > > DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_CONFIG -------= -------- > > --\n")); > > DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiCon= fig- > > >Header.Revision)); > > - ASSERT (MePeiConfig->Header.Revision =3D=3D ME_PEI_CONFIG_REVISION)= ; > > + ASSERT (MePeiConfig->Header.Revision >=3D ME_PEI_CONFIG_REVISION); > > > > DEBUG ((DEBUG_INFO, " EndOfPostMessage : 0x%x\n", > MePeiConfig- > > >EndOfPostMessage)); > > DEBUG ((DEBUG_INFO, " Heci3Enabled : 0x%x\n", MePeiCon= fig- > > >Heci3Enabled)); > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/= Dxe > > SaPolicyLib.c > > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/= Dxe > > SaPolicyLib.c > > index 67fe214d0e..be36468b1e 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/= Dxe > > SaPolicyLib.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicy= Li > > +++ b/DxeSaPolicyLib.c > > @@ -1,7 +1,7 @@ > > /** @file > > This file provide services for DXE phase policy default initializat= ion > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -38,7 +38,7 @@ SaPrintPolicyProtocol ( > > > > DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) pri= nt BEGIN > > -----------------\n")); > > DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy- > > >TableHeader.Header.Revision)); > > - ASSERT (SaPolicy->TableHeader.Header.Revision =3D=3D > > SA_POLICY_PROTOCOL_REVISION); > > + ASSERT (SaPolicy->TableHeader.Header.Revision >=3D > > + SA_POLICY_PROTOCOL_REVISION); > > DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION= -- > > ---------------\n")); > > DEBUG ((DEBUG_INFO, " EnableAbove4GBMmio : %x\n", MiscDxeConfig- > > >EnableAbove4GBMmio)); > > DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) pri= nt END --- > > --------------\n")); diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/= SaPri > > ntPolicy.c > > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/= SaPri > > ntPolicy.c > > index 8b3a81a1c4..5c80fca88e 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/= SaPri > > ntPolicy.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicy= Li > > +++ b/SaPrintPolicy.c > > @@ -1,7 +1,7 @@ > > /** @file > > This file provides service for PEI phase policy printing > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -41,11 +41,11 @@ SaPrintPolicyPpiPreMem ( > > > > DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreM= em) > > Print BEGIN -----------------\n")); > > DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPreMemPpi- > > >TableHeader.Header.Revision)); > > - ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision =3D=3D > > SI_PREMEM_POLICY_REVISION); > > + ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision >=3D > > + SI_PREMEM_POLICY_REVISION); > > > > DEBUG ((DEBUG_INFO, "------------------------ > > SA_MISC_PEI_PREMEM_CONFIG -----------------\n")); > > DEBUG ((DEBUG_INFO, " Revision : %d\n", MiscPeiPreMemConfig- > > >Header.Revision)); > > - ASSERT (MiscPeiPreMemConfig->Header.Revision =3D=3D > > SA_MISC_PEI_PREMEM_CONFIG_REVISION); > > + ASSERT (MiscPeiPreMemConfig->Header.Revision >=3D > > + SA_MISC_PEI_PREMEM_CONFIG_REVISION); > > DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", > > SA_MC_MAX_SOCKETS)); > > for (Index =3D 0; Index < SA_MC_MAX_SOCKETS; Index++) { > > DEBUG ((DEBUG_INFO, " 0x%x", MiscPeiPreMemConfig- > > >SpdAddressTable[Index])); > > @@ -56,7 +56,7 @@ SaPrintPolicyPpiPreMem ( > > DEBUG ((DEBUG_INFO, "------------------------ MEMORY_CONFIG -------= ------ > > -----------------\n")); > > DEBUG ((DEBUG_INFO, " Guid : %g\n", &MemConfig- > > >Header.GuidHob.Name)); > > DEBUG ((DEBUG_INFO, " Revision : %d\n", MemConfig- > > >Header.Revision)); > > - ASSERT (MemConfig->Header.Revision =3D=3D MEMORY_CONFIG_REVISION); > > + ASSERT (MemConfig->Header.Revision >=3D MEMORY_CONFIG_REVISION); > > DEBUG ((DEBUG_INFO, " Size : 0x%x\n", MemConfig- > > >Header.GuidHob.Header.HobLength)); > > DEBUG ((DEBUG_INFO, " HobBufferSize : 0x%x\n", MemConfig- > > >HobBufferSize)); > > DEBUG ((DEBUG_INFO, " EccSupport : 0x%x\n", MemConfig- > > >EccSupport)); > > @@ -296,17 +296,17 @@ SaPrintPolicyPpi ( > > > > DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Pri= nt BEGIN - > > ----------------\n")); > > DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPpi- > > >TableHeader.Header.Revision)); > > - ASSERT (SiPolicyPpi->TableHeader.Header.Revision =3D=3D > > SI_POLICY_REVISION); > > + ASSERT (SiPolicyPpi->TableHeader.Header.Revision >=3D > > + SI_POLICY_REVISION); > > DEBUG ((DEBUG_INFO, "------------------------ GRAPHICS_PEI_CONFIG -= ------ > > ----------\n")); > > DEBUG ((DEBUG_INFO, " Revision : %d\n", GtConfig->Header.Revision))= ; > > - ASSERT (GtConfig->Header.Revision =3D=3D > > GRAPHICS_PEI_CONFIG_REVISION); > > + ASSERT (GtConfig->Header.Revision >=3D > > GRAPHICS_PEI_CONFIG_REVISION); > > DEBUG ((DEBUG_INFO, " PeiGraphicsPeimInit : 0x%x\n", GtConfig- > > >PeiGraphicsPeimInit)); > > DEBUG ((DEBUG_INFO, " LogoPtr : 0x%x\n", GtConfig->LogoPtr)); > > DEBUG ((DEBUG_INFO, " LogoSize : 0x%x\n", GtConfig->LogoSize)); > > DEBUG ((DEBUG_INFO, " GraphicsConfigPtr : 0x%x\n", GtConfig- > > >GraphicsConfigPtr)); > > DEBUG ((DEBUG_INFO, "------------------------ VTD_CONFIG ----------= ------- > > \n")); > > DEBUG ((DEBUG_INFO, " Revision : %d\n", Vtd->Header.Revision)); > > - ASSERT (Vtd->Header.Revision =3D=3D VTD_CONFIG_REVISION); > > + ASSERT (Vtd->Header.Revision >=3D VTD_CONFIG_REVISION); > > DEBUG ((DEBUG_INFO, " VtdDisable : 0x%x\n", Vtd->VtdDisable)); > > DEBUG ((DEBUG_INFO, " X2ApicOptOut : 0x%x\n", Vtd->X2ApicOptOut)); > > DEBUG ((DEBUG_INFO, " VtdBaseAddress[%d] :", > > SA_VTD_ENGINE_NUMBER)); diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > > b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > > index 2dc7be45d2..aa88e761b8 100644 > > --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h > > @@ -1,7 +1,7 @@ > > /** @file > > This file declares various data structures used in CPU reference co= de. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -24,6 +24,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #define CPU_CAUSE_BY_ASSOCIATION 0x0100 > > #define CPU_CAUSE_UNSPECIFIED 0x8000 > > > > +#define MAX_MICROCODE_PATCH_SIZE 0x20000 > > + > > typedef UINT32 CPU_STATE_CHANGE_CAUSE; > > > > /// > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuP= olicy > > Library.h > > b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuP= olicy > > Library.h > > index d2a475591d..23321d6432 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuP= olicy > > Library.h > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/Pei= Cp > > +++ uPolicyLibrary.h > > @@ -1,7 +1,7 @@ > > /** @file > > Header file for the PeiCpuPolicyLib library. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -24,6 +24,4 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #inclu= de > > #include > > > > -#define MAX_MICROCODE_PATCH_SIZE 0x20000 > > - > > #endif // _PEI_CPU_POLICY_LIBRARY_H_ > > diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicy= Lib.h > > b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > > index 7bd26863b5..2c0387f678 100644 > > --- a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h > > @@ -1,7 +1,7 @@ > > /** @file > > Prototype of the SiPolicyLib library. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -65,8 +65,6 @@ SiCreateConfigBlocks ( > > > > /** > > SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. > > - While installed, RC assumes the Policy is ready and finalized. So p= lease > > update and override > > - any setting before calling this function. > > > > @param[in] SiPreMemPolicyPpi The pointer to Silicon PREMEM Policy= PPI > > instance > > > > @@ -80,10 +78,22 @@ SiPreMemInstallPolicyPpi ( > > ); > > > > /** > > - SiInstallPolicyPpi installs SiPolicyPpi. > > + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. > > While installed, RC assumes the Policy is ready and finalized. So p= lease > > update and override > > any setting before calling this function. > > > > + @retval EFI_SUCCESS The policy is installed. > > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buf= fer > > +**/ > > +EFI_STATUS > > +EFIAPI > > +SiPreMemInstallPolicyReadyPpi ( > > + VOID > > + ); > > + > > +/** > > + SiInstallPolicyPpi installs SiPolicyPpi. > > + > > @param[in] SiPolicyPpi The pointer to Silicon Policy PPI in= stance > > > > @retval EFI_SUCCESS The policy is installed. > > @@ -96,6 +106,20 @@ SiInstallPolicyPpi ( > > ); > > > > /** > > + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. > > + While installed, RC assumes the Policy is ready and finalized. So > > + please update and override any setting before calling this function= . > > + > > + @retval EFI_SUCCESS The policy is installed. > > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buf= fer > > +**/ > > +EFI_STATUS > > +EFIAPI > > +SiInstallPolicyReadyPpi ( > > + VOID > > + ); > > + > > +/** > > Print out all silicon policy information. > > > > @param[in] SiPolicyPpi The pointer to Silicon Policy PPI in= stance > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolic= yIni > > t.h > > b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolic= yIni > > t.h > > new file mode 100644 > > index 0000000000..b8a526b9b7 > > --- /dev/null > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultP= ol > > +++ icyInit.h > > @@ -0,0 +1,36 @@ > > +/** @file > > + This file defines the PPI function for installing PreMem silicon > > +policy > > + PPI with default settings. > > + > > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> > +SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ > > +#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ > > + > > +// > > +// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI. > > +// > > +typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI > > +PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI; > > + > > +/** > > + Initialize and install default silicon policy PPI **/ typedef > > +EFI_STATUS (EFIAPI *PEI_PREMEM_POLICY_INIT) ( > > + VOID > > + ); > > + > > +/// > > +/// This PPI provides function to install default silicon policy /// > > +struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI { > > + PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; > > +}; > > + > > +extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid; > > + > > +#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_ > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.= h > > b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyInit.= h > > new file mode 100644 > > index 0000000000..d620cf29d4 > > --- /dev/null > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicyI= ni > > +++ t.h > > @@ -0,0 +1,36 @@ > > +/** @file > > + This file defines the PPI function for installing PostMem silicon > > +policy > > + PPI with default settings. > > + > > +Copyright (c) 2019, Intel Corporation. All rights reserved.
> > +SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ > > +#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ > > + > > +// > > +// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI. > > +// > > +typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI > > +PEI_SI_DEFAULT_POLICY_INIT_PPI; > > + > > +/** > > + Initialize and install default silicon policy PPI **/ typedef > > +EFI_STATUS (EFIAPI *PEI_POLICY_INIT) ( > > + VOID > > + ); > > + > > +/// > > +/// This PPI provides function to install default silicon policy /// > > +struct _PEI_SI_DEFAULT_POLICY_INIT_PPI { > > + PEI_POLICY_INIT PeiPolicyInit; > > +}; > > + > > +extern EFI_GUID gSiDefaultPolicyInitPpiGuid; > > + > > +#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_ > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyL= ib.inf > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyL= ib.inf > > index 1d992cfbbd..47f58d16e9 100644 > > --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPol= icyLib.inf > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPol= ic > > +++ yLib.inf > > @@ -1,7 +1,7 @@ > > ## @file > > # Component description file for the PeiSiPolicyLib library. > > # > > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > > +reserved.
> > # > > # SPDX-License-Identifier: BSD-2-Clause-Patent # > > @@ -49,8 +49,10 @@ gSiConfigGuid ## CONSUMES > > > > > > [Ppis] > > -gSiPolicyPpiGuid ## PRODUCES > > -gSiPreMemPolicyPpiGuid ## PRODUCES > > +gSiPolicyPpiGuid ## PRODUCES > > +gSiPreMemPolicyPpiGuid ## PRODUCES > > +gSiPreMemPolicyReadyPpiGuid ## PRODUCES > > +gSiPolicyReadyPpiGuid ## PRODUCES > > > > [Pcd] > > gSiPkgTokenSpaceGuid.PcdSiCsmEnable ## CONSUMES diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/Pei= PolicyInit > > .h > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/Pei= PolicyInit > > .h > > index c38294cfbe..f2fecee8c6 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/Pei= PolicyInit > > .h > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib= /P > > +++ eiPolicyInit.h > > @@ -1,7 +1,7 @@ > > /** @file > > Header file for the PolicyInitPei PEIM. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -12,6 +12,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #inclu= de > > #include #include > > > > +#include > > +#include > > > > #include "PeiSiPolicyInit.h" > > > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/Pei= PostMe > > mSiliconPolicyInitLib.inf > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/Pei= PostMe > > mSiliconPolicyInitLib.inf > > new file mode 100644 > > index 0000000000..83c909e681 > > --- /dev/null > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib= /P > > +++ eiPostMemSiliconPolicyInitLib.inf > > @@ -0,0 +1,75 @@ > > +## @file > > +# Library functions for Policy Initialization Library. > > +# > > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
# # > > +SPDX-License-Identifier: BSD-2-Clause-Patent # ## > > + > > +######################################################### > > ############## > > +######### > > +# > > +# Defines Section - statements that will be processed to create a Mak= efile. > > +# > > +######################################################### > > ############## > > +######### > > +[Defines] > > + INF_VERSION =3D 0x00010005 > > + BASE_NAME =3D PeiPostMemSiliconPolicyInitLib > > + FILE_GUID =3D FA0795E2-BCB3-4627-9FB3-A3255486= 58B4 > > + MODULE_TYPE =3D BASE > > + VERSION_STRING =3D 1.0 > > + LIBRARY_CLASS =3D SiliconPolicyInitLib > > + > > +# > > +# The following information is for reference only and not required by= the > > build tools. > > +# > > +# VALID_ARCHITECTURES =3D IA32 > > +# > > + > > +######################################################### > > ############## > > +######### > > +# > > +# Sources Section - list of files that are required for the build to = succeed. > > +# > > +######################################################### > > ############## > > +######### > > + > > +[Sources] > > + PeiPolicyInit.c > > + PeiPolicyInit.h > > + > > +######################################################### > > ############## > > +######### > > +# > > +# Package Dependency Section - list of Package files that are require= d for > > +# this module. > > +# > > +######################################################### > > ############## > > +######### > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + MdeModulePkg/MdeModulePkg.dec > > + KabylakeSiliconPkg/SiPkg.dec > > + UefiCpuPkg/UefiCpuPkg.dec > > + > > +[LibraryClasses] > > + SiPolicyLib > > + DebugLib > > + PeiServicesLib > > + > > +[Ppis] > > + gSiDefaultPolicyInitPpiGuid ## CONSUMES > > + > > +[Pcd] > > + # > > + # Below PCD may not be consumed by this library but still adding th= em > > +here > > + # to make sure all of them can be built into PcdDataBase. > > + # Those PCD will be consumed by FSP in dispatch mode as DynamicEx t= ype. > > + # > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber > > + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress > > + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode > > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate > > + > > +[Depex] > > + gSiDefaultPolicyInitPpiGuid > > diff --git > > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSi= liconPol > > icyInitLib.inf > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/Pei= PreMem > > SiliconPolicyInitLib.inf > > similarity index 83% > > rename from > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSi= liconPolic > > yInitLib.inf > > rename to > > > Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPreM= emSili > > conPolicyInitLib.inf > > index 7982a5d87f..782e04a476 100644 > > --- > > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiSi= liconPol > > icyInitLib.inf > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib= /P > > +++ eiPreMemSiliconPolicyInitLib.inf > > @@ -1,7 +1,7 @@ > > ### @file > > # Library functions for Policy Initialization Library. > > # > > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > > +reserved.
> > # > > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -14,7 +14,7 @@ > > ########################################################## > > ###################### > > [Defines] > > INF_VERSION =3D 0x00010005 > > - BASE_NAME =3D PeiSiliconPolicyInitLib > > + BASE_NAME =3D PeiPreMemSiliconPolicyInitLib > > FILE_GUID =3D 80920B16-7778-4793-878E-4555F68B= DC69 > > MODULE_TYPE =3D BASE > > VERSION_STRING =3D 1.0 > > @@ -34,7 +34,6 @@ > > > > [Sources] > > PeiPolicyInitPreMem.c > > - PeiPolicyInit.c > > PeiPolicyInit.h > > > > > > ########################################################## > > ###################### > > @@ -53,3 +52,9 @@ > > SiPolicyLib > > DebugLib > > PeiServicesLib > > + > > +[Ppis] > > + gSiPreMemDefaultPolicyInitPpiGuid ## CONSUMES > > + > > +[Depex] > > + gSiPreMemDefaultPolicyInitPpiGuid > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/= PeiSilico > > nPolicyInitLibFsp.inf > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/= PeiSilico > > nPolicyInitLibFsp.inf > > index 9ffb84fa1e..c11680656d 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/= PeiSilico > > nPolicyInitLibFsp.inf > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib= Fs > > +++ p/PeiSiliconPolicyInitLibFsp.inf > > @@ -1,7 +1,7 @@ > > ### @file > > # Library functions for Fsp Policy Initialization Library. > > # > > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > > +reserved.
> > # > > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -72,6 +72,7 @@ > > MemoryAllocationLib > > DebugPrintErrorLevelLib > > FspWrapperApiLib > > + SiPolicyLib > > > > [Pcd] > > gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES > > @@ -84,7 +85,7 @@ > > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## > CONSUMES > > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## > > CONSUMES > > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## > CONSUMES > > - > > + > > [Ppis] > > gSiPolicyPpiGuid ## CONSUMES > > gSiPreMemPolicyPpiGuid ## CONSUMES > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/= PeiSilico > > nPolicyInitLibFspAml.inf > > b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/= PeiSilico > > nPolicyInitLibFspAml.inf > > index aebd3583bc..1ace9aeb52 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/= PeiSilico > > nPolicyInitLibFspAml.inf > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib= Fs > > +++ p/PeiSiliconPolicyInitLibFspAml.inf > > @@ -72,6 +72,7 @@ > > MemoryAllocationLib > > DebugPrintErrorLevelLib > > FspWrapperApiLib > > + SiPolicyLib > > > > [Pcd] > > gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES > > diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > > b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > > index a613079dd4..e9d3e5f918 100644 > > --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > > +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec > > @@ -347,6 +347,10 @@ gPeiTpmInitializationDonePpiGuid =3D {0xa030d115, > > 0x54dd, 0x447b, { 0x90, 0x64, 0x ## gSiPolicyPpiGuid =3D {0xaebffa= 01, > 0x7edc, > > 0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}} > > gSiPreMemPolicyPpiGuid =3D {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0= x97, > > 0xc1, 0x89, 0xd0, 0xab, 0x8d}} > > +gSiPolicyReadyPpiGuid =3D {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0= xee, 0xa5, > > 0x82, 0x7c, 0xe3, 0x17, 0x79}} > > +gSiPreMemPolicyReadyPpiGuid =3D {0x85270bef, 0x6984, 0x4375, {0xa6, 0= xea, > > +0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}} gSiPreMemDefaultPolicyInitPpiGui= d > > +=3D {0xfec36242, 0xf8d8, 0x4b43, {0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63= , > > +0x8d, 0xdc}} gSiDefaultPolicyInitPpiGuid =3D {0xf69abf86, 0x4048, 0x4= 4ef, > > +{ 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}} > > ## > > ## SystemAgent > > ## > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Gra= phi > > csPeiConfig.h > > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Gra= phi > > csPeiConfig.h > > index 4063f800e8..b835155c68 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/Gra= phi > > csPeiConfig.h > > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock= /G > > +++ raphicsPeiConfig.h > > @@ -1,7 +1,7 @@ > > /** @file > > Policy definition for Internal Graphics Config Block (PostMem) > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved. > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -19,8 +19,20 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ > > typedef struct { > > CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Co= nfig > Block > > Header > > + UINT32 RenderStandby : 1; ///< Offset > 28:0 :(Test) This > > field is used to enable or disable RC6 (Render Standby): 0=3DFALSE, > > 1=3DTRUE > > + UINT32 PmSupport : 1; ///< Offset > 28:1 :(Test) IGD > > PM Support TRUE/FALSE: 0=3DFALSE, 1=3DTRUE > > + UINT32 PavpEnable : 1; ///< Offset 28:2 :I= GD PAVP > > TRUE/FALSE: 0=3DFALSE, 1=3DTRUE > > + /** > > + Offset 28:3 > > + CdClock Frequency select\n > > + 0 =3D 337.5 Mhz, 1 =3D 450 Mhz,\n > > + 2 =3D 540 Mhz, 3 =3D 675 Mhz,\n > > + **/ > > + UINT32 CdClock : 3; > > UINT32 PeiGraphicsPeimInit: 1; ///< Offset 28:6 :T= his policy is > used > > to enable/disable Intel Gfx PEIM.0- Disable, 1- Enable > > - UINT32 RsvdBits0 : 31; ///< Offser 28:16 := Reserved for > future > > use > > + UINT32 CdynmaxClampEnable : 1; ///< Offset 28:7 : = This > policy is > > used to enable/disable CDynmax Clamping Feature (CCF) 1- Enable= , > > 0- Disable > > + UINT32 GtFreqMax : 8; ///< Offset 28:8 : > (Test) Max > > GT frequency limited by user in multiples of 50MHz: Default value whic= h > > indicates normal frequency is 0xFF > > + UINT32 RsvdBits0 : 16; ///< Offser 28:16 := Reserved for > future > > use > > VOID* LogoPtr; ///< Offset 32 Addr= ess of Logo > to be > > displayed in PEI > > UINT32 LogoSize; ///< Offset 36 Logo= Size > > VOID* GraphicsConfigPtr; ///< Offset 40 Addr= ess of the > > Graphics Configuration Table > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/= PeiS > > aPolicyLib.inf > > b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/= PeiS > > aPolicyLib.inf > > index 8fae4cee61..c7454bd4a5 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/= PeiS > > aPolicyLib.inf > > +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicy= Li > > +++ b/PeiSaPolicyLib.inf > > @@ -1,7 +1,7 @@ > > ## @file > > # Component description file for the PeiSaPolicy library. > > # > > -# Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +# Copyright (c) 2017 - 2019, Intel Corporation. All rights > > +reserved.
> > # > > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -28,6 +28,7 @@ > > CpuMailboxLib SiConfigBlockLib RngLib SmbusLib > > +PchCycleDecodingLib > > > > [Packages] > > MdePkg/MdePkg.dec > > -- > > 2.13.3.windows.1 > > > > > >=20