From: "Chiu, Chasel" <chasel.chiu@intel.com>
To: "coeur@gmx.fr" <coeur@gmx.fr>,
"devel@edk2.groups.io" <devel@edk2.groups.io>,
"Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>,
"Zeng, Star" <star.zeng@intel.com>
Subject: Re: [PATCH] IntelFsp2Pkg: Fix various typos
Date: Sun, 7 Jul 2019 23:59:45 +0000 [thread overview]
Message-ID: <3C3EFB470A303B4AB093197B6777CCEC50422022@PGSMSX111.gar.corp.intel.com> (raw)
In-Reply-To: <20190705141705.82437-1-coeur@gmx.fr>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Thanks!!
> -----Original Message-----
> From: Antoine Cœur [mailto:coeur@gmx.fr]
> Sent: Friday, July 5, 2019 10:17 PM
> To: devel@edk2.groups.io; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>; Chiu,
> Chasel <chasel.chiu@intel.com>
> Cc: Antoine Cœur <coeur@gmx.fr>
> Subject: [PATCH] IntelFsp2Pkg: Fix various typos
>
> Fix various typos in IntelFsp2Pkg.
> ---
> .../FspSecCore/Ia32/FspApiEntryM.nasm | 4 +--
> .../FspSecCore/Ia32/InitializeFpu.nasm | 2 +-
> .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 2 +-
> IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 2 +-
> IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +-
> IntelFsp2Pkg/FspSecCore/SecMain.c | 2 +-
> .../FspSecCore/Vtf0/Ia16/ResetVec.asm16 | 2 +-
> IntelFsp2Pkg/Include/FspEas/FspApi.h | 6 ++--
> .../Include/Library/FspSecPlatformLib.h | 2 +-
> IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c | 10 +++---
> .../BaseFspDebugLibSerialPort/DebugLib.c | 34 +++++++++----------
> .../BaseFspSwitchStackLib/Ia32/Stack.nasm | 2 +-
> .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +-
> .../PlatformSecLibNull.c | 2 +-
> IntelFsp2Pkg/Tools/GenCfgOpt.py | 2 +-
> IntelFsp2Pkg/Tools/PatchFv.py | 2 +-
> .../Tools/UserManuals/GenCfgOptUserManual.md | 2 +-
> .../Tools/UserManuals/PatchFvUserManual.md | 2 +-
> 18 files changed, 41 insertions(+), 41 deletions(-)
>
> diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
> b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
> index f14c18c7b9..e7261b41cd 100644
> --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
> @@ -194,9 +194,9 @@ StackSetupDone:
>
> ;
> ; Pass BFV into the PEI Core
> - ; It uses relative address to calucate the actual boot FV base
> + ; It uses relative address to calculate the actual boot FV base
> ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase
> and
> - ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
> + ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs,
> ; they are different. The code below can handle both cases.
> ;
> call ASM_PFX(AsmGetFspBaseAddress)
> diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
> b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
> index e1886ea11b..c45520c6c1 100644
> --- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
> @@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits):
> fldcw [ASM_PFX(mFpuControlWord)]
>
> ;
> - ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
> + ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
> ; whether the processor supports SSE instruction.
> ;
> mov eax, 1
> diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
> b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
> index b257deb76c..09cb813497 100644
> --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
> +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
> @@ -150,7 +150,7 @@ NextAddress:
> fldcw [FpuControlWord]
>
> ;
> - ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
> + ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to
> + test
> ; whether the processor supports SSE instruction.
> ;
> mov eax, 1
> diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
> b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
> index d72212ed45..f183d0d10b 100644
> --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
> +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
> @@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack):
> mov esp, eax ; From now, esp is pointed to permanent
> memory
>
> ;
> - ; Fixup the ebp point to permenent memory
> + ; Fixup the ebp point to permanent memory
> ;
> mov eax, ebp
> sub eax, ebx
> diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c
> b/IntelFsp2Pkg/FspSecCore/SecFsp.c
> index 6497c88ebe..a939b7e836 100644
> --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
> +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
> @@ -169,7 +169,7 @@ FspGlobalDataInit (
> SerialPortInitialize ();
>
> //
> - // Ensure the golbal data pointer is valid
> + // Ensure the global data pointer is valid
> //
> ASSERT (GetFspGlobalDataPointer () == PeiFspData);
>
> diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c
> b/IntelFsp2Pkg/FspSecCore/SecMain.c
> index cd3ab46ce2..a63d1336e4 100644
> --- a/IntelFsp2Pkg/FspSecCore/SecMain.c
> +++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
> @@ -110,7 +110,7 @@ SecStartup (
> // |-------------------|---->
> // | |
> // | |
> - // | Heap | PeiTemporayRamSize
> + // | Heap | PeiTemporaryRamSize
> // | |
> // | |
> // |-------------------|----> TempRamBase diff --git
> a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
> b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
> index f25de0206a..e16d692a76 100644
> --- a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
> +++ b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
> @@ -61,7 +61,7 @@ ApStartup:
> ;
> ; Jmp Rel16 instruction
> ; Use machine code directly in case of the assembler optimization
> - ; SEC entry point relatvie address will be fixed up by some build tool.
> + ; SEC entry point relative address will be fixed up by some build tool.
> ;
> ; Typically, SEC entry point is the function _ModuleEntryPoint() defined in
> ; SecEntry.asm
> diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h
> b/IntelFsp2Pkg/Include/FspEas/FspApi.h
> index 1d38e639e6..dea99afc64 100644
> --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h
> +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h
> @@ -211,12 +211,12 @@ EFI_STATUS
> each FSP release.
> After FspMemInit completes its execution, it passes the pointer to the HobList
> and
> returns to the boot loader from where it was called. BootLoader is responsible
> to
> - migrate it's stack and data to Memory.
> + migrate its stack and data to Memory.
> FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate
> method to
> complete the silicon initialization and provides bootloader an opportunity to
> get
> control after system memory is available and before the temporary RAM is
> torn down.
>
> - @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data
> sructure.
> + @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data
> structure.
> @param[out] HobListPtr Pointer to receive the address of the HOB
> list.
>
> @retval EFI_SUCCESS FSP execution environment was initialized
> successfully.
> @@ -271,7 +271,7 @@ EFI_STATUS
> @retval EFI_INVALID_PARAMETER Input parameters are invalid.
> @retval EFI_UNSUPPORTED The FSP calling conditions were not
> met.
> @retval EFI_DEVICE_ERROR FSP initialization failed.
> - @retval FSP_STATUS_RESET_REQUIREDx A reset is reuired. These status
> codes will not be returned during S3.
> + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status
> codes will not be returned during S3.
> **/
> typedef
> EFI_STATUS
> diff --git a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h
> b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h
> index 48b04c5a90..bd057ecf1b 100644
> --- a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h
> +++ b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h
> @@ -66,7 +66,7 @@ SecCarInit (
> );
>
> /**
> - This function check the signture of UPD.
> + This function check the signature of UPD.
>
> @param[in] ApiIdx Internal index of the FSP API.
> @param[in] ApiParam Parameter of the FSP API.
> diff --git a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
> b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
> index 927cee13d3..cd404f9463 100644
> --- a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
> +++ b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c
> @@ -52,8 +52,8 @@ IsDefaultType (
> @param[in] BaseAddress Base address.
> @param[in] Size Size.
>
> - @retval Zero Alligned.
> - @retval Non-Zero Not alligned.
> + @retval Zero Aligned.
> + @retval Non-Zero Not aligned.
>
> **/
> UINT32
> @@ -217,7 +217,7 @@ Power2MaxMemory (
> }
>
> //
> - // Compute inital power of 2 size to return
> + // Compute initial power of 2 size to return
> //
> Result = GetPowerOfTwo64(MemoryLength);
>
> @@ -247,8 +247,8 @@ Power2MaxMemory (
> @param[in] BaseAddress Base address.
> @param[in] Size Size.
>
> - @retval Zero Alligned.
> - @retval Non-Zero Not alligned.
> + @retval Zero Aligned.
> + @retval Non-Zero Not aligned.
>
> **/
> UINT32
> diff --git a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
> b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
> index 17688c7fcb..b34905365d 100644
> --- a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
> +++ b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c
> @@ -186,7 +186,7 @@ DebugBPrint (
> }
>
> /**
> - Convert an UINT32 value into HEX string sepcified by Buffer.
> + Convert an UINT32 value into HEX string specified by Buffer.
>
> @param Value The HEX value to convert to string
> @param Buffer The pointer to the target buffer to be filled with HEX string
> @@ -211,8 +211,8 @@ FillHex (
>
> Print a message of the form "ASSERT <FileName>(<LineNumber>):
> <Description>\n"
> to the debug output device. If
> DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
> - PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
> - DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of
> PcdDebugProperyMask is set then
> + PcdDebugPropertyMask is set then CpuBreakpoint() is called.
> + Otherwise, if DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of
> + PcdDebugPropertyMask is set then
> CpuDeadLoop() is called. If neither of these bits are set, then this function
> returns immediately after the message is printed to the debug output device.
> DebugAssert() must actively prevent recursion. If DebugAssert() is called
> while @@ -265,8 +265,8 @@ DebugAssertInternal (
>
> Print a message of the form "ASSERT <FileName>(<LineNumber>):
> <Description>\n"
> to the debug output device. If
> DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
> - PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
> - DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of
> PcdDebugProperyMask is set then
> + PcdDebugPropertyMask is set then CpuBreakpoint() is called.
> + Otherwise, if DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of
> + PcdDebugPropertyMask is set then
> CpuDeadLoop() is called. If neither of these bits are set, then this function
> returns immediately after the message is printed to the debug output device.
> DebugAssert() must actively prevent recursion. If DebugAssert() is called
> while @@ -322,10 +322,10 @@ DebugClearMemory (
> Returns TRUE if ASSERT() macros are enabled.
>
> This function returns TRUE if the
> DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
> - PcdDebugProperyMask is set. Otherwise FALSE is returned.
> + PcdDebugPropertyMask is set. Otherwise FALSE is returned.
>
> - @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
> PcdDebugProperyMask is set.
> - @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
> PcdDebugProperyMask is clear.
> + @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
> PcdDebugPropertyMask is set.
> + @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
> PcdDebugPropertyMask is clear.
>
> **/
> BOOLEAN
> @@ -342,10 +342,10 @@ DebugAssertEnabled (
> Returns TRUE if DEBUG() macros are enabled.
>
> This function returns TRUE if the
> DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
> - PcdDebugProperyMask is set. Otherwise FALSE is returned.
> + PcdDebugPropertyMask is set. Otherwise FALSE is returned.
>
> - @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
> PcdDebugProperyMask is set.
> - @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
> PcdDebugProperyMask is clear.
> + @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
> PcdDebugPropertyMask is set.
> + @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
> PcdDebugPropertyMask is clear.
>
> **/
> BOOLEAN
> @@ -361,10 +361,10 @@ DebugPrintEnabled (
> Returns TRUE if DEBUG_CODE() macros are enabled.
>
> This function returns TRUE if the
> DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
> - PcdDebugProperyMask is set. Otherwise FALSE is returned.
> + PcdDebugPropertyMask is set. Otherwise FALSE is returned.
>
> - @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
> PcdDebugProperyMask is set.
> - @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
> PcdDebugProperyMask is clear.
> + @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
> PcdDebugPropertyMask is set.
> + @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
> PcdDebugPropertyMask is clear.
>
> **/
> BOOLEAN
> @@ -381,10 +381,10 @@ DebugCodeEnabled (
> Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
>
> This function returns TRUE if the
> DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
> - PcdDebugProperyMask is set. Otherwise FALSE is returned.
> + PcdDebugPropertyMask is set. Otherwise FALSE is returned.
>
> - @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
> PcdDebugProperyMask is set.
> - @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
> PcdDebugProperyMask is clear.
> + @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
> PcdDebugPropertyMask is set.
> + @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
> PcdDebugPropertyMask is clear.
>
> **/
> BOOLEAN
> diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm
> b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm
> index 45cc974788..aaa3fc0867 100644
> --- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm
> +++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm
> @@ -5,7 +5,7 @@
> ;
> ; Abstract:
> ;
> -; Switch the stack from temporary memory to permenent memory.
> +; Switch the stack from temporary memory to permanent memory.
> ;
> ;------------------------------------------------------------------------------
>
> diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm
> b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm
> index dc4af7c078..ff919681a8 100644
> --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm
> +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm
> @@ -54,7 +54,7 @@ ASM_PFX(SecPlatformInit):
> ; esp
> ;
> ; Description:
> -; Perform any essential early platform initilaisation
> +; Perform any essential early platform initialisation
> ; Setup a stack
> ;
> ;----------------------------------------------------------------------------
> diff --git
> a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
> b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
> index 50cb3142d2..c445190d8e 100644
> --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
> +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c
> @@ -10,7 +10,7 @@
> #include <Library/FspCommonLib.h>
>
> /**
> - This function check the signture of UPD.
> + This function check the signature of UPD.
>
> @param[in] ApiIdx Internal index of the FSP API.
> @param[in] ApiParam Parameter of the FSP API.
> diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py
> b/IntelFsp2Pkg/Tools/GenCfgOpt.py index c4e1e6239d..a42717caae 100644
> --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
> +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
> @@ -535,7 +535,7 @@ EndList
> Offset = 0
> else:
> if DscLine.startswith('!'):
> - print("ERROR: Unrecoginized directive for
> line '%s'" % DscLine)
> + print("ERROR: Unrecognized
> + directive for line '%s'" % DscLine)
> raise SystemExit
> if not Handle:
> continue
> diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
> index 2173984dea..edb30c816b 100644
> --- a/IntelFsp2Pkg/Tools/PatchFv.py
> +++ b/IntelFsp2Pkg/Tools/PatchFv.py
> @@ -160,7 +160,7 @@ class Symbols:
> #
> def createDicts (self, fvDir, fvNames):
> #
> - # If the fvDir is not a dirctory, then raise an exception
> + # If the fvDir is not a directory, then raise an exception
> #
> if not os.path.isdir(fvDir):
> raise Exception ("'%s' is not a valid directory!" % FvDir) diff --git
> a/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md
> b/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md
> index 938c18416d..0a0f592801 100644
> --- a/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md
> +++ b/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md
> @@ -213,7 +213,7 @@ in the third.
> ```@Bsf NAME:{Variable 1} TYPE:{Combo}```
>
> There is a special **None** type that puts the variable in the **StructDef**
> -region of the BSF, but doesn?t put it in any **Page** section. This makes the
> +region of the BSF, but doesn't put it in any **Page** section. This
> +makes the
> variable visible to BCT, but not to the end user.
>
> ###HELP
> diff --git a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> index becaf96b21..5f1031e729 100644
> --- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> +++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md
> @@ -30,7 +30,7 @@ FSP tree.
>
> The example used contains Windows batch script %VARIABLES%.
>
> -#FvFileBaseNames (Argument 2: 0ptional Part 1)
> +#FvFileBaseNames (Argument 2: Optional Part 1)
> The firmware volume file base names (**_FvFileBaseNames_**) are the
> independent Fv?s that are to be patched within the FD. (0 or more in the form
> **FVFILEBASENAME:**) The colon **:** is used for delimiting the single
> --
> 2.20.1 (Apple Git-117)
next prev parent reply other threads:[~2019-07-07 23:59 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-05 14:17 [PATCH] IntelFsp2Pkg: Fix various typos Cœur
2019-07-07 14:58 ` Zeng, Star
2019-07-07 23:59 ` Chiu, Chasel [this message]
2019-07-09 13:44 ` Chiu, Chasel
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