* [PATCH 1/4] MinPlatformPkg: Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 [PATCH 0/4] Auto configure Fsp*BaseAddress PCD Chiu, Chasel
@ 2019-07-29 11:07 ` Chiu, Chasel
2019-07-30 22:18 ` Nate DeSimone
2019-07-31 18:58 ` [edk2-devel] " Sinha, Ankit
2019-07-29 11:07 ` [PATCH 2/4] Platform/Intel: " Chiu, Chasel
` (4 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Chiu, Chasel @ 2019-07-29 11:07 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Nate DeSimone, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
Add python script which will rebase FSP binary without
patching platform DSC for Fsp*BaseAddress PCDs.
Those base address PCD will be updated in FDF basing
on flash map.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py
new file mode 100644
index 0000000000..a8165b08e6
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py
@@ -0,0 +1,96 @@
+## @ RebaseFspBinBaseAddress.py
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+import os
+import sys
+import re
+import subprocess
+
+if len(sys.argv) not in [5,6]:
+ print ("RebaseFspBinBaseAddress.py - Error in number of arguments received")
+ print ("Usage - RebaseFspBinBaseAddress.py <FlashMap file path> <FspBinPkg Folder> <Fsp.fd file name>\
+ <pad_offset for Fsp-S Base Address> <OPTIONAL SplitFspBin.py tool path>")
+ exit(1)
+
+flashMapName = sys.argv[1]
+fspBinPath = sys.argv[2]
+fspBinFile = sys.argv[3]
+fvOffset = int(sys.argv[4], 16)
+fspBinFileRebased = "Fsp_Rebased.fd"
+splitFspBinPath = os.path.join("edk2","IntelFsp2Pkg","Tools","SplitFspBin.py")
+
+if len(sys.argv) == 6:
+ splitFspBinPath = sys.argv[5]
+
+#
+# Make sure argument passed or valid
+#
+if not os.path.exists(flashMapName):
+ print ("WARNING! " + str(flashMapName) + " is not found.")
+ exit(1)
+fspBinFilePath = fspBinPath + os.sep + fspBinFile
+if not os.path.exists(fspBinFilePath):
+ print ("WARNING! " + str(fspBinFilePath) + " is not found.")
+ exit(1)
+if not os.path.exists(splitFspBinPath):
+ print ("WARNING! " + str(splitFspBinPath) + " is not found.")
+ exit(1)
+
+#
+# Get the FSP-S / FSP-M-T FV Base Address from Flash Map
+#
+file = open (flashMapName, "r")
+data = file.read ()
+
+# Get the Flash Base Address
+flashBase = int(data.split("FLASH_BASE")[1].split("=")[1].split()[0], 16)
+
+# Based on Build Target, select the section in the FlashMap file
+flashmap = data
+
+# Get FSP-S & FSP-M & FSP-T offset & calculate the base
+for line in flashmap.split("\n"):
+ if "PcdFlashFvFspSOffset" in line:
+ fspSBaseOffset = int(line.split("=")[1].split()[0], 16)
+ if "PcdFlashFvFspMOffset" in line:
+ fspMBaseOffset = int(line.split("=")[1].split()[0], 16)
+ if "PcdFlashFvFspTOffset" in line:
+ fspTBaseOffset = int(line.split("=")[1].split()[0], 16)
+file.close()
+
+#
+# Get FSP-M Size, in order to calculate the FSP-T Base. Used SplitFspBin.py script
+# to dump the header, and get the ImageSize in FSP-M section
+#
+pythontool = 'python'
+if 'PYTHON_HOME' in os.environ:
+ pythontool = os.environ['PYTHON_HOME'] + os.sep + 'python'
+Process = subprocess.Popen([pythontool, splitFspBinPath, "info","-f",fspBinFilePath], stdout=subprocess.PIPE)
+Output = Process.communicate()[0]
+FsptInfo = Output.rsplit(b"FSP_M", 1);
+for line in FsptInfo[1].split(b"\n"):
+ if b"ImageSize" in line:
+ fspMSize = int(line.split(b"=")[1], 16)
+ break
+
+# Calculate FSP-S/M/T base address, to which re-base has to be done
+fspSBaseAddress = flashBase + fspSBaseOffset + fvOffset
+fspMBaseAddress = flashBase + fspMBaseOffset
+fspTBaseAddress = flashBase + fspTBaseOffset
+
+#
+# Re-base FSP bin file to new address and save it as fspBinFileRebased using SplitFspBin.py
+#
+rebaseArguments = fspBinFilePath + " -c s m t -b " + str(hex(fspSBaseAddress).rstrip("L")) + " " + str(hex(fspMBaseAddress).rstrip("L")) + " " + str(hex(fspTBaseAddress).rstrip("L")) + " -o" + fspBinPath + " -n " + fspBinFileRebased
+os.system(pythontool + " " + splitFspBinPath + " rebase -f" + rebaseArguments)
+
+#
+# Split FSP bin to FSP-S/M/T segments
+#
+splitArguments = fspBinPath + os.sep + fspBinFileRebased + " -o " + fspBinPath + " -n Fsp_Rebased.fd"
+os.system(pythontool + " " + splitFspBinPath + " split -f" + splitArguments)
+
+exit(0)
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/4] MinPlatformPkg: Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 ` [PATCH 1/4] MinPlatformPkg: " Chiu, Chasel
@ 2019-07-30 22:18 ` Nate DeSimone
2019-07-31 18:58 ` [edk2-devel] " Sinha, Ankit
1 sibling, 0 replies; 17+ messages in thread
From: Nate DeSimone @ 2019-07-30 22:18 UTC (permalink / raw)
To: Chiu, Chasel, devel@edk2.groups.io; +Cc: Kubacki, Michael A, Gao, Liming
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: Chiu, Chasel
Sent: Monday, July 29, 2019 4:07 AM
To: devel@edk2.groups.io
Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [PATCH 1/4] MinPlatformPkg: Auto configure Fsp*BaseAddress PCD
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
Add python script which will rebase FSP binary without patching platform DSC for Fsp*BaseAddress PCDs.
Those base address PCD will be updated in FDF basing on flash map.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py
new file mode 100644
index 0000000000..a8165b08e6
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py
@@ -0,0 +1,96 @@
+## @ RebaseFspBinBaseAddress.py
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> #
+SPDX-License-Identifier: BSD-2-Clause-Patent #
+
+import os
+import sys
+import re
+import subprocess
+
+if len(sys.argv) not in [5,6]:
+ print ("RebaseFspBinBaseAddress.py - Error in number of arguments
+received")
+ print ("Usage - RebaseFspBinBaseAddress.py <FlashMap file path>
+<FspBinPkg Folder> <Fsp.fd file name>\
+ <pad_offset for Fsp-S Base Address> <OPTIONAL SplitFspBin.py tool
+path>")
+ exit(1)
+
+flashMapName = sys.argv[1]
+fspBinPath = sys.argv[2]
+fspBinFile = sys.argv[3]
+fvOffset = int(sys.argv[4], 16)
+fspBinFileRebased = "Fsp_Rebased.fd"
+splitFspBinPath = os.path.join("edk2","IntelFsp2Pkg","Tools","SplitFspBin.py")
+
+if len(sys.argv) == 6:
+ splitFspBinPath = sys.argv[5]
+
+#
+# Make sure argument passed or valid
+#
+if not os.path.exists(flashMapName):
+ print ("WARNING! " + str(flashMapName) + " is not found.")
+ exit(1)
+fspBinFilePath = fspBinPath + os.sep + fspBinFile if not
+os.path.exists(fspBinFilePath):
+ print ("WARNING! " + str(fspBinFilePath) + " is not found.")
+ exit(1)
+if not os.path.exists(splitFspBinPath):
+ print ("WARNING! " + str(splitFspBinPath) + " is not found.")
+ exit(1)
+
+#
+# Get the FSP-S / FSP-M-T FV Base Address from Flash Map # file = open
+(flashMapName, "r") data = file.read ()
+
+# Get the Flash Base Address
+flashBase = int(data.split("FLASH_BASE")[1].split("=")[1].split()[0],
+16)
+
+# Based on Build Target, select the section in the FlashMap file
+flashmap = data
+
+# Get FSP-S & FSP-M & FSP-T offset & calculate the base for line in
+flashmap.split("\n"):
+ if "PcdFlashFvFspSOffset" in line:
+ fspSBaseOffset = int(line.split("=")[1].split()[0], 16)
+ if "PcdFlashFvFspMOffset" in line:
+ fspMBaseOffset = int(line.split("=")[1].split()[0], 16)
+ if "PcdFlashFvFspTOffset" in line:
+ fspTBaseOffset = int(line.split("=")[1].split()[0], 16)
+file.close()
+
+#
+# Get FSP-M Size, in order to calculate the FSP-T Base. Used
+SplitFspBin.py script # to dump the header, and get the ImageSize in
+FSP-M section # pythontool = 'python'
+if 'PYTHON_HOME' in os.environ:
+ pythontool = os.environ['PYTHON_HOME'] + os.sep + 'python'
+Process = subprocess.Popen([pythontool, splitFspBinPath,
+"info","-f",fspBinFilePath], stdout=subprocess.PIPE) Output =
+Process.communicate()[0] FsptInfo = Output.rsplit(b"FSP_M", 1); for
+line in FsptInfo[1].split(b"\n"):
+ if b"ImageSize" in line:
+ fspMSize = int(line.split(b"=")[1], 16)
+ break
+
+# Calculate FSP-S/M/T base address, to which re-base has to be done
+fspSBaseAddress = flashBase + fspSBaseOffset + fvOffset fspMBaseAddress
+= flashBase + fspMBaseOffset fspTBaseAddress = flashBase +
+fspTBaseOffset
+
+#
+# Re-base FSP bin file to new address and save it as fspBinFileRebased
+using SplitFspBin.py # rebaseArguments = fspBinFilePath + " -c s m t -b
+" + str(hex(fspSBaseAddress).rstrip("L")) + " " +
+str(hex(fspMBaseAddress).rstrip("L")) + " " +
+str(hex(fspTBaseAddress).rstrip("L")) + " -o" + fspBinPath + " -n " +
+fspBinFileRebased os.system(pythontool + " " + splitFspBinPath + "
+rebase -f" + rebaseArguments)
+
+#
+# Split FSP bin to FSP-S/M/T segments
+#
+splitArguments = fspBinPath + os.sep + fspBinFileRebased + " -o " + fspBinPath + " -n Fsp_Rebased.fd"
+os.system(pythontool + " " + splitFspBinPath + " split -f" +
+splitArguments)
+
+exit(0)
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [edk2-devel] [PATCH 1/4] MinPlatformPkg: Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 ` [PATCH 1/4] MinPlatformPkg: " Chiu, Chasel
2019-07-30 22:18 ` Nate DeSimone
@ 2019-07-31 18:58 ` Sinha, Ankit
1 sibling, 0 replies; 17+ messages in thread
From: Sinha, Ankit @ 2019-07-31 18:58 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel
Cc: Kubacki, Michael A, Desimone, Nathaniel L, Gao, Liming
Reviewed-by: Ankit Sinha <ankit.sinha@intel.com>
-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Chiu, Chasel
Sent: Monday, July 29, 2019 4:07 AM
To: devel@edk2.groups.io
Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [edk2-devel] [PATCH 1/4] MinPlatformPkg: Auto configure Fsp*BaseAddress PCD
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
Add python script which will rebase FSP binary without patching platform DSC for Fsp*BaseAddress PCDs.
Those base address PCD will be updated in FDF basing on flash map.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py
new file mode 100644
index 0000000000..a8165b08e6
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py
@@ -0,0 +1,96 @@
+## @ RebaseFspBinBaseAddress.py
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> #
+SPDX-License-Identifier: BSD-2-Clause-Patent #
+
+import os
+import sys
+import re
+import subprocess
+
+if len(sys.argv) not in [5,6]:
+ print ("RebaseFspBinBaseAddress.py - Error in number of arguments
+received")
+ print ("Usage - RebaseFspBinBaseAddress.py <FlashMap file path>
+<FspBinPkg Folder> <Fsp.fd file name>\
+ <pad_offset for Fsp-S Base Address> <OPTIONAL SplitFspBin.py tool
+path>")
+ exit(1)
+
+flashMapName = sys.argv[1]
+fspBinPath = sys.argv[2]
+fspBinFile = sys.argv[3]
+fvOffset = int(sys.argv[4], 16)
+fspBinFileRebased = "Fsp_Rebased.fd"
+splitFspBinPath = os.path.join("edk2","IntelFsp2Pkg","Tools","SplitFspBin.py")
+
+if len(sys.argv) == 6:
+ splitFspBinPath = sys.argv[5]
+
+#
+# Make sure argument passed or valid
+#
+if not os.path.exists(flashMapName):
+ print ("WARNING! " + str(flashMapName) + " is not found.")
+ exit(1)
+fspBinFilePath = fspBinPath + os.sep + fspBinFile if not
+os.path.exists(fspBinFilePath):
+ print ("WARNING! " + str(fspBinFilePath) + " is not found.")
+ exit(1)
+if not os.path.exists(splitFspBinPath):
+ print ("WARNING! " + str(splitFspBinPath) + " is not found.")
+ exit(1)
+
+#
+# Get the FSP-S / FSP-M-T FV Base Address from Flash Map # file = open
+(flashMapName, "r") data = file.read ()
+
+# Get the Flash Base Address
+flashBase = int(data.split("FLASH_BASE")[1].split("=")[1].split()[0],
+16)
+
+# Based on Build Target, select the section in the FlashMap file
+flashmap = data
+
+# Get FSP-S & FSP-M & FSP-T offset & calculate the base for line in
+flashmap.split("\n"):
+ if "PcdFlashFvFspSOffset" in line:
+ fspSBaseOffset = int(line.split("=")[1].split()[0], 16)
+ if "PcdFlashFvFspMOffset" in line:
+ fspMBaseOffset = int(line.split("=")[1].split()[0], 16)
+ if "PcdFlashFvFspTOffset" in line:
+ fspTBaseOffset = int(line.split("=")[1].split()[0], 16)
+file.close()
+
+#
+# Get FSP-M Size, in order to calculate the FSP-T Base. Used
+SplitFspBin.py script # to dump the header, and get the ImageSize in
+FSP-M section # pythontool = 'python'
+if 'PYTHON_HOME' in os.environ:
+ pythontool = os.environ['PYTHON_HOME'] + os.sep + 'python'
+Process = subprocess.Popen([pythontool, splitFspBinPath,
+"info","-f",fspBinFilePath], stdout=subprocess.PIPE) Output =
+Process.communicate()[0] FsptInfo = Output.rsplit(b"FSP_M", 1); for
+line in FsptInfo[1].split(b"\n"):
+ if b"ImageSize" in line:
+ fspMSize = int(line.split(b"=")[1], 16)
+ break
+
+# Calculate FSP-S/M/T base address, to which re-base has to be done
+fspSBaseAddress = flashBase + fspSBaseOffset + fvOffset fspMBaseAddress
+= flashBase + fspMBaseOffset fspTBaseAddress = flashBase +
+fspTBaseOffset
+
+#
+# Re-base FSP bin file to new address and save it as fspBinFileRebased
+using SplitFspBin.py # rebaseArguments = fspBinFilePath + " -c s m t -b
+" + str(hex(fspSBaseAddress).rstrip("L")) + " " +
+str(hex(fspMBaseAddress).rstrip("L")) + " " +
+str(hex(fspTBaseAddress).rstrip("L")) + " -o" + fspBinPath + " -n " +
+fspBinFileRebased os.system(pythontool + " " + splitFspBinPath + "
+rebase -f" + rebaseArguments)
+
+#
+# Split FSP bin to FSP-S/M/T segments
+#
+splitArguments = fspBinPath + os.sep + fspBinFileRebased + " -o " + fspBinPath + " -n Fsp_Rebased.fd"
+os.system(pythontool + " " + splitFspBinPath + " split -f" +
+splitArguments)
+
+exit(0)
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/4] Platform/Intel: Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 [PATCH 0/4] Auto configure Fsp*BaseAddress PCD Chiu, Chasel
2019-07-29 11:07 ` [PATCH 1/4] MinPlatformPkg: " Chiu, Chasel
@ 2019-07-29 11:07 ` Chiu, Chasel
2019-07-30 22:18 ` [edk2-devel] " Nate DeSimone
2019-07-31 18:59 ` Sinha, Ankit
2019-07-29 11:07 ` [PATCH 3/4] KabylakeOpenBoardPkg: " Chiu, Chasel
` (3 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Chiu, Chasel @ 2019-07-29 11:07 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Nate DeSimone, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
Consume RebaseFspBinBaseAddress.py which will only rebase
FSP binary without patching platform DSC.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/build_bios.py | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py
index c01b953d16..37b5ee2f5b 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -303,21 +303,18 @@ def build(config):
os.path.join(config['WORKSPACE_PLATFORM'],
config['PLATFORM_PACKAGE'],
'Tools', 'Fsp',
- 'RebaseAndPatchFspBinBaseAddress.py'),
+ 'RebaseFspBinBaseAddress.py'),
os.path.join(config['WORKSPACE_PLATFORM'],
config['FLASH_MAP_FDF']),
os.path.join(config['WORKSPACE_FSP_BIN'],
config['FSP_BIN_PKG']),
"Fsp.fd",
- os.path.join(config['WORKSPACE_PLATFORM'],
- config['PROJECT'],
- config['BOARD_PKG_PCD_DSC']),
"0x0"]
_, _, _, return_code = execute_script(command, config, shell=False)
if return_code != 0:
- print("ERROR:RebaseAndPatchFspBinBaseAddress failed")
+ print("ERROR:RebaseFspBinBaseAddress failed")
sys.exit(return_code)
# create Fsp_Rebased.fd which is Fsp_Rebased_S.fd +
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [edk2-devel] [PATCH 2/4] Platform/Intel: Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 ` [PATCH 2/4] Platform/Intel: " Chiu, Chasel
@ 2019-07-30 22:18 ` Nate DeSimone
2019-07-31 18:59 ` Sinha, Ankit
1 sibling, 0 replies; 17+ messages in thread
From: Nate DeSimone @ 2019-07-30 22:18 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel; +Cc: Kubacki, Michael A, Gao, Liming
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
Sent: Monday, July 29, 2019 4:07 AM
To: devel@edk2.groups.io
Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [edk2-devel] [PATCH 2/4] Platform/Intel: Auto configure Fsp*BaseAddress PCD
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
Consume RebaseFspBinBaseAddress.py which will only rebase FSP binary without patching platform DSC.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/build_bios.py | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index c01b953d16..37b5ee2f5b 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -303,21 +303,18 @@ def build(config):
os.path.join(config['WORKSPACE_PLATFORM'],
config['PLATFORM_PACKAGE'],
'Tools', 'Fsp',
- 'RebaseAndPatchFspBinBaseAddress.py'),
+ 'RebaseFspBinBaseAddress.py'),
os.path.join(config['WORKSPACE_PLATFORM'],
config['FLASH_MAP_FDF']),
os.path.join(config['WORKSPACE_FSP_BIN'],
config['FSP_BIN_PKG']),
"Fsp.fd",
- os.path.join(config['WORKSPACE_PLATFORM'],
- config['PROJECT'],
- config['BOARD_PKG_PCD_DSC']),
"0x0"]
_, _, _, return_code = execute_script(command, config, shell=False)
if return_code != 0:
- print("ERROR:RebaseAndPatchFspBinBaseAddress failed")
+ print("ERROR:RebaseFspBinBaseAddress failed")
sys.exit(return_code)
# create Fsp_Rebased.fd which is Fsp_Rebased_S.fd +
--
2.13.3.windows.1
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [edk2-devel] [PATCH 2/4] Platform/Intel: Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 ` [PATCH 2/4] Platform/Intel: " Chiu, Chasel
2019-07-30 22:18 ` [edk2-devel] " Nate DeSimone
@ 2019-07-31 18:59 ` Sinha, Ankit
1 sibling, 0 replies; 17+ messages in thread
From: Sinha, Ankit @ 2019-07-31 18:59 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel
Cc: Kubacki, Michael A, Desimone, Nathaniel L, Gao, Liming
Reviewed-by: Ankit Sinha <ankit.sinha@intel.com>
-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Chiu, Chasel
Sent: Monday, July 29, 2019 4:07 AM
To: devel@edk2.groups.io
Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [edk2-devel] [PATCH 2/4] Platform/Intel: Auto configure Fsp*BaseAddress PCD
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
Consume RebaseFspBinBaseAddress.py which will only rebase FSP binary without patching platform DSC.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/build_bios.py | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index c01b953d16..37b5ee2f5b 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -303,21 +303,18 @@ def build(config):
os.path.join(config['WORKSPACE_PLATFORM'],
config['PLATFORM_PACKAGE'],
'Tools', 'Fsp',
- 'RebaseAndPatchFspBinBaseAddress.py'),
+ 'RebaseFspBinBaseAddress.py'),
os.path.join(config['WORKSPACE_PLATFORM'],
config['FLASH_MAP_FDF']),
os.path.join(config['WORKSPACE_FSP_BIN'],
config['FSP_BIN_PKG']),
"Fsp.fd",
- os.path.join(config['WORKSPACE_PLATFORM'],
- config['PROJECT'],
- config['BOARD_PKG_PCD_DSC']),
"0x0"]
_, _, _, return_code = execute_script(command, config, shell=False)
if return_code != 0:
- print("ERROR:RebaseAndPatchFspBinBaseAddress failed")
+ print("ERROR:RebaseFspBinBaseAddress failed")
sys.exit(return_code)
# create Fsp_Rebased.fd which is Fsp_Rebased_S.fd +
--
2.13.3.windows.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/4] KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 [PATCH 0/4] Auto configure Fsp*BaseAddress PCD Chiu, Chasel
2019-07-29 11:07 ` [PATCH 1/4] MinPlatformPkg: " Chiu, Chasel
2019-07-29 11:07 ` [PATCH 2/4] Platform/Intel: " Chiu, Chasel
@ 2019-07-29 11:07 ` Chiu, Chasel
2019-07-30 22:19 ` [edk2-devel] " Nate DeSimone
2019-07-31 18:59 ` Sinha, Ankit
2019-07-29 11:07 ` [PATCH 4/4] ClevoOpenBoardPkg: " Chiu, Chasel
` (2 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Chiu, Chasel @ 2019-07-29 11:07 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Nate DeSimone, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
PcdFsp*BaseAddress now will be updated in FDF basing
on flash map.
DSC will only define types of those PCDs and always
having 0 as default.
Test: interanl platform booted with this patch.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 3 +++
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 12 +++++++++---
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
index abafd8e44d..7267d478ad 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
@@ -53,6 +53,9 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceG
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
################################################################################
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index c22e91af12..55ae9f47ac 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
@@ -144,8 +144,11 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
!endif
- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
# @Prompt Timeout for the BSP to detect all APs for the first time.
@@ -252,7 +255,10 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
!endif
[PcdsDynamicDefault]
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFDA0000
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
# Platform will pre-allocate UPD buffer and pass it to FspWrapper
# Those dummy address will be patched before FspWrapper executing
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [edk2-devel] [PATCH 3/4] KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 ` [PATCH 3/4] KabylakeOpenBoardPkg: " Chiu, Chasel
@ 2019-07-30 22:19 ` Nate DeSimone
2019-07-31 18:59 ` Sinha, Ankit
1 sibling, 0 replies; 17+ messages in thread
From: Nate DeSimone @ 2019-07-30 22:19 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel; +Cc: Kubacki, Michael A, Gao, Liming
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
Sent: Monday, July 29, 2019 4:07 AM
To: devel@edk2.groups.io
Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [edk2-devel] [PATCH 3/4] KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
PcdFsp*BaseAddress now will be updated in FDF basing on flash map.
DSC will only define types of those PCDs and always having 0 as default.
Test: interanl platform booted with this patch.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 3 +++
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 12 +++++++++---
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
index abafd8e44d..7267d478ad 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
@@ -53,6 +53,9 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceG
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
################################################################################
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index c22e91af12..55ae9f47ac 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d
+++ sc
@@ -144,8 +144,11 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
!endif
- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
# @Prompt Timeout for the BSP to detect all APs for the first time.
@@ -252,7 +255,10 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
!endif
[PcdsDynamicDefault]
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFDA0000
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
# Platform will pre-allocate UPD buffer and pass it to FspWrapper
# Those dummy address will be patched before FspWrapper executing
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [edk2-devel] [PATCH 3/4] KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 ` [PATCH 3/4] KabylakeOpenBoardPkg: " Chiu, Chasel
2019-07-30 22:19 ` [edk2-devel] " Nate DeSimone
@ 2019-07-31 18:59 ` Sinha, Ankit
1 sibling, 0 replies; 17+ messages in thread
From: Sinha, Ankit @ 2019-07-31 18:59 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel
Cc: Kubacki, Michael A, Desimone, Nathaniel L, Gao, Liming
Reviewed-by: Ankit Sinha <ankit.sinha@intel.com>
-----Original Message-----
From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Chiu, Chasel
Sent: Monday, July 29, 2019 4:07 AM
To: devel@edk2.groups.io
Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [edk2-devel] [PATCH 3/4] KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
PcdFsp*BaseAddress now will be updated in FDF basing on flash map.
DSC will only define types of those PCDs and always having 0 as default.
Test: interanl platform booted with this patch.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 3 +++
Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 12 +++++++++---
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
index abafd8e44d..7267d478ad 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
@@ -53,6 +53,9 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceG
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
################################################################################
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index c22e91af12..55ae9f47ac 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d
+++ sc
@@ -144,8 +144,11 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
!endif
- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
# @Prompt Timeout for the BSP to detect all APs for the first time.
@@ -252,7 +255,10 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
!endif
[PcdsDynamicDefault]
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFDA0000
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
# Platform will pre-allocate UPD buffer and pass it to FspWrapper
# Those dummy address will be patched before FspWrapper executing
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/4] ClevoOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 [PATCH 0/4] Auto configure Fsp*BaseAddress PCD Chiu, Chasel
` (2 preceding siblings ...)
2019-07-29 11:07 ` [PATCH 3/4] KabylakeOpenBoardPkg: " Chiu, Chasel
@ 2019-07-29 11:07 ` Chiu, Chasel
2019-07-30 22:19 ` [edk2-devel] " Nate DeSimone
2019-07-31 19:00 ` Sinha, Ankit
2019-07-29 13:47 ` [edk2-devel] [PATCH 0/4] " Laszlo Ersek
2019-07-30 3:46 ` Liming Gao
5 siblings, 2 replies; 17+ messages in thread
From: Chiu, Chasel @ 2019-07-29 11:07 UTC (permalink / raw)
To: devel; +Cc: Michael Kubacki, Ankit Sinha, Nate DeSimone, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
PcdFsp*BaseAddress now will be updated in FDF basing
on flash map.
DSC will only define types of those PCDs and always
having 0 as default.
Test: interanl platform booted with this patch.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 3 +++
Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc | 12 +++++++++---
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
index da498ad379..c425e4b280 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
@@ -53,6 +53,9 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceG
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
################################################################################
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
index c6bce19856..83cbd18557 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
@@ -109,8 +109,11 @@
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
!endif
- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
## Specifies max supported number of Logical Processors.
# @Prompt Configure max supported number of Logical Processorss
@@ -201,7 +204,10 @@
!endif
[PcdsDynamicDefault]
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFDA0000
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
# Platform will pre-allocate UPD buffer and pass it to FspWrapper
# Those dummy address will be patched before FspWrapper executing
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [edk2-devel] [PATCH 4/4] ClevoOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 ` [PATCH 4/4] ClevoOpenBoardPkg: " Chiu, Chasel
@ 2019-07-30 22:19 ` Nate DeSimone
2019-07-31 19:00 ` Sinha, Ankit
1 sibling, 0 replies; 17+ messages in thread
From: Nate DeSimone @ 2019-07-30 22:19 UTC (permalink / raw)
To: devel@edk2.groups.io, Chiu, Chasel
Cc: Kubacki, Michael A, Sinha, Ankit, Gao, Liming
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
Sent: Monday, July 29, 2019 4:07 AM
To: devel@edk2.groups.io
Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [edk2-devel] [PATCH 4/4] ClevoOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
PcdFsp*BaseAddress now will be updated in FDF basing on flash map.
DSC will only define types of those PCDs and always having 0 as default.
Test: interanl platform booted with this patch.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 3 +++
Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc | 12 +++++++++---
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
index da498ad379..c425e4b280 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
@@ -53,6 +53,9 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceG
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
################################################################################
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
index c6bce19856..83cbd18557 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
@@ -109,8 +109,11 @@
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
!endif
- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
## Specifies max supported number of Logical Processors.
# @Prompt Configure max supported number of Logical Processorss @@ -201,7 +204,10 @@ !endif
[PcdsDynamicDefault]
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFDA0000
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
# Platform will pre-allocate UPD buffer and pass it to FspWrapper
# Those dummy address will be patched before FspWrapper executing
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 4/4] ClevoOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 ` [PATCH 4/4] ClevoOpenBoardPkg: " Chiu, Chasel
2019-07-30 22:19 ` [edk2-devel] " Nate DeSimone
@ 2019-07-31 19:00 ` Sinha, Ankit
1 sibling, 0 replies; 17+ messages in thread
From: Sinha, Ankit @ 2019-07-31 19:00 UTC (permalink / raw)
To: Chiu, Chasel, devel@edk2.groups.io
Cc: Kubacki, Michael A, Desimone, Nathaniel L, Gao, Liming
Reviewed-by: Ankit Sinha <ankit.sinha@intel.com>
-----Original Message-----
From: Chiu, Chasel
Sent: Monday, July 29, 2019 4:07 AM
To: devel@edk2.groups.io
Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
Subject: [PATCH 4/4] ClevoOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
PcdFsp*BaseAddress now will be updated in FDF basing on flash map.
DSC will only define types of those PCDs and always having 0 as default.
Test: interanl platform booted with this patch.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 3 +++
Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc | 12 +++++++++---
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
index da498ad379..c425e4b280 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
@@ -53,6 +53,9 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceG
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdFlashAreaSize
################################################################################
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
index c6bce19856..83cbd18557 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
@@ -109,8 +109,11 @@
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
!endif
- gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
## Specifies max supported number of Logical Processors.
# @Prompt Configure max supported number of Logical Processorss @@ -201,7 +204,10 @@ !endif
[PcdsDynamicDefault]
- gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFDA0000
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
# Platform will pre-allocate UPD buffer and pass it to FspWrapper
# Those dummy address will be patched before FspWrapper executing
gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF
--
2.13.3.windows.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [edk2-devel] [PATCH 0/4] Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 [PATCH 0/4] Auto configure Fsp*BaseAddress PCD Chiu, Chasel
` (3 preceding siblings ...)
2019-07-29 11:07 ` [PATCH 4/4] ClevoOpenBoardPkg: " Chiu, Chasel
@ 2019-07-29 13:47 ` Laszlo Ersek
2019-07-30 1:07 ` Chiu, Chasel
2019-07-30 3:46 ` Liming Gao
5 siblings, 1 reply; 17+ messages in thread
From: Laszlo Ersek @ 2019-07-29 13:47 UTC (permalink / raw)
To: devel, chasel.chiu
Cc: Michael Kubacki, Ankit Sinha, Nate DeSimone, Liming Gao
On 07/29/19 13:07, Chiu, Chasel wrote:
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
>
> PcdFsp*BaseAddress now will be updated in FDF basing
> on flash map.
> DSC will only define types of those PCDs and always
> having 0 as default.
> New script added to only rebase FSP binary without
> patching DSC file.
>
> Test: interanl platform booted with this patch.
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
>
> Chasel Chiu (4):
> MinPlatformPkg: Auto configure Fsp*BaseAddress PCD
> Platform/Intel: Auto configure Fsp*BaseAddress PCD
> KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
> ClevoOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 3 +++
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc | 12 +++++++++---
> Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 3 +++
> Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 12 +++++++++---
> Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> Platform/Intel/build_bios.py | 7 ++-----
> 6 files changed, 122 insertions(+), 11 deletions(-)
> create mode 100644 Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py
>
I think the classification on TianoCore BZ#1863 is wrong. It should be
"EDK2 Platforms", probably. Please update the BZ.
Accordingly, the subject prefix on this patch series should not be
"PATCH", but "edk2-platforms PATCH". No need to resend the v1 patch
series just for this, but if you send a v2, please set the correct
subject prefix:
git format-patch -v2 --subject-prefix='edk2-platforms PATCH' ...
Thanks
Laszlo
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [edk2-devel] [PATCH 0/4] Auto configure Fsp*BaseAddress PCD
2019-07-29 13:47 ` [edk2-devel] [PATCH 0/4] " Laszlo Ersek
@ 2019-07-30 1:07 ` Chiu, Chasel
0 siblings, 0 replies; 17+ messages in thread
From: Chiu, Chasel @ 2019-07-30 1:07 UTC (permalink / raw)
To: Laszlo Ersek, devel@edk2.groups.io
Cc: Kubacki, Michael A, Sinha, Ankit, Desimone, Nathaniel L,
Gao, Liming
Thanks for the good catch!
I have corrected BZ and will update subject from next patch.
Thanks!
Chasel
> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Monday, July 29, 2019 9:47 PM
> To: devel@edk2.groups.io; Chiu, Chasel <chasel.chiu@intel.com>
> Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Sinha, Ankit
> <ankit.sinha@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: Re: [edk2-devel] [PATCH 0/4] Auto configure Fsp*BaseAddress PCD
>
> On 07/29/19 13:07, Chiu, Chasel wrote:
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
> >
> > PcdFsp*BaseAddress now will be updated in FDF basing on flash map.
> > DSC will only define types of those PCDs and always having 0 as
> > default.
> > New script added to only rebase FSP binary without patching DSC file.
> >
> > Test: interanl platform booted with this patch.
> >
> > Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> > Cc: Ankit Sinha <ankit.sinha@intel.com>
> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> > Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
> >
> > Chasel Chiu (4):
> > MinPlatformPkg: Auto configure Fsp*BaseAddress PCD
> > Platform/Intel: Auto configure Fsp*BaseAddress PCD
> > KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
> > ClevoOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
> >
> > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
> | 3 +++
> > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
> | 12 +++++++++---
> > Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> | 3 +++
> >
> Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> | 12 +++++++++---
> > Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py |
> 96
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++
> > Platform/Intel/build_bios.py | 7 ++-----
> > 6 files changed, 122 insertions(+), 11 deletions(-) create mode
> > 100644
> > Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py
> >
>
> I think the classification on TianoCore BZ#1863 is wrong. It should be
> "EDK2 Platforms", probably. Please update the BZ.
>
>
> Accordingly, the subject prefix on this patch series should not be "PATCH", but
> "edk2-platforms PATCH". No need to resend the v1 patch series just for this, but
> if you send a v2, please set the correct subject prefix:
>
> git format-patch -v2 --subject-prefix='edk2-platforms PATCH' ...
>
> Thanks
> Laszlo
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/4] Auto configure Fsp*BaseAddress PCD
2019-07-29 11:07 [PATCH 0/4] Auto configure Fsp*BaseAddress PCD Chiu, Chasel
` (4 preceding siblings ...)
2019-07-29 13:47 ` [edk2-devel] [PATCH 0/4] " Laszlo Ersek
@ 2019-07-30 3:46 ` Liming Gao
2019-07-30 3:49 ` Chiu, Chasel
5 siblings, 1 reply; 17+ messages in thread
From: Liming Gao @ 2019-07-30 3:46 UTC (permalink / raw)
To: Chiu, Chasel, devel@edk2.groups.io
Cc: Kubacki, Michael A, Sinha, Ankit, Desimone, Nathaniel L
Chasel:
This is a good enhancement. With this change, can RebaseAndPatchFspBinBaseAddress.py and PatchFspBinFvsBaseAddress.py be removed?
Thanks
Liming
> -----Original Message-----
> From: Chiu, Chasel
> Sent: Monday, July 29, 2019 7:07 PM
> To: devel@edk2.groups.io
> Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: [PATCH 0/4] Auto configure Fsp*BaseAddress PCD
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
>
> PcdFsp*BaseAddress now will be updated in FDF basing
> on flash map.
> DSC will only define types of those PCDs and always
> having 0 as default.
> New script added to only rebase FSP binary without
> patching DSC file.
>
> Test: interanl platform booted with this patch.
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
>
> Chasel Chiu (4):
> MinPlatformPkg: Auto configure Fsp*BaseAddress PCD
> Platform/Intel: Auto configure Fsp*BaseAddress PCD
> KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
> ClevoOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
>
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 3 +++
> Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc | 12 +++++++++---
> Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf | 3 +++
> Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 12 +++++++++---
> Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py | 96
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> Platform/Intel/build_bios.py | 7 ++-----
> 6 files changed, 122 insertions(+), 11 deletions(-)
> create mode 100644 Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py
>
> --
> 2.13.3.windows.1
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 0/4] Auto configure Fsp*BaseAddress PCD
2019-07-30 3:46 ` Liming Gao
@ 2019-07-30 3:49 ` Chiu, Chasel
0 siblings, 0 replies; 17+ messages in thread
From: Chiu, Chasel @ 2019-07-30 3:49 UTC (permalink / raw)
To: Gao, Liming, devel@edk2.groups.io
Cc: Kubacki, Michael A, Sinha, Ankit, Desimone, Nathaniel L
Yes, we will remove them later after confirming no impact to all platforms.
Regards,
Chasel
> -----Original Message-----
> From: Gao, Liming
> Sent: Tuesday, July 30, 2019 11:46 AM
> To: Chiu, Chasel <chasel.chiu@intel.com>; devel@edk2.groups.io
> Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Sinha, Ankit
> <ankit.sinha@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>
> Subject: RE: [PATCH 0/4] Auto configure Fsp*BaseAddress PCD
>
> Chasel:
> This is a good enhancement. With this change, can
> RebaseAndPatchFspBinBaseAddress.py and PatchFspBinFvsBaseAddress.py be
> removed?
>
> Thanks
> Liming
> > -----Original Message-----
> > From: Chiu, Chasel
> > Sent: Monday, July 29, 2019 7:07 PM
> > To: devel@edk2.groups.io
> > Cc: Kubacki, Michael A <michael.a.kubacki@intel.com>; Sinha, Ankit
> > <ankit.sinha@intel.com>; Desimone, Nathaniel L
> > <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>
> > Subject: [PATCH 0/4] Auto configure Fsp*BaseAddress PCD
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1863
> >
> > PcdFsp*BaseAddress now will be updated in FDF basing on flash map.
> > DSC will only define types of those PCDs and always having 0 as
> > default.
> > New script added to only rebase FSP binary without patching DSC file.
> >
> > Test: interanl platform booted with this patch.
> >
> > Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> > Cc: Ankit Sinha <ankit.sinha@intel.com>
> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> > Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
> >
> > Chasel Chiu (4):
> > MinPlatformPkg: Auto configure Fsp*BaseAddress PCD
> > Platform/Intel: Auto configure Fsp*BaseAddress PCD
> > KabylakeOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
> > ClevoOpenBoardPkg: Auto configure Fsp*BaseAddress PCD
> >
> > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
> | 3 +++
> > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
> | 12 +++++++++---
> > Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
> | 3 +++
> >
> Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> | 12 +++++++++---
> > Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py |
> 96
> >
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++
> > Platform/Intel/build_bios.py | 7 ++-----
> > 6 files changed, 122 insertions(+), 11 deletions(-) create mode
> > 100644
> > Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseFspBinBaseAddress.py
> >
> > --
> > 2.13.3.windows.1
^ permalink raw reply [flat|nested] 17+ messages in thread