From: "Chiu, Chasel" <chasel.chiu@intel.com>
To: "Kubacki, Michael A" <michael.a.kubacki@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>,
"Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>,
"Gao, Liming" <liming.gao@intel.com>,
"Kinney, Michael D" <michael.d.kinney@intel.com>,
"Sinha, Ankit" <ankit.sinha@intel.com>
Subject: Re: [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add ConfigBlock headers
Date: Sat, 17 Aug 2019 01:09:06 +0000 [thread overview]
Message-ID: <3C3EFB470A303B4AB093197B6777CCEC50462267@PGSMSX111.gar.corp.intel.com> (raw)
In-Reply-To: <20190817001603.30632-6-michael.a.kubacki@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>;
> Kinney, Michael D <michael.d.kinney@intel.com>; Sinha, Ankit
> <ankit.sinha@intel.com>
> Subject: [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add
> ConfigBlock headers
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
>
> Adds header files to Pch/Include/ConfigBlock.
>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
> ---
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
> | 69 ++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h
> | 56 +++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h
> | 43 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h
> | 40 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionC
> onfig.h | 54 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/GpioDevConfig.h
> | 39 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h
> | 178 ++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h
> | 57 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h
> | 58 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h
> | 66 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfig.
> h | 58 +++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h
> | 68 ++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h
> | 57 +++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h
> | 35 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.
> h | 70 ++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h
> | 34 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h
> | 49 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfi
> g.h | 71 ++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchTraceHubCon
> fig.h | 36 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h
> | 429 ++++++++++++++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h
> | 311 ++++++++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h
> | 230 +++++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h
> | 63 +++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.h
> | 96 +++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig.h
> | 43 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h
> | 52 +++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig.h
> | 139 +++++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConfig.
> h | 33 ++
> 28 files changed, 2534 insertions(+)
>
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
> new file mode 100644
> index 0000000000..35fa125ba3
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h
> @@ -0,0 +1,69 @@
> +/** @file
> + CNVI policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _CNVI_CONFIG_H_
> +#define _CNVI_CONFIG_H_
> +
> +#define CNVI_CONFIG_REVISION 2
> +extern EFI_GUID gCnviConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + CNVi Mode options
> +**/
> +typedef enum {
> + CnviModeDisabled = 0,
> + CnviModeAuto
> +} CNVI_MODE;
> +
> +/**
> + CNVi MfUart1 connection options
> +**/
> +typedef enum {
> + CnviMfUart1Ish = 0,
> + CnviMfUart1SerialIo,
> + CnviBtUart1ExtPads,
> + CnviBtUart1NotConnected
> +} CNVI_MFUART1_TYPE;
> +
> +
> +/**
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Remove BtInterface and BtUartType.
> +
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + This option allows for automatic detection of Connectivity Solution.
> + Auto Detection assumes that CNVi will be enabled when available;
> + Disable allows for disabling CNVi.
> + CnviModeDisabled = Disabled,
> + <b>CnviModeAuto = Auto Detection</b>
> + **/
> + UINT32 Mode : 1;
> + /**
> + <b>(Test)</b> This option configures Uart type which connects to MfUart1
> + For production configuration ISH is the default, for tests SerialIO Uart0 or
> external pads can be used
> + Use CNVI_MFUART1_TYPE enum for selection
> + <b>CnviMfUart1Ish = MfUart1 over ISH Uart0</b>,
> + CnviMfUart1SerialIo = MfUart1 over SerialIO Uart2,
> + CnviBtUart1ExtPads = MfUart1 over exteranl pads,
> + CnviBtUart1NotConnected = MfUart1 not connected
> + **/
> + UINT32 MfUart1Type : 2;
> + UINT32 RsvdBits : 29;
> +} PCH_CNVI_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _CNVI_CONFIG_H_
> +
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h
> new file mode 100644
> index 0000000000..791546bdfe
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h
> @@ -0,0 +1,56 @@
> +/** @file
> + Dci policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _DCI_CONFIG_H_
> +#define _DCI_CONFIG_H_
> +
> +#define DCI_PREMEM_CONFIG_REVISION 1
> +extern EFI_GUID gDciPreMemConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +typedef enum {
> + ProbeTypeDisabled = 0x0,
> + ProbeTypeDciOobDbc = 0x1,
> + ProbeTypeDciOob = 0x2,
> + ProbeTypeUsb3Dbc = 0x3,
> + ProbeTypeXdp3 = 0x4,
> + ProbeTypeUsb2Dbc = 0x5,
> + ProbeTypeMax
> +} PLATFORM_DEBUG_CONSENT_PROBE_TYPE;
> +
> +/**
> + The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct
> Connection Interface (DCI)
> +
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + Platform Debug Consent
> + As a master switch to enable platform debug capability and relevant
> settings with specified probe type.
> + Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC]
> have the same setting.
> + Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE
> + <b>0:Disabled</b>; 1:DCI OOB+DbC; 2:DCI OOB; 3:USB3 DbC;
> 4:XDP3/MIPI60 5:USB2 DbC;
> + **/
> + UINT32 PlatformDebugConsent : 3;
> + /**
> + USB3 Type-C UFP2DFP kenel / platform debug support. No change will do
> nothing to UFP2DFP configuration.
> + When enabled, USB3 Type C UFP (upstream-facing port) may switch to DFP
> (downstream-facing port) for first connection.
> + It must be enabled for USB3 kernel(kernel mode debug) and platform
> debug(DFx, DMA, Trace) over UFP Type-C receptacle.
> + Refer to definition of DCI_USB_TYPE_C_DEBUG_MODE for supported
> settings.
> + 0:Disabled; 1:Enabled; <b>2:No Change</b>
> + **/
> + UINT32 DciUsb3TypecUfpDbg : 2;
> + UINT32 RsvdBits : 27; ///< Reserved bits
> +} PCH_DCI_PREMEM_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _DCI_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h
> new file mode 100644
> index 0000000000..03f83d9bf8
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h
> @@ -0,0 +1,43 @@
> +/** @file
> + DMI policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _DMI_CONFIG_H_
> +#define _DMI_CONFIG_H_
> +
> +#define DMI_CONFIG_REVISION 3
> +extern EFI_GUID gDmiConfigGuid;
> +
> +
> +#pragma pack (push,1)
> +
> +
> +/**
> + The PCH_DMI_CONFIG block describes the expected configuration of the
> PCH for DMI.
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Deprecate DmiAspm and add DmiAspmCtrl
> + <b>Revision 3</b>
> + - Added policy to enable/disable Central Write Buffer feature
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + @deprecated since revision 2
> + **/
> +
> + UINT32 DmiAspm : 1;
> + UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI
> Power Optimizer on PCH side.
> + UINT32 DmiAspmCtrl : 8; ///< ASPM configuration
> (PCH_PCIE_ASPM_CONTROL) on the PCH side of the DMI/OPI Link. Default is
> <b>PchPcieAspmAutoConfig</b>
> + UINT32 CwbEnable : 1; ///< <b>0: Disable</b>; Central Write
> Buffer feature configurable and disabled by default
> + UINT32 Rsvdbits : 21; ///< Reserved bits
> +} PCH_DMI_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _DMI_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h
> new file mode 100644
> index 0000000000..5de9b73397
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h
> @@ -0,0 +1,40 @@
> +/** @file
> + Espi policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _ESPI_CONFIG_H_
> +#define _ESPI_CONFIG_H_
> +
> +#define ESPI_CONFIG_REVISION 1
> +extern EFI_GUID gEspiConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + This structure contains the policies which are related to ESPI.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + LPC (eSPI) Memory Range Decode Enable. When TRUE, then the range
> + specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI).
> + <b>0: FALSE</b>, 1: TRUE
> + **/
> + UINT32 LgmrEnable : 1;
> + /**
> + eSPI Master and Slave BME settings.
> + When TRUE, then the BME bit enabled in eSPI Master and Slave.
> + 0: FALSE, <b>1: TRUE </b>
> + **/
> + UINT32 BmeMasterSlaveEnabled : 1;
> + UINT32 RsvdBits : 30; ///< Reserved bits
> +} PCH_ESPI_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _ESPI_CONFIG_H_
> +
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectio
> nConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectio
> nConfig.h
> new file mode 100644
> index 0000000000..2a6c19de7e
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectio
> nConfig.h
> @@ -0,0 +1,54 @@
> +/** @file
> + FlashProtection policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _FLASH_PROTECTION_CONFIG_H_
> +#define _FLASH_PROTECTION_CONFIG_H_
> +
> +#define FLASH_PROTECTION_CONFIG_REVISION 1
> +extern EFI_GUID gFlashProtectionConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +//
> +// Flash Protection Range Register
> +//
> +#define PCH_FLASH_PROTECTED_RANGES 5
> +
> +/**
> + The PCH provides a method for blocking writes and reads to specific ranges
> + in the SPI flash when the Protected Ranges are enabled.
> + PROTECTED_RANGE is used to specify if flash protection are enabled,
> + the write protection enable bit and the read protection enable bit,
> + and to specify the upper limit and lower base for each register
> + Platform code is responsible to get the range base by
> PchGetSpiRegionAddresses routine,
> + and set the limit and base accordingly.
> +**/
> +typedef struct {
> + UINT32 WriteProtectionEnable : 1; ///< Write or erase is
> blocked by hardware. <b>0: Disable</b>; 1: Enable.
> + UINT32 ReadProtectionEnable : 1; ///< Read is blocked
> by hardware. <b>0: Disable</b>; 1: Enable.
> + UINT32 RsvdBits : 30; ///< Reserved
> + /**
> + The address of the upper limit of protection
> + This is a left shifted address by 12 bits with address bits 11:0 are assumed
> to be FFFh for limit comparison
> + **/
> + UINT16 ProtectedRangeLimit;
> + /**
> + The address of the upper limit of protection
> + This is a left shifted address by 12 bits with address bits 11:0 are assumed
> to be 0
> + **/
> + UINT16 ProtectedRangeBase;
> +} PROTECTED_RANGE;
> +
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES];
> +} PCH_FLASH_PROTECTION_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _FLASH_PROTECTION_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/GpioDevConfig
> .h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/GpioDevConfig
> .h
> new file mode 100644
> index 0000000000..2b32a21f54
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/GpioDevConfig
> .h
> @@ -0,0 +1,39 @@
> +/** @file
> + GPIO device policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _GPIO_DEV_CONFIG_H_
> +#define _GPIO_DEV_CONFIG_H_
> +
> +extern EFI_GUID gGpioDxeConfigGuid;
> +
> +#define GPIO_DXE_CONFIG_REVISION 1
> +
> +#pragma pack (push,1)
> +
> +/**
> + This structure contains the DXE policies which are related to GPIO device.
> +
> + <b>Revision 1:</b>
> + - Inital version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + If GPIO ACPI device is not used by OS it can be hidden. In such case
> + no other device exposed to the system can reference GPIO device in one
> + of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors.
> + <b>0: Disable</b>; 1: Enable
> + **/
> + UINT32 HideGpioAcpiDevice : 1;
> + UINT32 RsvdBits : 31; ///< Reserved bits
> +
> +} PCH_GPIO_DXE_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _PCH_GPIO_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfi
> g.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfi
> g.h
> new file mode 100644
> index 0000000000..a810d4f1fc
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfi
> g.h
> @@ -0,0 +1,178 @@
> +/** @file
> + HDAUDIO policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _HDAUDIO_CONFIG_H_
> +#define _HDAUDIO_CONFIG_H_
> +
> +#include <PchHda.h>
> +
> +#define HDAUDIO_PREMEM_CONFIG_REVISION 1
> +#define HDAUDIO_CONFIG_REVISION 2
> +#define HDAUDIO_DXE_CONFIG_REVISION 2
> +
> +extern EFI_GUID gHdAudioPreMemConfigGuid;
> +extern EFI_GUID gHdAudioConfigGuid;
> +extern EFI_GUID gHdAudioDxeConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +///
> +/// The PCH_HDAUDIO_CONFIG block describes the expected configuration
> of the Intel HD Audio feature.
> +///
> +
> +#define HDAUDIO_VERB_TABLE_VIDDID(Vid,Did)
> (UINT32)((UINT16)Vid | ((UINT16)Did << 16))
> +#define HDAUDIO_VERB_TABLE_RID_SDI_SIZE(Rid,Sdi,VerbTableSize)
> (UINT32)((UINT8)Rid | ((UINT8)Sdi << 8) | ((UINT16)VerbTableSize << 16))
> +#define HDAUDIO_VERB_TABLE_CMD_SIZE(VerbTable) ((sizeof
> (VerbTable) - sizeof (PCH_HDA_VERB_TABLE_HEADER)) / (sizeof (UINT32)))
> +
> +///
> +/// Use this macro to create HDAUDIO_VERB_TABLE and populate size
> automatically
> +///
> +#define HDAUDIO_VERB_TABLE_INIT(Vid,Did,Rid,Sdi,...) \
> +{ \
> + { Vid, Did, Rid, Sdi, (sizeof((UINT32[]){__VA_ARGS__})/sizeof(UINT32)) }, \
> + { __VA_ARGS__ } \
> +}
> +
> +
> +/**
> + Azalia verb table header
> + Every verb table should contain this defined header and followed by azalia
> verb commands.
> +**/
> +typedef struct {
> + UINT16 VendorId; ///< Codec Vendor ID
> + UINT16 DeviceId; ///< Codec Device ID
> + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any
> revision.
> + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
> + UINT16 DataDwords; ///< Number of data DWORDs following the
> header.
> +} PCH_HDA_VERB_TABLE_HEADER;
> +
> +#ifdef _MSC_VER
> +//
> +// Disable "zero-sized array in struct/union" extension warning.
> +// Used for neater verb table definitions.
> +//
> +#pragma warning (push)
> +#pragma warning (disable: 4200)
> +#endif
> +typedef struct {
> + PCH_HDA_VERB_TABLE_HEADER Header;
> + UINT32 Data[];
> +} HDAUDIO_VERB_TABLE;
> +#ifdef _MSC_VER
> +#pragma warning (pop)
> +#endif
> +
> +/**
> + This structure contains the policies which are related to HD Audio device
> (cAVS).
> +
> + <b>Revision 1:</b>
> + - Inital version.
> + <b>Revision 2:</b>
> + - Move DspEndpointDmic, DspEndpointBluetooth, DspEndpointI2s and
> DspFeatureMask to PCH_HDAUDIO_DXE_CONFIG
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1:
> Enable</b>
> + UINT32 Pme : 1; ///< Azalia wake-on-ring, <b>0:
> Disable</b>; 1: Enable
> + UINT32 VcType : 1; ///< Virtual Channel Type Select: <b>0:
> VC0</b>, 1: VC1
> + UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency
> (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>2: 24MHz</b>, 1: 12MHz, 0:
> 6MHz
> + UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency
> (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>4: 96MHz</b>, 3: 48MHz
> + UINT32 IDispLinkTmode : 3; ///< iDisp-Link T-Mode
> (PCH_HDAUDIO_IDISP_TMODE enum): <b>0: 2T</b>, 1: 1T, 2: 4T, 3: 8T, 4: 16T
> + /**
> + Universal Audio Architecture compliance for DSP enabled system:
> + <b>0: Not-UAA Compliant (Intel SST driver supported only)</b>,
> + 1: UAA Compliant (HDA Inbox driver or SST driver supported)
> + **/
> + UINT32 DspUaaCompliance : 1;
> + UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec
> disconnection, <b>0: Not disconnected, enumerable</b>; 1: Disconnected SDI,
> not enumerable
> + UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake
> initiated by a codec in Sx (eg by modem codec), <b>0: Disable</b>; 1: Enable
> + /**
> + Audio Link Mode configuration bitmask.
> + Allows to configure enablement of the following interfaces: HDA-Link,
> DMIC, SSP, SoundWire.
> + **/
> + UINT32 AudioLinkHda : 1; ///< HDA-Link enablement: 0: Disable;
> <b>1: Enable</b>. Muxed with SSP0/SSP1/SNDW1
> + UINT32 AudioLinkDmic0 : 1; ///< DMIC0 link enablement: 0:
> Disable; <b>1: Enable</b>. Muxed with SNDW4
> + UINT32 AudioLinkDmic1 : 1; ///< DMIC1 link enablement: 0:
> Disable; <b>1: Enable</b>. Muxed with SNDW3
> + UINT32 AudioLinkSsp0 : 1; ///< I2S/SSP0 link enablement: <b>0:
> Disable</b>; 1: Enable. Muxed with HDA SDI0
> + UINT32 AudioLinkSsp1 : 1; ///< I2S/SSP1 link enablement: <b>0:
> Disable</b>; 1: Enable. Muxed with HDA SDI1/SNDW2
> + /**
> + I2S/SSP2 link enablement: <b>0: Disable</b>; 1: Enable.
> + @note Since the I2S/SSP2 pin set contains pads which are also used for
> CNVi purpose, enabling AudioLinkSsp2
> + is exclusive with CNVi is present.
> + **/
> + UINT32 AudioLinkSsp2 : 1;
> + UINT32 AudioLinkSndw1 : 1; ///< SoundWire1 link enablement:
> <b>0: Disable</b>; 1: Enable. Muxed with HDA
> + UINT32 AudioLinkSndw2 : 1; ///< SoundWire2 link enablement:
> <b>0: Disable</b>; 1: Enable. Muxed with SSP1
> + UINT32 AudioLinkSndw3 : 1; ///< SoundWire3 link enablement:
> <b>0: Disable</b>; 1: Enable. Muxed with DMIC1
> + UINT32 AudioLinkSndw4 : 1; ///< SoundWire4 link enablement:
> <b>0: Disable</b>; 1: Enable. Muxed with DMIC0
> + /**
> + Soundwire Clock Buffer GPIO RCOMP adjustments based on bus topology:
> + <b>0: non-ACT</b> - 50 Ohm driver impedance when bus topology does
> not have the external AC termination;
> + 1: ACT - 8 Ohm driver impedance when bus topology has the external AC
> termination.
> + **/
> + UINT32 SndwBufferRcomp : 1;
> + UINT32 RsvdBits0 : 4; ///< Reserved bits 0
> + UINT16 ResetWaitTimer; ///< <b>(Test)</b> The delay timer
> after Azalia reset, the value is number of microseconds. Default is <b>600</b>.
> + UINT8 Rsvd0; ///< Reserved bytes, align to multiple 4
> + /**
> + Number of the verb table entry defined in VerbTablePtr.
> + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE
> structure and verb command blocks.
> + **/
> + UINT8 VerbTableEntryNum;
> + /**
> + Pointer to a verb table array.
> + This pointer points to 32bits address, and is only eligible and consumed in
> post mem phase.
> + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE
> structure and verb command blocks.
> + The prototype of this is:
> + HDAUDIO_VERB_TABLE **VerbTablePtr;
> + **/
> + UINT32 VerbTablePtr;
> +} PCH_HDAUDIO_CONFIG;
> +
> +/**
> + This structure contains the premem policies which are related to HD Audio
> device (cAVS).
> +
> + <b>Revision 1:</b>
> + - Inital version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + UINT32 Enable : 1; ///< Intel HD Audio (Azalia) enablement:
> 0: Disable, <b>1: Enable</b>
> + UINT32 RsvdBits : 31; ///< Reserved bits 0
> +} PCH_HDAUDIO_PREMEM_CONFIG;
> +
> +/**
> + This structure contains the DXE policies which are related to HD Audio
> device (cAVS).
> +
> + <b>Revision 1:</b>
> + - Inital version.
> + <b>Revision 2:</b>
> + - Add NhltDefaultFlow option for disabling NHLT flow from Si code.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + AudioDSP/iSST endpoints configuration exposed via NHLT ACPI table:
> + **/
> + UINT32 DspEndpointDmic : 2; ///< DMIC Select
> (PCH_HDAUDIO_DMIC_TYPE enum): 0: Disable; 1: 2ch array; <b>2: 4ch
> array</b>; 3: 1ch array
> + UINT32 DspEndpointBluetooth : 1; ///< Bluetooth enablement: <b>0:
> Disable</b>; 1: Enable
> + UINT32 DspEndpointI2s : 1; ///< I2S enablement: <b>0:
> Disable</b>; 1: Enable
> + UINT32 NhltDefaultFlow : 1; ///< Default Nhlt flow: 0: Disable, <b>1:
> Enable</b>
> + UINT32 RsvdBits1 : 27; ///< Reserved bits 1
> + /**
> + Bitmask of supported DSP features:
> + [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP;
> [BIT6] - BT Intel A2DP
> + [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1:
> Windows Voice Activation
> + Default is <b>zero</b>.
> + **/
> + UINT32 DspFeatureMask;
> +} PCH_HDAUDIO_DXE_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _HDAUDIO_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h
> new file mode 100644
> index 0000000000..8c3186153c
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h
> @@ -0,0 +1,57 @@
> +/** @file
> + HSIO policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _HSIO_CONFIG_H_
> +#define _HSIO_CONFIG_H_
> +
> +#define HSIO_PREMEM_CONFIG_REVISION 1 //@deprecated
> +#define HSIO_CONFIG_REVISION 1
> +extern EFI_GUID gHsioPreMemConfigGuid; //@deprecated
> +extern EFI_GUID gHsioConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related
> settings. //@deprecated
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> //@deprecated
> +
> + /**
> + <b>(Test)</b>
> + 0- Disable, disable will prevent the HSIO version check and ChipsetInit HECI
> message from being sent
> + <b>1- Enable</b> ChipsetInit HECI message //@deprecated
> + **/
> + UINT32 ChipsetInitMessage : 1;
> + /**
> + <b>(Test)</b>
> + <b>0- Disable</b>
> + 1- Enable When enabled, this is used to bypass the reset after ChipsetInit
> HECI message. //@deprecated
> + **/
> + UINT32 BypassPhySyncReset : 1;
> + UINT32 RsvdBits : 30;
> +} PCH_HSIO_PREMEM_CONFIG;
> +
> +/**
> + The PCH_HSIO_CONFIG block provides HSIO message related settings.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + Policy used to point to the Base (+ OEM) ChipsetInit binary used to sync
> between BIOS and CSME
> + **/
> + UINT32 ChipsetInitBinPtr;
> + /**
> + Policy used to indicate the size of the Base (+ OEM) ChipsetInit binary used
> to sync between BIOS and CSME
> + **/
> + UINT32 ChipsetInitBinLen;
> +} PCH_HSIO_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _HSIO_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig
> .h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig
> .h
> new file mode 100644
> index 0000000000..93131ea07a
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig
> .h
> @@ -0,0 +1,58 @@
> +/** @file
> + HSIO pcie policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _HSIO_PCIE_CONFIG_H_
> +#define _HSIO_PCIE_CONFIG_H_
> +
> +#define HSIO_PCIE_PREMEM_CONFIG_REVISION 1
> +extern EFI_GUID gHsioPciePreMemConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane
> +**/
> +typedef struct {
> + //
> + // HSIO Rx Eq
> + // Refer to the EDS for recommended values.
> + // Note that these setting are per-lane and not per-port
> + //
> + UINT32 HsioRxSetCtleEnable : 1; ///< <b>0: Disable</b>; 1:
> Enable PCH PCIe Gen 3 Set CTLE Value
> + UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set CTLE
> Value
> + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>;
> 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value
> override
> + UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX
> Output Downscale Amplitude Adjustment value
> + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>;
> 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value
> override
> + UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX
> Output Downscale Amplitude Adjustment value
> + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>;
> 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value
> override
> + UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX
> Output Downscale Amplitude Adjustment value
> + UINT32 RsvdBits0 : 4; ///< Reserved Bits
> +
> + UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1:
> Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value
> override
> + UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX
> Output De-Emphasis Adjustment Setting
> + UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< <b>0: Disable</b>;
> 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment
> Setting value override
> + UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX
> Output -3.5dB Mode De-Emphasis Adjustment Setting
> + UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< <b>0: Disable</b>;
> 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment
> Setting value override
> + UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX
> Output -6.0dB Mode De-Emphasis Adjustment Setting
> + UINT32 RsvdBits1 : 11; ///< Reserved Bits
> +} PCH_HSIO_PCIE_LANE_CONFIG;
> +
> +///
> +/// The PCH_HSIO_PCIE_CONFIG block describes the configuration of the
> HSIO for PCIe lanes
> +///
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + ///
> + /// These members describe the configuration of HSIO for PCIe lanes.
> + ///
> + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS];
> +} PCH_HSIO_PCIE_PREMEM_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _HSIO_PCIE_LANE_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig
> .h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfi
> g.h
> new file mode 100644
> index 0000000000..a79542d657
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfi
> g.h
> @@ -0,0 +1,66 @@
> +/** @file
> + Hsio Sata policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _HSIO_SATA_CONFIG_H_
> +#define _HSIO_SATA_CONFIG_H_
> +
> +#define HSIO_SATA_PREMEM_CONFIG_REVISION 1
> +extern EFI_GUID gHsioSataPreMemConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane
> +**/
> +typedef struct {
> + //
> + // HSIO Rx Eq
> + //
> + UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< <b>0: Disable</b>;
> 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
> + UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiver
> Equalization Boost Magnitude Adjustment value
> + UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< <b>0: Disable</b>;
> 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
> + UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiver
> Equalization Boost Magnitude Adjustment value
> + UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< <b>0: Disable</b>;
> 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
> + UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiver
> Equalization Boost Magnitude Adjustment value
> + //
> + // HSIO Tx Eq
> + //
> + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>;
> 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
> override
> + UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX
> Output Downscale Amplitude Adjustment value
> + UINT32 RsvdBits0 : 4; ///< Reserved bits
> +
> + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>;
> 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
> override
> + UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX
> Output Downscale Amplitude Adjustment
> + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>;
> 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
> override
> + UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX
> Output Downscale Amplitude Adjustment
> + UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1:
> Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value
> override
> + UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Output
> De-Emphasis Adjustment Setting
> +
> + UINT32 HsioTxGen2DeEmphEnable : 1; ///< <b>0: Disable</b>; 1:
> Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value
> override
> + UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Output
> De-Emphasis Adjustment Setting
> + UINT32 RsvdBits1 : 4; ///< Reserved bits
> +
> + UINT32 HsioTxGen3DeEmphEnable : 1; ///< <b>0: Disable</b>; 1:
> Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value
> override
> + UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Output
> De-Emphasis Adjustment Setting value override
> + UINT32 RsvdBits2 : 25; ///< Reserved bits
> +} PCH_HSIO_SATA_PORT_LANE;
> +
> +///
> +/// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of
> the SATA controller.
> +///
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + ///
> + /// These members describe the configuration of HSIO for SATA lanes.
> + ///
> + PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS];
> +} PCH_HSIO_SATA_PREMEM_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _HSIO_SATA_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfi
> g.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfi
> g.h
> new file mode 100644
> index 0000000000..788931b83d
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfi
> g.h
> @@ -0,0 +1,58 @@
> +/** @file
> + Interrupt policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _INTERRUPT_CONFIG_H_
> +#define _INTERRUPT_CONFIG_H_
> +
> +#define INTERRUPT_CONFIG_REVISION 1
> +extern EFI_GUID gInterruptConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +//
> +// --------------------- Interrupts Config ------------------------------
> +//
> +typedef enum {
> + PchNoInt, ///< No Interrupt Pin
> + PchIntA,
> + PchIntB,
> + PchIntC,
> + PchIntD
> +} PCH_INT_PIN;
> +
> +///
> +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ
> and interrupt mode for PCH device.
> +///
> +typedef struct {
> + UINT8 Device; ///< Device number
> + UINT8 Function; ///< Device function
> + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see
> PCH_INT_PIN)
> + UINT8 Irq; ///< IRQ to be set for device.
> +} PCH_DEVICE_INTERRUPT_CONFIG;
> +
> +#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all
> PCH devices
> +#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC
> registers in ITSS
> +
> +///
> +/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.
> +///
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///<
> Config Block Header
> + UINT8 NumOfDevIntConfig; ///<
> Number of entries in DevIntConfig table
> + UINT8 Rsvd0[3]; ///<
> Reserved bytes, align to multiple 4.
> + PCH_DEVICE_INTERRUPT_CONFIG
> DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which
> stores PCH devices interrupts settings
> + UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG];
> ///< Array which stores interrupt routing for 8259 controller
> + UINT8 GpioIrqRoute; ///<
> Interrupt routing for GPIO. Default is <b>14</b>.
> + UINT8 SciIrqSelect; ///<
> Interrupt select for SCI. Default is <b>9</b>.
> + UINT8 TcoIrqSelect; ///<
> Interrupt select for TCO. Default is <b>9</b>.
> + UINT8 TcoIrqEnable; ///< Enable
> IRQ generation for TCO. <b>0: Disable</b>; 1: Enable.
> +} PCH_INTERRUPT_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _INTERRUPT_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h
> new file mode 100644
> index 0000000000..ce1d8f746d
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h
> @@ -0,0 +1,68 @@
> +/** @file
> + IoApic policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _IOAPIC_CONFIG_H_
> +#define _IOAPIC_CONFIG_H_
> +
> +#define IOAPIC_CONFIG_REVISION 2
> +extern EFI_GUID gIoApicConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + The PCH_IOAPIC_CONFIG block describes the expected configuration of the
> PCH
> + IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is
> + not TRUE. Bus:device:function fields will be programmed to the register
> + P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose:
> + As the Requester ID when initiating Interrupt Messages to the processor.
> + As the Completer ID when responding to the reads targeting the IOxAPI's
> + Memory-Mapped I/O registers.
> + This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can
> + program this field to provide a unique Bus:Device:Function number for the
> + internal IOxAPIC.
> + The address resource range of IOAPIC must be reserved in E820 and ACPI as
> + system resource.
> +
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Add Enable8254ClockGatingOnS3.
> +
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; <b>1: Enable</b>
> IOAPIC Entry 24-119
> + /**
> + Enable 8254 Static Clock Gating during early POST time. 0: Disable, <b>1:
> Enable</b>
> + Setting 8254CGE is required to support SLP_S0.
> + Enable this if 8254 timer is not used.
> + However, set 8254CGE=1 in POST time might fail to boot legacy OS using
> 8254 timer.
> + Make sure it is disabled to support legacy OS using 8254 timer.
> + @note:
> + For some OS environment that it needs to set 8254CGE in late state it
> should
> + set this policy to FALSE and use PmcSet8254ClockGateState (TRUE) in SMM
> later.
> + This is also required during S3 resume.
> + To avoid SMI requirement in S3 reusme path, it can enable the
> Enable8254ClockGatingOnS3
> + and RC will do 8254 CGE programming in PEI during S3 resume with
> BOOT_SAI.
> + **/
> + UINT32 Enable8254ClockGating : 1;
> + /**
> + Enable 8254 Static Clock Gating on S3 resume path. 0: Disable, <b>1:
> Enable</b>
> + This is only applicable when Enable8254ClockGating is disabled.
> + If Enable8254ClockGating is enabled, RC will do the 8254 CGE
> programming on
> + S3 resume path as well.
> + **/
> + UINT32 Enable8254ClockGatingOnS3 : 1;
> + UINT32 RsvdBits1 : 29; ///< Reserved bits
> + UINT8 IoApicId; ///< This member determines IOAPIC ID.
> Default is <b>0x02</b>.
> + UINT8 Rsvd0[3]; ///< Reserved bytes
> +} PCH_IOAPIC_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _IOAPIC_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h
> new file mode 100644
> index 0000000000..d03ef377ce
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h
> @@ -0,0 +1,57 @@
> +/** @file
> + ISH policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _ISH_CONFIG_H_
> +#define _ISH_CONFIG_H_
> +
> +#define ISH_PREMEM_CONFIG_REVISION 1
> +#define ISH_CONFIG_REVISION 1
> +extern EFI_GUID gIshPreMemConfigGuid;
> +extern EFI_GUID gIshConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +///
> +/// The PCH_ISH_CONFIG block describes Integrated Sensor Hub device.
> +///
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + UINT32 SpiGpioAssign : 1; ///< ISH SPI GPIO pins assigned: <b>0:
> False</b> 1: True
> + UINT32 Uart0GpioAssign : 1; ///< ISH UART0 GPIO pins assigned: <b>0:
> False</b> 1: True
> + UINT32 Uart1GpioAssign : 1; ///< ISH UART1 GPIO pins assigned: <b>0:
> False</b> 1: True
> + UINT32 I2c0GpioAssign : 1; ///< ISH I2C0 GPIO pins assigned: <b>0:
> False</b> 1: True
> + UINT32 I2c1GpioAssign : 1; ///< ISH I2C1 GPIO pins assigned: <b>0:
> False</b> 1: True
> + UINT32 I2c2GpioAssign : 1; ///< ISH I2C2 GPIO pins assigned: <b>0:
> False</b> 1: True
> + UINT32 Gp0GpioAssign : 1; ///< ISH GP_0 GPIO pin assigned: <b>0:
> False</b> 1: True
> + UINT32 Gp1GpioAssign : 1; ///< ISH GP_1 GPIO pin assigned: <b>0:
> False</b> 1: True
> + UINT32 Gp2GpioAssign : 1; ///< ISH GP_2 GPIO pin assigned: <b>0:
> False</b> 1: True
> + UINT32 Gp3GpioAssign : 1; ///< ISH GP_3 GPIO pin assigned: <b>0:
> False</b> 1: True
> + UINT32 Gp4GpioAssign : 1; ///< ISH GP_4 GPIO pin assigned: <b>0:
> False</b> 1: True
> + UINT32 Gp5GpioAssign : 1; ///< ISH GP_5 GPIO pin assigned: <b>0:
> False</b> 1: True
> + UINT32 Gp6GpioAssign : 1; ///< ISH GP_6 GPIO pin assigned: <b>0:
> False</b> 1: True
> + UINT32 Gp7GpioAssign : 1; ///< ISH GP_7 GPIO pin assigned: <b>0:
> False</b> 1: True
> + UINT32 PdtUnlock : 1; ///< ISH PDT Unlock Msg: <b>0: False</b> 1:
> True
> + UINT32 RsvdBits0 : 17; ///< Reserved Bits
> +} PCH_ISH_CONFIG;
> +
> +///
> +/// Premem Policy for Integrated Sensor Hub device.
> +///
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + ISH Controler 0: Disable; <b>1: Enable</b>.
> + For Desktop sku, the ISH POR should be disabled. <b> 0:Disable </b>.
> + **/
> + UINT32 Enable : 1;
> + UINT32 RsvdBits0 : 31; ///< Reserved Bits
> +} PCH_ISH_PREMEM_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _ISH_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h
> new file mode 100644
> index 0000000000..6bf34f8fe7
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h
> @@ -0,0 +1,35 @@
> +/** @file
> + Lan policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _LAN_CONFIG_H_
> +#define _LAN_CONFIG_H_
> +
> +#define LAN_CONFIG_REVISION 1
> +extern EFI_GUID gLanConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + PCH intergrated LAN controller configuration settings.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + Determines if enable PCH internal LAN, 0: Disable; <b>1: Enable</b>.
> + When Enable is changed (from disabled to enabled or from enabled to
> disabled),
> + it needs to set LAN Disable register, which might be locked by FDSWL
> register.
> + So it's recommendated to issue a global reset when changing the status for
> PCH Internal LAN.
> + **/
> + UINT32 Enable : 1;
> + UINT32 LtrEnable : 1; ///< <b>0: Disable</b>; 1: Enable LTR capabilty
> of PCH internal LAN.
> + UINT32 RsvdBits0 : 30; ///< Reserved bits
> +} PCH_LAN_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _LAN_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConf
> ig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConf
> ig.h
> new file mode 100644
> index 0000000000..a3a08c3cf6
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConf
> ig.h
> @@ -0,0 +1,70 @@
> +/** @file
> + Lock down policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _LOCK_DOWN_CONFIG_H_
> +#define _LOCK_DOWN_CONFIG_H_
> +
> +#define LOCK_DOWN_CONFIG_REVISION 1
> +extern EFI_GUID gLockDownConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + The PCH_LOCK_DOWN_CONFIG block describes the expected configuration
> of the PCH
> + for security requirement.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + <b>(Test)</b> Enable SMI_LOCK bit to prevent writes to the Global SMI
> Enable bit. 0: Disable; <b>1: Enable</b>.
> + **/
> + UINT32 GlobalSmi : 1;
> + /**
> + <b>(Test)</b> Enable BIOS Interface Lock Down bit to prevent writes to the
> Backup Control Register
> + Top Swap bit and the General Control and Status Registers Boot BIOS
> Straps.
> + Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit.
> Enabling this bit
> + will mitigate malicious software attempts to replace the system BIOS with
> its own code.
> + 0: Disable; <b>1: Enable</b>.
> + **/
> + UINT32 BiosInterface : 1;
> + /**
> + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the
> upper
> + and lower 128-byte bank of RTC RAM. 0: Disable; <b>1: Enable</b>.
> + **/
> + UINT32 RtcMemoryLock : 1;
> + /**
> + Enable the BIOS Lock Enable (BLE) feature and set EISS bit
> (D31:F5:RegDCh[5])
> + for the BIOS region protection. When it is enabled, the BIOS Region can
> only be
> + modified from SMM after EndOfDxe protocol is installed.
> + Note: When BiosLock is enabled, platform code also needs to update to
> take care
> + of BIOS modification (including SetVariable) in DXE or runtime phase after
> + EndOfDxe protocol is installed.
> + Enable InSMM.STS (EISS) in SPI
> + If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be '1' also
> + in order to write to BIOS regions of SPI Flash. If this EISS bit is clear,
> + then the InSMM.STS is a don't care.
> + The BIOS must set the EISS bit while BIOS Guard support is enabled.
> + In recovery path, platform can temporary disable EISS for SPI programming
> in
> + PEI phase or early DXE phase.
> + 0: Disable; <b>1: Enable.</b>
> + **/
> + UINT32 BiosLock : 1;
> + /**
> + <b>(Test)</b> This test option when set will force all GPIO pads to be
> unlocked
> + before BIOS transitions to POSTBOOT_SAI. This option should not be
> enabled in production
> + configuration and used only for debug purpose when free runtime
> reconfiguration of
> + GPIO pads is needed.
> + <b>0: Disable</b>; 1: Enable.
> + **/
> + UINT32 UnlockGpioPads : 1;
> + UINT32 RsvdBits0 : 27; ///< Reserved bits
> +} PCH_LOCK_DOWN_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _LOCK_DOWN_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h
> new file mode 100644
> index 0000000000..6ee9fe2d75
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h
> @@ -0,0 +1,34 @@
> +/** @file
> + Lpc policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _LPC_CONFIG_H_
> +#define _LPC_CONFIG_H_
> +
> +#define LPC_PREMEM_CONFIG_REVISION 1
> +extern EFI_GUID gLpcPreMemConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + This structure contains the policies which are related to LPC.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + Enhance the port 8xh decoding.
> + Original LPC only decodes one byte of port 80h, with this enhancement LPC
> can decode word or dword of port 80h-83h.
> + @note: this will occupy one LPC generic IO range register. While this is
> enabled, read from port 80h always return 0x00.
> + 0: Disable, <b>1: Enable</b>
> + **/
> + UINT32 EnhancePort8xhDecoding : 1;
> + UINT32 RsvdBits : 31; ///< Reserved bits
> +} PCH_LPC_PREMEM_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _LPC_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h
> new file mode 100644
> index 0000000000..5e1971cb9c
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h
> @@ -0,0 +1,49 @@
> +/** @file
> + P2sb policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _P2SB_CONFIG_H_
> +#define _P2SB_CONFIG_H_
> +
> +#define P2SB_CONFIG_REVISION 2
> +extern EFI_GUID gP2sbConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + This structure contains the policies which are related to P2SB device.
> +
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Deprecate SbiUnlock policy.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + @deprecated from REVISION 2.
> + <b>(Test)</b>
> + This unlock the SBI lock bit to allow SBI after post time.
> + For CFL: <b>0: Lock SBI</b>; 1: Unlock SBI.
> + NOTE: Do not change this policy "SbiUnlock" unless its necessary.
> + **/
> + UINT32 SbiUnlock : 1;
> + /**
> + <b>(Test)</b>
> + The sideband MMIO register access to specific ports will be locked
> + before 3rd party code execution. Currently it disables PSFx access.
> + This policy unlocks the sideband MMIO space for those IPs.
> + <b>0: Lock sideband access </b>; 1: Unlock sideband access.
> + NOTE: Do not set this policy "SbAccessUnlock" unless its necessary.
> + **/
> + UINT32 SbAccessUnlock : 1;
> + UINT32 Rsvdbits : 30; ///< Reserved bits
> +} PCH_P2SB_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _P2SB_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralCo
> nfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralCo
> nfig.h
> new file mode 100644
> index 0000000000..67f9a121ca
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralCo
> nfig.h
> @@ -0,0 +1,71 @@
> +/** @file
> + PCH General policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_GENERAL_CONFIG_H_
> +#define _PCH_GENERAL_CONFIG_H_
> +
> +#define PCH_GENERAL_CONFIG_REVISION 3
> +#define PCH_GENERAL_PREMEM_CONFIG_REVISION 1
> +
> +extern EFI_GUID gPchGeneralConfigGuid;
> +extern EFI_GUID gPchGeneralPreMemConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +enum PCH_RESERVED_PAGE_ROUTE {
> + PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC.
> + PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe.
> +};
> +
> +/**
> + PCH postmem general config block.
> +
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Remove SubSystemVendorId and SubSystemId.
> + <b>Revision 3</b>:
> + - Add LegacyIoLowLatency support.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + This member describes whether or not the Compatibility Revision ID (CRID)
> feature
> + of PCH should be enabled. <b>0: Disable</b>; 1: Enable
> + **/
> + UINT32 Crid : 1;
> + /**
> + Set to enable low latency of legacy IO.
> + Some systems require lower IO latency irrespective of power.
> + This is a tradeoff between power and IO latency.
> + @note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent
> + and ITSS Clock Gating are forced to disabled.
> + <b>0: Disable</b>, 1: Enable
> + **/
> + UINT32 LegacyIoLowLatency : 1;
> + UINT32 RsvdBits0 : 30; ///< Reserved bits
> +} PCH_GENERAL_CONFIG;
> +
> +/**
> + PCH premem general config block.
> +
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + Control where the Port 80h cycles are sent, <b>0: LPC</b>; 1: PCI.
> + **/
> + UINT32 Port80Route : 1;
> + UINT32 RsvdBits0 : 31; ///< Reserved bits
> +} PCH_GENERAL_PREMEM_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _PCH_GENERAL_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchTraceHubC
> onfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchTraceHubC
> onfig.h
> new file mode 100644
> index 0000000000..36527a5af3
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchTraceHubC
> onfig.h
> @@ -0,0 +1,36 @@
> +/** @file
> + PCH Trace Hub policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_TRACEHUB_CONFIG_H_
> +#define _PCH_TRACEHUB_CONFIG_H_
> +
> +#define PCH_TRACEHUB_PREMEM_CONFIG_REVISION 1
> +extern EFI_GUID gPchTraceHubPreMemConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +///
> +/// The PCH_TRACE_HUB_CONFIG block describes TraceHub settings for PCH.
> +///
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + UINT32 EnableMode : 2; ///< <b>0 = Disable</b>; 1 = Target
> Debugger mode; 2 = Host Debugger mode
> + /**
> + Pch Trace hub memory buffer region size policy.
> + The avaliable memory size options are: <b>0:0MB (none)</b>, 1:1MB,
> 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB.
> + Refer to TRACE_BUFFER_SIZE in TraceHubCommon.h for supported
> settings.
> + Note : Limitation of total buffer size (CPU + PCH) is 512MB.
> + **/
> + UINT32 MemReg0Size : 8;
> + UINT32 MemReg1Size : 8;
> + UINT32 RsvdBits0 : 14; ///< Reserved bits
> +} PCH_TRACE_HUB_PREMEM_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _TRACEHUB_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h
> new file mode 100644
> index 0000000000..7d23fcd15f
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h
> @@ -0,0 +1,429 @@
> +/** @file
> + Pcie root port policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_PCIE_CONFIG_H_
> +#define _PCH_PCIE_CONFIG_H_
> +
> +#include <PchLimits.h>
> +
> +#define PCIE_RP_CONFIG_REVISION 3
> +#define PCIE_RP_PREMEM_CONFIG_REVISION 1
> +
> +extern EFI_GUID gPcieRpConfigGuid;
> +extern EFI_GUID gPcieRpPreMemConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +#define PCH_PCIE_SWEQ_COEFFS_MAX 5
> +
> +typedef enum {
> + PchPcieOverrideDisabled = 0,
> + PchPcieL1L2Override = 0x01,
> + PchPcieL1SubstatesOverride = 0x02,
> + PchPcieL1L2AndL1SubstatesOverride = 0x03,
> + PchPcieLtrOverride = 0x04
> +} PCH_PCIE_OVERRIDE_CONFIG;
> +
> +/**
> + PCIe device table entry entry
> +
> + The PCIe device table is being used to override PCIe device ASPM settings.
> + To take effect table consisting of such entries must be instelled as PPI
> + on gPchPcieDeviceTablePpiGuid.
> + Last entry VendorId must be 0.
> +**/
> +typedef struct {
> + UINT16 VendorId; ///< The vendor Id of Pci Express card
> ASPM setting override, 0xFFFF means any Vendor ID
> + UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM
> setting override, 0xFFFF means any Device ID
> + UINT8 RevId; ///< The Rev Id of Pci Express card ASPM
> setting override, 0xFF means all steppings
> + UINT8 BaseClassCode; ///< The Base Class Code of Pci Express
> card ASPM setting override, 0xFF means all base class
> + UINT8 SubClassCode; ///< The Sub Class Code of Pci Express
> card ASPM setting override, 0xFF means all sub class
> + UINT8 EndPointAspm; ///< Override device ASPM (see:
> PCH_PCIE_ASPM_CONTROL)
> + ///< Bit 1 must be set in OverrideConfig for this
> field to take effect
> + UINT16 OverrideConfig; ///< The override config bitmap (see:
> PCH_PCIE_OVERRIDE_CONFIG).
> + /**
> + The L1Substates Capability Offset Override. (applicable if bit 2 is set in
> OverrideConfig)
> + This field can be zero if only the L1 Substate value is going to be override.
> + **/
> + UINT16 L1SubstatesCapOffset;
> + /**
> + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
> + Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s
> values are override.
> + Only bit [3:0] are applicable. Other bits are ignored.
> + **/
> + UINT8 L1SubstatesCapMask;
> + /**
> + L1 Substate Port Common Mode Restore Time Override. (applicable if bit
> 2 is set in OverrideConfig)
> + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid
> value of 0, but not the L1sTpowerOnValue.
> + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime,
> L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
> + and only L1SubstatesCapOffset is override.
> + **/
> + UINT8 L1sCommonModeRestoreTime;
> + /**
> + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in
> OverrideConfig)
> + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid
> value of 0, but not the L1sTpowerOnValue.
> + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime,
> L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
> + and only L1SubstatesCapOffset is override.
> + **/
> + UINT8 L1sTpowerOnScale;
> + /**
> + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in
> OverrideConfig)
> + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid
> value of 0, but not the L1sTpowerOnValue.
> + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime,
> L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
> + and only L1SubstatesCapOffset is override.
> + **/
> + UINT8 L1sTpowerOnValue;
> +
> + /**
> + SnoopLatency bit definition
> + Note: All Reserved bits must be set to 0
> +
> + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
> + When clear values in bits 9:0 will be ignored
> + BITS[14:13] - Reserved
> + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
> + 000b - 1 ns
> + 001b - 32 ns
> + 010b - 1024 ns
> + 011b - 32,768 ns
> + 100b - 1,048,576 ns
> + 101b - 33,554,432 ns
> + 110b - Reserved
> + 111b - Reserved
> + BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied
> with
> + the scale in bits 12:10
> +
> + This field takes effect only if bit 3 is set in OverrideConfig.
> + **/
> + UINT16 SnoopLatency;
> + /**
> + NonSnoopLatency bit definition
> + Note: All Reserved bits must be set to 0
> +
> + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
> + When clear values in bits 9:0 will be ignored
> + BITS[14:13] - Reserved
> + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
> + 000b - 1 ns
> + 001b - 32 ns
> + 010b - 1024 ns
> + 011b - 32,768 ns
> + 100b - 1,048,576 ns
> + 101b - 33,554,432 ns
> + 110b - Reserved
> + 111b - Reserved
> + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be
> multiplied with
> + the scale in bits 12:10
> +
> + This field takes effect only if bit 3 is set in OverrideConfig.
> + **/
> + UINT16 NonSnoopLatency;
> +
> + /**
> + Forces LTR override to be permanent
> + The default way LTR override works is:
> + rootport uses LTR override values provided by BIOS until connected
> device sends an LTR message, then it will use values from the message
> + This settings allows force override of LTR mechanism. If it's enabled, then:
> + rootport will use LTR override values provided by BIOS forever; LTR
> messages sent from connected device will be ignored
> + **/
> + UINT8 ForceLtrOverride;
> + UINT8 Reserved[3];
> +} PCH_PCIE_DEVICE_OVERRIDE;
> +
> +enum PCH_PCIE_SPEED {
> + PchPcieAuto,
> + PchPcieGen1,
> + PchPcieGen2,
> + PchPcieGen3
> +};
> +
> +///
> +/// The values before AutoConfig match the setting of PCI Express Base
> Specification 1.1, please be careful for adding new feature
> +///
> +typedef enum {
> + PchPcieAspmDisabled,
> + PchPcieAspmL0s,
> + PchPcieAspmL1,
> + PchPcieAspmL0sL1,
> + PchPcieAspmAutoConfig,
> + PchPcieAspmMax
> +} PCH_PCIE_ASPM_CONTROL;
> +
> +/**
> + Refer to PCH EDS for the PCH implementation values corresponding
> + to below PCI-E spec defined ranges
> +**/
> +typedef enum {
> + PchPcieL1SubstatesDisabled,
> + PchPcieL1SubstatesL1_1,
> + PchPcieL1SubstatesL1_1_2,
> + PchPcieL1SubstatesMax
> +} PCH_PCIE_L1SUBSTATES_CONTROL;
> +
> +enum PCH_PCIE_MAX_PAYLOAD {
> + PchPcieMaxPayload128 = 0,
> + PchPcieMaxPayload256,
> + PchPcieMaxPayloadMax
> +};
> +
> +enum PCH_PCIE_COMPLETION_TIMEOUT {
> + PchPcieCompletionTO_Default,
> + PchPcieCompletionTO_50_100us,
> + PchPcieCompletionTO_1_10ms,
> + PchPcieCompletionTO_16_55ms,
> + PchPcieCompletionTO_65_210ms,
> + PchPcieCompletionTO_260_900ms,
> + PchPcieCompletionTO_1_3P5s,
> + PchPcieCompletionTO_4_13s,
> + PchPcieCompletionTO_17_64s,
> + PchPcieCompletionTO_Disabled
> +};
> +
> +typedef enum {
> + PchPcieEqDefault = 0, ///< @deprecated since revision 3. Behaves as
> PchPcieEqHardware.
> + PchPcieEqHardware = 1, ///< Hardware equalization
> + PchPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient
> settings per lane)
> +} PCH_PCIE_EQ_METHOD;
> +
> +/**
> + Represent lane specific PCIe Gen3 equalization parameters.
> +**/
> +typedef struct {
> + UINT8 Cm; ///< Coefficient C-1
> + UINT8 Cp; ///< Coefficient C+1
> + UINT8 Rsvd0[2]; ///< Reserved bytes
> +} PCH_PCIE_EQ_LANE_PARAM, PCH_PCIE_EQ_PARAM;
> +
> +
> +/**
> + PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
> +**/
> +typedef struct {
> + UINT8 Usage; ///< Purpose of given clock (see
> PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF
> + UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping
> with Clock numbers
> + UINT8 RsvdBytes[2]; ///< Reserved byte
> +} PCH_PCIE_CLOCK;
> +
> +/**
> + The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and
> capability of each PCH PCIe root port.
> +**/
> +typedef struct {
> + UINT32 HotPlug : 1; ///< Indicate whether the root
> port is hot plug available. <b>0: Disable</b>; 1: Enable.
> + UINT32 PmSci : 1; ///< Indicate whether the root port
> power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
> + UINT32 ExtSync : 1; ///< Indicate whether the
> extended synch is enabled. <b>0: Disable</b>; 1: Enable.
> + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the
> Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
> + UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is
> enabled. 0: Disable; <b>1: Enable</b>.
> + UINT32 RsvdBits0 : 11; ///< Reserved bits.
> + /**
> + Probe CLKREQ# signal before enabling CLKREQ# based power
> management.
> + Conforming device shall hold CLKREQ# low until CPM is enabled. This
> feature attempts
> + to verify CLKREQ# signal is connected by testing pad state before enabling
> CPM.
> + In particular this helps to avoid issues with open-ended PCIe slots.
> + This is only applicable to non hot-plug ports.
> + <b>0: Disable</b>; 1: Enable.
> + **/
> + UINT32 ClkReqDetect : 1;
> + //
> + // Error handlings
> + //
> + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the
> Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
> + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the
> Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
> + UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal
> Error Report is enabled. <b>0: Disable</b>; 1: Enable.
> + UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No
> Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
> + UINT32 CorrectableErrorReport : 1; ///< Indicate whether the
> Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
> + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the
> System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
> + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the
> System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
> + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the
> System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
> + /**
> + Max Payload Size supported, Default <b>128B</b>, see enum
> PCH_PCIE_MAX_PAYLOAD
> + Changes Max Payload Size Supported field in Device Capabilities of the
> root port.
> + **/
> + UINT32 MaxPayload : 2;
> + UINT32 RsvdBits1 : 1; ///< Reserved fields for future
> expansion w/o protocol change
> + UINT32 DpcEnabled : 1; ///< Downstream Port
> Containment. 0: Disable; <b>1: Enable</b>
> + UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for
> Downstream Port Containment. 0: Disable; <b>1: Enable</b>
> + /**
> + Indicates how this root port is connected to endpoint. 0: built-in device;
> <b>1: slot</b>
> + Built-in is incompatible with hotplug-capable ports.
> + **/
> + UINT32 SlotImplemented : 1;
> + UINT32 RsvdBits3 : 1; ///< Placeholder for deleted field
> + /**
> + Determines each PCIE Port speed capability.
> + <b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)
> + **/
> + UINT8 PcieSpeed;
> + /**
> + PCIe Gen3 Equalization Phase 3 Method (see PCH_PCIE_EQ_METHOD).
> + 0: DEPRECATED, hardware equalization; <b>1: hardware equalization</b>;
> 4: Fixed Coefficients
> + **/
> + UINT8 Gen3EqPh3Method;
> +
> + UINT8 PhysicalSlotNumber; ///< Indicates the slot number
> for the root port. Default is the value as root port index.
> + UINT8 CompletionTimeout; ///< The completion timeout
> configuration of the root port (see: PCH_PCIE_COMPLETION_TIMEOUT).
> Default is <b>PchPcieCompletionTO_Default</b>.
> + /**
> + The PCH pin assigned to device PERST# signal if available, zero otherwise.
> + This entry is used mainly in Gen3 software equalization flow. It is necessary
> for some devices
> + (mainly some graphic adapters) to successfully complete the software
> equalization flow.
> + See also DeviceResetPadActiveHigh
> + **/
> + UINT32 RsvdBytes0[2]; ///< Reserved bytes
> + //
> + // Power Management
> + //
> + UINT8 Aspm; ///< The ASPM configuration of the
> root port (see: PCH_PCIE_ASPM_CONTROL). Default is
> <b>PchPcieAspmAutoConfig</b> for CNP-LP B1 it is limited to
> <b>PchPcieAspmL1</b>.
> + UINT8 L1Substates; ///< The L1 Substates
> configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
> Default is <b>PchPcieL1SubstatesL1_1_2</b>.
> + UINT8 LtrEnable; ///< Latency Tolerance Reporting
> Mechanism. <b>0: Disable</b>; 1: Enable.
> + UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
> + UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency
> Tolerance Reporting, Max Snoop Latency.
> + UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency
> Tolerance Reporting, Max Non-Snoop Latency.
> + UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency
> Tolerance Reporting, Snoop Latency Override Mode.
> + UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency
> Tolerance Reporting, Snoop Latency Override Multiplier.
> + UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency
> Tolerance Reporting, Snoop Latency Override Value.
> + UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b>
> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
> + UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b>
> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
> + UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b>
> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
> + UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies
> scale used for slot power limit value. Leave as 0 to set to default. Default is
> <b>zero</b>.
> + UINT32 SlotPowerLimitValue : 12; ///< <b>(Test)</b> Specifies
> upper limit on power supplies by slot. Leave as 0 to set to default. Default is
> <b>zero</b>.
> + //
> + // Gen3 Equalization settings
> + //
> + UINT32 Uptp : 4; ///< <b>(Test)</b> Upstream Port
> Transmitter Preset used during Gen3 Link Equalization. Used for all lanes.
> Default is <b>5</b>.
> + UINT32 Dptp : 4; ///< <b>(Test)</b> Downstream
> Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes.
> Default is <b>7</b>.
> + /**
> + <b>(Test)</b>
> + Forces LTR override to be permanent
> + The default way LTR override works is:
> + rootport uses LTR override values provided by BIOS until connected
> device sends an LTR message, then it will use values from the message
> + This settings allows force override of LTR mechanism. If it's enabled, then:
> + rootport will use LTR override values provided by BIOS forever; LTR
> messages sent from connected device will be ignored
> + **/
> + UINT32 ForceLtrOverride : 1;
> + UINT32 EnableCpm : 1; ///< Enables Clock
> Power Management; even if disabled, CLKREQ# signal can still be controlled by
> L1 PM substates mechanism
> + UINT32 PtmEnabled : 1; ///< Enables PTM
> capability
> + UINT32 PcieRootPortGen2PllL1CgDisable : 1; ///< Disables
> Gen2PLL shutdown and L1 state controller power gating
> + UINT32 RsvdBits2 : 6; ///< Reserved Bits
> + /**
> + The number of milliseconds reference code will wait for link to exit Detect
> state for enabled ports
> + before assuming there is no device and potentially disabling the port.
> + It's assumed that the link will exit detect state before root port
> initialization (sufficient time
> + elapsed since PLTRST de-assertion) therefore default timeout is zero.
> However this might be useful
> + if device power-up seqence is controlled by BIOS or a specific device
> requires more time to detect.
> + In case of non-common clock enabled the default timout is 15ms.
> + <b>Default: 0</b>
> + **/
> + UINT16 DetectTimeoutMs;
> + UINT16 RsvdBytes1[3]; ///< Reserved bytes
> +} PCH_PCIE_ROOT_PORT_CONFIG;
> +
> +/**
> + The PCH_PCIE_CONFIG block describes the expected configuration of the
> PCH PCI Express controllers
> +
> + <b>Revision 1</b>:
> + - Init version
> + <b>Revision 2</b>:
> + - Add policy PcieRootPortGen2PllL1CgDisable in
> PCH_PCIE_ROOT_PORT_CONFIG.
> + <b>Revision 3</b>:
> + - Deleted all items related to PCIe Gen3 software equalization:
> + DeviceResetPad, DeviceResetPadActiveHigh policies and two values from
> PCH_PCIE_EQ_METHOD enum used for Gen3EqPh3Method field
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + ///
> + /// These members describe the configuration of each PCH PCIe root port.
> + ///
> + PCH_PCIE_ROOT_PORT_CONFIG
> RootPort[PCH_MAX_PCIE_ROOT_PORTS];
> + ///
> + /// Configuration of PCIe source clocks
> + ///
> + PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];
> + ///
> + /// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe
> lane 1, etc.
> + /// Corresponding entries are used when root port EqPh3Method is
> PchPcieEqStaticCoeff (default).
> + ///
> + PCH_PCIE_EQ_LANE_PARAM
> EqPh3LaneParam[PCH_MAX_PCIE_ROOT_PORTS];
> + ///
> + /// List of coefficients used during equalization (applicable to both software
> and hardware EQ)
> + ///
> + PCH_PCIE_EQ_PARAM
> SwEqCoeffList[PCH_PCIE_SWEQ_COEFFS_MAX];
> + PCH_PCIE_EQ_PARAM Rsvd0[3];
> + ///
> + /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh
> Decode is enabled. <b>0: Disable</b>; 1: Enable.
> + ///
> + UINT32 EnablePort8xhDecode : 1;
> + ///
> + /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode
> (0 Based)
> + ///
> + UINT32 PchPciePort8xhDecodePortIndex : 5;
> + ///
> + /// This member describes whether the PCI Express Clock Gating for each
> root port
> + /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
> + ///
> + UINT32 DisableRootPortClockGating : 1;
> + ///
> + /// This member describes whether Peer Memory Writes are enabled on the
> platform. <b>0: Disable</b>; 1: Enable.
> + ///
> + UINT32 EnablePeerMemoryWrite : 1;
> + /**
> + Compliance Test Mode shall be enabled when using Compliance Load
> Board.
> + <b>0: Disable</b>, 1: Enable
> + **/
> + UINT32 ComplianceTestMode : 1;
> + /**
> + RpFunctionSwap allows BIOS to use root port function number swapping
> when root port of function 0 is disabled.
> + A PCIE device can have higher functions only when Function0 exists. To
> satisfy this requirement,
> + BIOS will always enable Function0 of a device that contains more than 0
> enabled root ports.
> + - <b>Enabled: One of enabled root ports get assigned to Function0.</b>
> + This offers no guarantee that any particular root port will be available at
> a specific DevNr:FuncNr location
> + - Disabled: Root port that corresponds to Function0 will be kept visible
> even though it might be not used.
> + That way rootport - to - DevNr:FuncNr assignment is constant. This
> option will impact ports 1, 9, 17.
> + NOTE: This option will not work if ports 1, 9, 17 are fused or configured for
> RST PCIe storage or disabled through policy
> + In other words, it only affects ports that would become hidden
> because they have no device connected.
> + NOTE: Disabling function swap may have adverse impact on power
> management. This option should ONLY
> + be used when each one of root ports 1, 9, 17:
> + - is configured as PCIe and has correctly configured ClkReq signal, or
> + - does not own any mPhy lanes (they are configured as SATA or USB)
> + **/
> + UINT32 RpFunctionSwap : 1;
> +
> + UINT32 RsvdBits0 : 22;
> + /**
> + PCIe device override table
> + The PCIe device table is being used to override PCIe device ASPM settings.
> + This is a pointer points to a 32bit address. And it's only used in PostMem
> phase.
> + Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table.
> + Last entry VendorId must be 0.
> + The prototype of this policy is:
> + PCH_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
> + **/
> + UINT32 PcieDeviceOverrideTablePtr;
> +
> +} PCH_PCIE_CONFIG;
> +
> +/**
> + The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of
> the PCH PCI Express controllers
> + <b>Revision 1</b>:
> + - Init version
> + - Add RpEnable in premem phase.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block
> Header
> + /**
> + Root Port enabling mask.
> + Bit0 presents RP1, Bit1 presents RP2, and so on.
> + 0: Disable; <b>1: Enable</b>.
> + **/
> + UINT32 RpEnabledMask;
> + UINT16 PcieImrSize; ///< PCIe IMR size in
> megabytes
> + UINT8 PcieImrEnabled; ///< PCIe IMR. <b>0:
> Disable</b>; 1: Enable.
> + UINT8 ImrRpSelection; ///< Index of PCIe root
> port that is selected for IMR (0 based)
> +} PCH_PCIE_RP_PREMEM_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _PCH_PCIE_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h
> new file mode 100644
> index 0000000000..8748db5e1a
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h
> @@ -0,0 +1,311 @@
> +/** @file
> + Power Management policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PM_CONFIG_H_
> +#define _PM_CONFIG_H_
> +
> +#define PM_CONFIG_REVISION 5
> +extern EFI_GUID gPmConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + This structure allows to customize PCH wake up capability from S5 or DeepSx
> by WOL, LAN, PCIE wake events.
> +**/
> +typedef struct {
> + /**
> + Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B
> (GEN_PMCON_B) register.
> + When set to 1, this bit blocks wake events from PME_B0_STS in S5,
> regardless of the state of PME_B0_EN.
> + When cleared (default), wake events from PME_B0_STS are allowed in S5
> if PME_B0_EN = 1. <b>0: Disable</b>; 1: Enable.
> + **/
> + UINT32 PmeB0S5Dis : 1;
> + UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL
> Enable Override" bit in the General PM Configuration B (GEN_PMCON_B)
> register. 0: Disable; <b>1: Enable</b>.
> + UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to
> wake from deep Sx. <b>0: Disable</b>; 1: Enable.
> + UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from Sx,
> corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register.
> <b>0: Disable</b>; 1: Enable.
> + UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from
> DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3
> register. <b>0: Disable</b>; 1: Enable.
> + UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to
> wake from deep Sx. 0: Disable; <b>1: Enable</b>.
> + UINT32 RsvdBits0 : 26;
> +} PCH_WAKE_CONFIG;
> +
> +typedef enum {
> + PchDeepSxPolDisable,
> + PchDpS5BatteryEn,
> + PchDpS5AlwaysEn,
> + PchDpS4S5BatteryEn,
> + PchDpS4S5AlwaysEn,
> +} PCH_DEEP_SX_CONFIG;
> +
> +typedef enum {
> + PchSlpS360us = 1,
> + PchSlpS31ms,
> + PchSlpS350ms,
> + PchSlpS32s
> +} PCH_SLP_S3_MIN_ASSERT;
> +
> +typedef enum {
> + PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing
> and Reset Signal Timings table
> + PchSlpS41s,
> + PchSlpS42s,
> + PchSlpS43s,
> + PchSlpS44s
> +} PCH_SLP_S4_MIN_ASSERT;
> +
> +typedef enum {
> + PchSlpSus0ms = 1,
> + PchSlpSus500ms,
> + PchSlpSus1s,
> + PchSlpSus4s,
> +} PCH_SLP_SUS_MIN_ASSERT;
> +
> +typedef enum {
> + PchSlpA0ms = 1,
> + PchSlpA4s,
> + PchSlpA98ms,
> + PchSlpA2s,
> +} PCH_SLP_A_MIN_ASSERT;
> +
> +typedef enum {
> + S0ixDisQNoChange,
> + S0ixDisQDciOob,
> + S0ixDisQUsb2Dbc,
> + S0ixDisQAuto,
> + S0ixDisQMax,
> +} S0IX_DISQ_PROBE_TYPE;
> +
> +typedef enum {
> + SlpS0OverrideDisabled = 0x0,
> + SlpS0OverrideEnabled = 0x1,
> + SlpS0OverrideAuto = 0x2,
> + SlpS0OverrideMax
> +} SLP_S0_OVERRIDE;
> +
> +/**
> + The PCH_PM_CONFIG block describes expected miscellaneous power
> management settings.
> + The PowerResetStatusClear field would clear the Power/Reset status bits,
> please
> + set the bits if you want PCH Init driver to clear it, if you want to check the
> + status later then clear the bits.
> +
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Add PsOnEnable and PowerButtonDebounce.
> + <b>Revision 3</b>:
> + - Add CpuC10GatePinEnable in PCH_PM_CONFIG.
> + <b>Revision 4</b>:
> + - Add PmcDbgMsgEn.
> + - Removed PmcReadDisable in PCH_PM_CONFIG.
> + <b>Revision 5</b>:
> + - Add ModPhySusPgEnable
> + <b>Revision 6</b>:
> + - Add SlpS0WithGbeSupport
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block
> Header
> +
> + PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake
> Policy
> + UINT32 PchDeepSxPol : 4; ///< Deep Sx Policy.
> Refer to PCH_DEEP_SX_CONFIG for each value. Default is
> <b>PchDeepSxPolDisable</b>.
> + UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 Minimum
> Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value.
> Default is <b>PchSlpS350ms</b>.
> + UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 Minimum
> Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value.
> Default is <b>PchSlpS44s</b>.
> + UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS
> Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each
> value. Default is <b>PchSlpSus4s</b>.
> + UINT32 PchSlpAMinAssert : 4; ///< SLP_A Minimum
> Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value.
> Default is <b>PchSlpA2s</b>.
> + UINT32 RsvdBits0 : 12;
> + /**
> + This member describes whether or not the LPC ClockRun feature of PCH
> should
> + be enabled. 0: Disable; <b>1: Enable</b>
> + **/
> + UINT32 LpcClockRun : 1; /// 0: Disable; <b>1:
> Enable</b>
> + UINT32 SlpStrchSusUp : 1; ///< <b>0: Disable</b>;
> 1: Enable SLP_X Stretching After SUS Well Power Up
> + /**
> + Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; <b>1: Enable</b>.
> + Configure On DC PHY Power Diable according to policy SlpLanLowDc.
> + When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low.
> + This indicates that LAN PHY should be powered off on battery mode.
> + This will override the DC_PP_DIS setting by WolEnableOverride.
> + **/
> + UINT32 SlpLanLowDc : 1;
> + /**
> + PCH power button override period.
> + 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s
> + <b>Default is 0: 4s</b>
> + **/
> + UINT32 PwrBtnOverridePeriod : 3;
> + /**
> + <b>(Test)</b>
> + Disable/Enable PCH to CPU enery report feature. <b>0: Disable</b>; 1:
> Enable.
> + Enery Report is must have feature. Wihtout Energy Report, the
> performance report
> + by workloads/benchmarks will be unrealistic because PCH's energy is not
> being accounted
> + in power/performance management algorithm.
> + If for some reason PCH energy report is too high, which forces CPU to try to
> reduce
> + its power by throttling, then it could try to disable Energy Report to do first
> debug.
> + This might be due to energy scaling factors are not correct or the LPM
> settings are not
> + kicking in.
> + **/
> + UINT32 DisableEnergyReport : 1;
> + /**
> + When set to Disable, PCH will internal pull down AC_PRESENT in deep SX
> and during G3 exit.
> + When set to Enable, PCH will not pull down AC_PRESENT.
> + This setting is ignored when DeepSx is not supported.
> + Default is <b>0:Disable</b>
> + **/
> + UINT32 DisableDsxAcPresentPulldown : 1;
> + /**
> + Power button native mode disable.
> + While FALSE, the PMC's power button logic will act upon the input value
> from the GPIO unit, as normal.
> + While TRUE, this will result in the PMC logic constantly seeing the power
> button as de-asserted.
> + <b>Default is FALSE.</b>
> + **/
> + UINT32 DisableNativePowerButton : 1;
> + /**
> + Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
> + When set to one SLP_S0# will be asserted in idle state.
> + When set to zero SLP_S0# will not toggle and is always drivern high.
> + 0:Disable, <b>1:Enable</b>
> +
> + If a platform is using SLP_S0 to lower PCH voltage the below policy must be
> disabled.
> + **/
> + UINT32 SlpS0Enable : 1;
> + /**
> + SLP_S0 Voltage Margining Runtime Control.
> + PCH VCCPRIM_CORE Voltage Margining is under ACPI control. Software in
> runtime
> + may change VCCPRIM_CORE supply voltage based on conditions like
> HDAudio power state
> + after SLP_S0# assertion. Enable VM runtime control requires ACPI VMON
> method
> + which will allow configuring VCCPRIM_CORE supply voltage. If this
> configuration is used
> + ACPI VMON method needs to be provided as it is not implemented in RC.
> + This setting is dependent on PMIC/VR type used on the platform.
> + <b>0: Disable</b>; 1: Enable.
> + **/
> + UINT32 SlpS0VmRuntimeControl : 1;
> + /**
> + SLP_S0 0.70V Voltage Margining Support.
> + Indicates whether SLP_S0# Voltage Margining supports setting PCH
> VCCPRIM_CORE down to 0.70V.
> + This setting is dependent on PMIC/VR type used on the platform.
> + <b>0: Disable</b>; 1: Enable.
> + **/
> + UINT32 SlpS0Vm070VSupport : 1;
> + /**
> + SLP_S0 0.75V Voltage Margining Support.
> + Indicates whether SLP_S0# Voltage Margining supports setting PCH
> VCCPRIM_CORE down to 0.75V.
> + This setting is dependent on PMIC/VR type used on the platform.
> + <b>0: Disable</b>; 1: Enable.
> + **/
> + UINT32 SlpS0Vm075VSupport : 1;
> + /**
> + Decide if SLP_S0# needs to be overriden (de-asserted) when system is in
> debug mode. This is available since CNP-B0.
> + Select 'Auto', it will be auto-configured according to probe type. Select
> 'Enabled' will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0#
> assertion when debug is enabled.
> + This policy should keep 'Auto', other options are intended for advanced
> configuration only.
> + please refer to SLP_S0_OVERRIDE
> + 0: Disable; 1: Enable; <b>2:Auto</b>
> + **/
> + UINT32 SlpS0Override : 2;
> + /**
> + SLP_S0# disqualify for debug prode
> + used to configure power management setting per debug probe to be
> disqualified from S0ix.
> + Reminder: USB3 DbC supports S0 only. DCI OOB (aka BSSB) uses CCA probe
> + Select 'Auto', it will be auto-configured according to probe type. 'No
> Change' will keep PMC default settings. Or select the desired debug probe type
> for S0ix Override settings.\nReminder: USB3 DbC supports S0 only. DCI OOB
> (aka BSSB) uses CCA probe.
> + Note: This policy should keep 'Auto', other options are intended for
> advanced configuration only.
> + please refer to S0IX_DISQ_PROBE_TYPE
> + 0: No Probe; 1: DCI OOB; 2: USB2 DbC; <b>3:Auto</b>
> + **/
> + UINT32 SlpS0DisQForDebug : 3;
> + UINT32 MeWakeSts : 1; ///< Clear the
> ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable;
> <b>1: Enable</b>.
> + UINT32 WolOvrWkSts : 1; ///< Clear the
> WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0:
> Disable; <b>1: Enable</b>.
> + /*
> + Set true to enable TCO timer.
> + When FALSE, it disables PCH ACPI timer, and stops TCO timer.
> + @note: This will have significant power impact when it's enabled.
> + If TCO timer is disabled, uCode ACPI timer emulation must be enabled,
> + and WDAT table must not be exposed to the OS.
> + <b>0: Disable</b>, 1: Enable
> + */
> + UINT32 EnableTcoTimer : 1;
> + /*
> + When VRAlert# feature pin is enabled and its state is '0',
> + the PMC requests throttling to a T3 Tstate to the PCH throttling unit.
> + <b>0: Disable</b>; 1: Enable.
> + */
> + UINT32 VrAlert : 1;
> + /**
> + Decide if PS_ON is to be enabled. This is available on desktop only.
> + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a
> + lower power target that will be required by the California Energy
> + Commission (CEC). When FALSE, PS_ON is to be disabled.}
> + <b>0: Disable</b>; 1: Enable.
> + **/
> + UINT32 PsOnEnable : 1;
> + /**
> + Enable/Disable platform support for CPU_C10_GATE# pin to control gating
> + of CPU VccIO and VccSTG rails instead of SLP_S0# pin. This policy needs
> + to be set if board design includes support for CPU_C10_GATE# pin.
> + 0: Disable; <b>1: Enable</b>
> + **/
> + UINT32 CpuC10GatePinEnable : 1;
> + /**
> + Control whether to enable PMC debug messages to Trace Hub.
> + When Enabled, PMC HW will send debug messages to trace hub;
> + When Disabled, PMC HW will never send debug meesages to trace hub.
> + @note: When enabled, system may not enter S0ix
> + <b>0: Disable</b>; 1: Enable.
> + **/
> + UINT32 PmcDbgMsgEn : 1;
> + /**
> + Enable/Disable ModPHY SUS Power Domain Dynamic Gating.
> + EXT_PWR_GATE# signal (if supported on platform) can be used to
> + control external FET for power gating ModPHY
> + @note: This setting is not supported and ignored on PCH-H
> + 0: Disable; <b>1: Enable</b>.
> + **/
> + UINT32 ModPhySusPgEnable : 1;
> + /**
> + Enable/Disable SLP_S0 with GBE Support. This policy is ignored when GbE
> is not present.
> + 0: Disable; <b>1: Enable</b>.
> + Default is 0 when paired with WHL V0 stepping CPU and 1 for all other
> CPUs.
> + **/
> + UINT32 SlpS0WithGbeSupport : 1;
> +
> + UINT32 RsvdBits1 : 5;
> + /*
> + Power button debounce configuration
> + Debounce time can be specified in microseconds. Only certain values
> according
> + to below formula are supported:
> + DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock
> period).
> + RTC clock with f = 32 KHz is used for glitch filter.
> + DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us).
> + Supported DebounceTime values are following:
> + DebounceTime = 0 -> Debounce feature disabled
> + DebounceTime > 0 && < 250us -> Not supported
> + DebounceTime = 250us - 1024000us -> Supported range (DebounceTime =
> 250us * 2^n)
> + For values not supported by HW, they will be rounded down to closest
> supported one
> + <b>Default is 0</b>
> + */
> + UINT32 PowerButtonDebounce;
> + /**
> + Reset Power Cycle Duration could be customized in the unit of second.
> Please refer to EDS
> + for all support settings. PCH HW default is 4 seconds, and range is 1~4
> seconds, where
> + <b>0 is default</b>, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds.
> + And make sure the setting correct, which never less than the following
> register.
> + - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH
> + - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH
> + - PWRM_CFG.SLP_A_MIN_ASST_WDTH
> + - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH
> + **/
> + UINT8 PchPwrCycDur;
> + /**
> + Specifies the Pcie Pll Spread Spectrum Percentage
> + The value of this policy is in 1/10th percent units.
> + Valid spread range is 0-20. A value of 0xFF is reserved for AUTO.
> + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%
> + The default is <b>0xFF: AUTO - No BIOS override</b>.
> + **/
> + UINT8 PciePllSsc;
> + UINT8 Rsvd0[2]; ///< Reserved bytes
> +
> +} PCH_PM_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _PM_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h
> new file mode 100644
> index 0000000000..ce1013b05e
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h
> @@ -0,0 +1,230 @@
> +/** @file
> + Sata policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SATA_CONFIG_H_
> +#define _SATA_CONFIG_H_
> +
> +#include <PchLimits.h>
> +
> +#define SATA_CONFIG_REVISION 2
> +extern EFI_GUID gSataConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +typedef enum {
> + PchSataModeAhci,
> + PchSataModeRaid,
> + PchSataModeMax
> +} PCH_SATA_MODE;
> +
> +typedef enum {
> + PchSataOromDelay2sec,
> + PchSataOromDelay4sec,
> + PchSataOromDelay6sec,
> + PchSataOromDelay8sec
> +} PCH_SATA_OROM_DELAY;
> +
> +typedef enum {
> + PchSataSpeedDefault,
> + PchSataSpeedGen1,
> + PchSataSpeedGen2,
> + PchSataSpeedGen3
> +} PCH_SATA_SPEED;
> +
> +typedef enum {
> + PchSataRstMsix,
> + PchSataRstMsi,
> + PchSataRstLegacy
> +} PCH_SATA_RST_INTERRUPT;
> +
> +typedef enum {
> + PchSataRaidClient,
> + PchSataRaidAlternate,
> + PchSataRaidServer
> +} PCH_SATA_RAID_DEV_ID;
> +
> +/**
> + This structure configures the features, property, and capability for each
> SATA port.
> +**/
> +typedef struct {
> + /**
> + Enable SATA port.
> + It is highly recommended to disable unused ports for power savings
> + **/
> + UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>
> + UINT32 HotPlug : 1; ///< <b>0: Disable</b>; 1: Enable
> + UINT32 InterlockSw : 1; ///< <b>0: Disable</b>; 1: Enable
> + UINT32 External : 1; ///< <b>0: Disable</b>; 1: Enable
> + UINT32 SpinUp : 1; ///< <b>0: Disable</b>; 1: Enable
> the COMRESET initialization Sequence to the device
> + UINT32 SolidStateDrive : 1; ///< <b>0: HDD</b>; 1: SSD
> + UINT32 DevSlp : 1; ///< <b>0: Disable</b>; 1: Enable
> DEVSLP on the port
> + UINT32 EnableDitoConfig : 1; ///< <b>0: Disable</b>; 1:
> Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
> + UINT32 DmVal : 4; ///< DITO multiplier. Default is
> <b>15</b>.
> + UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO),
> Default is <b>625</b>.
> + /**
> + Support zero power ODD <b>0: Disable</b>, 1: Enable.
> + This is also used to disable ModPHY dynamic power gate.
> + **/
> + UINT32 ZpOdd : 1;
> + UINT32 RsvdBits0 : 9; ///< Reserved fields for future
> expansion w/o protocol change
> +} PCH_SATA_PORT_CONFIG;
> +
> +/**
> + Rapid Storage Technology settings.
> +**/
> +typedef struct {
> + UINT32 Raid0 : 1; ///< 0 : Disable; <b>1 : Enable</b>
> RAID0
> + UINT32 Raid1 : 1; ///< 0 : Disable; <b>1 : Enable</b>
> RAID1
> + UINT32 Raid10 : 1; ///< 0 : Disable; <b>1 : Enable</b>
> RAID10
> + UINT32 Raid5 : 1; ///< 0 : Disable; <b>1 : Enable</b>
> RAID5
> + UINT32 Irrt : 1; ///< 0 : Disable; <b>1 : Enable</b> Intel
> Rapid Recovery Technology
> + UINT32 OromUiBanner : 1; ///< 0 : Disable; <b>1 : Enable</b>
> OROM UI and BANNER
> + UINT32 OromUiDelay : 2; ///< <b>00b : 2 secs</b>; 01b : 4
> secs; 10b : 6 secs; 11 : 8 secs (see : PCH_SATA_OROM_DELAY)
> + UINT32 HddUnlock : 1; ///< 0 : Disable; <b>1 : Enable</b>.
> Indicates that the HDD password unlock in the OS is enabled
> + UINT32 LedLocate : 1; ///< 0 : Disable; <b>1 : Enable</b>.
> Indicates that the LED/SGPIO hardware is attached and ping to locate feature
> is enabled on the OS
> + UINT32 IrrtOnly : 1; ///< 0 : Disable; <b>1 : Enable</b>.
> Allow only IRRT drives to span internal and external ports
> + UINT32 SmartStorage : 1; ///< 0 : Disable; <b>1 : Enable</b>
> RST Smart Storage caching Bit
> + UINT32 LegacyOrom : 1; ///< <b>0 : Disable</b>; 1 : Enable
> RST Legacy OROM
> + UINT32 OptaneMemory : 1; ///< 0: Disable; <b>1: Enable</b>
> RST Optane(TM) Memory
> + UINT32 CpuAttachedStorage : 1; ///< 0: Disable; <b>1: Enable</b>
> CPU Attached Storage
> + /**
> + This option allows to configure SATA controller device ID while in RAID
> mode.
> + Refer to PCH_SATA_RAID_DEV_ID enumeration for supported options.
> + Choosing Client will allow RST driver loading, RSTe driver will not be able
> to load
> + Choosing Alternate will not allow RST inbox driver loading in Windows
> + Choosing Server will allow RSTe driver loading, RST driver will not load
> + <b>0: Client</b>; 1: Alternate; 2: Server
> + **/
> + UINT32 RaidDeviceId : 2;
> + /**
> + Controlls which interrupts will be linked to SATA controller CAP list
> + This option will take effect only if SATA controller is in RAID mode
> + Default: <b>PchSataMsix</b>
> + **/
> + UINT32 SataRstInterrupt : 2;
> + UINT32 RsvdBits0 : 13; ///< Reserved Bits
> +} PCH_SATA_RST_CONFIG;
> +
> +/**
> + This structure lists PCH supported SATA thermal throttling register setting
> for customization.
> + The settings is programmed through SATA Index/Data registers.
> + When the SuggestedSetting is enabled, the customized values are ignored.
> +**/
> +typedef struct {
> + UINT32 P0T1M : 2; ///< Port 0 T1 Multipler
> + UINT32 P0T2M : 2; ///< Port 0 T2 Multipler
> + UINT32 P0T3M : 2; ///< Port 0 T3 Multipler
> + UINT32 P0TDisp : 2; ///< Port 0 Tdispatch
> +
> + UINT32 P1T1M : 2; ///< Port 1 T1 Multipler
> + UINT32 P1T2M : 2; ///< Port 1 T2 Multipler
> + UINT32 P1T3M : 2; ///< Port 1 T3 Multipler
> + UINT32 P1TDisp : 2; ///< Port 1 Tdispatch
> +
> + UINT32 P0Tinact : 2; ///< Port 0 Tinactive
> + UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Tdispatch
> + UINT32 P1Tinact : 2; ///< Port 1 Tinactive
> + UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Tdispatch
> + UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b>
> suggested representative values
> + UINT32 RsvdBits0 : 9; ///< Reserved bits
> +} SATA_THERMAL_THROTTLING;
> +
> +/**
> + This structure describes the details of Intel RST for PCIe Storage remapping
> + Note: In order to use this feature, Intel RST Driver is required
> +**/
> +typedef struct {
> + /**
> + This member describes whether or not the Intel RST for PCIe Storage
> remapping should be enabled. <b>0: Disable</b>; 1: Enable.
> + Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be
> disabled as well
> + Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI
> controllers Class Code is configured as RAID
> + **/
> + UINT32 Enable : 1;
> + /**
> + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <b>0 =
> autodetect</b>)
> + The supported ports for PCIe Storage remapping is different depend on
> the platform and cycle router, the assignments are as below:
> + i.) RST PCIe Storage Cycle Router 2 -> RP5 - RP8
> + ii.) RST PCIe Storage Cycle Router 3 -> RP9 - RP12
> +
> + i.) RST PCIe Storage Cycle Router 1 -> RP9 - RP12
> + ii.) RST PCIe Storage Cycle Router 2 -> RP13 - RP16
> + iii.) RST PCIe Storage Cycle Router 3 -> RP17 - RP20
> + **/
> + UINT32 RstPcieStoragePort : 5;
> + UINT32 RsvdBits0 : 2; ///< Reserved bit
> + /**
> + PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees
> such delay gap is fulfilled
> + before PCIe Storage Device configuration space is accessed after an reset
> caused by the link disable and enable step.
> + Default value is <b>100ms</b>.
> + **/
> + UINT32 DeviceResetDelay : 8;
> + UINT32 RsvdBits1 : 16; ///< Reserved bits
> +
> + UINT32 Rsvd0[2]; ///< Reserved bytes
> +} PCH_RST_PCIE_STORAGE_CONFIG;
> +
> +/**
> + The PCH_SATA_CONFIG block describes the expected configuration of the
> SATA controllers.
> +
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Add CpuAttachedStorage in PCH_SATA_RST_CONFIG.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block
> Header
> + ///
> + /// This member describes whether or not the SATA controllers should be
> enabled. 0: Disable; <b>1: Enable</b>.
> + ///
> + UINT32 Enable : 1;
> + UINT32 TestMode : 1; ///< <b>(Test)</b> <b>0:
> Disable</b>; 1: Allow entrance to the PCH SATA test modes
> + UINT32 SalpSupport : 1; ///< 0: Disable; <b>1:
> Enable</b> Aggressive Link Power Management
> + UINT32 PwrOptEnable : 1; ///< 0: Disable; <b>1:
> Enable</b> SATA Power Optimizer on PCH side.
> + /**
> + EsataSpeedLimit
> + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA
> port speed.
> + Please be noted, this setting could be cleared by HBA reset, which might be
> issued
> + by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after
> POST.
> + To support the Speed Limitation when POST, the EFI AHCI driver should
> preserve the
> + setting before and after initialization. For support it after POST, it's
> dependent on
> + driver's behavior.
> + <b>0: Disable</b>; 1: Enable
> + **/
> + UINT32 EsataSpeedLimit : 1;
> + UINT32 LedEnable : 1; ///< SATA LED indicates
> SATA controller activity. 0: Disable; <b>1: Enable</b> SATA LED.
> + UINT32 RsvdBits0 : 26; ///< Reserved bits
> +
> + /**
> + Determines the system will be configured to which SATA mode
> (PCH_SATA_MODE). Default is <b>PchSataModeAhci</b>.
> + **/
> + PCH_SATA_MODE SataMode;
> + /**
> + Indicates the maximum speed the SATA controller can support
> + <b>0h: PchSataSpeedDefault</b>; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2);
> 3h: 6 Gb/s (Gen 1)
> + **/
> + PCH_SATA_SPEED SpeedLimit;
> + /**
> + This member configures the features, property, and capability for each
> SATA port.
> + **/
> + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS];
> + PCH_SATA_RST_CONFIG Rst; ///< Setting
> applicable to Rapid Storage Technology
> + /**
> + This member describes the details of implementation of Intel RST for PCIe
> Storage remapping (Intel RST Driver is required)
> + Note: RST for PCIe Sorage remapping is supported only for first SATA
> controller if more controllers are available
> + **/
> + PCH_RST_PCIE_STORAGE_CONFIG
> RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR];
> + /**
> + This field decides the settings of Sata thermal throttling. When the
> Suggested Setting
> + is enabled, PCH RC will use the suggested representative values.
> + **/
> + SATA_THERMAL_THROTTLING ThermalThrottling;
> +} PCH_SATA_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _SATA_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h
> new file mode 100644
> index 0000000000..1e91143b93
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h
> @@ -0,0 +1,63 @@
> +/** @file
> + Scs policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SCS_CONFIG_H_
> +#define _SCS_CONFIG_H_
> +
> +#include <ConfigBlock.h>
> +
> +#define SCS_CONFIG_REVISION 2
> +extern EFI_GUID gScsConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +typedef enum {
> + DriverStrength33Ohm = 0,
> + DriverStrength40Ohm,
> + DriverStrength50Ohm
> +} PCH_SCS_EMMC_DRIVER_STRENGTH;
> +
> +/**
> + The PCH_SCS_CONFIG block describes Storage and Communication
> Subsystem (SCS) settings for PCH.
> +
> + <b>Revision 1</b>:
> + - Initial version
> + <b>Revision 2</b>:
> + - Add policy SdCardPowerEnableActiveHigh
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> +
> + UINT32 ScsEmmcEnabled : 2; ///< Determine if eMMC is
> enabled - 0: Disabled, <b>1: Enabled</b>.
> + UINT32 ScsEmmcHs400Enabled : 1; ///< Determine eMMC
> HS400 Mode if ScsEmmcEnabled - <b>0: Disabled</b>, 1: Enabled
> + /**
> + Determine if HS400 Training is required, set to FALSE if Hs400 Data is valid.
> <b>0: Disabled</b>, 1: Enabled.
> + First Boot or CMOS clear, system boot with Default settings, set tuning
> required.
> + Subsequent Boots, Get Variable 'Hs400TuningData'
> + - if failed to get variable, set tuning required
> + - if passed, retrieve Hs400DataValid, Hs400RxStrobe1Dll and
> Hs400TxDataDll from variable. Set tuning not required.
> + **/
> + UINT32 ScsEmmcHs400TuningRequired : 1;
> + UINT32 ScsEmmcHs400DllDataValid : 1; ///< Set if HS400 Tuning
> Data Valid
> + UINT32 ScsEmmcHs400RxStrobeDll1 : 7; ///< Rx Strobe Delay
> Control - Rx Strobe Delay DLL 1 (HS400 Mode)
> + UINT32 ScsEmmcHs400TxDataDll : 7; ///< Tx Data Delay Control 1
> - Tx Data Delay (HS400 Mode)
> + UINT32 ScsEmmcHs400DriverStrength : 3; ///< I/O driver strength: 0
> - 33 Ohm, <b>1 - 40 Ohm</b>, 2 - 50 Ohm
> + /**
> + Sd Card Controler 0: Disable; <b>1: Enable</b>.
> + For Desktop sku, the SD Card Controller POR should be disabled. <b>
> 0:Disable </b>.
> + **/
> + UINT32 ScsSdcardEnabled : 1;
> + UINT32 ScsUfsEnabled : 1; ///< Determine if Ufs is enabled
> 0: Disabled 1: Enabled
> + UINT32 SdCardPowerEnableActiveHigh : 1; ///< Determine
> SD_PWREN# polarity 0: Active low, <b>1: Active high</b>
> + UINT32 RsvdBits : 7;
> + UINT32 Rsvd0; ///< Reserved bytes
> +} PCH_SCS_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _SCS_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.
> h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.
> h
> new file mode 100644
> index 0000000000..73dfd17c47
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.
> h
> @@ -0,0 +1,96 @@
> +/** @file
> + Serial IO policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SERIAL_IO_CONFIG_H_
> +#define _SERIAL_IO_CONFIG_H_
> +
> +#define SERIAL_IO_CONFIG_REVISION 2
> +extern EFI_GUID gSerialIoConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + The PCH_SERIAL_IO_CONFIG block provides the configurations to set the
> Serial IO controllers
> +
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Add I2cPadsTermination
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block
> Header
> + /**
> + 0: Disabled;
> + - Device is placed in D3
> + - Gpio configuration is skipped
> + - Device will be disabled in PSF
> + - !important! If given device is Function 0 and not all other LPSS
> functions on given device
> + are disabled, then PSF disabling is skipped.
> + PSF default will remain and device PCI CFG Space will still be
> visible.
> + This is needed to allow PCI enumerator access functions
> above 0 in a multifunction device.
> + <b>1: Pci</b>;
> + - Gpio pin configuration in native mode for each assigned pin
> + RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl
> + - Device will be enabled in PSF
> + - Only Bar 0 will be enabled
> + 2: Acpi;
> + - Gpio pin configuration in native mode for each assigned pin
> + RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl
> + - Device will be hidden in PSF and not available to PCI enumerator
> + - Both BARs are enabled, BAR1 becomes devices Pci config Space
> + @note Intel does not provide Windows SerialIo drivers for this mode
> + 3: Hidden;
> + Designated for Kernel Debug and Legacy UART configuartion, might
> also be used for IO Expander on I2C
> + - Device is placed in D0
> + - Gpio pin configuration in native mode for each assigned pin
> + RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl
> + - Device will be hidden in PSF and not available to PCI enumerator
> + - Both BARs are enabled, BAR1 becomes devices Pci config Space
> + - !important! In this mode UART will work in 16550 Legacy 8BIT Mode,
> it's resources will be assigned to mother board through ACPI (PNP0C02)
> + @note Considering the PcdSerialIoUartDebugEnable and
> PcdSerialIoUartNumber for all SerialIo UARTx,
> + the PCD is more meaningful to represent the board design. It means,
> if PcdSerialIoUartDebugEnable is not 0,
> + the board is designed to use the SerialIo UART for debug message and
> the PcdSerialIoUartNumber is dedicated
> + to be Debug UART usage. Therefore, it should grayout the option from
> setup menu since no other options
> + available for this UART controller on this board, and also override the
> policy default accordingly.
> + While PcdSerialIoUartDebugEnable is 0, then it's allowed to configure
> the UART controller by policy.
> + **/
> + UINT8 DevMode[PCH_MAX_SERIALIO_CONTROLLERS];
> + UINT8 SpiCsPolarity[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///<
> Selects SPI ChipSelect signal polarity, <b>0=active low</b>.
> + UINT8 UartHwFlowCtrl[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///<
> Enables UART hardware flow control, CTS and RTS lines, <b>0:disabled</b>,
> 1:enabled
> + /**
> + I2C Pads Internal Termination.
> + For more information please see Platform Design Guide.
> + Supported values (check GPIO_ELECTRICAL_CONFIG for reference):
> + <b>GpioTermNone: No termination</b>,
> + GpioTermWpu1K: 1kOhm weak pull-up,
> + GpioTermWpu5K: 5kOhm weak pull-up,
> + GpioTermWpu20K: 20kOhm weak pull-up
> + **/
> + UINT8 I2cPadsTermination[PCH_MAX_SERIALIO_I2C_CONTROLLERS];
> + /**
> + UART device for debug purpose. 0:UART0, 1: UART1, <b>2:UART2</b>
> + @note If CNVi solution is on the platform and UART0 is selected as BT Core
> interface,
> + UART0 cannot be used for debug purpose.
> + **/
> + UINT32 DebugUartNumber : 2;
> + UINT32 EnableDebugUartAfterPost : 1; ///< Enable debug
> UART controller after post. 0: diabled, <b>1: enabled</b>
> + /**
> + <b>0: default pins</b>; 1: pins muxed with CNV_BRI/RGI
> + UART0 can be configured to use two different sets of pins:
> + This setting gives flexibility to use UART0 functionality on other pins when
> + default ones are used for a different purpose.
> + @note Since the second pin set contains pads which are also used for CNVi
> purpose, setting Uart0PinMuxing
> + is exclusive with CNVi being enabled.
> + **/
> + UINT32 Uart0PinMuxing : 1;
> + UINT32 RsvdBits0 : 28;
> +} PCH_SERIAL_IO_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _SERIAL_IO_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig
> .h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig
> .h
> new file mode 100644
> index 0000000000..7ccfe65428
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig
> .h
> @@ -0,0 +1,43 @@
> +/** @file
> + Serial IRQ policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SERIAL_IRQ_CONFIG_H_
> +#define _SERIAL_IRQ_CONFIG_H_
> +
> +#define SERIAL_IRQ_CONFIG_REVISION 1
> +extern EFI_GUID gSerialIrqConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +typedef enum {
> + PchQuietMode,
> + PchContinuousMode
> +} PCH_SIRQ_MODE;
> +///
> +/// Refer to PCH EDS for the details of Start Frame Pulse Width in Continuous
> and Quiet mode
> +///
> +typedef enum {
> + PchSfpw4Clk,
> + PchSfpw6Clk,
> + PchSfpw8Clk
> +} PCH_START_FRAME_PULSE;
> +
> +///
> +/// The PCH_LPC_SIRQ_CONFIG block describes the expected configuration of
> the PCH for Serial IRQ.
> +///
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + UINT32 SirqEnable : 1; ///< Determines if enable Serial
> IRQ. 0: Disable; <b>1: Enable</b>.
> + UINT32 SirqMode : 2; ///< Serial IRQ Mode Select. Refer
> to PCH_SIRQ_MODE for each value. <b>0: quiet mode</b> 1: continuous
> mode.
> + UINT32 StartFramePulse : 3; ///< Start Frame Pulse Width.
> Refer to PCH_START_FRAME_PULSE for each value. Default is
> <b>PchSfpw4Clk</b>.
> + UINT32 RsvdBits0 : 26; ///< Reserved bits
> +} PCH_LPC_SIRQ_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _SERIAL_IRQ_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h
> new file mode 100644
> index 0000000000..d96cf9f6cd
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h
> @@ -0,0 +1,52 @@
> +/** @file
> + Smbus policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SMBUS_CONFIG_H_
> +#define _SMBUS_CONFIG_H_
> +
> +#define SMBUS_PREMEM_CONFIG_REVISION 1
> +extern EFI_GUID gSmbusPreMemConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
> +
> +///
> +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP
> capable devices in the platform.
> +///
> +typedef struct {
> + /**
> + Revision 1: Init version
> + **/
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + This member describes whether or not the SMBus controller of PCH should
> be enabled.
> + 0: Disable; <b>1: Enable</b>.
> + **/
> + UINT32 Enable : 1;
> + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0:
> Disable</b>; 1: Enable.
> + UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b>
> or Enable Smbus dynamic power gating.
> + ///
> + /// <b>(Test)</b> SPD Write Disable, 0: leave SPD Write Disable bit; <b>1: set
> SPD Write Disable bit.</b>
> + /// For security recommendations, SPD write disable bit must be set.
> + ///
> + UINT32 SpdWriteDisable : 1;
> + UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin
> (SMBALERT#). 0: <b>Disabled<b>, 1: Enabled.
> + UINT32 RsvdBits0 : 27; ///< Reserved bits
> + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space).
> Default is <b>0xEFA0</b>.
> + UINT8 Rsvd0; ///< Reserved bytes
> + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in
> the RsvdSmbusAddressTable.
> + /**
> + Array of addresses reserved for non-ARP-capable SMBus devices.
> + **/
> + UINT8
> RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
> +} PCH_SMBUS_PREMEM_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _SMBUS_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig
> .h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig
> .h
> new file mode 100644
> index 0000000000..d3ea563f95
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig
> .h
> @@ -0,0 +1,139 @@
> +/** @file
> + Thermal policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _THERMAL_CONFIG_H_
> +#define _THERMAL_CONFIG_H_
> +
> +#define THERMAL_CONFIG_REVISION 1
> +extern EFI_GUID gThermalConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + This structure lists PCH supported throttling register setting for
> custimization.
> + When the SuggestedSetting is enabled, the customized values are ignored.
> +**/
> +typedef struct {
> + UINT32 T0Level : 9; ///< Custimized T0Level value. If
> SuggestedSetting is used, this setting is ignored.
> + UINT32 T1Level : 9; ///< Custimized T1Level value. If
> SuggestedSetting is used, this setting is ignored.
> + UINT32 T2Level : 9; ///< Custimized T2Level value. If
> SuggestedSetting is used, this setting is ignored.
> + UINT32 TTEnable : 1; ///< Enable the thermal throttle function.
> If SuggestedSetting is used, this settings is ignored.
> + /**
> + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13
> will force at least T2 state.
> + If SuggestedSetting is used, this setting is ignored.
> + **/
> + UINT32 TTState13Enable : 1;
> + /**
> + When set to 1, this entire register (TL) is locked and remains locked until
> the next platform reset.
> + If SuggestedSetting is used, this setting is ignored.
> + **/
> + UINT32 TTLock : 1;
> + UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b>
> suggested representative values.
> + /**
> + ULT processors support thermal management and cross thermal throttling
> between the processor package
> + and LP PCH. The PMSYNC message from PCH to CPU includes specific bit
> fields to update the PCH
> + thermal status to the processor which is factored into the processor
> throttling.
> + Enable/Disable PCH Cross Throttling; 0: Disabled, 1: <b>Enabled</b>.
> + **/
> + UINT32 PchCrossThrottling : 1;
> + UINT32 Rsvd0; ///< Reserved bytes
> +} THERMAL_THROTTLE_LEVELS;
> +
> +/**
> + This structure allows to customize DMI HW Autonomous Width Control for
> Thermal and Mechanical spec design.
> + When the SuggestedSetting is enabled, the customized values are ignored.
> + Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values
> +**/
> +typedef struct {
> + UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous
> Width Enable
> + UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b>
> suggested representative values
> + UINT32 RsvdBits0 : 6; ///< Reserved bits
> + UINT32 TS0TW : 3; ///< Thermal Sensor 0 Target Width
> (<b>DmiThermSensWidthx8</b>)
> + UINT32 TS1TW : 3; ///< Thermal Sensor 1 Target Width
> (<b>DmiThermSensWidthx4</b>)
> + UINT32 TS2TW : 3; ///< Thermal Sensor 2 Target Width
> (<b>DmiThermSensWidthx2</b>)
> + UINT32 TS3TW : 3; ///< Thermal Sensor 3 Target Width
> (<b>DmiThermSensWidthx1</b>)
> + UINT32 RsvdBits1 : 12; ///< Reserved bits
> +} DMI_HW_WIDTH_CONTROL;
> +
> +/**
> + This structure configures PCH memory throttling thermal sensor GPIO PIN
> settings
> +**/
> +typedef struct {
> + /**
> + GPIO PM_SYNC enable, 0:Diabled, 1:<b>Enabled</b>
> + When enabled, RC will overrides the selected GPIO native mode.
> + For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1
> + For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2
> + **/
> + UINT32 PmsyncEnable : 1;
> + UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 state,
> 0:Disabled, 1:<b>Enabled</b>
> + UINT32 PinSelection : 1; ///< GPIO Pin assignment selection, <b>0:
> default</b>, 1: secondary
> + UINT32 RsvdBits0 : 29;
> +} TS_GPIO_PIN_SETTING;
> +
> +enum PCH_PMSYNC_GPIO_X_SELECTION {
> + TsGpioC,
> + TsGpioD,
> + MaxTsGpioPin
> +};
> +
> +/**
> + This structure supports an external memory thermal sensor (TS-on-DIMM or
> TS-on-Board).
> +**/
> +typedef struct {
> + /**
> + This will enable PCH memory throttling.
> + While this policy is enabled, must also enable EnableExtts in SA policy.
> + <b>0: Disable</b>; 1: Enable
> + **/
> + UINT32 Enable : 1;
> + UINT32 RsvdBits0 : 31;
> + /**
> + GPIO_C and GPIO_D selection for memory throttling.
> + It's strongly recommended to choose GPIO_C and GPIO_D for memory
> throttling feature,
> + and route EXTTS# accordingly.
> + **/
> + TS_GPIO_PIN_SETTING TsGpioPinSetting[2];
> +} PCH_MEMORY_THROTTLING;
> +
> +/**
> + The PCH_THERMAL_CONFIG block describes the expected configuration of
> the PCH for Thermal.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + /**
> + This locks down "SMI Enable on Alert Thermal Sensor Trip". 0: Disabled, 1:
> <b>Enabled</b>.
> + **/
> + UINT32 TsmicLock : 1;
> + UINT32 PchHotEnable : 1; ///< Enable PCHHOT# pin assertion
> when temperature is higher than PchHotLevel. 0: <b>Disabled<b>, 1: Enabled.
> + UINT32 RsvdBits0 : 30;
> + /**
> + This field decides the settings of Thermal throttling. When the Suggested
> Setting
> + is enabled, PCH RC will use the suggested representative values.
> + **/
> + THERMAL_THROTTLE_LEVELS TTLevels;
> + /**
> + This field decides the settings of DMI throttling. When the Suggested
> Setting
> + is enabled, PCH RC will use the suggested representative values.
> + **/
> + DMI_HW_WIDTH_CONTROL DmiHaAWC;
> + /**
> + Memory Thermal Management settings
> + **/
> + PCH_MEMORY_THROTTLING MemoryThrottling;
> + /**
> + This field decides the temperature, default is <b>0x154</b>.
> + The recommendation is the same as Cat Trip point.
> + **/
> + UINT16 PchHotLevel;
> + UINT8 Rsvd0[6];
> +} PCH_THERMAL_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _THERMAL_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConf
> ig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConf
> ig.h
> new file mode 100644
> index 0000000000..78e4497d90
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConf
> ig.h
> @@ -0,0 +1,33 @@
> +/** @file
> + WatchDog policy
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _WATCH_DOG_CONFIG_H_
> +#define _WATCH_DOG_CONFIG_H_
> +
> +#define WATCH_DOG_PREMEM_CONFIG_REVISION 1
> +extern EFI_GUID gWatchDogPreMemConfigGuid;
> +
> +#pragma pack (push,1)
> +
> +/**
> + This policy clears status bits and disable watchdog, then lock the
> + WDT registers.
> + while WDT is designed to be disabled and locked by Policy,
> + bios should not enable WDT by WDT PPI. In such case, bios shows the
> + warning message but not disable and lock WDT register to make sure
> + WDT event trigger correctly.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Config Block Header
> + UINT32 DisableAndLock : 1; ///< <b>(Test)</b> Set 1 to clear WDT
> status, then disable and lock WDT registers. <b>0: Disable</b>; 1: Enable.
> + UINT32 RsvdBits : 31;
> +} PCH_WDT_PREMEM_CONFIG;
> +
> +#pragma pack (pop)
> +
> +#endif // _WATCH_DOG_CONFIG_H_
> --
> 2.16.2.windows.1
next prev parent reply other threads:[~2019-08-17 1:09 UTC|newest]
Thread overview: 121+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-17 0:15 [edk2-platforms][PATCH V1 00/37] Coffee Lake and Whiskey Lake support Kubacki, Michael A
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and Include headers Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:08 ` Chiu, Chasel
2019-08-17 1:18 ` Chaganty, Rangasai V
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:08 ` Chiu, Chasel
2019-08-17 6:58 ` Chaganty, Rangasai V
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:08 ` Chiu, Chasel
2019-08-17 7:04 ` Chaganty, Rangasai V
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add include headers Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:08 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add ConfigBlock headers Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel [this message]
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add Library include headers Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI and Protocol " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 08/37] CoffeelakeSiliconPkg/Pch: Add Register " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add Private " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add Private/Library " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:10 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode: Add Include headers Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 13/37] CoffeelakeSiliconPkg/SystemAgent: " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 14/37] CoffeelakeSiliconPkg: Add package common library instances Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:15 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 16/37] CoffeelakeSiliconPkg/Me: " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 17/37] CoffeelakeSiliconPkg/Pch: Add Base " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 18/37] CoffeelakeSiliconPkg/Pch: Add DXE " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 19/37] CoffeelakeSiliconPkg/Pch: Add PEI " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 20/37] CoffeelakeSiliconPkg/Pch: Add SMM " Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 21/37] CoffeelakeSiliconPkg/Pch: Add Base " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 22/37] CoffeelakeSiliconPkg/Pch: Add DXE private " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 23/37] CoffeelakeSiliconPkg/Pch: Add PEI " Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 24/37] CoffeelakeSiliconPkg/Pch: Add SMM " Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 25/37] CoffeelakeSiliconPkg/SystemAgent: Add " Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 26/37] CoffeelakeSiliconPkg/Pch: Add modules Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 27/37] CoffeelakeSiliconPkg/Pch: Add PchSmiDispatcher Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:15 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 28/37] CoffeelakeSiliconPkg/SystemAgent: Add modules Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:15 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package DSC files Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 30/37] Maintainers.txt: Add CoffeelakeSiliconPkg maintainers Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:15 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 31/37] WhiskeylakeOpenBoardPkg: Add package and headers Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-19 18:09 ` Sinha, Ankit
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 32/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 33/37] WhiskeylakeOpenBoardPkg: Add library instances Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-17 0:16 ` [edk2-platforms][PATCH V1 34/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: " Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:17 ` Chiu, Chasel
2019-08-17 20:08 ` Chaganty, Rangasai V
2019-08-17 0:16 ` [edk2-platforms][PATCH V1 35/37] WhiskeylakeOpenBoardPkg: Add modules Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:17 ` Chiu, Chasel
2019-08-17 7:50 ` Chaganty, Rangasai V
2019-08-17 0:16 ` [edk2-platforms][PATCH V1 36/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-17 20:11 ` Chaganty, Rangasai V
2019-08-17 0:16 ` [edk2-platforms][PATCH V1 37/37] Add WhiskeylakeOpenBoardPkg to global build config and documentation Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:17 ` Chiu, Chasel
2019-08-17 20:00 ` Chaganty, Rangasai V
2019-08-19 18:14 ` [edk2-platforms][PATCH V1 00/37] Coffee Lake and Whiskey Lake support Sinha, Ankit
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