From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: chasel.chiu@intel.com) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by groups.io with SMTP; Fri, 16 Aug 2019 18:09:34 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 18:09:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="376874433" Received: from pgsmsx104.gar.corp.intel.com ([10.221.44.91]) by fmsmga005.fm.intel.com with ESMTP; 16 Aug 2019 18:09:31 -0700 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.22]) by PGSMSX104.gar.corp.intel.com ([169.254.3.208]) with mapi id 14.03.0439.000; Sat, 17 Aug 2019 09:09:30 +0800 From: "Chiu, Chasel" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Desimone, Nathaniel L" , "Gao, Liming" , "Kinney, Michael D" , "Sinha, Ankit" Subject: Re: [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI and Protocol include headers Thread-Topic: [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI and Protocol include headers Thread-Index: AQHVVJEVgfOJt+rXQEKMgQ8bXeVXwqb+h6ww Date: Sat, 17 Aug 2019 01:09:29 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC50462287@PGSMSX111.gar.corp.intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> <20190817001603.30632-8-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-8-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNWFiZTAzMzktMDFiMC00ZDBhLWIwN2MtZTc4NjZmN2MyMDc1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoibTFsZG9Ob0xoMUFac05CNmpWQkNrVEZadlpnWVRPdUV6T1wvMnpFQWNma0tLSkp4REVIbVRrajFlOEd5ZldablgifQ== x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.206] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: Kubacki, Michael A > Sent: Saturday, August 17, 2019 8:16 AM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Chiu, Chasel > ; Desimone, Nathaniel L > ; Gao, Liming ; > Kinney, Michael D ; Sinha, Ankit > > Subject: [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add P= PI > and Protocol include headers >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 >=20 > Adds the following header files: > * Pch/Include/Ppi > * Pch/Include/Protocol >=20 > Cc: Sai Chaganty > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Liming Gao > Cc: Michael D Kinney > Cc: Ankit Sinha > Signed-off-by: Michael Kubacki > --- > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h > | 42 +++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h > | 27 ++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h > | 28 ++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch= .h > | 186 ++++++++++++ >=20 > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatc= h > .h | 136 +++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning.h > | 68 +++++ >=20 > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatc= h. > h | 146 ++++++++++ >=20 > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatc= h. > h | 132 +++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h > | 42 +++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchReset.h > | 42 +++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h > | 134 +++++++++ >=20 > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapContr > ol.h | 67 +++++ >=20 > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTim > erControl.h | 67 +++++ >=20 > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch= . > h | 152 ++++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h > | 15 + > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Spi.h > | 295 ++++++++++++++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Wdt.h > | 113 ++++++++ > 17 files changed, 1692 insertions(+) >=20 > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.= h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h > new file mode 100644 > index 0000000000..840a2355f1 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h > @@ -0,0 +1,42 @@ > +/** @file > + PCH Reset PPI > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_RESET_PPI_H_ > +#define _PCH_RESET_PPI_H_ > + > +// > +// Member functions > +// > +/** > + Execute call back function for Pch Reset. > + > + @param[in] ResetType Reset Types which includes GlobalReset= . > + @param[in] ResetTypeGuid Pointer to an EFI_GUID, which is the R= eset > Type Guid. > + > + @retval EFI_SUCCESS The callback function has been done > successfully > + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback ppi.= Or, > none of > + callback ppi is installed. > + @retval Others Do not do any reset from PCH > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_RESET_CALLBACK) ( > + IN EFI_RESET_TYPE ResetType, > + IN EFI_GUID *ResetTypeGuid > + ); > + > +/** > + This ppi is used to execute PCH Reset from the host controller. > + If drivers need to run their callback function right before issuing th= e PCH > Reset, > + they can install PCH Reset Callback PPI before PCH Reset PEI driver to > achieve that. > +**/ > +typedef struct { > + PCH_RESET_CALLBACK ResetCallback; > +} PCH_RESET_CALLBACK_PPI; > + > +#endif > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h > new file mode 100644 > index 0000000000..d3ff152742 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h > @@ -0,0 +1,27 @@ > +/** @file > + This file defines the PCH SPI PPI which implements the > + Intel(R) PCH SPI Host Controller Compatibility Interface. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_SPI_PPI_H_ > +#define _PCH_SPI_PPI_H_ > + > +#include > + > +// > +// Extern the GUID for PPI users. > +// > +extern EFI_GUID gPchSpiPpiGuid; > + > +/** > + Reuse the PCH_SPI_PROTOCOL definitions > + This is possible becaues the PPI implementation does not rely on a > PeiService pointer, > + as it uses EDKII Glue Lib to do IO accesses > +**/ > +typedef PCH_SPI_PROTOCOL PCH_SPI_PPI; > + > +#endif > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h > new file mode 100644 > index 0000000000..59a9f0f251 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h > @@ -0,0 +1,28 @@ > +/** @file > + Watchdog Timer PPI > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_WDT_H_ > +#define _PEI_WDT_H_ > + > +#include > +// > +// MRC takes a lot of time to execute in debug mode > +// > +#define WDT_TIMEOUT_BETWEEN_PEI_DXE 60 > + > +// > +// Extern the GUID for PPI users. > +// > +extern EFI_GUID gWdtPpiGuid; > + > +/// > +/// Reuse WDT_PROTOCOL definition > +/// > +typedef WDT_PROTOCOL WDT_PPI; > + > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatc= h. > h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatc= h. > h > new file mode 100644 > index 0000000000..4f14065bd1 > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatc= h. > h > @@ -0,0 +1,186 @@ > +/** @file > + PCH IO TrapEx Dispatch Protocol > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _IO_TRAP_EX_DISPATCH_H_ > +#define _IO_TRAP_EX_DISPATCH_H_ > + > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID > gIoTrapExDispatchProtocolGuid; > + > +typedef struct _IO_TRAP_EX_DISPATCH_PROTOCOL > IO_TRAP_EX_DISPATCH_PROTOCOL; > + > +/** > + IO Trap Ex valid types > +**/ > +typedef enum { > + IoTrapExTypeWrite, > + IoTrapExTypeRead, > + IoTrapExTypeReadWrite, > + IoTrapExTypeMaximum > +} IO_TRAP_EX_DISPATCH_TYPE; > + > +/** > + IO Trap Ex context structure containing information about the > + IO trap Ex event that should invoke the handler. > + ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b fo= r any > byte access. > + > + Here are some examples for the usage. > + 1. To trigger the TRAP for the IO address from 0x2000 to 0x20FF with > BYTE/WORD/DWORD read/write access: > + Address =3D 0x2000 > + Length =3D 0x100 > + Type =3D IoTrapExTypeReadWrite > + ByteEnable =3D 0x00 (BE is not matter) > + ByteEnableMask =3D 0x0F (BEM 0xF for any BYTE/WORD/DWORD access) > + 2. To trigger the TRAP for port 0x61 with BYTE read access: > + Address =3D 0x60 > + Length =3D 4 > + Type =3D IoTrapExTypeRead > + ByteEnable =3D 0x02 (BE is 0010b to trap only second byte of e= very > DWORD) > + ByteEnableMask =3D 0x00 (BEM doesn't mask any BE bit) > + 3. To trigger the TRAP for port 0x60 and 0x64 with BYTE write access: > + Address =3D 0x60 > + Length =3D 8 > + Type =3D IoTrapExTypeWrite > + ByteEnable =3D 0x01 (BE is 0001b to trap only first byte of ev= ery DWORD) > + ByteEnableMask =3D 0x00 (BEM doesn't mask any BE bit) > +**/ > +typedef struct { > + /** > + The Address must be dword alignment. > + **/ > + UINT16 Address; > + UINT16 Length; > + IO_TRAP_EX_DISPATCH_TYPE Type; > + /** > + Bitmap to enable trap for each byte of every dword alignment address= . > + The Io Trap Address must be dword alignment for ByteEnable. > + E.g. 0001b for first byte, 0010b for second byte, 1100b for third an= d fourth > byte. > + **/ > + UINT8 ByteEnable; > + /** > + ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b = for > any byte access. > + The Io Trap Address must be dword alignment for ByteEnableMask. > + **/ > + UINT8 ByteEnableMask; > +} IO_TRAP_EX_REGISTER_CONTEXT; > + > +/** > + Callback function for an PCH IO TRAP EX handler dispatch. > + > + @param[in] Address DWord-aligned address of the tra= pped > cycle. > + @param[in] ByteEnable This is the DWord-aligned byte e= nables > associated with the trapped cycle. > + A 1 in any bit location indicate= s that the > corresponding byte is enabled in the cycle. > + @param[in] WriteCycle TRUE =3D Write cycle; FALSE =3D = Read cycle > + @param[in] WriteData DWord of I/O write data. This fi= eld is > undefined after trapping a read cycle. > + The byte of WriteData is only va= lid if the > corresponding bits in ByteEnable is 1. > + E.g. > + If ByteEnable is 0001b, then onl= y first byte of > WriteData is valid. > + If ByteEnable is 0010b, then onl= y second byte of > WriteData is valid. > +**/ > +typedef > +VOID > +(EFIAPI *IO_TRAP_EX_DISPATCH_CALLBACK) ( > + IN UINT16 Address, > + IN UINT8 ByteEnable, > + IN BOOLEAN WriteCycle, > + IN UINT32 WriteData > + ); > + > +/** > + Register a new IO Trap Ex SMI dispatch function. > + The caller will provide information of IO trap setting via the context= . > + Please consider to use EfiSmmIoTrapDispatch2Protocol as possible. > + This is the function to extend the IoTrap capability, and it's expecte= d > + to handle the special ByteEnable and ByteEnableMask setting. > + This register function will occupy one IoTrap register if possible. > + And it only support one handler for one IoTrap event. > + The Address of context MUST NOT be 0, and MUST be dword alignment. > + The Length of context MUST not less than 4, and MUST be power of 2. > + The ByteEnable and ByteEnableMask MUST not be zero at the same time. > + if the IO Trap handler is not used. It also enable the IO Trap Range t= o > generate > + SMI. > + Caller must take care of reserving the IO addresses in ACPI. > + > + @param[in] This Pointer to the > IO_TRAP_EX_DISPATCH_PROTOCOL instance. > + @param[in] DispatchFunction Pointer to dispatch function to be > invoked for > + this SMI source. > + @param[in] RegisterContext Pointer to the dispatch function's con= text. > + The caller fills this context in befor= e calling > + the register function to indicate to t= he register > + function the IO trap Ex SMI source for= which the > dispatch > + function should be invoked. This MUST= not be > NULL. > + @param[out] DispatchHandle Handle of dispatch function. > + > + @retval EFI_SUCCESS The dispatch function has been success= fully > + registered and the SMI source has been= enabled. > + @retval EFI_OUT_OF_RESOURCES Insufficient resources are available > + @retval EFI_INVALID_PARAMETER Address requested is already in use. > + @retval EFI_ACCESS_DENIED Return access denied if the > SmmReadyToLock event has been triggered > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *IO_TRAP_EX_DISPATCH_REGISTER) ( > + IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, > + IN IO_TRAP_EX_DISPATCH_CALLBACK DispatchFunction, > + IN IO_TRAP_EX_REGISTER_CONTEXT *RegisterContext, > + OUT EFI_HANDLE *DispatchHandle > + ); > + > +/** > + Unregister a SMI source dispatch function. > + This function is unsupported. > + > + @param[in] This Pointer to the > IO_TRAP_EX_DISPATCH_PROTOCOL instance. > + @param[in] DispatchHandle Handle of dispatch function to deregis= ter. > + > + @retval EFI_UNSUPPORTED The function is unsupported. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *IO_TRAP_EX_DISPATCH_UNREGISTER) ( > + IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, > + IN EFI_HANDLE DispatchHandle > + ); > + > +/** > + Interface structure for the IO trap Extention protocol. > + This protocol exposes full IO TRAP capability for ByteEnable and > ByteEnableMask setting. > + Platform code should fully control the ByteEnable and ByteEnableMake > while using this protocol. > + > + Please consider to use EfiSmmIoTrapDispatch2Protocol as possible. > + This is the function to extend the IoTrap capability, and it's expecte= d > + to handle the special ByteEnable and ByteEnableMask setting. > + > + The protocol is low level, It returns PSTH trapped cycle. This might n= ot be > safe for multithread > + if more than one thread triggers the same IOTRAP at the same time. > +**/ > +struct _IO_TRAP_EX_DISPATCH_PROTOCOL { > + /** > + Register function for PCH IO TRAP EX DISPATCH PROTOCOL. > + The caller will provide information of IO trap setting via the conte= xt. > + Please consider to use EfiSmmIoTrapDispatch2Protocol as possible. > + This is the function to extend the IoTrap capability, and it's expec= ted > + to handle the special ByteEnable and ByteEnableMask setting. > + This register function will occupy one IoTrap register if possible. > + And it only support one handler for one IoTrap event. > + The Address of context MUST NOT be 0, and MUST be dword alignment. > + The Length of context MUST not less than 4, and MUST be power of 2. > + The ByteEnable and ByteEnableMask MUST not be zero at the same time. > + if the IO Trap handler is not used. It also enable the IO Trap Range= to > + generate SMI. > + **/ > + IO_TRAP_EX_DISPATCH_REGISTER Register; > + /** > + Unregister function for PCH IO TRAP EX DISPATCH PROTOCOL. > + **/ > + IO_TRAP_EX_DISPATCH_UNREGISTER UnRegister; > +}; > + > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispa= t > ch.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispa= t > ch.h > new file mode 100644 > index 0000000000..f3e788a2e1 > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispa= t > ch.h > @@ -0,0 +1,136 @@ > +/** @file > + APIs of PCH ACPI SMI Dispatch Protocol. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_ > +#define _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_ > + > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID gPchAcpiSmiDispatchProtocolGuid; > + > +// > +// Forward reference for ANSI C compatibility > +// > +typedef struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL > PCH_ACPI_SMI_DISPATCH_PROTOCOL; > + > +// > +// Member functions > +// > + > +/** > + Callback function for an PCH ACPI SMI handler dispatch. > + > + @param[in] DispatchHandle The unique handle assigned to th= is > handler by register function. > + > +**/ > +typedef > +VOID > +(EFIAPI *PCH_ACPI_SMI_DISPATCH_CALLBACK) ( > + IN EFI_HANDLE DispatchHandle > + ); > + > +/** > + Register a child SMI source dispatch function for PCH ACPI SMI events. > + > + @param[in] This Protocol instance pointer. > + @param[in] DispatchFunction Pointer to dispatch function to = be > invoked for > + this SMI source > + @param[out] DispatchHandle Handle of dispatch function, for > when interfacing > + with the parent SMM driver. > + > + @retval EFI_SUCCESS The dispatch function has been > successfully > + registered and the SMI source ha= s been > enabled. > + @retval EFI_DEVICE_ERROR The driver was unable to enable = the > SMI source. > + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or > SMM) to manage this child. > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_ACPI_SMI_DISPATCH_REGISTER) ( > + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, > + IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction, > + OUT EFI_HANDLE *DispatchHandle > + ); > + > +/** > + Unregister a child SMI source dispatch function with a parent ACPI SMM > driver > + > + @param[in] This Protocol instance pointer. > + @param[in] DispatchHandle Handle of dispatch function to > deregister. > + > + @retval EFI_SUCCESS The dispatch function has been > successfully > + unregistered and the SMI source = has been > disabled > + if there are no other registered= child dispatch > + functions for this SMI source. > + @retval EFI_INVALID_PARAMETER Handle is invalid. > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_ACPI_SMI_DISPATCH_UNREGISTER) ( > + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, > + IN EFI_HANDLE DispatchHandle > + ); > + > +/** > + Interface structure for PCH ACPI SMIs Dispatch Protocol > + The PCH ACPI SMI DISPATCH PROTOCOL provides the ability to dispatch > function for PCH ACPI related SMIs. > + It contains SMI types of Pme, RtcAlarm, PmeB0, and Time overflow. > +**/ > +struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL { > + /** > + This member specifies the revision of this structure. This field is = used to > + indicate backwards compatible changes to the protocol. > + **/ > + UINT8 Revision; > + /** > + Smi unregister function for PCH ACPI SMI DISPATCH PROTOCOL. > + **/ > + PCH_ACPI_SMI_DISPATCH_UNREGISTER UnRegister; > + /** > + Pme > + The event is triggered by hardware when the PME# signal goes active. > + Additionally, the event is only triggered when SCI_EN is not set. > + **/ > + PCH_ACPI_SMI_DISPATCH_REGISTER PmeRegister; > + /** > + PmeB0 > + The event is triggered PCH when any internal device with PCI Power > Management > + capabilities on bus 0 asserts the equivalent of the PME# signal. > + Additionally, the event is only triggered when SCI_EN is not set. > + The following are internal devices which can set this bit: > + Intel HD Audio, Intel Management Engine "maskable" wake events, > Integrated LAN, > + SATA, xHCI, Intel SST > + **/ > + PCH_ACPI_SMI_DISPATCH_REGISTER PmeB0Register; > + /** > + RtcAlarm > + The event is triggered by hardware when the RTC generates an alarm > + (assertion of the IRQ8# signal). > + **/ > + PCH_ACPI_SMI_DISPATCH_REGISTER RtcAlarmRegister; > + /** > + TmrOverflow > + The event is triggered any time bit 22 of the 24-bit timer goes high > + (bits are numbered from 0 to 23). > + This will occur every 2.3435 seconds. When the TMROF_EN bit (ABASE + > 02h, bit 0) is set, > + then the setting of the TMROF_STS bit will additionally generate an = SMI# > + Additionally, the event is only triggered when SCI_EN is not set. > + **/ > + PCH_ACPI_SMI_DISPATCH_REGISTER TmrOverflowRegister; > +}; > + > +/** > + PCH ACPI SMI dispatch revision number > + > + Revision 1: Initial version > +**/ > +#define PCH_ACPI_SMI_DISPATCH_REVISION 1 > + > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning.h > new file mode 100644 > index 0000000000..45fae6e2d5 > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning.h > @@ -0,0 +1,68 @@ > +/** @file > + PCH eMMC HS400 Tuning Protocol > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_EMMC_TUNING_PROTOCOL_H_ > +#define _PCH_EMMC_TUNING_PROTOCOL_H_ > + > +#define PCH_EMMC_TUNING_PROTOCOL_REVISION 1 > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID gPchEmmcTuningProtocolGuid; > + > +// > +// Forward declaration for PCH_EMMC_TUNING_PROTOCOL > +// > +typedef struct _PCH_EMMC_TUNING_PROTOCOL > PCH_EMMC_TUNING_PROTOCOL; > + > +/** > + This structure decribes the required Emmc info for HS400 tuning > +**/ > +typedef struct { > + EFI_HANDLE PartitionHandle; ///< eMMC partition hand= le for > block read/write > + EFI_LBA Lba; ///< Logical Block Addre= ss for HS400 > Tuning block read/write > + UINT32 RelativeDevAddress; ///< Device system addre= ss, > dynamically assigned by the host during initialization. > + UINT8 HS200BusWidth; ///< The value to be > programmed for BUS_WIDTH[183] byte > +} EMMC_INFO; > + > +/// > +/// This structure describes the return value after HS400 tuning > +/// > +typedef struct { > + UINT8 Hs400DataValid; ///< Set if Hs400 Tuning Data is valid= after > tuning > + UINT8 Hs400RxStrobe1Dll; ///< Rx Strobe Delay Control - Rx Stro= be > Delay DLL 1 (HS400 Mode) > + UINT8 Hs400TxDataDll; ///< Tx Data Delay Control 1 - Tx Data= Delay > (HS400 Mode) > +} EMMC_TUNING_DATA; > + > +/// > +/// EMMC HS400 TUNING INTERFACE > +/// > +typedef EFI_STATUS (EFIAPI *EMMC_TUNE) ( > + IN PCH_EMMC_TUNING_PROTOCOL *This, ///< This > pointer to PCH_EMMC_TUNING_PROTOCOL > + /** > + Revision parameter is used to verify the layout of EMMC_INFO and > TUNINGDATA. > + If the revision is not matched, means the revision of EMMC_INFO and > TUNINGDATA is not matched. > + And function will return immediately. > + **/ > + IN UINT8 Revision, > + IN EMMC_INFO *EmmcInfo, ///< Pointer= to > EMMC_INFO > + OUT EMMC_TUNING_DATA *EmmcTuningData ///< Pointer > to EMMC_TUNING_DATA > +); > + > +/** > + PCH EMMC TUNING PROTOCOL INTERFACE > + Platform code uses this protocol to configure Emmc Hs400 mode, by pass= ing > the EMMC_INFO information. > + PCH will setting EMMC controller based on EMMC_INFO and return > EMMC_TUNING_DATA to platform code. > + Platform should keep values of EMMC_TUNING_DATA and uses to configure > EMMC through policies, to > + prevent from doing EMMC tuning every boot. > +**/ > +struct _PCH_EMMC_TUNING_PROTOCOL { > + EMMC_TUNE EmmcTune; ///< Emmc Hs400 Tuning Interface > +}; > + > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispa= t > ch.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispa= t > ch.h > new file mode 100644 > index 0000000000..9a180b4285 > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispa= t > ch.h > @@ -0,0 +1,146 @@ > +/** @file > + SmmEspiDispatch Protocol > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_ > +#define _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_ > + > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID gPchEspiSmiDispatchProtocolGuid; > + > +// > +// Forward reference for ANSI C compatibility > +// > +typedef struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL > PCH_ESPI_SMI_DISPATCH_PROTOCOL; > + > +// > +// Member functions > +// > + > +/** > + Callback function for an PCH eSPI SMI handler dispatch. > + > + @param[in] DispatchHandle The unique handle assigned to th= is > handler by register function. > +**/ > +typedef > +VOID > +(EFIAPI *PCH_ESPI_SMI_DISPATCH_CALLBACK) ( > + IN EFI_HANDLE DispatchHandle > + ); > + > +/** > + Generic function to register different types of eSPI SMI types > + > + @param[in] This Not used > + @param[in] DispatchFunction The callback to execute > + @param[out] DispatchHandle The handle for this callback registratio= n > + > + @retval EFI_SUCCESS Registration successful > + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe eve= nt > has been triggered > + @retval others Registration failed > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_ESPI_SMI_REGISTER) ( > + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, > + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, > + OUT EFI_HANDLE *DispatchHandle > + ); > + > +/** > + eSPI SMI Dispatch Protocol instance to unregister a callback based on = handle > + > + @param[in] This Not used > + @param[in] DispatchHandle Handle acquired during registratio= n > + > + @retval EFI_SUCCESS Unregister successful > + @retval EFI_INVALID_PARAMETER DispatchHandle is null > + @retval EFI_INVALID_PARAMETER DispatchHandle's forward link has > bad pointer > + @retval EFI_INVALID_PARAMETER DispatchHandle does not exist in > database > + @retval EFI_ACCESS_DENIED Unregistration is done after end o= f > DXE > +**/ > + > +typedef > +EFI_STATUS > +(EFIAPI *PCH_ESPI_SMI_UNREGISTER) ( > + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, > + IN EFI_HANDLE DispatchHandle > + ); > + > +/** > + Interface structure for PCH eSPI SMIs Dispatch Protocol > + The PCH ESPI SMI DISPATCH PROTOCOL provides the ability to dispatch > function for PCH eSPI related SMIs. > + It contains SMI types of BiosWr, EcAssertedVw, and eSPI Master asserte= d > SMIs > +**/ > +struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL { > + /** > + This member specifies the revision of this structure. This field is = used to > + indicate backwards compatible changes to the protocol. > + **/ > + UINT8 Revision; > + /** > + Unregister eSPI SMI events > + **/ > + PCH_ESPI_SMI_UNREGISTER UnRegister; > + /** > + Register a BIOS Write Protect event > + **/ > + PCH_ESPI_SMI_REGISTER BiosWrProtectRegister; > + /** > + Register a BIOS Write Report event > + **/ > + PCH_ESPI_SMI_REGISTER BiosWrReportRegister; > + /** > + Register a Peripheral Channel Non Fatal Error event > + **/ > + PCH_ESPI_SMI_REGISTER PcErrNonFatalRegister; > + /** > + Register a Peripheral Channel Fatal Error event > + **/ > + PCH_ESPI_SMI_REGISTER PcErrFatalRegister; > + /** > + Register a Virtual Wire Non Fatal Error event > + **/ > + PCH_ESPI_SMI_REGISTER VwErrNonFatalRegister; > + /** > + Register a Virtual Wire Fatal Error event > + **/ > + PCH_ESPI_SMI_REGISTER VwErrFatalRegister; > + /** > + Register a Flash Channel Non Fatal Error event > + **/ > + PCH_ESPI_SMI_REGISTER FlashErrNonFatalRegister; > + /** > + Register a Flash Channel Fatal Error event > + **/ > + PCH_ESPI_SMI_REGISTER FlashErrFatalRegister; > + /** > + Register a Link Error event > + **/ > + PCH_ESPI_SMI_REGISTER LnkErrType1Register; > + /** > + Register a SMI handler for Espi slaver > + This routine will also lock down ESPI_SMI_LOCK bit after registratio= n and > prevent > + this handler from unregistration. > + On platform that supports more than 1 device through another chip se= lect > (SPT-H), > + the SMI handler itself needs to inspect both the eSPI devices' inter= rupt > status registers > + (implementation specific for each Slave) in order to identify and se= rvice > the cause. > + After servicing it, it has to clear the Slaves' internal SMI# status= registers > + **/ > + PCH_ESPI_SMI_REGISTER EspiSlaveSmiRegister; > +}; > + > +/** > + PCH ESPI SMI dispatch revision number > + > + Revision 1: Initial version > +**/ > +#define PCH_ESPI_SMI_DISPATCH_REVISION 1 > + > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispa= tc > h.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispa= t > ch.h > new file mode 100644 > index 0000000000..c5e8bc3f28 > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispa= t > ch.h > @@ -0,0 +1,132 @@ > +/** @file > + APIs of PCH PCIE SMI Dispatch Protocol. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_ > +#define _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_ > + > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID gPchPcieSmiDispatchProtocolGuid; > + > +// > +// Forward reference for ANSI C compatibility > +// > +typedef struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL > PCH_PCIE_SMI_DISPATCH_PROTOCOL; > + > +// > +// Member functions > +// > + > +typedef struct { > + UINT8 RpIndex; ///< Root port index (0= -based), 0: > RP1, 1: RP2, n: RP(N+1) > + UINT8 BusNum; ///< Root port pci bus = number > + UINT8 DevNum; ///< Root port pci devi= ce number > + UINT8 FuncNum; ///< Root port pci func= tion > number > +} PCH_PCIE_SMI_RP_CONTEXT; > + > +/** > + Callback function for an PCH PCIE RP SMI handler dispatch. > + > + @param[in] DispatchHandle The unique handle assigned to th= is > handler by register function. > + @param[in] RpContext Pointer of PCH PCIE Root Port co= ntext. > + > +**/ > +typedef > +VOID > +(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_CALLBACK) ( > + IN EFI_HANDLE DispatchHandle, > + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext > + ); > + > +/** > + Register a child SMI source dispatch function for PCH PCIERP SMI event= s. > + > + @param[in] This Protocol instance pointer. > + @param[in] DispatchFunction Pointer to dispatch function to = be > invoked for > + this SMI source > + @param[in] RpIndex Refer to PCH PCIE Root Port inde= x. > + 0: RP1, 1: RP2, n: RP(N+1) > + @param[out] DispatchHandle Handle of dispatch function, for > when interfacing > + with the parent SMM driver. > + > + @retval EFI_SUCCESS The dispatch function has been > successfully > + registered and the SMI source ha= s been > enabled. > + @retval EFI_DEVICE_ERROR The driver was unable to enable = the > SMI source. > + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or > SMM) to manage this child. > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_REGISTER) ( > + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, > + IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction, > + IN UINTN RpIndex, > + OUT EFI_HANDLE *DispatchHandle > + ); > + > +/** > + Unregister a child SMI source dispatch function with a parent PCIE SMM > driver > + > + @param[in] This Protocol instance pointer. > + @param[in] DispatchHandle Handle of dispatch function to > deregister. > + > + @retval EFI_SUCCESS The dispatch function has been > successfully > + unregistered and the SMI source = has been > disabled > + if there are no other registered= child dispatch > + functions for this SMI source. > + @retval EFI_INVALID_PARAMETER Handle is invalid. > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_PCIE_SMI_DISPATCH_UNREGISTER) ( > + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, > + IN EFI_HANDLE DispatchHandle > + ); > + > +/** > + Interface structure for PCH PCIE SMIs Dispatch Protocol > + The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch > function for PCH PCIE related SMIs. > + It contains SMI types of HotPlug, LinkActive, and Link EQ. > +**/ > +struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL { > + /** > + This member specifies the revision of this structure. This field is = used to > + indicate backwards compatible changes to the protocol. > + **/ > + UINT8 Revision; > + /** > + Smi unregister function for PCH PCIE SMI DISPATCH PROTOCOL. > + **/ > + PCH_PCIE_SMI_DISPATCH_UNREGISTER UnRegister; > + /** > + PcieRpXHotPlug > + The event is triggered when PCIE root port Hot-Plug Presence Detect. > + **/ > + PCH_PCIE_SMI_RP_DISPATCH_REGISTER HotPlugRegister; > + /** > + PcieRpXLinkActive > + The event is triggered when Hot-Plug Link Active State Changed. > + **/ > + PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkActiveRegister; > + /** > + PcieRpXLinkEq > + The event is triggered when Device Requests Software Link Equalizati= on. > + **/ > + PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkEqRegister; > +}; > + > +/** > + PCH PCIE SMI dispatch revision number > + > + Revision 1: Initial version > +**/ > +#define PCH_PCIE_SMI_DISPATCH_REVISION 1 > + > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h > new file mode 100644 > index 0000000000..ff35b43b61 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h > @@ -0,0 +1,42 @@ > +/** @file > + Interface definition details between Pch and platform drivers during D= XE > phase. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_POLICY_H_ > +#define _PCH_POLICY_H_ > + > +#include > +#include > +#include > +#include > + > +extern EFI_GUID gPchPolicyProtocolGuid; > + > +#define PCH_POLICY_PROTOCOL_REVISION 1 > + > + > +/** > + PCH DXE Policy > + > + The PCH_POLICY_PROTOCOL producer drvier is recommended to > + set all the PCH_POLICY_PROTOCOL size buffer zero before init any membe= r > parameter, > + this clear step can make sure no random value for those unknown new > version parameters. > + > + Make sure to update the Revision if any change to the protocol, includ= ing > the existing > + internal structure definations.\n > + Note: Here revision will be bumped up when adding/removing any config > block under this structure.\n > + Revision 1: > + - Initial version. > +**/ > +typedef struct { > + CONFIG_BLOCK_TABLE_HEADER TableHeader; > +/* > + Individual Config Block Structures are added here in memory as part of > AddConfigBlock() > +*/ > +} PCH_POLICY_PROTOCOL; > + > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchReset.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchReset.h > new file mode 100644 > index 0000000000..4c49d082fc > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchReset.h > @@ -0,0 +1,42 @@ > +/** @file > + PCH Reset Protocol > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_RESET_PROTOCOL_H_ > +#define _PCH_RESET_PROTOCOL_H_ > + > +// > +// Member functions > +// > +/** > + Execute call back function for Pch Reset. > + > + @param[in] ResetType Reset Types which includes GlobalReset= . > + @param[in] ResetTypeGuid Pointer to an EFI_GUID, which is the R= eset > Type Guid. > + > + @retval EFI_SUCCESS The callback function has been done > successfully > + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback prot= ocol. > Or, none of > + callback protocol is installed. > + @retval Others Do not do any reset from PCH > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_RESET_CALLBACK) ( > + IN EFI_RESET_TYPE ResetType, > + IN EFI_GUID *ResetTypeGuid > + ); > + > +/** > + This protocol is used to execute PCH Reset from the host controller. > + If drivers need to run their callback function right before issuing th= e PCH > Reset, > + they can install PCH Reset Callback Protocol before PCH Reset DXE driv= er to > achieve that. > +**/ > +typedef struct { > + PCH_RESET_CALLBACK ResetCallback; > +} PCH_RESET_CALLBACK_PROTOCOL; > + > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.= h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.= h > new file mode 100644 > index 0000000000..6fdfed1de7 > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.= h > @@ -0,0 +1,134 @@ > +/** @file > + APIs of PCH SMI Dispatch Protocol. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_SMI_DISPATCH_PROTOCOL_H_ > +#define _PCH_SMI_DISPATCH_PROTOCOL_H_ > + > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID gPchSmiDispatchProtocolGuid; > + > +// > +// Forward reference for ANSI C compatibility > +// > +typedef struct _PCH_SMI_DISPATCH_PROTOCOL > PCH_SMI_DISPATCH_PROTOCOL; > + > +// > +// Member functions > +// > + > +/** > + Callback function for an PCH SMI handler dispatch. > + > + @param[in] DispatchHandle The unique handle assigned to th= is > handler by register function. > + > +**/ > +typedef > +VOID > +(EFIAPI *PCH_SMI_DISPATCH_CALLBACK) ( > + IN EFI_HANDLE DispatchHandle > + ); > + > +/** > + Register a child SMI source dispatch function for specific PCH SMI dis= patch > event. > + > + @param[in] This Protocol instance pointer. > + @param[in] DispatchFunction Pointer to dispatch function to = be > invoked for > + this SMI source > + @param[out] DispatchHandle Handle of dispatch function, for > when interfacing > + with the parent SMM driver. > + > + @retval EFI_SUCCESS The dispatch function has been > successfully > + registered and the SMI source ha= s been > enabled. > + @retval EFI_DEVICE_ERROR The driver was unable to enable = the > SMI source. > + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or > SMM) to manage this child. > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SMI_DISPATCH_REGISTER) ( > + IN PCH_SMI_DISPATCH_PROTOCOL *This, > + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, > + OUT EFI_HANDLE *DispatchHandle > + ); > + > +/** > + Unregister a child SMI source dispatch function with a parent SMM driv= er > + > + @param[in] This Protocol instance pointer. > + @param[in] DispatchHandle Handle of dispatch function to > deregister. > + > + @retval EFI_SUCCESS The dispatch function has been > successfully > + unregistered and the SMI source = has been > disabled > + if there are no other registered= child dispatch > + functions for this SMI source. > + @retval EFI_INVALID_PARAMETER Handle is invalid. > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SMI_DISPATCH_UNREGISTER) ( > + IN PCH_SMI_DISPATCH_PROTOCOL *This, > + IN EFI_HANDLE DispatchHandle > + ); > + > +/** > + Interface structure for PCH specific SMIs Dispatch Protocol > + The PCH SMI DISPATCH PROTOCOL provides the ability to dispatch functio= n > for PCH misc SMIs. > + It contains legacy SMIs and new PCH SMI types like: > + SerialIrq, McSmi, Smbus, ... > +**/ > +struct _PCH_SMI_DISPATCH_PROTOCOL { > + /** > + This member specifies the revision of this structure. This field is = used to > + indicate backwards compatible changes to the protocol. > + **/ > + UINT8 Revision; > + /** > + Smi unregister function for PCH SMI DISPATCH PROTOCOL. > + **/ > + PCH_SMI_DISPATCH_UNREGISTER UnRegister; > + /** > + SerialIrq > + The event is triggered while the SMI# was caused by the SERIRQ decod= er. > + **/ > + PCH_SMI_DISPATCH_REGISTER SerialIrqRegister; > + /** > + McSmi > + The event is triggered if there has been an access to the power > management > + microcontroller range (62h or 66h) and the Microcontroller Decode En= able > #1 bit > + in the LPC Bridge I/O Enables configuration register is 1 . > + **/ > + PCH_SMI_DISPATCH_REGISTER McSmiRegister; > + /** > + SmBus > + The event is triggered while the SMI# was caused by: > + 1. The SMBus Slave receiving a message that an SMI# should be caused= , or > + 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set an= d > the > + SMBALERT_DIS bit is cleared, or > + 3. The SMBus Slave receiving a Host Notify message and the > HOST_NOTIFY_INTREN and > + the SMB_SMI_EN bits are set, or > + 4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 > state. > + **/ > + PCH_SMI_DISPATCH_REGISTER SmbusRegister; > + /** > + SPI Asynchronous > + When registered, the flash controller will generate an SMI when it b= locks > a BIOS write or erase. > + **/ > + PCH_SMI_DISPATCH_REGISTER SpiAsyncRegister; > +}; > + > +/** > + PCH SMI dispatch revision number > + > + Revision 1: Initial version > +**/ > +#define PCH_SMI_DISPATCH_REVISION 1 > + > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapCo > ntrol.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapCo > ntrol.h > new file mode 100644 > index 0000000000..73386a570e > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapCo > ntrol.h > @@ -0,0 +1,67 @@ > +/** @file > + PCH SMM IO Trap Control Protocol > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_SMM_IO_TRAP_CONTROL_H_ > +#define _PCH_SMM_IO_TRAP_CONTROL_H_ > + > + > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID gPchSmmIoTrapControlGu= id; > + > +// > +// Forward reference for ANSI C compatibility > +// > +typedef struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL > PCH_SMM_IO_TRAP_CONTROL_PROTOCOL; > + > +// > +// Related Definitions > +// > + > +// > +// Member functions > +// > + > +/** > + The Prototype of Pause and Resume IoTrap callback function. > + > + @param[in] This Pointer to the > PCH_SMM_IO_TRAP_CONTROL_PROTOCOL instance. > + @param[in] DispatchHandle Handle of the child service to change > state. > + > + @retval EFI_SUCCESS This operation is complete. > + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. > + @retval EFI_ACCESS_DENIED The SMI status is alrady > PAUSED/RESUMED. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SMM_IO_TRAP_CONTROL_FUNCTION) ( > + IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL * This, > + IN EFI_HANDLE DispatchHandle > + ); > + > +/** > + Interface structure for the SMM IO trap pause and resume protocol > + This protocol provides the functions to runtime control the IoTrap SMI > enabled/disable. > + This applys the capability to the DispatchHandle which returned by IoT= rap > callback > + registration, and the DispatchHandle which must be MergeDisable =3D TR= UE > and Address !=3D 0. > + Besides, when S3 resuem, it only restores the state of IoTrap callback > registration. > + The Paused/Resume state won't be restored after S3 resume. > +**/ > +struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL { > + /** > + This runtime pauses a registered IoTrap handler. > + **/ > + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Pause; > + /** > + This runtime resumes a registered IoTrap handler. > + **/ > + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Resume; > +}; > + > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicT= i > merControl.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicT= i > merControl.h > new file mode 100644 > index 0000000000..06ddc3e1cd > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicT= i > merControl.h > @@ -0,0 +1,67 @@ > +/** @file > + PCH SMM Periodic Timer Control Protocol > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ > +#define _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ > + > + > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID > gPchSmmPeriodicTimerControlGuid; > + > +// > +// Forward reference for ANSI C compatibility > +// > +typedef struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL > PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL; > + > +// > +// Related Definitions > +// > + > +// > +// Member functions > +// > + > +/** > + The Prototype of Pause and Resume SMM PERIODIC TIMER function. > + > + @param[in] This Pointer to the > PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL instance. > + @param[in] DispatchHandle Handle of the child service to c= hange > state. > + > + @retval EFI_SUCCESS This operation is complete. > + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. > + @retval EFI_ACCESS_DENIED The SMI status is alrady > PAUSED/RESUMED. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION) ( > + IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This, > + IN EFI_HANDLE DispatchHandle > + ); > + > +/** > + Interface structure for the SMM PERIODIC TIMER pause and resume > protocol > + This protocol provides the functions to runtime control the SM periodi= c > timer enabled/disable. > + This applies the capability to the DispatchHandle which returned by SM= M > periodic timer callback > + registration. > + Besides, when S3 resume, it only restores the state of callback regist= ration. > + The Paused/Resume state won't be restored after S3 resume. > +**/ > +struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL { > + /** > + This runtime pauses the registered periodic timer handler. > + **/ > + PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Pause; > + /** > + This runtime resumes the registered periodic timer handler. > + **/ > + PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Resume; > +}; > + > +#endif // _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispat= c > h.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispat= c > h.h > new file mode 100644 > index 0000000000..d397712092 > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispat= c > h.h > @@ -0,0 +1,152 @@ > +/** @file > + APIs of PCH TCO SMI Dispatch Protocol. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_ > +#define _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_ > + > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID gPchTcoSmiDispatchProtocolGuid; > + > +// > +// Forward reference for ANSI C compatibility > +// > +typedef struct _PCH_TCO_SMI_DISPATCH_PROTOCOL > PCH_TCO_SMI_DISPATCH_PROTOCOL; > + > +// > +// Member functions > +// > + > +/** > + Callback function for an PCH TCO SMI handler dispatch. > + > + @param[in] DispatchHandle The unique handle assigned to th= is > handler by register function. > + > +**/ > +typedef > +VOID > +(EFIAPI *PCH_TCO_SMI_DISPATCH_CALLBACK) ( > + IN EFI_HANDLE DispatchHandle > + ); > + > +/** > + Register a child SMI source dispatch function for PCH TCO SMI events. > + > + @param[in] This Protocol instance pointer. > + @param[in] DispatchFunction Pointer to dispatch function to = be > invoked for > + this SMI source > + @param[out] DispatchHandle Handle of dispatch function, for > when interfacing > + with the parent SMM driver. > + > + @retval EFI_SUCCESS The dispatch function has been > successfully > + registered and the SMI source ha= s been > enabled. > + @retval EFI_DEVICE_ERROR The driver was unable to enable = the > SMI source. > + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or > SMM) to manage this child. > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_TCO_SMI_DISPATCH_REGISTER) ( > + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, > + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, > + OUT EFI_HANDLE *DispatchHandle > + ); > + > +/** > + Unregister a child SMI source dispatch function with a parent TCO SMM > driver > + > + @param[in] This Protocol instance pointer. > + @param[in] DispatchHandle Handle of dispatch function to > deregister. > + > + @retval EFI_SUCCESS The dispatch function has been > successfully > + unregistered and the SMI source = has been > disabled > + if there are no other registered= child dispatch > + functions for this SMI source. > + @retval EFI_INVALID_PARAMETER Handle is invalid. > + @retval EFI_ACCESS_DENIED Return access denied if the EndO= fDxe > event has been triggered > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_TCO_SMI_DISPATCH_UNREGISTER) ( > + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, > + IN EFI_HANDLE DispatchHandle > + ); > + > +/** > + Interface structure for PCH TCO SMIs Dispatch Protocol > + The PCH TCO SMI DISPATCH PROTOCOL provides the ability to dispatch > function for PCH TCO related SMIs. > + It contains SMI types of Mch, TcoTimeout, OsTco, Nmi, IntruderDectect,= and > BiowWp. > +**/ > +struct _PCH_TCO_SMI_DISPATCH_PROTOCOL { > + /** > + This member specifies the revision of this structure. This field is = used to > + indicate backwards compatible changes to the protocol. > + **/ > + UINT8 Revision; > + /** > + Smi unregister function for PCH TCO SMI DISPATCH PROTOCOL. > + **/ > + PCH_TCO_SMI_DISPATCH_UNREGISTER UnRegister; > + /** > + Mch > + The event is triggered when PCH received a DMI special cycle message > using DMI indicating that > + it wants to cause an SMI. > + The software must read the processor to determine the reason for the= SMI. > + **/ > + PCH_TCO_SMI_DISPATCH_REGISTER MchRegister; > + /** > + TcoTimeout > + The event is triggered by PCH to indicate that the SMI was caused by= the > TCO timer reaching 0. > + **/ > + PCH_TCO_SMI_DISPATCH_REGISTER TcoTimeoutRegister; > + /** > + OsTco > + The event is triggered when software caused an SMI# by writing to th= e > TCO_DAT_IN register (TCOBASE + 02h). > + **/ > + PCH_TCO_SMI_DISPATCH_REGISTER OsTcoRegister; > + /** > + Nmi > + The event is triggered by the PCH when an SMI# occurs because an eve= nt > occurred that would otherwise have > + caused an NMI (because NMI2SMI_EN is set) > + **/ > + PCH_TCO_SMI_DISPATCH_REGISTER NmiRegister; > + /** > + IntruderDectect > + The event is triggered by PCH to indicate that an intrusion was dete= cted. > + **/ > + PCH_TCO_SMI_DISPATCH_REGISTER IntruderDetRegister; > + /** > + SpiBiosWp > + This event is triggered when SMI# was caused by the TCO logic and > + SPI flash controller asserted Synchronous SMI by BIOS lock enable se= t. > + **/ > + PCH_TCO_SMI_DISPATCH_REGISTER SpiBiosWpRegister; > + /** > + LpcBiosWp > + This event is triggered when SMI# was caused by the TCO logic and > + LPC/eSPI BIOS lock enable set. > + **/ > + PCH_TCO_SMI_DISPATCH_REGISTER LpcBiosWpRegister; > + /** > + NewCentury > + This event is triggered when SMI# was caused by the TCO logic and > + year of RTC date rolls over a century (99 to 00). > + **/ > + PCH_TCO_SMI_DISPATCH_REGISTER NewCenturyRegister; > +}; > + > +/** > + PCH TCO SMI dispatch revision number > + > + Revision 1: Initial version > + Revision 2: Add NEWCENTURY support > +**/ > +#define PCH_TCO_SMI_DISPATCH_REVISION 2 > + > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h > new file mode 100644 > index 0000000000..ece65cd729 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h > @@ -0,0 +1,15 @@ > +/** @file > + SmmSmbus Protocol > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef __EFI_SMM_SMBUS_PROTOCOL_H__ > +#define __EFI_SMM_SMBUS_PROTOCOL_H__ > + > +extern EFI_GUID gEfiSmmSmbusProtocolGuid; > + > +#endif > + > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Spi.= h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Spi.h > new file mode 100644 > index 0000000000..22df7fe351 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Spi.h > @@ -0,0 +1,295 @@ > +/** @file > + This file defines the PCH SPI Protocol which implements the > + Intel(R) PCH SPI Host Controller Compatibility Interface. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_SPI_PROTOCOL_H_ > +#define _PCH_SPI_PROTOCOL_H_ > + > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID gPchSpiProtocolGuid; > +extern EFI_GUID gPchSmmSpiProtocolGuid; > + > +// > +// Forward reference for ANSI C compatibility > +// > +typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL; > + > +// > +// SPI protocol data structures and definitions > +// > + > +/** > + Flash Region Type > +**/ > +typedef enum { > + FlashRegionDescriptor, > + FlashRegionBios, > + FlashRegionMe, > + FlashRegionGbE, > + FlashRegionPlatformData, > + FlashRegionDer, > + FlashRegionEC =3D 8, > + FlashRegionAll, > + FlashRegionMax > +} FLASH_REGION_TYPE; > + > +// > +// Protocol member functions > +// > + > +/** > + Read data from the flash part. > + > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. > + @param[in] FlashRegionType The Flash Region type for flash cycle > which is listed in the Descriptor. > + @param[in] Address The Flash Linear Address must fall wit= hin a > region for which BIOS has access permissions. > + @param[in] ByteCount Number of bytes in the data portion of= the > SPI cycle. > + @param[out] Buffer The Pointer to caller-allocated buffer > containing the dada received. > + It is the caller's responsibility to m= ake sure Buffer is > large enough for the total number of bytes read. > + > + @retval EFI_SUCCESS Command succeed. > + @retval EFI_INVALID_PARAMETER The parameters specified are not valid= . > + @retval EFI_DEVICE_ERROR Device error, command aborts > abnormally. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SPI_FLASH_READ) ( > + IN PCH_SPI_PROTOCOL *This, > + IN FLASH_REGION_TYPE FlashRegionType, > + IN UINT32 Address, > + IN UINT32 ByteCount, > + OUT UINT8 *Buffer > + ); > + > +/** > + Write data to the flash part. Remark: Erase may be needed before write= to > the flash part. > + > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. > + @param[in] FlashRegionType The Flash Region type for flash cycle > which is listed in the Descriptor. > + @param[in] Address The Flash Linear Address must fall wit= hin a > region for which BIOS has access permissions. > + @param[in] ByteCount Number of bytes in the data portion of= the > SPI cycle. > + @param[in] Buffer Pointer to caller-allocated buffer con= taining > the data sent during the SPI cycle. > + > + @retval EFI_SUCCESS Command succeed. > + @retval EFI_INVALID_PARAMETER The parameters specified are not valid= . > + @retval EFI_DEVICE_ERROR Device error, command aborts > abnormally. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SPI_FLASH_WRITE) ( > + IN PCH_SPI_PROTOCOL *This, > + IN FLASH_REGION_TYPE FlashRegionType, > + IN UINT32 Address, > + IN UINT32 ByteCount, > + IN UINT8 *Buffer > + ); > + > +/** > + Erase some area on the flash part. > + > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. > + @param[in] FlashRegionType The Flash Region type for flash cycle > which is listed in the Descriptor. > + @param[in] Address The Flash Linear Address must fall wit= hin a > region for which BIOS has access permissions. > + @param[in] ByteCount Number of bytes in the data portion of= the > SPI cycle. > + > + @retval EFI_SUCCESS Command succeed. > + @retval EFI_INVALID_PARAMETER The parameters specified are not valid= . > + @retval EFI_DEVICE_ERROR Device error, command aborts > abnormally. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SPI_FLASH_ERASE) ( > + IN PCH_SPI_PROTOCOL *This, > + IN FLASH_REGION_TYPE FlashRegionType, > + IN UINT32 Address, > + IN UINT32 ByteCount > + ); > + > +/** > + Read SFDP data from the flash part. > + > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. > + @param[in] ComponentNumber The Componen Number for chip select > + @param[in] Address The starting byte address for SFDP dat= a read. > + @param[in] ByteCount Number of bytes in SFDP data portion o= f the > SPI cycle > + @param[out] SfdpData The Pointer to caller-allocated buffer > containing the SFDP data received > + It is the caller's responsibility to m= ake sure Buffer is > large enough for the total number of bytes read > + > + @retval EFI_SUCCESS Command succeed. > + @retval EFI_INVALID_PARAMETER The parameters specified are not valid= . > + @retval EFI_DEVICE_ERROR Device error, command aborts > abnormally. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SPI_FLASH_READ_SFDP) ( > + IN PCH_SPI_PROTOCOL *This, > + IN UINT8 ComponentNumber, > + IN UINT32 Address, > + IN UINT32 ByteCount, > + OUT UINT8 *SfdpData > + ); > + > +/** > + Read Jedec Id from the flash part. > + > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. > + @param[in] ComponentNumber The Componen Number for chip select > + @param[in] ByteCount Number of bytes in JedecId data portio= n of > the SPI cycle, the data size is 3 typically > + @param[out] JedecId The Pointer to caller-allocated buffer > containing JEDEC ID received > + It is the caller's responsibility to m= ake sure Buffer is > large enough for the total number of bytes read. > + > + @retval EFI_SUCCESS Command succeed. > + @retval EFI_INVALID_PARAMETER The parameters specified are not valid= . > + @retval EFI_DEVICE_ERROR Device error, command aborts > abnormally. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) ( > + IN PCH_SPI_PROTOCOL *This, > + IN UINT8 ComponentNumber, > + IN UINT32 ByteCount, > + OUT UINT8 *JedecId > + ); > + > +/** > + Write the status register in the flash part. > + > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. > + @param[in] ByteCount Number of bytes in Status data portion= of > the SPI cycle, the data size is 1 typically > + @param[in] StatusValue The Pointer to caller-allocated buffer > containing the value of Status register writing > + > + @retval EFI_SUCCESS Command succeed. > + @retval EFI_INVALID_PARAMETER The parameters specified are not valid= . > + @retval EFI_DEVICE_ERROR Device error, command aborts > abnormally. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) ( > + IN PCH_SPI_PROTOCOL *This, > + IN UINT32 ByteCount, > + IN UINT8 *StatusValue > + ); > + > +/** > + Read status register in the flash part. > + > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. > + @param[in] ByteCount Number of bytes in Status data portion= of > the SPI cycle, the data size is 1 typically > + @param[out] StatusValue The Pointer to caller-allocated buffer > containing the value of Status register received. > + > + @retval EFI_SUCCESS Command succeed. > + @retval EFI_INVALID_PARAMETER The parameters specified are not valid= . > + @retval EFI_DEVICE_ERROR Device error, command aborts > abnormally. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SPI_FLASH_READ_STATUS) ( > + IN PCH_SPI_PROTOCOL *This, > + IN UINT32 ByteCount, > + OUT UINT8 *StatusValue > + ); > + > +/** > + Get the SPI region base and size, based on the enum type > + > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. > + @param[in] FlashRegionType The Flash Region type for for the base > address which is listed in the Descriptor. > + @param[out] BaseAddress The Flash Linear Address for the Regio= n 'n' > Base > + @param[out] RegionSize The size for the Region 'n' > + > + @retval EFI_SUCCESS Read success > + @retval EFI_INVALID_PARAMETER Invalid region type given > + @retval EFI_DEVICE_ERROR The region is not used > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) ( > + IN PCH_SPI_PROTOCOL *This, > + IN FLASH_REGION_TYPE FlashRegionType, > + OUT UINT32 *BaseAddress, > + OUT UINT32 *RegionSize > + ); > + > +/** > + Read PCH Soft Strap Values > + > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. > + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPS= BA. > + @param[in] ByteCount Number of bytes in SoftStrap data port= ion > of the SPI cycle > + @param[out] SoftStrapValue The Pointer to caller-allocated buffer > containing PCH Soft Strap Value. > + If the value of ByteCount is 0, the da= ta type of > SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap > Length > + It is the caller's responsibility to m= ake sure Buffer is > large enough for the total number of bytes read. > + > + @retval EFI_SUCCESS Command succeed. > + @retval EFI_INVALID_PARAMETER The parameters specified are not valid= . > + @retval EFI_DEVICE_ERROR Device error, command aborts > abnormally. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) ( > + IN PCH_SPI_PROTOCOL *This, > + IN UINT32 SoftStrapAddr, > + IN UINT32 ByteCount, > + OUT VOID *SoftStrapValue > + ); > + > +/** > + Read CPU Soft Strap Values > + > + @param[in] This Pointer to the PCH_SPI_PROTOCOL instan= ce. > + @param[in] SoftStrapAddr CPU Soft Strap address offset from > FCPUSBA. > + @param[in] ByteCount Number of bytes in SoftStrap data port= ion > of the SPI cycle. > + @param[out] SoftStrapValue The Pointer to caller-allocated buffer > containing CPU Soft Strap Value. > + If the value of ByteCount is 0, the da= ta type of > SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap > Length > + It is the caller's responsibility to m= ake sure Buffer is > large enough for the total number of bytes read. > + > + @retval EFI_SUCCESS Command succeed. > + @retval EFI_INVALID_PARAMETER The parameters specified are not valid= . > + @retval EFI_DEVICE_ERROR Device error, command aborts > abnormally. > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) ( > + IN PCH_SPI_PROTOCOL *This, > + IN UINT32 SoftStrapAddr, > + IN UINT32 ByteCount, > + OUT VOID *SoftStrapValue > + ); > + > +/** > + These protocols/PPI allows a platform module to perform SPI operations > through the > + Intel PCH SPI Host Controller Interface. > +**/ > +struct _PCH_SPI_PROTOCOL { > + /** > + This member specifies the revision of this structure. This field is = used to > + indicate backwards compatible changes to the protocol. > + **/ > + UINT8 Revision; > + PCH_SPI_FLASH_READ FlashRead; ///< Read data f= rom > the flash part. > + PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data = to the > flash part. Remark: Erase may be needed before write to the flash part. > + PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some = area > on the flash part. > + PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP > data from the flash part. > + PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec > Id from the flash part. > + PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the > status register in the flash part. > + PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status > register in the flash part. > + PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the > SPI region base and size > + PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH > Soft Strap Values > + PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU > Soft Strap Values > +}; > + > +/** > + PCH SPI PPI/PROTOCOL revision number > + > + Revision 1: Initial version > +**/ > +#define PCH_SPI_SERVICES_REVISION 1 > + > +#endif > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Wdt.= h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Wdt.h > new file mode 100644 > index 0000000000..67554e526f > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Wdt.h > @@ -0,0 +1,113 @@ > +/** @file > + Watchdog Timer protocol > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _DXE_WDT_H_ > +#define _DXE_WDT_H_ > + > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID gWdtProtocolGuid; > +// > +// Forward reference for ANSI C compatibility > +// > +typedef struct _WDT_PROTOCOL WDT_PROTOCOL; > + > +/** > + Reloads WDT with new timeout value and starts it. Also sets Unexpected > Reset bit, which > + causes the next reset to be treated as watchdog expiration - unless > AllowKnownReset() > + function was called too. > + > + @param[in] TimeoutValue Time in seconds before WDT times out. > Supported range =3D 1 - 1024. > + > + @retval EFI_SUCCESS if everything's OK > + @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong > +**/ > +typedef > +EFI_STATUS > +(EFIAPI *WDT_RELOAD_AND_START) ( > + UINT32 TimeoutValue > + ); > + > +/** > + Returns WDT failure status. > + > + @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT > expiration or unexpected reset > + @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise > +**/ > +typedef > +UINT8 > +(EFIAPI *WDT_CHECK_STATUS) ( > + VOID > + ); > + > +/** > + Returns information if WDT coverage for the duration of BIOS execution > + was requested by an OS application. > + > + @retval TRUE if WDT was requested > + @retval FALSE if WDT was not requested > +**/ > +typedef > +UINT8 > +(EFIAPI *IS_WDT_REQUIRED) ( > + VOID > + ); > + > +/** > + Returns WDT enabled/disabled status. > + > + @retval TRUE if WDT is enabled > + @retval FALSE if WDT is disabled > +**/ > +typedef > +UINT8 > +(EFIAPI *IS_WDT_ENABLED) ( > + VOID > + ); > + > +/** > + Disables WDT timer. > +**/ > +typedef > +VOID > +(EFIAPI *WDT_DISABLE) ( > + VOID > + ); > + > +/** > + Normally, each reboot performed while watchdog runs is considered a > failure. > + This function allows platform to perform expected reboots with WDT > running, > + without being interpreted as failures. > + In DXE phase, it is enough to call this function any time before reset= . > + In PEI phase, between calling this function and performing reset, > ReloadAndStart() > + must not be called. > +**/ > +typedef > +VOID > +(EFIAPI *WDT_ALLOW_KNOWN_RESET) ( > + VOID > + ); > + > +/** > + These protocols and PPI allow a platform module to perform watch dog > timer operations > + through the Intel PCH LPC Host Controller Interface. The WDT protocol = and > WDT PPI > + implement the Intel (R) Watch Dog timer for DXE, and PEI environments, > respectively. > + WDT_PROTOCOL referenced hereafter represents both WDT_PROTOCOL > and WDT_PPI, as they > + share the identical data structure. > +**/ > +struct _WDT_PROTOCOL { > + WDT_RELOAD_AND_START ReloadAndStart; ///< Reloads WDT with new > timeout value and starts it. > + WDT_CHECK_STATUS CheckStatus; ///< Returns WDT failure statu= s. > + WDT_DISABLE Disable; ///< Disables WDT timer. > + WDT_ALLOW_KNOWN_RESET AllowKnownReset; ///< Perform expected > reboots with WDT running, without being interpreted as failures. > + IS_WDT_REQUIRED IsWdtRequired; ///< Returns information if WD= T > coverage for the duration of BIOS execution was requested by an OS > application. > + IS_WDT_ENABLED IsWdtEnabled; ///< Returns WDT > enabled/disabled status. > +}; > + > +#endif > -- > 2.16.2.windows.1