From: "Chiu, Chasel" <chasel.chiu@intel.com>
To: "Kubacki, Michael A" <michael.a.kubacki@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>,
"Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>,
"Gao, Liming" <liming.gao@intel.com>,
"Kinney, Michael D" <michael.d.kinney@intel.com>,
"Sinha, Ankit" <ankit.sinha@intel.com>
Subject: Re: [edk2-platforms][PATCH V1 08/37] CoffeelakeSiliconPkg/Pch: Add Register include headers
Date: Sat, 17 Aug 2019 01:09:45 +0000 [thread overview]
Message-ID: <3C3EFB470A303B4AB093197B6777CCEC50462291@PGSMSX111.gar.corp.intel.com> (raw)
In-Reply-To: <20190817001603.30632-9-michael.a.kubacki@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>;
> Kinney, Michael D <michael.d.kinney@intel.com>; Sinha, Ankit
> <ankit.sinha@intel.com>
> Subject: [edk2-platforms][PATCH V1 08/37] CoffeelakeSiliconPkg/Pch: Add
> Register include headers
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
>
> Adds the following header files:
> * Pch/Include/Register
>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
> ---
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegs.h |
> 54 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDci.h
> | 57 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi.h
> | 122 ++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi14.h
> | 54 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi15.h
> | 62 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsFia.h
> | 90 +++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGpio.h
> | 273 ++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGpioCnl.h
> | 694 ++++++++++++++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHda.h
> | 204 ++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHsio.h
> | 170 +++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsIsh.h
> | 79 +++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsItss.h |
> 103 +++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLan.h
> | 58 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h
> | 360 ++++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> | 61 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsP2sb.h
> | 116 ++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcie.h
> | 484 ++++++++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcr.h
> | 73 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmc.h
> | 670 +++++++++++++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmcCnl.h
> | 72 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h
> | 104 +++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsfCnl.h
> | 113 ++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h
> | 77 +++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSata.h
> | 668 +++++++++++++++++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScs.h
> | 52 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScsCnl.h
> | 48 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h
> | 232 +++++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSerialIoCnl.h
> | 138 ++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSmbus.h
> | 151 +++++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSpi.h
> | 295 +++++++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsThermalCnl.
> h | 49 ++
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsTraceHub.h
> | 134 ++++
> 32 files changed, 5917 insertions(+)
>
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegs.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegs.h
> new file mode 100644
> index 0000000000..10fcb316fc
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegs.h
> @@ -0,0 +1,54 @@
> +/** @file
> + Generic register definitions for PCH.
> +
> +Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_H_
> +#define _PCH_REGS_H_
> +
> +///
> +/// The default PCH PCI segment and bus number
> +///
> +#define DEFAULT_PCI_SEGMENT_NUMBER_PCH 0
> +#define DEFAULT_PCI_BUS_NUMBER_PCH 0
> +
> +//
> +// Default Vendor ID and Subsystem ID
> +//
> +#define V_PCH_INTEL_VENDOR_ID 0x8086 ///< Default Intel PCH
> Vendor ID
> +#define V_PCH_DEFAULT_SID 0x7270 ///< Default Intel PCH
> Subsystem ID
> +#define V_PCH_DEFAULT_SVID_SID (V_INTEL_VENDOR_ID +
> (V_PCH_DEFAULT_SID << 16)) ///< Default INTEL PCH Vendor ID and
> Subsystem ID
> +
> +#endif //_PCH_REGS_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDci.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDci.h
> new file mode 100644
> index 0000000000..47dd73215e
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDci.h
> @@ -0,0 +1,57 @@
> +/** @file
> + Register names for PCH DCI device
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_DCI_H_
> +#define _PCH_REGS_DCI_H_
> +
> +//
> +// DCI PCR Registers
> +//
> +
> +#define R_DCI_PCR_ECTRL 0x04 ///< DCI Control
> Register
> +
> +#define B_DCI_PCR_ECTRL_HDCIEN_LOCK BIT0 ///< Host DCI
> Enable Lock
> +#define B_DCI_PCR_ECTRL_HDCIEN BIT4 ///< Host DCI
> Enable
> +
> +#define R_DCI_PCR_ECKPWRCTL 0x08 ///< DCI Power
> Control
> +// CNP-A0 (DCI Gen2) and backwards
> +#define R_DCI_PCR_PCE 0x30 ///< DCI Power
> Control Enable Register
> +#define B_DCI_PCR_PCE_HAE BIT5 ///< Hardware
> Autonomous Enable
> +#define B_DCI_PCR_PCE_D3HE BIT2 ///< D3-Hot
> Enable
> +#define B_DCI_PCR_PCE_I3E BIT1 ///< I3 Enable
> +#define B_DCI_PCR_PCE_PMCRE BIT0 ///< PMC
> Request Enable
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi.h
> new file mode 100644
> index 0000000000..44f708dd92
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi.h
> @@ -0,0 +1,122 @@
> +/** @file
> + Register names for DMI and OP-DMI
> +
> +Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_DMI_H_
> +#define _PCH_REGS_DMI_H_
> +
> +//
> +// DMI Chipset Configuration Registers (PID:DMI)
> +//
> +
> +//
> +// VC Configuration (Common)
> +//
> +#define B_PCH_DMI_PCR_V0CTL_EN BIT31
> +#define B_PCH_DMI_PCR_V0CTL_ID (7 << 24) ///<
> Bit[26:24]
> +#define N_PCH_DMI_PCR_V0CTL_ID 24
> +#define V_PCH_DMI_PCR_V0CTL_ETVM_MASK 0xFC00
> +#define V_PCH_DMI_PCR_V0CTL_TVM_MASK 0x7E
> +#define B_PCH_DMI_PCR_V0STS_NP BIT1
> +#define B_PCH_DMI_PCR_V1CTL_EN BIT31
> +#define B_PCH_DMI_PCR_V1CTL_ID (0x0F << 24) ///<
> Bit[27:24]
> +#define N_PCH_DMI_PCR_V1CTL_ID 24
> +#define V_PCH_DMI_PCR_V1CTL_ETVM_MASK 0xFC00
> +#define V_PCH_DMI_PCR_V1CTL_TVM_MASK 0xFE
> +#define B_PCH_DMI_PCR_V1STS_NP BIT1
> +
> +
> +//
> +// DMI Source Decode PCRs (Common)
> +//
> +#define R_PCH_DMI_PCR_PCIEPAR1E 0x2700 ///< PCIE Port
> IOxAPIC Range 1 Enable
> +#define R_PCH_DMI_PCR_PCIEPAR2E 0x2704 ///< PCIE Port
> IOxAPIC Range 2 Enable
> +#define R_PCH_DMI_PCR_PCIEPAR3E 0x2708 ///< PCIE Port
> IOxAPIC Range 3 Enable
> +#define R_PCH_DMI_PCR_PCIEPAR4E 0x270C ///< PCIE Port
> IOxAPIC Range 4 Enable
> +#define R_PCH_DMI_PCR_PCIEPAR1DID 0x2710 ///< PCIE
> Port IOxAPIC Range 1 Destination ID
> +#define R_PCH_DMI_PCR_PCIEPAR2DID 0x2714 ///< PCIE
> Port IOxAPIC Range 2 Destination ID
> +#define R_PCH_DMI_PCR_PCIEPAR3DID 0x2718 ///< PCIE
> Port IOxAPIC Range 3 Destination ID
> +#define R_PCH_DMI_PCR_PCIEPAR4DID 0x271C ///< PCIE
> Port IOxAPIC Range 4 Destination ID
> +#define R_PCH_DMI_PCR_P2SBIOR 0x2720 ///< P2SB IO
> Range
> +#define R_PCH_DMI_PCR_TTTBARB 0x2724 ///< Thermal
> Throttling BIOS Assigned Thermal Base Address
> +#define R_PCH_DMI_PCR_TTTBARBH 0x2728 ///< Thermal
> Throttling BIOS Assigned Thermal Base High Address
> +#define R_PCH_DMI_PCR_LPCLGIR1 0x2730 ///< LPC
> Generic I/O Range 1
> +#define R_PCH_DMI_PCR_LPCLGIR2 0x2734 ///< LPC
> Generic I/O Range 2
> +#define R_PCH_DMI_PCR_LPCLGIR3 0x2738 ///< LPC
> Generic I/O Range 3
> +#define R_PCH_DMI_PCR_LPCLGIR4 0x273C ///< LPC
> Generic I/O Range 4
> +#define R_PCH_DMI_PCR_LPCGMR 0x2740 ///< LPC
> Generic Memory Range
> +#define R_PCH_DMI_PCR_SEGIR 0x27BC ///< Second
> ESPI Generic I/O Range
> +#define R_PCH_DMI_PCR_SEGMR 0x27C0 ///< Second
> ESPI Generic Memory Range
> +#define R_PCH_DMI_PCR_LPCBDE 0x2744 ///< LPC BIOS
> Decode Enable
> +#define R_PCH_DMI_PCR_UCPR 0x2748 ///< uCode
> Patch Region
> +#define B_PCH_DMI_PCR_UCPR_UPRE BIT0 ///< uCode
> Patch Region Enable
> +#define R_PCH_DMI_PCR_GCS 0x274C ///< Generic
> Control and Status
> +#define B_PCH_DMI_PCR_RPRDID 0xFFFF0000 ///< RPR
> Destination ID
> +#define B_PCH_DMI_PCR_BBS BIT10 ///< Boot BIOS
> Strap
> +#define B_PCH_DMI_PCR_RPR BIT11 ///< Reserved
> Page Route
> +#define B_PCH_DMI_PCR_BILD BIT0 ///< BIOS
> Interface Lock-Down
> +#define R_PCH_DMI_PCR_IOT1 0x2750 ///< I/O Trap
> Register 1
> +#define R_PCH_DMI_PCR_IOT2 0x2758 ///< I/O Trap
> Register 2
> +#define R_PCH_DMI_PCR_IOT3 0x2760 ///< I/O Trap
> Register 3
> +#define R_PCH_DMI_PCR_IOT4 0x2768 ///< I/O Trap
> Register 4
> +#define R_PCH_DMI_PCR_LPCIOD 0x2770 ///< LPC I/O
> Decode Ranges
> +#define R_PCH_DMI_PCR_LPCIOE 0x2774 ///< LPC I/O
> Enables
> +#define R_PCH_DMI_PCR_TCOBASE 0x2778 ///< TCO Base
> Address
> +#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 ///< TCO
> Base Address Mask
> +#define R_PCH_DMI_PCR_GPMR1 0x277C ///< General
> Purpose Memory Range 1
> +#define R_PCH_DMI_PCR_GPMR1DID 0x2780 ///< General
> Purpose Memory Range 1 Destination ID
> +#define R_PCH_DMI_PCR_GPMR2 0x2784 ///< General
> Purpose Memory Range 2
> +#define R_PCH_DMI_PCR_GPMR2DID 0x2788 ///< General
> Purpose Memory Range 2 Destination ID
> +#define R_PCH_DMI_PCR_GPMR3 0x278C ///< General
> Purpose Memory Range 3
> +#define R_PCH_DMI_PCR_GPMR3DID 0x2790 ///< General
> Purpose Memory Range 3 Destination ID
> +#define R_PCH_DMI_PCR_GPIOR1 0x2794 ///< General
> Purpose I/O Range 1
> +#define R_PCH_DMI_PCR_GPIOR1DID 0x2798 ///< General
> Purpose I/O Range 1 Destination ID
> +#define R_PCH_DMI_PCR_GPIOR2 0x279C ///< General
> Purpose I/O Range 2
> +#define R_PCH_DMI_PCR_GPIOR2DID 0x27A0 ///< General
> Purpose I/O Range 2 Destination ID
> +#define R_PCH_DMI_PCR_GPIOR3 0x27A4 ///< General
> Purpose I/O Range 3
> +#define R_PCH_DMI_PCR_GPIOR3DID 0x27A8 ///< General
> Purpose I/O Range 3 Destination ID
> +
> +//
> +// Opi PHY registers
> +//
> +#define R_PCH_OPIPHY_PCR_0110 0x0110
> +#define R_PCH_OPIPHY_PCR_0118 0x0118
> +#define R_PCH_OPIPHY_PCR_011C 0x011C
> +#define R_PCH_OPIPHY_PCR_0354 0x0354
> +#define R_PCH_OPIPHY_PCR_B104 0xB104
> +#define R_PCH_OPIPHY_PCR_B10C 0xB10C
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi14.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi14.h
> new file mode 100644
> index 0000000000..36c0054d63
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi14.h
> @@ -0,0 +1,54 @@
> +/** @file
> + Register names for DMI SIP14
> +
> +Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_DMI14_H_
> +#define _PCH_REGS_DMI14_H_
> +
> +//
> +// DMI Chipset Configuration Registers (PID:DMI)
> +//
> +
> +//
> +// DMI Control
> +//
> +#define R_PCH_DMI14_PCR_DMIC 0x2234
> ///< DMI Control
> +#define B_PCH_DMI14_PCR_DMIC_SRL BIT31
> ///< Secured register lock
> +#define B_PCH_DMI14_PCR_DMIC_DMICGEN (BIT4 | BIT3 | BIT2 |
> BIT1 | BIT0) ///< DMI Clock Gate Enable
> +
> +#define R_PCH_DMI14_PCR_2314 0x2314
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi15.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi15.h
> new file mode 100644
> index 0000000000..c885fdd34d
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi15.h
> @@ -0,0 +1,62 @@
> +/** @file
> + Register names for DMI and OP-DMI
> +
> +Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_DMI15_H_
> +#define _PCH_REGS_DMI15_H_
> +
> +#define R_PCH_DMI15_PCR_MPC 0x20D8 ///<
> Miscellaneous Port Configuration
> +#define B_PCH_DMI15_PCR_MPC_SRL BIT23 ///<
> Secured register lock
> +#define R_PCH_DMI15_PCR_V0CTL 0x2284 ///<
> Virtual channel 0 resource control
> +#define R_PCH_DMI15_PCR_V0STS 0x228A ///<
> Virtual channel 0 status
> +
> +#define R_PCH_DMI15_PCR_V1CTL 0x2290 ///<
> Virtual channel 1 resource control
> +#define R_PCH_DMI15_PCR_V1STS 0x2296 ///<
> Virtual channel 1 status
> +
> +#define R_PCH_DMI15_PCR_VMCTL 0x22B0 ///<
> ME Virtual Channel (VCm) resource control
> +
> +#define R_PCH_DMI15_PCR_UPHWAWC 0x249C
> ///< Upstream Port HW Autonomous Width Control
> +#define B_PCH_DMI15_PCR_UPHWAWC_TS3TW (BIT15 | BIT14 | BIT13)
> ///< Thermal Sensor 3 Target Width
> +#define N_PCH_DMI15_PCR_UPHWAWC_TS3TW 13
> ///< Thermal Sensor 3 Target Width
> +#define B_PCH_DMI15_PCR_UPHWAWC_TS2TW (BIT12 | BIT11 | BIT10)
> ///< Thermal Sensor 2 Target Width
> +#define N_PCH_DMI15_PCR_UPHWAWC_TS2TW 10
> ///< Thermal Sensor 2 Target Width
> +#define B_PCH_DMI15_PCR_UPHWAWC_TS1TW (BIT9 | BIT8 | BIT7)
> ///< Thermal Sensor 1 Target Width
> +#define N_PCH_DMI15_PCR_UPHWAWC_TS1TW 7
> ///< Thermal Sensor 1 Target Width
> +#define B_PCH_DMI15_PCR_UPHWAWC_TS0TW (BIT6 | BIT5 | BIT4)
> ///< Thermal Sensor 0 Target Width
> +#define N_PCH_DMI15_PCR_UPHWAWC_TS0TW 4
> ///< Thermal Sensor 0 Target Width
> +#define B_PCH_DMI15_PCR_UPHWAWC_TSAWEN BIT0
> ///< Thermal Sensor Autonomous Width Enable
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsFia.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsFia.h
> new file mode 100644
> index 0000000000..837fdc5609
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsFia.h
> @@ -0,0 +1,90 @@
> +/** @file
> + Register definition for FIA component
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_FIA_H_
> +#define _PCH_REGS_FIA_H_
> +
> +
> +//
> +// Private chipset register (Memory space) offset definition
> +// The PCR register defines is used for PCR MMIO programming and PCH SBI
> programming as well.
> +//
> +
> +//
> +// PCH FIA lane owner encoding
> +//
> +#define V_PCH_FIA_PCR_LANE_OWN_PCIEDMI 0x0
> +#define V_PCH_FIA_PCR_LANE_OWN_USB3 0x1
> +#define V_PCH_FIA_PCR_LANE_OWN_SATA 0x2
> +#define V_PCH_FIA_PCR_LANE_OWN_GBE 0x3
> +#define V_PCH_FIA_PCR_LANE_OWN_MOBEXP 0x4
> +#define V_PCH_FIA_PCR_LANE_OWN_SSIC 0x5
> +#define V_PCH_FIA_PCR_LANE_OWN_CSI3 0x6
> +#define V_PCH_FIA_PCR_LANE_OWN_UFS 0x7
> +
> +#define B_PCH_FIA_PCR_L0O (BIT3 | BIT2 | BIT1 |
> BIT0)
> +#define B_PCH_FIA_PCR_L1O (BIT7 | BIT6 | BIT5 |
> BIT4)
> +#define B_PCH_FIA_PCR_L2O (BIT11 | BIT10 | BIT9 |
> BIT8)
> +#define B_PCH_FIA_PCR_L3O (BIT15 | BIT14 | BIT13 |
> BIT12)
> +#define B_PCH_FIA_PCR_L4O (BIT19 | BIT18 | BIT17 |
> BIT16)
> +#define B_PCH_FIA_PCR_L5O (BIT23 | BIT22 | BIT21 |
> BIT20)
> +#define B_PCH_FIA_PCR_L6O (BIT27 | BIT26 | BIT25 |
> BIT24)
> +#define B_PCH_FIA_PCR_L7O (BIT31 | BIT30 | BIT29 |
> BIT28)
> +#define B_PCH_FIA_PCR_L8O (BIT3 | BIT2 | BIT1 |
> BIT0)
> +#define B_PCH_FIA_PCR_L9O (BIT7 | BIT6 | BIT5 |
> BIT4)
> +#define B_PCH_FIA_PCR_L10O (BIT11 | BIT10 | BIT9 |
> BIT8)
> +#define B_PCH_FIA_PCR_L11O (BIT15 | BIT14 | BIT13 |
> BIT12)
> +#define B_PCH_FIA_PCR_L12O (BIT19 | BIT18 | BIT17 |
> BIT16)
> +#define B_PCH_FIA_PCR_L13O (BIT23 | BIT22 | BIT21 |
> BIT20)
> +#define B_PCH_FIA_PCR_L14O (BIT27 | BIT26 | BIT25 |
> BIT24)
> +#define B_PCH_FIA_PCR_L15O (BIT31 | BIT30 | BIT29 |
> BIT28)
> +#define B_PCH_FIA_PCR_L16O (BIT3 | BIT2 | BIT1 |
> BIT0)
> +#define B_PCH_FIA_PCR_L17O (BIT7 | BIT6 | BIT5 |
> BIT4)
> +#define B_PCH_FIA_PCR_L18O (BIT11 | BIT10 | BIT9 |
> BIT8)
> +#define B_PCH_FIA_PCR_L19O (BIT15 | BIT14 | BIT13 |
> BIT12)
> +#define B_PCH_FIA_PCR_L20O (BIT19 | BIT18 | BIT17 |
> BIT16)
> +#define B_PCH_FIA_PCR_L21O (BIT23 | BIT22 | BIT21 |
> BIT20)
> +#define B_PCH_FIA_PCR_L22O (BIT27 | BIT26 | BIT25 |
> BIT24)
> +#define B_PCH_FIA_PCR_L23O (BIT31 | BIT30 | BIT29 |
> BIT28)
> +#define B_PCH_FIA_PCR_L24O (BIT3 | BIT2 | BIT1 |
> BIT0)
> +#define B_PCH_FIA_PCR_L25O (BIT7 | BIT6 | BIT5 |
> BIT4)
> +#define B_PCH_FIA_PCR_L26O (BIT11 | BIT10 | BIT9 |
> BIT8)
> +#define B_PCH_FIA_PCR_L27O (BIT15 | BIT14 | BIT13 |
> BIT12)
> +#define B_PCH_FIA_PCR_L28O (BIT19 | BIT18 | BIT17 |
> BIT16)
> +#define B_PCH_FIA_PCR_L29O (BIT23 | BIT22 | BIT21 |
> BIT20)
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGpio.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGpio.h
> new file mode 100644
> index 0000000000..3f614ba002
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGpio.h
> @@ -0,0 +1,273 @@
> +/** @file
> + Register names for PCH GPIO
> +
> +Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_GPIO_H_
> +#define _PCH_REGS_GPIO_H_
> +
> +//
> +// GPIO Common Private Configuration Registers
> +//
> +#define R_GPIO_PCR_REV_ID 0x00
> +#define R_GPIO_PCR_CAP_LIST 0x04
> +#define R_GPIO_PCR_FAMBAR 0x08
> +#define R_GPIO_PCR_PADBAR 0x0C
> +#define B_GPIO_PCR_PADBAR 0x0000FFFF
> +#define R_GPIO_PCR_MISCCFG 0x10
> +#define B_GPIO_PCR_MISCCFG_IRQ_ROUTE 0xFF000000
> +#define N_GPIO_PCR_MISCCFG_IRQ_ROUTE 24
> +#define B_GPIO_PCR_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16)
> +#define N_GPIO_PCR_MISCCFG_GPE0_DW2 16
> +#define B_GPIO_PCR_MISCCFG_GPE0_DW1 (BIT15 | BIT14 | BIT13 | BIT12)
> +#define N_GPIO_PCR_MISCCFG_GPE0_DW1 12
> +#define B_GPIO_PCR_MISCCFG_GPE0_DW0 (BIT11 | BIT10 | BIT9 | BIT8)
> +#define N_GPIO_PCR_MISCCFG_GPE0_DW0 8
> +#define B_GPIO_PCR_MISCCFG_GPSIDEDPCGEN BIT5
> +#define B_GPIO_PCR_MISCCFG_GPRCOMPCDLCGEN BIT4
> +#define B_GPIO_PCR_MISCCFG_GPRTCDLCGEN BIT3
> +#define B_GPIO_PCR_MISCCFG_GPDPCGEN BIT1
> +#define B_GPIO_PCR_MISCCFG_GPDLCGEN BIT0
> +
> +//
> +// GPIO SerialBlink/PWM registers
> +//
> +#define R_GPIO_PCR_CAP_LIST_1_PWM 0x0200
> +#define R_GPIO_PCR_PWMC 0x0204
> +#define R_GPIO_PCR_CAP_LIST_2_SER_BLINK 0x0208
> +#define R_GPIO_PCR_GP_SER_BLINK 0x020C
> +#define B_GPIO_PCR_GP_SER_BLINK 0x1F
> +#define R_GPIO_PCR_GP_SER_CMDSTS 0x0210
> +#define B_GPIO_PCR_GP_SER_CMDSTS_DLS (BIT23 | BIT22)
> +#define N_GPIO_PCR_GP_SER_CMDSTS_DLS 22
> +#define B_GPIO_PCR_GP_SER_CMDSTS_DRS 0x003F0000
> +#define N_GPIO_PCR_GP_SER_CMDSTS_DRS 16
> +#define B_GPIO_PCR_GP_SER_CMDSTS_BUSY BIT8
> +#define B_GPIO_PCR_GP_SER_CMDSTS_GO BIT0
> +#define R_GPIO_PCR_GP_SER_DATA 0x0210
> +
> +//
> +// PADCFG register is split into multiple DW registers
> +// S_GPIO_PCR_PADCFG refers to number of bytes used by all those registers
> for one pad
> +//
> +#define S_GPIO_PCR_PADCFG 0x10
> +
> +//
> +// Pad Configuration Register DW0
> +//
> +
> +//Pad Reset Config
> +#define B_GPIO_PCR_RST_CONF (BIT31 | BIT30)
> +#define N_GPIO_PCR_RST_CONF 30
> +#define V_GPIO_PCR_RST_CONF_POW_GOOD 0x00
> +#define V_GPIO_PCR_RST_CONF_DEEP_RST 0x01
> +#define V_GPIO_PCR_RST_CONF_GPIO_RST 0x02
> +#define V_GPIO_PCR_RST_CONF_RESUME_RST 0x03 // Only for GPD Group
> +
> +//RX Pad State Select
> +#define B_GPIO_PCR_RX_PAD_STATE BIT29
> +#define N_GPIO_PCR_RX_PAD_STATE 29
> +#define V_GPIO_PCR_RX_PAD_STATE_RAW 0x00
> +#define V_GPIO_PCR_RX_PAD_STATE_INT 0x01
> +
> +//RX Raw Overrride to 1
> +#define B_GPIO_PCR_RX_RAW1 BIT28
> +#define N_GPIO_PCR_RX_RAW1 28
> +#define V_GPIO_PCR_RX_RAW1_DIS 0x00
> +#define V_GPIO_PCR_RX_RAW1_EN 0x01
> +
> +//RX Level/Edge Configuration
> +#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25)
> +#define N_GPIO_PCR_RX_LVL_EDG 25
> +#define V_GPIO_PCR_RX_LVL_EDG_LVL 0x00
> +#define V_GPIO_PCR_RX_LVL_EDG_EDG 0x01
> +#define V_GPIO_PCR_RX_LVL_EDG_0 0x02
> +#define V_GPIO_PCR_RX_LVL_EDG_RIS_FAL 0x03
> +
> +//RX Invert
> +#define B_GPIO_PCR_RXINV BIT23
> +#define N_GPIO_PCR_RXINV 23
> +#define V_GPIO_PCR_RXINV_NO 0x00
> +#define V_GPIO_PCR_RXINV_YES 0x01
> +
> +//GPIO Input Route IOxAPIC
> +#define B_GPIO_PCR_RX_APIC_ROUTE BIT20
> +#define N_GPIO_PCR_RX_APIC_ROUTE 20
> +#define V_GPIO_PCR_RX_APIC_ROUTE_DIS 0x00
> +#define V_GPIO_PCR_RX_APIC_ROUTE_EN 0x01
> +
> +//GPIO Input Route SCI
> +#define B_GPIO_PCR_RX_SCI_ROUTE BIT19
> +#define N_GPIO_PCR_RX_SCI_ROUTE 19
> +#define V_GPIO_PCR_RX_SCI_ROUTE_DIS 0x00
> +#define V_GPIO_PCR_RX_SCI_ROUTE_EN 0x01
> +
> +//GPIO Input Route SMI
> +#define B_GPIO_PCR_RX_SMI_ROUTE BIT18
> +#define N_GPIO_PCR_RX_SMI_ROUTE 18
> +#define V_GPIO_PCR_RX_SMI_ROUTE_DIS 0x00
> +#define V_GPIO_PCR_RX_SMI_ROUTE_EN 0x01
> +
> +//GPIO Input Route NMI
> +#define B_GPIO_PCR_RX_NMI_ROUTE BIT17
> +#define N_GPIO_PCR_RX_NMI_ROUTE 17
> +#define V_GPIO_PCR_RX_NMI_ROUTE_DIS 0x00
> +#define V_GPIO_PCR_RX_NMI_ROUTE_EN 0x01
> +
> +//GPIO Pad Mode
> +#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10)
> +#define N_GPIO_PCR_PAD_MODE 10
> +#define V_GPIO_PCR_PAD_MODE_GPIO 0
> +#define V_GPIO_PCR_PAD_MODE_NAT_1 1
> +#define V_GPIO_PCR_PAD_MODE_NAT_2 2
> +#define V_GPIO_PCR_PAD_MODE_NAT_3 3
> +#define V_GPIO_PCR_PAD_MODE_NAT_4 4 // SPT-H only
> +
> +//GPIO RX Disable
> +#define B_GPIO_PCR_RXDIS BIT9
> +#define N_GPIO_PCR_RXDIS 9
> +#define V_GPIO_PCR_RXDIS_EN 0x00
> +#define V_GPIO_PCR_RXDIS_DIS 0x01
> +
> +//GPIO TX Disable
> +#define B_GPIO_PCR_TXDIS BIT8
> +#define N_GPIO_PCR_TXDIS 8
> +#define V_GPIO_PCR_TXDIS_EN 0x00
> +#define V_GPIO_PCR_TXDIS_DIS 0x01
> +
> +//GPIO RX State
> +#define B_GPIO_PCR_RX_STATE BIT1
> +#define N_GPIO_PCR_RX_STATE 1
> +#define V_GPIO_PCR_RX_STATE_LOW 0x00
> +#define V_GPIO_PCR_RX_STATE_HIGH 0x01
> +
> +//GPIO TX State
> +#define B_GPIO_PCR_TX_STATE BIT0
> +#define N_GPIO_PCR_TX_STATE 0
> +#define V_GPIO_PCR_TX_STATE_LOW 0x00
> +#define V_GPIO_PCR_TX_STATE_HIGH 0x01
> +
> +//
> +// Pad Configuration Register DW1
> +//
> +
> +//Padtol
> +#define B_GPIO_PCR_PADTOL BIT25
> +#define N_GPIO_PCR_PADTOL 25
> +#define V_GPIO_PCR_PADTOL_NONE 0x00
> +#define V_GPIO_PCR_PADTOL_CLEAR 0x00
> +#define V_GPIO_PCR_PADTOL_SET 0x01
> +
> +//Termination
> +#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10)
> +#define N_GPIO_PCR_TERM 10
> +#define V_GPIO_PCR_TERM_WPD_NONE 0x00
> +#define V_GPIO_PCR_TERM_WPD_5K 0x02
> +#define V_GPIO_PCR_TERM_WPD_20K 0x04
> +#define V_GPIO_PCR_TERM_WPU_NONE 0x08
> +#define V_GPIO_PCR_TERM_WPU_1K 0x09
> +#define V_GPIO_PCR_TERM_WPU_2K 0x0B
> +#define V_GPIO_PCR_TERM_WPU_5K 0x0A
> +#define V_GPIO_PCR_TERM_WPU_20K 0x0C
> +#define V_GPIO_PCR_TERM_WPU_1K_2K 0x0D
> +#define V_GPIO_PCR_TERM_NATIVE 0x0F
> +
> +//Interrupt number
> +#define B_GPIO_PCR_INTSEL 0x7F
> +#define N_GPIO_PCR_INTSEL 0
> +
> +//
> +//Debounce
> +#define B_GPIO_PCR_DEBOUNCE (BIT4 | BIT3 | BIT2 | BIT1)
> +#define N_GPIO_PCR_DEBOUNCE 1
> +
> +//Debounce Enable
> +#define B_GPIO_PCR_DEBEN BIT0
> +#define N_GPIO_PCR_DEBEN 0
> +
> +//
> +// Ownership
> +//
> +#define V_GPIO_PCR_OWN_GPIO 0x01
> +#define V_GPIO_PCR_OWN_ACPI 0x00
> +
> +//
> +// GPE
> +//
> +#define V_GPIO_PCR_GPE_EN 0x01
> +#define V_GPIO_PCR_GPE_DIS 0x00
> +//
> +// SMI
> +//
> +#define V_GPIO_PCR_SMI_EN 0x01
> +#define V_GPIO_PCR_SMI_DIS 0x00
> +//
> +// NMI
> +//
> +#define V_GPIO_PCR_NMI_EN 0x01
> +#define V_GPIO_PCR_NMI_DIS 0x00
> +
> +//
> +// GPIO native features pins data
> +//
> +#define PCH_GPIO_HDA_LINK_NUMBER_OF_PINS 6
> +#define PCH_GPIO_HDA_DMIC_NUMBER_OF_PINS 2
> +#define PCH_GPIO_HDA_SSP_NUMBER_OF_PINS 4
> +#define PCH_GPIO_HDA_SNDW_NUMBER_OF_PINS 2
> +#define PCH_GPIO_SMBUS_NUMBER_OF_PINS 2
> +#define PCH_GPIO_CPU_GP_NUMBER_OF_PINS 4
> +#define PCH_GPIO_EDP_NUMBER_OF_PINS 4
> +#define PCH_GPIO_DDSP_HPD_NUMBER_OF_PINS 4
> +#define PCH_GPIO_DDP_NUMBER_OF_INTERFACES 4
> +#define PCH_GPIO_DDP_NUMBER_OF_PINS 2
> +#define PCH_GPIO_CNVI_UART_NUMBER_OF_PINS 4
> +#define PCH_GPIO_CNVI_SSP_NUMBER_OF_PINS 4
> +#define PCH_GPIO_CNVI_BRI_RGI_NUMBER_OF_PINS 4
> +
> +
> +///
> +/// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL
> +/// Below defines are to be used internally by PCH SMI dispatcher only
> +///
> +#define PCH_GPIO_NUM_SUPPORTED_GPIS 512
> +#define S_GPIO_PCR_GP_SMI_EN 4
> +#define S_GPIO_PCR_GP_SMI_STS 4
> +
> +///
> +/// Groups mapped to 2-tier General Purpose Event will all be under
> +/// one master GPE_111 (0x6F)
> +///
> +#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGpioCnl.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGpioCnl.h
> new file mode 100644
> index 0000000000..140c758730
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGpioCnl.h
> @@ -0,0 +1,694 @@
> +/** @file
> + Register names for GPIO
> +
> +Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_GPIO_CNL_H_
> +#define _PCH_REGS_GPIO_CNL_H_
> +
> +//
> +// PCH-LP GPIO
> +//
> +#define CNL_PCH_LP_GPIO_GROUP_MAX 15
> +
> +#define CNL_PCH_LP_GPIO_GPP_A_PAD_MAX 25
> +#define CNL_PCH_LP_GPIO_GPP_B_PAD_MAX 26
> +#define CNL_PCH_LP_GPIO_GPP_C_PAD_MAX 24
> +#define CNL_PCH_LP_GPIO_GPP_D_PAD_MAX 24
> +#define CNL_PCH_LP_GPIO_GPP_E_PAD_MAX 24
> +#define CNL_PCH_LP_GPIO_GPP_F_PAD_MAX 24
> +#define CNL_PCH_LP_GPIO_GPP_G_PAD_MAX 8
> +#define CNL_PCH_LP_GPIO_GPP_H_PAD_MAX 24
> +#define CNL_PCH_LP_GPIO_GPD_PAD_MAX 16
> +#define CNL_PCH_LP_GPIO_VGPIO_PAD_MAX 40
> +#define CNL_PCH_LP_GPIO_SPI_PAD_MAX 9
> +#define CNL_PCH_LP_GPIO_AZA_PAD_MAX 8
> +#define CNL_PCH_LP_GPIO_CPU_PAD_MAX 11
> +#define CNL_PCH_LP_GPIO_JTAG_PAD_MAX 9
> +#define CNL_PCH_LP_GPIO_HVMOS_PAD_MAX 6
> +
> +//
> +// PCH-H GPIO
> +//
> +#define CNL_PCH_H_GPIO_GROUP_MAX 17
> +
> +#define CNL_PCH_H_GPIO_GPP_A_PAD_MAX 25
> +#define CNL_PCH_H_GPIO_GPP_B_PAD_MAX 26
> +#define CNL_PCH_H_GPIO_GPP_C_PAD_MAX 24
> +#define CNL_PCH_H_GPIO_GPP_D_PAD_MAX 24
> +#define CNL_PCH_H_GPIO_GPP_E_PAD_MAX 13
> +#define CNL_PCH_H_GPIO_GPP_F_PAD_MAX 24
> +#define CNL_PCH_H_GPIO_GPP_G_PAD_MAX 8
> +#define CNL_PCH_H_GPIO_GPP_H_PAD_MAX 24
> +#define CNL_PCH_H_GPIO_GPP_I_PAD_MAX 18
> +#define CNL_PCH_H_GPIO_GPP_J_PAD_MAX 12
> +#define CNL_PCH_H_GPIO_GPP_K_PAD_MAX 24
> +#define CNL_PCH_H_GPIO_GPD_PAD_MAX 16
> +#define CNL_PCH_H_GPIO_VGPIO_PAD_MAX 40
> +#define CNL_PCH_H_GPIO_SPI_PAD_MAX 9
> +#define CNL_PCH_H_GPIO_AZA_PAD_MAX 8
> +#define CNL_PCH_H_GPIO_CPU_PAD_MAX 11
> +#define CNL_PCH_H_GPIO_JTAG_PAD_MAX 9
> +
> +//
> +// PCH-LP GPIO registers
> +//
> +//
> +// GPIO Community Common Private Configuration Registers
> +//
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_A 0x0
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_B 0x1
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_C 0xC
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_D 0x4
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_E 0xD
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_F 0x5
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_G 0x2
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_H 0x6
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPD 0x9
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_VGPIO 0x7
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_SPI 0x3
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_AZA 0xA
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_CPU 0xB
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_JTAG 0xE
> +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_HVMOS 0xF
> +
> +//
> +// GPIO Community 0 Private Configuration Registers
> +//
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN 0x20
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN 0x30
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_PAD_OWN 0x40
> +#define R_CNL_PCH_LP_GPIO_PCR_SPI_PAD_OWN 0x44
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK 0x80
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x84
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK 0x88
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x8C
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_PADCFGLOCK 0x90
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_PADCFGLOCKTX 0x94
> +#define R_CNL_PCH_LP_GPIO_PCR_SPI_PADCFGLOCK 0x98
> +#define R_CNL_PCH_LP_GPIO_PCR_SPI_PADCFGLOCKTX 0x9C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN 0xB0
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN 0xB4
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_HOSTSW_OWN 0xB8
> +#define R_CNL_PCH_LP_GPIO_PCR_SPI_HOSTSW_OWN 0xBC
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_GPI_IS 0x0100
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_GPI_IS 0x0104
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_GPI_IS 0x0108
> +#define R_CNL_PCH_LP_GPIO_PCR_SPI_GPI_IS 0x010C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_GPI_IE 0x0120
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_GPI_IE 0x0124
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_GPI_IE 0x0128
> +#define R_CNL_PCH_LP_GPIO_PCR_SPI_GPI_IE 0x012C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0140
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0144
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_GPI_GPE_STS 0x0148
> +#define R_CNL_PCH_LP_GPIO_PCR_SPI_GPI_GPE_STS 0x014C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0160
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0164
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_GPI_GPE_EN 0x0168
> +#define R_CNL_PCH_LP_GPIO_PCR_SPI_GPI_GPE_EN 0x016C
> +
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_SMI_STS 0x0180 // Not
> supported setting for this group
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_SMI_STS 0x0184
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_SMI_STS 0x0188 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_SPI_SMI_STS 0x018C // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_SMI_EN 0x01A0 // Not
> supported setting for this group
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_SMI_EN 0x01A4
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_SMI_EN 0x01A8 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_SPI_SMI_EN 0x01AC // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_NMI_STS 0x01C0 // Not
> supported setting for this group
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_NMI_STS 0x01C4
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_NMI_STS 0x01C8 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_SPI_NMI_STS 0x01CC // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_NMI_EN 0x01E0 // Not
> supported setting for this group
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_NMI_EN 0x01E4
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_NMI_EN 0x01E8 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_SPI_NMI_EN 0x01EC // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x600
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x790
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_PADCFG_OFFSET 0x930
> +#define R_CNL_PCH_LP_GPIO_PCR_SPI_PADCFG_OFFSET 0x9B0
> +
> +//
> +// GPIO Community 1 Private Configuration Registers
> +//
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN 0x20
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN 0x30
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN 0x3C
> +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_PAD_OWN 0x48
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK 0x80
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x84
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK 0x88
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x8C
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK 0x90
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x94
> +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_0_PADCFGLOCK 0x98
> +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_0_PADCFGLOCKTX 0x9C
> +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_1_PADCFGLOCK 0xA0
> +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_1_PADCFGLOCKTX 0xA4
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN 0xB0
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN 0xB4
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN 0xB8
> +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_HOSTSW_OWN 0xBC
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_GPI_IS 0x0100
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_GPI_IS 0x0104
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_GPI_IS 0x0108
> +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_GPI_IS 0x010C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_GPI_IE 0x0120
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_GPI_IE 0x0124
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_GPI_IE 0x0128
> +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_GPI_IE 0x012C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0140
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS 0x0144
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0148
> +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_GPI_GPE_STS 0x014C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0160
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN 0x0164
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0168
> +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_GPI_GPE_EN 0x016C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_SMI_STS 0x0180
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_SMI_STS 0x0184 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_SMI_STS 0x0188 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_SMI_STS 0x018C // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_SMI_EN 0x01A0
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_SMI_EN 0x01A4 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_SMI_EN 0x01A8 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_SMI_EN 0x01AC // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_NMI_STS 0x01C0
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_NMI_STS 0x01C4 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_NMI_STS 0x01C8 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_NMI_STS 0x01CC // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_NMI_EN 0x01E0
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_NMI_EN 0x01E4 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_NMI_EN 0x01E8 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_NMI_EN 0x01EC // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x600
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x790
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x910
> +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_PADCFG_OFFSET 0xA90
> +
> +//
> +// GPIO Community 2 Private Configuration Registers
> +//
> +#define R_CNL_PCH_LP_GPIO_PCR_GPD_PAD_OWN 0x20
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK 0x80
> +#define R_CNL_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX 0x84
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN 0xB0
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPD_GPI_IS 0x0100
> +#define R_CNL_PCH_LP_GPIO_PCR_GPD_GPI_IE 0x0120
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS 0x0140
> +#define R_CNL_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN 0x0160
> +
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPD_SMI_STS 0x0180 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPD_SMI_EN 0x01A0 // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPD_NMI_STS 0x01C0 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_GPD_NMI_EN 0x01E0 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET 0x600
> +
> +//
> +// GPIO Community 3 Private Configuration Registers
> +//
> +#define R_CNL_PCH_LP_GPIO_PCR_AZA_PAD_OWN 0x20
> +#define R_CNL_PCH_LP_GPIO_PCR_CPU_PAD_OWN 0x24
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_AZA_PADCFGLOCK 0x80
> +#define R_CNL_PCH_LP_GPIO_PCR_AZA_PADCFGLOCKTX 0x84
> +#define R_CNL_PCH_LP_GPIO_PCR_CPU_PADCFGLOCK 0x88
> +#define R_CNL_PCH_LP_GPIO_PCR_CPU_PADCFGLOCKTX 0x8C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_AZA_HOSTSW_OWN 0xB0
> +#define R_CNL_PCH_LP_GPIO_PCR_CPU_HOSTSW_OWN 0xB4
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_AZA_GPI_IS 0x0100
> +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_GPI_IS 0x0104 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_AZA_GPI_IE 0x0120
> +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_GPI_IE 0x0124 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_AZA_GPI_GPE_STS 0x0140
> +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_GPI_GPE_STS 0x0144 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_AZA_GPI_GPE_EN 0x0160
> +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_GPI_GPE_EN 0x0164 // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_LP_GPIO_PCR_AZA_SMI_STS 0x0180 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_SMI_STS 0x0184 // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_LP_GPIO_PCR_AZA_SMI_EN 0x01A0 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_SMI_EN 0x01A4 // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_LP_GPIO_PCR_AZA_NMI_STS 0x01C0 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_NMI_STS 0x01C4 // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_LP_GPIO_PCR_AZA_NMI_EN 0x01E0 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_NMI_EN 0x01E4 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_AZA_PADCFG_OFFSET 0x600
> +#define R_CNL_PCH_LP_GPIO_PCR_CPU_PADCFG_OFFSET 0x680
> +
> +//
> +// GPIO Community 4 Private Configuration Registers
> +//
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN 0x20
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN 0x2C
> +#define R_CNL_PCH_LP_GPIO_PCR_JTAG_PAD_OWN 0x38
> +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_PAD_OWN 0x40
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK 0x80
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK 0x88
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x8C
> +#define R_CNL_PCH_LP_GPIO_PCR_JTAG_PADCFGLOCK 0x90
> +#define R_CNL_PCH_LP_GPIO_PCR_JTAG_PADCFGLOCKTX 0x94
> +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_PADCFGLOCK 0x98
> +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_PADCFGLOCKTX 0x9C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN 0xB0
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN 0xB4
> +#define R_CNL_PCH_LP_GPIO_PCR_JTAG_HOSTSW_OWN 0xB8
> +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_HOSTSW_OWN 0xBC
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_GPI_IS 0x0100
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_GPI_IS 0x0104
> +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_GPI_IS 0x0108 // Not
> supported setting for this group
> +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_GPI_IS 0x010C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_GPI_IE 0x0120
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_GPI_IE 0x0124
> +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_GPI_IE 0x0128 // Not
> supported setting for this group
> +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_GPI_IE 0x012C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS 0x0144
> +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_GPI_GPE_STS 0x0148 // Not
> supported setting for this group
> +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_GPI_GPE_STS 0x014C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN 0x0164
> +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_GPI_GPE_EN 0x0168 // Not
> supported setting for this group
> +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_GPI_GPE_EN 0x016C
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_SMI_STS 0x0180
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_SMI_STS 0x0184
> +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_SMI_STS 0x0188 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_SMI_STS 0x018C // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_SMI_EN 0x01A0
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_SMI_EN 0x01A4
> +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_SMI_EN 0x01A8 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_SMI_EN 0x01AC // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_NMI_STS 0x01C0
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_NMI_STS 0x01C4
> +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_NMI_STS 0x01C8 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_NMI_STS 0x01CC // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_NMI_EN 0x01E0
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_NMI_EN 0x01E4
> +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_NMI_EN 0x01E8 // Not
> supported setting for this group
> +//#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_NMI_EN 0x01EC // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x600
> +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET 0x780
> +#define R_CNL_PCH_LP_GPIO_PCR_JTAG_PADCFG_OFFSET 0x900
> +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_PADCFG_OFFSET 0x990
> +
> +//
> +// PCH-H GPIO registers
> +//
> +//
> +// GPIO Community Common Private Configuration Registers
> +//
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_A 0x0
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_B 0x1
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_C 0x2
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_D 0x3
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_E 0x6
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_F 0x7
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_G 0x4
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_H 0x8
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_K 0x9
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_I 0xA
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_J 0xB
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPD 0x5
> +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_VGPIO 0xD
> +
> +//
> +// GPIO Community 0 Private Configuration Registers
> +//
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_PAD_OWN 0x20
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_PAD_OWN 0x30
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_PADCFGLOCK 0x80
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x84
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_PADCFGLOCK 0x88
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x8C
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_HOSTSW_OWN 0xC0
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_HOSTSW_OWN 0xC4
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_GPI_IS 0x0100
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_GPI_IS 0x0104
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_GPI_IE 0x0120
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_GPI_IE 0x0124
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0140
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0144
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0160
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0164
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_A_SMI_STS 0x0180 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_SMI_STS 0x0184
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_A_SMI_EN 0x01A0 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_SMI_EN 0x01A4
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_A_NMI_STS 0x01C0 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_NMI_STS 0x01C4
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_A_NMI_EN 0x01E0 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_NMI_EN 0x01E4
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x600
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x790
> +
> +//
> +// GPIO Community 1 Private Configuration Registers
> +//
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_PAD_OWN 0x20
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_PAD_OWN 0x2C
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_PAD_OWN 0x38
> +#define R_CNL_PCH_H_GPIO_PCR_AZA_PAD_OWN 0x3C
> +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_PAD_OWN 0x40
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_PADCFGLOCK 0x80
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_PADCFGLOCK 0x88
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x8C
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_PADCFGLOCK 0x90
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_PADCFGLOCKTX 0x94
> +#define R_CNL_PCH_H_GPIO_PCR_AZA_PADCFGLOCK 0x98
> +#define R_CNL_PCH_H_GPIO_PCR_AZA_PADCFGLOCKTX 0x9C
> +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_0_PADCFGLOCK 0xA0
> +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_0_PADCFGLOCKTX 0xA4
> +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_1_PADCFGLOCK 0xA8
> +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_1_PADCFGLOCKTX 0xAC
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_HOSTSW_OWN 0xC0
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_HOSTSW_OWN 0xC4
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_HOSTSW_OWN 0xC8
> +#define R_CNL_PCH_H_GPIO_PCR_AZA_HOSTSW_OWN 0xCC
> +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_HOSTSW_OWN 0xD0
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_GPI_IS 0x0100
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_GPI_IS 0x0104
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_GPI_IS 0x0108
> +//#define R_CNL_PCH_H_GPIO_PCR_AZA_GPI_IS 0x010C // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_GPI_IS 0x0110
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_GPI_IE 0x0120
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_GPI_IE 0x0124
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_GPI_IE 0x0128
> +//#define R_CNL_PCH_H_GPIO_PCR_AZA_GPI_IE 0x012C // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_GPI_IE 0x0130
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0144
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_GPI_GPE_STS 0x0148
> +//#define R_CNL_PCH_H_GPIO_PCR_AZA_GPI_GPE_STS 0x014C // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_GPI_GPE_STS 0x0150
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0164
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_GPI_GPE_EN 0x0168
> +//#define R_CNL_PCH_H_GPIO_PCR_AZA_GPI_GPE_EN 0x016C // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_GPI_GPE_EN 0x0170
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_SMI_STS 0x0180
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_SMI_STS 0x0184
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_SMI_STS 0x0188
> +//#define R_CNL_PCH_H_GPIO_PCR_AZA_SMI_STS 0x018C // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_VGPIO_SMI_STS 0x0190 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_SMI_EN 0x01A0
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_SMI_EN 0x01A4
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_SMI_EN 0x01A8
> +//#define R_CNL_PCH_H_GPIO_PCR_AZA_SMI_EN 0x01AC // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_VGPIO_SMI_EN 0x01B0 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_NMI_STS 0x01C0
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_NMI_STS 0x01C4
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_G_NMI_STS 0x01C8 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_AZA_NMI_STS 0x01CC // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_VGPIO_NMI_STS 0x01D0 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_NMI_EN 0x01E0
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_NMI_EN 0x01E4
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_G_NMI_EN 0x01E8 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_AZA_NMI_EN 0x01EC // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_VGPIO_NMI_EN 0x01F0 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x600
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x780
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_PADCFG_OFFSET 0x900
> +#define R_CNL_PCH_H_GPIO_PCR_AZA_PADCFG_OFFSET 0x980
> +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_PADCFG_OFFSET 0xA00
> +
> +//
> +// GPIO Community 2 Private Configuration Registers
> +//
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPD_PAD_OWN 0x20
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPD_PADCFGLOCK 0x80
> +#define R_CNL_PCH_H_GPIO_PCR_GPD_PADCFGLOCKTX 0x84
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPD_HOSTSW_OWN 0xB0
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPD_GPI_IS 0x0100
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPD_GPI_IE 0x0120
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPD_GPI_GPE_STS 0x0140
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPD_GPI_GPE_EN 0x0160
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_GPD_SMI_STS 0x0180 // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_GPD_SMI_EN 0x01A0 // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_GPD_NMI_STS 0x01C0 // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_GPD_NMI_EN 0x01E0 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPD_PADCFG_OFFSET 0x600
> +
> +//
> +// GPIO Community 3 Private Configuration Registers
> +//
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_PAD_OWN 0x20
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_PAD_OWN 0x2C
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_PAD_OWN 0x38
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_PAD_OWN 0x40
> +#define R_CNL_PCH_H_GPIO_PCR_SPI_PAD_OWN 0x4C
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_PADCFGLOCK 0x80
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_PADCFGLOCKTX 0x84
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_PADCFGLOCK 0x88
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x8C
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_PADCFGLOCK 0x90
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x94
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_PADCFGLOCK 0x98
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x9C
> +#define R_CNL_PCH_H_GPIO_PCR_SPI_PADCFGLOCK 0xA0
> +#define R_CNL_PCH_H_GPIO_PCR_SPI_PADCFGLOCKTX 0xA4
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_HOSTSW_OWN 0xC0
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_HOSTSW_OWN 0xC4
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_HOSTSW_OWN 0xC8
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_HOSTSW_OWN 0xCC
> +#define R_CNL_PCH_H_GPIO_PCR_SPI_HOSTSW_OWN 0xD0
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_GPI_IS 0x0100
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_GPI_IS 0x0104
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_GPI_IS 0x0108
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_GPI_IS 0x010C
> +//#define R_CNL_PCH_H_GPIO_PCR_SPI_GPI_IS 0x0110 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_GPI_IE 0x0120
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_GPI_IE 0x0124
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_GPI_IE 0x0128
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_GPI_IE 0x012C
> +//#define R_CNL_PCH_H_GPIO_PCR_SPI_GPI_IE 0x0130 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_GPI_GPE_STS 0x0140
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0144
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_GPI_GPE_STS 0x0148
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_GPI_GPE_STS 0x014C
> +//#define R_CNL_PCH_H_GPIO_PCR_SPI_GPI_GPE_STS 0x0150 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_GPI_GPE_EN 0x0160
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0164
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_GPI_GPE_EN 0x0168
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_GPI_GPE_EN 0x016C
> +//#define R_CNL_PCH_H_GPIO_PCR_SPI_GPI_GPE_EN 0x0170 // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_K_SMI_STS 0x0180 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_H_SMI_STS 0x0184 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_SMI_STS 0x0188
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_F_SMI_STS 0x018C // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_SPI_SMI_STS 0x0190 // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_K_SMI_EN 0x01A0 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_H_SMI_EN 0x01A4 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_SMI_EN 0x01A8
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_F_SMI_EN 0x01AC // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_SPI_SMI_EN 0x01B0 // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_K_NMI_STS 0x01C0 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_H_NMI_STS 0x01C4 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_NMI_STS 0x01C8
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_F_NMI_STS 0x01CC // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_SPI_NMI_STS 0x01D0 // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_K_NMI_EN 0x01E0 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_H_NMI_EN 0x01E4 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_NMI_EN 0x01E8
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_F_NMI_EN 0x01EC // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_SPI_NMI_EN 0x01F0 // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_PADCFG_OFFSET 0x600
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x780
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_PADCFG_OFFSET 0x900
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x9D0
> +#define R_CNL_PCH_H_GPIO_PCR_SPI_PADCFG_OFFSET 0xB50
> +
> +//
> +// GPIO Community 4 Private Configuration Registers
> +//
> +#define R_CNL_PCH_H_GPIO_PCR_CPU_PAD_OWN 0x20
> +#define R_CNL_PCH_H_GPIO_PCR_JTAG_PAD_OWN 0x28
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_PAD_OWN 0x30
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_PAD_OWN 0x3C
> +
> +#define R_CNL_PCH_H_GPIO_PCR_CPU_PADCFGLOCK 0x80
> +#define R_CNL_PCH_H_GPIO_PCR_CPU_PADCFGLOCKTX 0x84
> +#define R_CNL_PCH_H_GPIO_PCR_JTAG_PADCFGLOCK 0x88
> +#define R_CNL_PCH_H_GPIO_PCR_JTAG_PADCFGLOCKTX 0x8C
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_PADCFGLOCK 0x90
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_PADCFGLOCKTX 0x94
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_PADCFGLOCK 0x98
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_PADCFGLOCKTX 0x9C
> +
> +#define R_CNL_PCH_H_GPIO_PCR_CPU_HOSTSW_OWN 0xC0
> +#define R_CNL_PCH_H_GPIO_PCR_JTAG_HOSTSW_OWN 0xC4
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_HOSTSW_OWN 0xC8
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_HOSTSW_OWN 0xCC
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_CPU_GPI_IS 0x0100 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_GPI_IS 0x0104 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_GPI_IS 0x0108
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_GPI_IS 0x010C
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_CPU_GPI_IE 0x0120 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_GPI_IE 0x0124 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_GPI_IE 0x0128
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_GPI_IE 0x012C
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_CPU_GPI_GPE_STS 0x0140 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_GPI_GPE_STS 0x0144 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_GPI_GPE_STS 0x0148
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_GPI_GPE_STS 0x014C
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_CPU_GPI_GPE_EN 0x0160 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_GPI_GPE_EN 0x0164 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_GPI_GPE_EN 0x0168
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_GPI_GPE_EN 0x016C
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_CPU_SMI_STS 0x0180 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_SMI_STS 0x0184 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_SMI_STS 0x0188
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_J_SMI_STS 0x018C // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_CPU_SMI_EN 0x01A0 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_SMI_EN 0x01A4 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_SMI_EN 0x01A8
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_J_SMI_EN 0x01AC // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_CPU_NMI_STS 0x01C0 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_NMI_STS 0x01C4 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_NMI_STS 0x01C8
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_J_NMI_STS 0x01CC // Not
> supported setting for this group
> +
> +//#define R_CNL_PCH_H_GPIO_PCR_CPU_NMI_EN 0x01E0 // Not
> supported setting for this group
> +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_NMI_EN 0x01E4 // Not
> supported setting for this group
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_NMI_EN 0x01E8
> +//#define R_CNL_PCH_H_GPIO_PCR_GPP_J_NMI_EN 0x01EC // Not
> supported setting for this group
> +
> +#define R_CNL_PCH_H_GPIO_PCR_CPU_PADCFG_OFFSET 0x600
> +#define R_CNL_PCH_H_GPIO_PCR_JTAG_PADCFG_OFFSET 0x6B0
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_PADCFG_OFFSET 0x740
> +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_PADCFG_OFFSET 0x860
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHda.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHda.h
> new file mode 100644
> index 0000000000..bc099d9662
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHda.h
> @@ -0,0 +1,204 @@
> +/** @file
> + Register names for PCH High Definition Audio device.
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_HDA_H_
> +#define _PCH_REGS_HDA_H_
> +
> +//
> +// HD-A Controller Registers (D31:F3)
> +//
> +// PCI Configuration Space Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_HDA 31
> +#define PCI_FUNCTION_NUMBER_PCH_HDA 3
> +
> +#define R_HDA_CFG_PI 0x09
> +#define V_HDA_CFG_PI_ADSP_UAA 0x80
> +#define R_HDA_CFG_SCC 0x0A
> +#define V_HDA_CFG_SCC_ADSP 0x01
> +#define R_HDA_CFG_HDALBA 0x10
> +#define B_HDA_CFG_HDALBA_LBA 0xFFFFC000
> +#define V_HDA_CFG_HDBAR_SIZE (1 << 14)
> +#define R_HDA_CFG_HDAUBA 0x14
> +#define B_HDA_CFG_HDAUBA_UBA 0xFFFFFFFF
> +#define R_HDA_CFG_CGCTL 0x48
> +#define B_HDA_CFG_CGCTL_RSMTCGE BIT18
> +#define B_HDA_CFG_CGCTL_MISCBDCGE BIT6
> +#define R_HDA_CFG_PC 0x52
> +#define V_HDA_CFG_PC_PMES 0x18
> +#define N_HDA_CFG_PC_PMES 11
> +#define R_HDA_CFG_PCS 0x54
> +#define B_HDA_CFG_PCS_PMEE BIT8
> +#define B_HDA_CFG_PCS_PS (BIT1 | BIT0)
> +#define R_HDA_CFG_MMC 0x62
> +#define B_HDA_CFG_MMC_ME BIT0
> +#define R_HDA_CFG_DEVC 0x78
> +#define B_HDA_CFG_DEVC_NSNPEN BIT11
> +#define R_HDA_CFG_SEM1 0xC0
> +#define B_HDA_CFG_SEM1_LFLCS BIT24
> +#define B_HDA_CFG_SEM1_BLKC3DIS BIT17
> +#define B_HDA_CFG_SEM1_TMODE BIT12
> +#define B_HDA_CFG_SEM1_FIFORDYSEL (BIT10 | BIT9)
> +#define R_HDA_CFG_SEM2 0xC4
> +#define B_HDA_CFG_SEM2_BSMT (BIT27 | BIT26)
> +#define V_HDA_CFG_SEM2_BSMT 0x1
> +#define N_HDA_CFG_SEM2_BSMT 26
> +#define B_HDA_CFG_SEM2_VC0SNR BIT24
> +#define B_HDA_CFG_SEM2_DUM BIT23
> +#define R_HDA_CFG_SEM3L 0xC8
> +#define B_HDA_CFG_SEM3L_ISL1EXT2 (BIT21 | BIT20)
> +#define V_HDA_CFG_SEM3L_ISL1EXT2 0x2
> +#define N_HDA_CFG_SEM3L_ISL1EXT2 20
> +#define R_HDA_CFG_SEM4L 0xD0
> +#define B_HDA_CFG_SEM4L_OSL1EXT2 (BIT21 | BIT20)
> +#define V_HDA_CFG_SEM4L_OSL1EXT2 0x3
> +#define N_HDA_CFG_SEM4L_OSL1EXT2 20
> +
> +//
> +// Memory Space Registers
> +//
> +//
> +// Resides in 'HD Audio Global Registers' (0000h)
> +//
> +#define R_HDA_MEM_GCAP 0x00
> +#define R_HDA_MEM_GCTL 0x08
> +#define B_HDA_MEM_GCTL_CRST BIT0
> +
> +#define R_HDA_MEM_OUTPAY 0x04
> +#define R_HDA_MEM_INPAY 0x06
> +#define V_HDA_MEM_INPAY_DEFAULT 0x1C
> +
> +#define R_HDA_MEM_WAKEEN 0x0C
> +#define B_HDA_MEM_WAKEEN_SDI_3 BIT3
> +#define B_HDA_MEM_WAKEEN_SDI_2 BIT2
> +#define B_HDA_MEM_WAKEEN_SDI_1 BIT1
> +#define B_HDA_MEM_WAKEEN_SDI_0 BIT0
> +
> +#define R_HDA_MEM_WAKESTS 0x0E
> +#define B_HDA_MEM_WAKESTS_SDIN3 BIT3
> +#define B_HDA_MEM_WAKESTS_SDIN2 BIT2
> +#define B_HDA_MEM_WAKESTS_SDIN1 BIT1
> +#define B_HDA_MEM_WAKESTS_SDIN0 BIT0
> +
> +//
> +// Resides in 'HD Audio Controller Registers' (0030h)
> +//
> +#define R_HDA_MEM_IC 0x60
> +#define R_HDA_MEM_IR 0x64
> +#define R_HDA_MEM_ICS 0x68
> +#define B_HDA_MEM_ICS_IRV BIT1
> +#define B_HDA_MEM_ICS_ICB BIT0
> +
> +//
> +// Resides in 'HD Audio Processing Pipe Capability Structure' (0800h)
> +//
> +#define R_HDA_MEM_PPC 0x0800 // Processing Pipe
> Capability Structure (Memory Space, offset 0800h)
> +#define R_HDA_MEM_PPCTL (R_HDA_MEM_PPC + 0x04)
> +#define B_HDA_MEM_PPCTL_GPROCEN BIT30
> +
> +//
> +// Resides in 'HD Audio Multiple Links Capability Structure' (0C00h)
> +//
> +#define HDA_HDALINK_INDEX 0
> +#define HDA_IDISPLINK_INDEX 1
> +
> +#define R_HDA_MEM_MLC 0x0C00 // Multiple Links
> Capability Structure (Memory Space, offset 0C00h)
> +#define R_HDA_MEM_LCTLX(x) (R_HDA_MEM_MLC + (0x40 +
> (0x40 * (x)) + 0x04)) // x - Link index: 0 - HDA Link, 1 - iDisp Link
> +#define B_HDA_MEM_LCTLX_CPA BIT23
> +#define B_HDA_MEM_LCTLX_SPA BIT16
> +#define N_HDA_MEM_LCTLX_SCF 0
> +#define V_HDA_MEM_LCTLX_SCF_6MHZ 0x0
> +#define V_HDA_MEM_LCTLX_SCF_12MHZ 0x1
> +#define V_HDA_MEM_LCTLX_SCF_24MHZ 0x2
> +#define V_HDA_MEM_LCTLX_SCF_48MHZ 0x3
> +#define V_HDA_MEM_LCTLX_SCF_96MHZ 0x4
> +
> +//
> +// Resides in 'HD Audio Vendor Specific Registers' (1000h)
> +//
> +#define R_HDA_MEM_LTRC 0x1048
> +#define V_HDA_MEM_LTRC_GB 0x29
> +#define N_HDA_MEM_LTRC_GB 0
> +#define R_HDA_MEM_PCE 0x104B
> +#define B_HDA_MEM_PCE_D3HE BIT2
> +
> +//
> +// Private Configuration Space Registers
> +//
> +//
> +// Resides in IOSF & Fabric Configuration Registers (000h)
> +//
> +#define R_HDA_PCR_TTCCFG 0xE4
> +#define B_HDA_PCR_TTCCFG_HCDT BIT1
> +
> +//
> +// Resides in PCI & Codec Configuration Registers (500h)
> +//
> +#define R_HDA_PCR_PCICDCCFG 0x500 // PCI & Codec
> Configuration Registers (PCR, offset 500h)
> +#define B_HDA_PCR_PCICDCCFG_ACPIIN 0x0000FF00
> +#define N_HDA_PCR_PCICDCCFG_ACPIIN 8
> +#define R_HDA_PCR_FNCFG (R_HDA_PCR_PCICDCCFG + 0x30)
> +#define B_HDA_PCR_FNCFG_PGD BIT5
> +#define B_HDA_PCR_FNCFG_BCLD BIT4
> +#define B_HDA_PCR_FNCFG_CGD BIT3
> +#define B_HDA_PCR_FNCFG_ADSPD BIT2
> +#define B_HDA_PCR_FNCFG_HDASD BIT0
> +#define R_HDA_PCR_CDCCFG (R_HDA_PCR_PCICDCCFG +
> 0x34)
> +#define B_HDA_PCR_CDCCFG_DIS_SDIN2 BIT2
> +
> +//
> +// Resides in Power Management & EBB Configuration Registers (600h)
> +//
> +#define R_HDA_PCR_PWRMANCFG 0x600 // Power Management
> & EBB Configuration Registers (PCR, offset 600h)
> +#define R_HDA_PCR_APLLP0 (R_HDA_PCR_PWRMANCFG +
> 0x10)
> +#define V_HDA_PCR_APLLP0 0xFC1E0000
> +#define R_HDA_PCR_APLLP1 (R_HDA_PCR_PWRMANCFG +
> 0x14)
> +#define V_HDA_PCR_APLLP1 0x00003F00
> +#define R_HDA_PCR_APLLP2 (R_HDA_PCR_PWRMANCFG +
> 0x18)
> +#define V_HDA_PCR_APLLP2 0x0000011D
> +#define R_HDA_PCR_IOBCTL (R_HDA_PCR_PWRMANCFG +
> 0x1C)
> +#define B_HDA_PCR_IOBCTL_OSEL (BIT9 | BIT8)
> +#define V_HDA_PCR_IOBCTL_OSEL_HDALINK 0
> +#define V_HDA_PCR_IOBCTL_OSEL_HDALINK_I2S 1
> +#define V_HDA_PCR_IOBCTL_OSEL_I2S 3
> +#define N_HDA_PCR_IOBCTL_OSEL 8
> +#define B_HDA_PCR_IOBCTL_VSEL BIT1
> +#define R_HDA_PCR_PTDC (R_HDA_PCR_PWRMANCFG +
> 0x28)
> +#define B_HDA_PCR_PTDC_SRMIW (BIT6 | BIT5 | BIT4)
> +
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHsio.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHsio.h
> new file mode 100644
> index 0000000000..0cd69eb299
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHsio.h
> @@ -0,0 +1,170 @@
> +/** @file
> + Register definition for HSIO
> +
> +Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_HSIO_H_
> +#define _PCH_REGS_HSIO_H_
> +
> +#define B_HSIO_PCR_ACCESS_TYPE (BIT15 | BIT14)
> +#define N_HSIO_PCR_ACCESS_TYPE 14
> +#define V_HSIO_PCR_ACCESS_TYPE_BDCAST (BIT15 | BIT14)
> +#define V_HSIO_PCR_ACCESS_TYPE_MULCAST BIT15
> +#define B_HSIO_PCR_LANE_GROUP_NO (BIT13 | BIT12 |
> BIT11 | BIT10 | BIT9)
> +#define B_HSIO_PCR_FUNCTION_NO (BIT8 | BIT7)
> +#define N_HSIO_PCR_FUNCTION_NO 7
> +#define B_HSIO_PCR_REG_OFFSET (BIT6 | BIT5 | BIT4 |
> BIT3 | BIT2 | BIT1 | BIT0)
> +
> +#define V_HSIO_PCR_ACCESS_TYPE_BCAST 0x03
> +#define V_HSIO_PCR_ACCESS_TYPE_MCAST 0x02
> +#define V_HSIO_PCR_ACCESS_TYPE_UCAST 0x00
> +
> +#define V_HSIO_PCR_LANE_GROUP_NO_CMN_LANE 0x00
> +
> +#define V_HSIO_PCR_FUNCTION_NO_PCS 0x00
> +#define V_HSIO_PCR_FUNCTION_NO_TX 0x01
> +#define V_HSIO_PCR_FUNCTION_NO_RX 0x02
> +
> +#define V_HSIO_PCR_FUNCTION_NO_CMNDIG 0x00
> +#define V_HSIO_PCR_FUNCTION_NO_CMNANA 0x01
> +#define V_HSIO_PCR_FUNCTION_NO_PLL 0x02
> +
> +#define R_HSIO_PCR_PCS_DWORD4 0x10
> +
> +#define R_HSIO_PCR_PCS_DWORD8 0x20
> +#define B_HSIO_PCR_PCS_DWORD8_CRI_RXEB_PTR_INIT_4_0
> 0x1F000000
> +#define B_HSIO_PCR_PCS_DWORD8_CRI_RXEB_LOWATER_4_0
> 0x001F0000
> +#define N_HSIO_PCR_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 16
> +#define B_HSIO_PCR_PCS_DWORD8_CRI_RXEB_HIWATER_4_0
> 0x00001F00
> +#define N_HSIO_PCR_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 8
> +
> +#define R_HSIO_PCR_PCS_DWORD9 0x24
> +#define B_HSIO_PCR_PCS_DWORD9_REG_ENABLE_PWR_GATING BIT29
> +
> +#define R_HSIO_PCR_RX_DWORD8 0x220
> +#define B_HSIO_PCR_RX_DWORD8_ICFGDFETAP3_EN BIT10
> +
> +#define R_HSIO_PCR_RX_DWORD9 0x224
> +#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP4_OVERRIDE_EN BIT24
> +#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP3_OVERRIDE_EN BIT26
> +#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP2_OVERRIDE_EN BIT28
> +#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP1_OVERRIDE_EN BIT30
> +
> +#define R_HSIO_PCR_RX_DWORD12 0x230
> +#define B_HSIO_PCR_RX_DWORD12_O_CFGEWMARGINSEL BIT14
> +
> +#define R_HSIO_PCR_RX_DWORD20 0x250
> +#define B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0
> (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24)
> +#define N_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 24
> +
> +#define R_HSIO_PCR_RX_DWORD21 0x254
> +#define B_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0
> (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
> +#define N_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 8
> +#define B_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0
> (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
> +#define N_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 0
> +
> +#define R_HSIO_PCR_RX_DWORD23 0x25C
> +#define B_HSIO_PCR_RX_DWORD23_ICFGVGABLWTAP_OVERRIDE_EN
> BIT2
> +#define B_HSIO_PCR_RX_DWORD23_CFGVGATAP_ADAPT_OVERRIDE_EN
> BIT4
> +
> +#define R_HSIO_PCR_RX_DWORD25 0x264
> +#define B_HSIO_PCR_RX_DWORD25_RX_TAP_CFG_CTRL BIT3
> +#define B_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0
> 0x1F0000
> +#define N_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 16
> +
> +#define R_HSIO_PCR_RX_DWORD26 0x268
> +#define B_HSIO_PCR_RX_DWORD26_SATA_EQ_DIS BIT16
> +
> +#define R_HSIO_PCR_RX_DWORD34 0x288
> +#define B_HSIO_PCR_RX_DWORD34_MM_PH_OFC_SCALE_2_0 (BIT14 |
> BIT13 | BIT12)
> +#define N_HSIO_PCR_RX_DWORD34_MM_PH_OFC_SCALE_2_0 12
> +
> +#define R_HSIO_PCR_RX_DWORD44 0x2B0
> +#define B_HSIO_PCR_RX_DWORD44_0_DFE_DATASUMCAL0_7_0
> 0xFF0000
> +#define N_HSIO_PCR_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 16
> +
> +#define R_HSIO_PCR_RX_DWORD56 0x2E0
> +#define B_HSIO_PCR_RX_DWORD56_ICFGPIDACCFGVALID BIT16
> +
> +#define R_HSIO_PCR_RX_DWORD57 0x2E4
> +#define B_HSIO_PCR_RX_DWORD57_JIM_COURSE BIT30
> +#define B_HSIO_PCR_RX_DWORD57_JIM_ENABLE BIT29
> +#define B_HSIO_PCR_RX_DWORD57_JIMMODE BIT28
> +#define B_HSIO_PCR_RX_DWORD57_JIMNUMCYCLES_3_0
> 0x0F000000
> +#define N_HSIO_PCR_RX_DWORD57_JIMNUMCYCLES_3_0 24
> +#define B_HSIO_PCR_RX_DWORD57_ICFGMARGINEN BIT0
> +
> +#define R_HSIO_PCR_RX_DWORD59 0x2EC
> +#define R_HSIO_PCR_RX_DWORD60 0x2F0
> +
> +#define R_HSIO_PCR_TX_DWORD5 0x154
> +#define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 (BIT21
> | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
> +#define N_HSIO_PCR_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 16
> +#define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13
> | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
> +#define N_HSIO_PCR_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 8
> +
> +#define R_HSIO_PCR_TX_DWORD6 0x158
> +#define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 (BIT21
> | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
> +#define N_HSIO_PCR_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 16
> +#define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13
> | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
> +#define N_HSIO_PCR_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 8
> +#define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN1DEEMPH6P0_5_0 (BIT5
> | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
> +
> +#define R_HSIO_PCR_TX_DWORD8 0x160
> +#define B_HSIO_PCR_TX_DWORD8_ORATE10MARGIN_5_0 (BIT29 |
> BIT28 | BIT27 | BIT26 | BIT25 | BIT24)
> +#define N_HSIO_PCR_TX_DWORD8_ORATE10MARGIN_5_0 24
> +#define B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0 (BIT21 |
> BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
> +#define N_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0 16
> +#define B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 |
> BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
> +#define N_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0 8
> +
> +#define R_HSIO_PCR_TX_DWORD19 0x18C
> +
> +#define R_HSIO_PCR_CLANE0_CMN_ANA_DWORD2 0x80C8
> +#define
> B_HSIO_PCR_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_PLLEN_H_OVRDEN
> BIT5
> +#define
> B_HSIO_PCR_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_FULLCALRESET_L_
> OVERDEN BIT3
> +
> +#define R_HSIO_PCR_PLL_SSC_DWORD2 0x8188
> +#define B_HSIO_PCR_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 (BIT23 |
> BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
> +#define N_HSIO_PCR_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 16
> +#define B_HSIO_PCR_PLL_SSC_DWORD2_SSCSEN BIT10
> +#define N_HSIO_PCR_PLL_SSC_DWORD2_SSCSEN 10
> +
> +#define R_HSIO_PCR_PLL_SSC_DWORD3 0x818C
> +#define B_HSIO_PCR_PLL_SSC_DWORD3_SSC_PROPAGATE BIT0
> +
> +
> +#endif //_PCH_REGS_HSIO_H_
> +
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsIsh.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsIsh.h
> new file mode 100644
> index 0000000000..5b4e23c43f
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsIsh.h
> @@ -0,0 +1,79 @@
> +/** @file
> + Register names for PCH Integrated Sensor Hub (ISH3.0)
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_ISH_H_
> +#define _PCH_REGS_ISH_H_
> +
> +//
> +// ISH Controller Registers
> +//
> +// D19:F0
> +#define PCI_DEVICE_NUMBER_PCH_ISH 19
> +#define PCI_FUNCTION_NUMBER_PCH_ISH 0
> +
> +// PCI Configuration Space Registers
> +#define R_ISH_CFG_BAR0_LOW 0x10
> +#define R_ISH_CFG_BAR0_HIGH 0x14
> +#define V_ISH_CFG_BAR0_SIZE 0x100000
> +#define N_ISH_CFG_BAR0_ALIGNMENT 20
> +#define R_ISH_CFG_BAR1_LOW 0x18
> +#define R_ISH_CFG_BAR1_HIGH 0x1C
> +#define V_ISH_CFG_BAR1_SIZE 0x1000
> +#define N_ISH_CFG_BAR1_ALIGNMENT 12
> +
> +//
> +// ISH Private Configuration Space Registers (IOSF2OCP)
> +// (PID:ISH)
> +//
> +#define R_ISH_PCR_PMCTL 0x1D0 ///< Power
> Management
> +#define R_ISH_PCR_PCICFGCTRL 0x200 ///< PCI
> Configuration Control
> +#define B_ISH_PCR_PCICFGCTR_PCI_IRQ 0x0FF00000 ///<
> PCI IRQ number
> +#define N_ISH_PCR_PCICFGCTR_PCI_IRQ 20
> +#define B_ISH_PCR_PCICFGCTR_ACPI_IRQ 0x000FF000 ///<
> ACPI IRQ number
> +#define N_ISH_PCR_PCICFGCTR_ACPI_IRQ 12
> +#define B_ISH_PCR_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | BIT8) ///<
> Interrupt Pin
> +#define N_ISH_PCR_PCICFGCTR_IPIN1 8
> +#define B_ISH_PCR_PCICFGCTRL_BAR1DIS BIT7 ///<
> BAR1 Disable
> +
> +//
> +// Number of pins used by ISH controllers
> +//
> +#define PCH_ISH_PINS_PER_I2C_CONTROLLER 2
> +#define PCH_ISH_PINS_PER_UART_CONTROLLER 4
> +#define PCH_ISH_PINS_PER_SPI_CONTROLLER 4
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsItss.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsItss.h
> new file mode 100644
> index 0000000000..8d7c3f9015
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsItss.h
> @@ -0,0 +1,103 @@
> +/** @file
> + Register names for ITSS
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_ITSS_H_
> +#define _PCH_REGS_ITSS_H_
> +
> +//
> +// ITSS PCRs (PID:ITSS)
> +//
> +#define R_ITSS_PCR_PIRQA_ROUT 0x3100 ///< PIRQA
> Routing Control register
> +#define R_ITSS_PCR_PIRQB_ROUT 0x3101 ///< PIRQB Routing
> Control register
> +#define R_ITSS_PCR_PIRQC_ROUT 0x3102 ///< PIRQC Routing
> Control register
> +#define R_ITSS_PCR_PIRQD_ROUT 0x3103 ///< PIRQD
> Routing Control register
> +#define R_ITSS_PCR_PIRQE_ROUT 0x3104 ///< PIRQE Routing
> Control register
> +#define R_ITSS_PCR_PIRQF_ROUT 0x3105 ///< PIRQF Routing
> Control register
> +#define R_ITSS_PCR_PIRQG_ROUT 0x3106 ///< PIRQG
> Routing Control register
> +#define R_ITSS_PCR_PIRQH_ROUT 0x3107 ///< PIRQH
> Routing Control register
> +#define B_ITSS_PCR_PIRQX_ROUT_REN 0x80 ///< Interrupt
> Routing Enable
> +#define B_ITSS_PCR_PIRQX_ROUT_IR 0x0F ///< IRQ Routng
> +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_3 0x03 ///< Route PIRQx
> to IRQ3
> +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_4 0x04 ///< Route PIRQx
> to IRQ4
> +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_5 0x05 ///< Route PIRQx
> to IRQ5
> +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_6 0x06 ///< Route PIRQx
> to IRQ6
> +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_7 0x07 ///< Route PIRQx
> to IRQ7
> +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_9 0x09 ///< Route PIRQx
> to IRQ9
> +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_10 0x0A ///< Route
> PIRQx to IRQ10
> +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_11 0x0B ///< Route
> PIRQx to IRQ11
> +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_12 0x0C ///< Route
> PIRQx to IRQ12
> +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_14 0x0E ///< Route
> PIRQx to IRQ14
> +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_15 0x0F ///< Route PIRQx
> to IRQ15
> +
> +#define R_ITSS_PCR_PIR0 0x3140 ///< PCI Interrupt
> Route 0
> +#define R_ITSS_PCR_PIR1 0x3142 ///< PCI Interrupt
> Route 1
> +#define R_ITSS_PCR_PIR2 0x3144 ///< PCI Interrupt
> Route 2
> +#define R_ITSS_PCR_PIR3 0x3146 ///< PCI Interrupt
> Route 3
> +#define R_ITSS_PCR_PIR4 0x3148 ///< PCI Interrupt
> Route 4
> +#define R_ITSS_PCR_PIR5 0x314A ///< PCI Interrupt
> Route 5
> +#define R_ITSS_PCR_PIR6 0x314C ///< PCI Interrupt
> Route 6
> +#define R_ITSS_PCR_PIR7 0x314E ///< PCI Interrupt
> Route 7
> +#define R_ITSS_PCR_PIR8 0x3150 ///< PCI Interrupt
> Route 8
> +#define R_ITSS_PCR_PIR9 0x3152 ///< PCI Interrupt
> Route 9
> +#define R_ITSS_PCR_PIR10 0x3154 ///< PCI Interrupt
> Route 10
> +#define R_ITSS_PCR_PIR11 0x3156 ///< PCI Interrupt
> Route 11
> +#define R_ITSS_PCR_PIR12 0x3158 ///< PCI Interrupt
> Route 12
> +
> +#define R_ITSS_PCR_GIC 0x31FC ///< General Interrupt
> Control
> +#define B_ITSS_PCR_GIC_MAX_IRQ_24 BIT9 ///< Max IRQ
> entry size, 1 = 24 entry size, 0 = 120 entry size
> +#define B_ITSS_PCR_GIC_AME BIT17 ///< Alternate Access
> Mode Enable
> +#define B_ITSS_PCR_GIC_SPS BIT16 ///< Shutdown Policy
> Select
> +#define R_ITSS_PCR_IPC0 0x3200 ///< Interrupt Polarity
> Control 0
> +#define R_ITSS_PCR_IPC1 0x3204 ///< Interrupt Polarity
> Control 1
> +#define R_ITSS_PCR_IPC2 0x3208 ///< Interrupt Polarity
> Control 2
> +#define R_ITSS_PCR_IPC3 0x320C ///< Interrupt Polarity
> Control 3
> +#define R_ITSS_PCR_ITSSPRC 0x3300 ///< ITSS Power
> Reduction Control
> +#define B_ITSS_PCR_ITSSPRC_PGCBDCGE BIT4 ///< PGCB
> Dynamic Clock Gating Enable
> +#define B_ITSS_PCR_ITSSPRC_HPETDCGE BIT3 ///< HPET
> Dynamic Clock Gating Enable
> +#define B_ITSS_PCR_ITSSPRC_8254CGE BIT2 ///< 8254 Static
> Clock Gating Enable
> +#define B_ITSS_PCR_ITSSPRC_IOSFICGE BIT1 ///< IOSF-Sideband
> Interface Clock Gating Enable
> +#define B_ITSS_PCR_ITSSPRC_ITSSCGE BIT0 ///< ITSS Clock Gate
> Enable
> +#define R_ITSS_PCR_NMI 0x3330 ///< NMI Control
> +#define N_ITSS_PCR_NMI_NMI2SMI_STS 3 ///< NMI2SMI
> Status
> +#define N_ITSS_PCR_NMI_NMI2SMI_EN 2 ///< NMI2SMI
> Enable
> +#define B_ITSS_PCR_NMI_NMI2SMI_EN BIT2 ///< NMI2SMI
> Enable
> +#define B_ITSS_PCR_NMI_NMI_NOW_STS BIT1 ///<
> NMI_NOW_STS
> +#define B_ITSS_PCR_NMI_NMI_NOW BIT0 ///< NMI_NOW
> +#define R_ITSS_PCR_MMC 0x3334 ///< Master Message
> Control
> +#define B_ITSS_PCR_MMC_MSTRMSG_EN BIT0 ///< Master
> Message Enable
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLan.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLan.h
> new file mode 100644
> index 0000000000..f649873f67
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLan.h
> @@ -0,0 +1,58 @@
> +/** @file
> + Register names for PCH LAN device
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_LAN_H_
> +#define _PCH_REGS_LAN_H_
> +
> +//
> +// Gigabit LAN Controller configuration registers (D31:F6)
> +//
> +#define PCI_DEVICE_NUMBER_PCH_LAN 31
> +#define PCI_FUNCTION_NUMBER_PCH_LAN 6
> +
> +#define R_LAN_CFG_MBARA 0x10
> +#define N_LAN_CFG_MBARA_ALIGN 17
> +#define R_LAN_CFG_PMCS 0xCC
> +#define B_LAN_CFG_PMCS_PS (BIT1 | BIT0)
> +#define V_LAN_CFG_PMCS_PS0 0x00
> +#define R_LAN_MEM_CSR_RAL 0x5400
> +#define R_LAN_MEM_CSR_RAH 0x5404
> +#define B_LAN_MEM_CSR_RAH_RAH 0x0000FFFF
> +#define R_LAN_MEM_CSR_WUC 0x5800
> +#define B_LAN_MEM_CSR_WUC_APME BIT0
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h
> new file mode 100644
> index 0000000000..34fc3c4dd2
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h
> @@ -0,0 +1,360 @@
> +/** @file
> + Register names for PCH LPC/eSPI device
> +
> +Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_LPC_H_
> +#define _PCH_REGS_LPC_H_
> +
> +#define B_LPC_CFG_DID 0xFFE0
> +
> +//
> +// PCI to LPC Bridge Registers (D31:F0)
> +//
> +#define PCI_DEVICE_NUMBER_PCH_LPC 31
> +#define PCI_FUNCTION_NUMBER_PCH_LPC 0
> +
> +#define V_LPC_CFG_VENDOR_ID V_PCH_INTEL_VENDOR_ID
> +
> +
> +#define R_LPC_CFG_SERIRQ_CNT 0x64
> +#define B_LPC_CFG_SERIRQ_CNT_SIRQEN BIT7
> +#define B_LPC_CFG_SERIRQ_CNT_SIRQMD BIT6
> +#define B_LPC_CFG_SERIRQ_CNT_SIRQSZ (BIT5 | BIT4 | BIT3 | BIT2)
> +#define N_LPC_CFG_SERIRQ_CNT_SIRQSZ 2
> +#define B_LPC_CFG_SERIRQ_CNT_SFPW (BIT1 | BIT0)
> +#define N_LPC_CFG_SERIRQ_CNT_SFPW 0
> +#define V_LPC_CFG_SERIRQ_CNT_SFPW_4CLK 0x00
> +#define V_LPC_CFG_SERIRQ_CNT_SFPW_6CLK 0x01
> +#define V_LPC_CFG_SERIRQ_CNT_SFPW_8CLK 0x02
> +
> +#define R_LPC_CFG_IOD 0x80
> +#define B_LPC_CFG_IOD_FDD BIT12
> +#define N_LPC_CFG_IOD_FDD 12
> +#define V_LPC_CFG_IOD_FDD_3F0 0
> +#define V_LPC_CFG_IOD_FDD_370 1
> +#define B_LPC_CFG_IOD_LPT (BIT9 | BIT8)
> +#define N_LPC_CFG_IOD_LPT 8
> +#define V_LPC_CFG_IOD_LPT_378 0
> +#define V_LPC_CFG_IOD_LPT_278 1
> +#define V_LPC_CFG_IOD_LPT_3BC 2
> +#define B_LPC_CFG_IOD_COMB (BIT6 | BIT5 |BIT4)
> +#define N_LPC_CFG_IOD_COMB 4
> +#define V_LPC_CFG_IOD_COMB_3F8 0
> +#define V_LPC_CFG_IOD_COMB_2F8 1
> +#define V_LPC_CFG_IOD_COMB_220 2
> +#define V_LPC_CFG_IOD_COMB_228 3
> +#define V_LPC_CFG_IOD_COMB_238 4
> +#define V_LPC_CFG_IOD_COMB_2E8 5
> +#define V_LPC_CFG_IOD_COMB_338 6
> +#define V_LPC_CFG_IOD_COMB_3E8 7
> +#define B_LPC_CFG_IOD_COMA (BIT2 | BIT1 | BIT0)
> +#define N_LPC_CFG_IOD_COMA 0
> +#define V_LPC_CFG_IOD_COMA_3F8 0
> +#define V_LPC_CFG_IOD_COMA_2F8 1
> +#define V_LPC_CFG_IOD_COMA_220 2
> +#define V_LPC_CFG_IOD_COMA_228 3
> +#define V_LPC_CFG_IOD_COMA_238 4
> +#define V_LPC_CFG_IOD_COMA_2E8 5
> +#define V_LPC_CFG_IOD_COMA_338 6
> +#define V_LPC_CFG_IOD_COMA_3E8 7
> +#define R_LPC_CFG_IOE 0x82
> +#define B_LPC_CFG_IOE_ME2 BIT13 ///<
> Microcontroller Enable #2, Enables decoding of I/O locations 4Eh and 4Fh to
> LPC
> +#define B_LPC_CFG_IOE_SE BIT12 ///< Super I/O
> Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC.
> +#define B_LPC_CFG_IOE_ME1 BIT11 ///<
> Microcontroller Enable #1, Enables decoding of I/O locations 62h and 66h to
> LPC.
> +#define B_LPC_CFG_IOE_KE BIT10 ///< Keyboard
> Enable, Enables decoding of the keyboard I/O locations 60h and 64h to LPC.
> +#define B_LPC_CFG_IOE_HGE BIT9 ///< High
> Gameport Enable, Enables decoding of the I/O locations 208h to 20Fh to LPC.
> +#define B_LPC_CFG_IOE_LGE BIT8 ///< Low
> Gameport Enable, Enables decoding of the I/O locations 200h to 207h to LPC.
> +#define B_LPC_CFG_IOE_FDE BIT3 ///< Floppy
> Drive Enable, Enables decoding of the FDD range to LPC. Range is selected by
> LIOD.FDE
> +#define B_LPC_CFG_IOE_PPE BIT2 ///< Parallel
> Port Enable, Enables decoding of the LPT range to LPC. Range is selected by
> LIOD.LPT.
> +#define B_LPC_CFG_IOE_CBE BIT1 ///< Com Port B
> Enable, Enables decoding of the COMB range to LPC. Range is selected LIOD.CB.
> +#define B_LPC_CFG_IOE_CAE BIT0 ///< Com Port A
> Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA.
> +#define R_LPC_CFG_GEN1_DEC 0x84
> +#define R_LPC_CFG_GEN2_DEC 0x88
> +#define R_LPC_CFG_GEN3_DEC 0x8C
> +#define R_LPC_CFG_GEN4_DEC 0x90
> +#define B_LPC_CFG_GENX_DEC_IODRA 0x00FC0000
> +#define B_LPC_CFG_GENX_DEC_IOBAR 0x0000FFFC
> +#define B_LPC_CFG_GENX_DEC_EN 0x00000001
> +#define R_LPC_CFG_ULKMC 0x94
> +#define B_LPC_CFG_ULKMC_SMIBYENDPS BIT15
> +#define B_LPC_CFG_ULKMC_TRAPBY64W BIT11
> +#define B_LPC_CFG_ULKMC_TRAPBY64R BIT10
> +#define B_LPC_CFG_ULKMC_TRAPBY60W BIT9
> +#define B_LPC_CFG_ULKMC_TRAPBY60R BIT8
> +#define B_LPC_CFG_ULKMC_SMIATENDPS BIT7
> +#define B_LPC_CFG_ULKMC_PSTATE BIT6
> +#define B_LPC_CFG_ULKMC_A20PASSEN BIT5
> +#define B_LPC_CFG_ULKMC_USBSMIEN BIT4
> +#define B_LPC_CFG_ULKMC_64WEN BIT3
> +#define B_LPC_CFG_ULKMC_64REN BIT2
> +#define B_LPC_CFG_ULKMC_60WEN BIT1
> +#define B_LPC_CFG_ULKMC_60REN BIT0
> +#define R_LPC_CFG_LGMR 0x98
> +#define B_LPC_CFG_LGMR_MA 0xFFFF0000
> +#define B_LPC_CFG_LGMR_LMRD_EN BIT0
> +#define R_ESPI_CFG_CS1IORE 0xA0
> +#define R_ESPI_CFG_CS1IORE_DPCS1RE BIT14
> +#define R_ESPI_CFG_CS1GIR1 0xA4
> +#define R_ESPI_CFG_CS1GMR1 0xA8
> +
> +#define R_LPC_CFG_FWH_BIOS_SEL 0xD0
> +#define B_LPC_CFG_FWH_BIOS_SEL_F8 0xF0000000
> +#define B_LPC_CFG_FWH_BIOS_SEL_F0 0x0F000000
> +#define B_LPC_CFG_FWH_BIOS_SEL_E8 0x00F00000
> +#define B_LPC_CFG_FWH_BIOS_SEL_E0 0x000F0000
> +#define B_LPC_CFG_FWH_BIOS_SEL_D8 0x0000F000
> +#define B_LPC_CFG_FWH_BIOS_SEL_D0 0x00000F00
> +#define B_LPC_CFG_FWH_BIOS_SEL_C8 0x000000F0
> +#define B_LPC_CFG_FWH_BIOS_SEL_C0 0x0000000F
> +#define R_LPC_CFG_FWH_BIOS_SEL2 0xD4
> +#define B_LPC_CFG_FWH_BIOS_SEL2_70 0xF000
> +#define B_LPC_CFG_FWH_BIOS_SEL2_60 0x0F00
> +#define B_LPC_CFG_FWH_BIOS_SEL2_50 0x00F0
> +#define B_LPC_CFG_FWH_BIOS_SEL2_40 0x000F
> +#define R_LPC_CFG_BDE 0xD8 ///<
> BIOS decode enable
> +#define B_LPC_CFG_BDE_F8 BIT15
> +#define B_LPC_CFG_BDE_F0 BIT14
> +#define B_LPC_CFG_BDE_E8 BIT13
> +#define B_LPC_CFG_BDE_E0 BIT12
> +#define B_LPC_CFG_BDE_D8 BIT11
> +#define B_LPC_CFG_BDE_D0 BIT10
> +#define B_LPC_CFG_BDE_C8 BIT9
> +#define B_LPC_CFG_BDE_C0 BIT8
> +#define B_LPC_CFG_BDE_LEG_F BIT7
> +#define B_LPC_CFG_BDE_LEG_E BIT6
> +#define B_LPC_CFG_BDE_70 BIT3
> +#define B_LPC_CFG_BDE_60 BIT2
> +#define B_LPC_CFG_BDE_50 BIT1
> +#define B_LPC_CFG_BDE_40 BIT0
> +#define R_LPC_CFG_PCC 0xE0
> +#define B_LPC_CFG_PCC_CLKRUN_EN BIT0
> +
> +#define B_LPC_CFG_FVEC0_USB_PORT_CAP (BIT11 | BIT10)
> +#define V_LPC_CFG_FVEC0_USB_14_PORT 0x00000000
> +#define V_LPC_CFG_FVEC0_USB_12_PORT 0x00000400
> +#define V_LPC_CFG_FVEC0_USB_10_PORT 0x00000800
> +#define B_LPC_CFG_FVEC0_SATA_RAID_CAP BIT7
> +#define B_LPC_CFG_FVEC0_SATA_PORT23_CAP BIT6
> +#define B_LPC_CFG_FVEC0_SATA_PORT1_6GB_CAP BIT3
> +#define B_LPC_CFG_FVEC0_SATA_PORT0_6GB_CAP BIT2
> +#define B_LPC_CFG_FVEC0_PCI_CAP BIT1
> +#define R_LPC_CFG_FVEC1 0x01
> +#define B_LPC_CFG_FVEC1_USB_R_CAP BIT22
> +#define R_LPC_CFG_FVEC2 0x02
> +#define V_LPC_CFG_FVEC2_PCIE_PORT78_CAP 0x00200000
> +#define V_LPC_CFG_FVEC2_PCH_IG_SUPPORT_CAP 0x00020000 ///<
> PCH Integrated Graphics Support Capability
> +#define R_LPC_CFG_FVEC3 0x03
> +#define B_LPC_CFG_FVEC3_DCMI_CAP BIT13 ///< Data
> Center Manageability Interface (DCMI) Capability
> +#define B_LPC_CFG_FVEC3_NM_CAP BIT12 ///< Node
> Manager Capability
> +
> +#define R_LPC_CFG_MDAP 0xC0
> +#define B_LPC_CFG_MDAP_POLICY_EN BIT31
> +#define B_LPC_CFG_MDAP_PDMA_EN BIT30
> +#define B_LPC_CFG_MDAP_VALUE 0x0001FFFF
> +
> +//
> +// APM Registers
> +//
> +#define R_PCH_IO_APM_CNT 0xB2
> +#define R_PCH_IO_APM_STS 0xB3
> +
> +#define R_LPC_CFG_BC 0xDC ///< Bios Control
> +#define S_LPC_CFG_BC 1
> +#define B_LPC_CFG_BC_BILD BIT7 ///< BIOS
> Interface Lock-Down
> +#define B_LPC_CFG_BC_BBS BIT6 ///< Boot BIOS
> strap
> +#define N_LPC_CFG_BC_BBS 6
> +#define V_LPC_CFG_BC_BBS_SPI 0 ///< Boot BIOS
> strapped to SPI
> +#define V_LPC_CFG_BC_BBS_LPC 1 ///< Boot BIOS
> strapped to LPC
> +#define B_LPC_CFG_BC_EISS BIT5 ///< Enable
> InSMM.STS
> +#define B_LPC_CFG_BC_TS BIT4 ///< Top Swap
> +#define B_LPC_CFG_BC_LE BIT1 ///< Lock Enable
> +#define N_LPC_CFG_BC_LE 1
> +#define B_LPC_CFG_BC_WPD BIT0 ///< Write
> Protect Disable
> +
> +#define R_ESPI_CFG_PCBC 0xDC ///< Peripheral
> Channel BIOS Control
> +#define S_ESPI_CFG_PCBC 4 ///< Peripheral
> Channel BIOS Control register size
> +#define B_ESPI_CFG_PCBC_BWRE BIT11 ///< BIOS
> Write Report Enable
> +#define N_ESPI_CFG_PCBC_BWRE 11 ///< BIOS
> Write Report Enable bit position
> +#define B_ESPI_CFG_PCBC_BWRS BIT10 ///< BIOS
> Write Report Status
> +#define N_ESPI_CFG_PCBC_BWRS 10 ///< BIOS
> Write Report Status bit position
> +#define B_ESPI_CFG_PCBC_BWPDS BIT8 ///< BIOS
> Write Protect Disable Status
> +#define N_ESPI_CFG_PCBC_BWPDS 8 ///< BIOS
> Write Protect Disable Status bit position
> +#define B_ESPI_CFG_PCBC_ESPI_EN BIT2 ///< eSPI
> Enable Pin Strap
> +#define B_ESPI_CFG_PCBC_LE BIT1 ///< Lock Enable
> +#define N_ESPI_CFG_PCBC_LE 1
> +
> +//
> +// eSPI slave registers
> +//
> +#define R_ESPI_SLAVE_CHA_0_CAP_AND_CONF 0x10 ///<
> Channel 0 Capabilities and Configurations
> +#define B_ESPI_SLAVE_BME BIT2 ///< Bus Master
> Enable
> +
> +//
> +// Processor interface registers
> +//
> +#define R_PCH_IO_NMI_SC 0x61
> +#define B_PCH_IO_NMI_SC_SERR_NMI_STS BIT7
> +#define B_PCH_IO_NMI_SC_IOCHK_NMI_STS BIT6
> +#define B_PCH_IO_NMI_SC_TMR2_OUT_STS BIT5
> +#define B_PCH_IO_NMI_SC_REF_TOGGLE BIT4
> +#define B_PCH_IO_NMI_SC_IOCHK_NMI_EN BIT3
> +#define B_PCH_IO_NMI_SC_PCI_SERR_EN BIT2
> +#define B_PCH_IO_NMI_SC_SPKR_DAT_EN BIT1
> +#define B_PCH_IO_NMI_SC_TIM_CNT2_EN BIT0
> +#define R_PCH_IO_NMI_EN 0x70
> +#define B_PCH_IO_NMI_EN_NMI_EN BIT7
> +
> +//
> +// Reset Generator I/O Port
> +//
> +#define R_PCH_IO_RST_CNT 0xCF9
> +#define B_PCH_IO_RST_CNT_FULL_RST BIT3
> +#define B_PCH_IO_RST_CNT_RST_CPU BIT2
> +#define B_PCH_IO_RST_CNT_SYS_RST BIT1
> +#define V_PCH_IO_RST_CNT_FULLRESET 0x0E
> +#define V_PCH_IO_RST_CNT_HARDRESET 0x06
> +#define V_PCH_IO_RST_CNT_SOFTRESET 0x04
> +#define V_PCH_IO_RST_CNT_HARDSTARTSTATE 0x02
> +#define V_PCH_IO_RST_CNT_SOFTSTARTSTATE 0x00
> +
> +//
> +// RTC register
> +//
> +#define R_RTC_IO_INDEX 0x70
> +#define R_RTC_IO_TARGET 0x71
> +#define R_RTC_IO_EXT_INDEX 0x72
> +#define R_RTC_IO_EXT_TARGET 0x73
> +#define R_RTC_IO_INDEX_ALT 0x74
> +#define R_RTC_IO_TARGET_ALT 0x75
> +#define R_RTC_IO_EXT_INDEX_ALT 0x76
> +#define R_RTC_IO_EXT_TARGET_ALT 0x77
> +#define R_RTC_IO_REGA 0x0A
> +#define B_RTC_IO_REGA_UIP BIT7
> +#define R_RTC_IO_REGB 0x0B
> +#define B_RTC_IO_REGB_SET 0x80
> +#define B_RTC_IO_REGB_PIE 0x40
> +#define B_RTC_IO_REGB_AIE 0x20
> +#define B_RTC_IO_REGB_UIE 0x10
> +#define B_RTC_IO_REGB_DM 0x04
> +#define B_RTC_IO_REGB_HOURFORM 0x02
> +#define R_RTC_IO_REGC 0x0C
> +#define R_RTC_IO_REGD 0x0D
> +
> +//
> +// Private Configuration Register
> +// RTC PCRs (PID:RTC)
> +//
> +#define R_RTC_PCR_CONF 0x3400 ///< RTC
> Configuration register
> +#define B_RTC_PCR_CONF_BILD BIT31 ///< BIOS
> Interface Lock-Down
> +#define B_RTC_PCR_CONF_HPM_HW_DIS BIT6 ///< RTC
> High Power Mode HW Disable
> +#define B_RTC_PCR_CONF_UCMOS_LOCK BIT4 ///<
> Upper 128 Byte Lock
> +#define B_RTC_PCR_CONF_LCMOS_LOCK BIT3 ///<
> Lower 128 Byte Lock
> +#define B_RTC_PCR_CONF_UCMOS_EN BIT2 ///<
> Upper CMOS bank enable
> +#define R_RTC_PCR_BUC 0x3414 ///< Backed Up
> Control
> +#define B_RTC_PCR_BUC_DSO BIT4 ///< Daylight
> Savings Override
> +#define B_RTC_PCR_BUC_TS BIT0 ///< Top Swap
> +#define R_RTC_PCR_RTCDCG 0x3418 ///< RTC
> Dynamic Clock Gating Control
> +#define R_RTC_PCR_RTCDCG_RTCPGCBDCGEN BIT2 ///<
> pgcb_clk (12Mhz) Dynamic Clock Gate Enable
> +#define R_RTC_PCR_RTCDCG_RTCPCICLKDCGEN BIT1 ///<
> ipciclk_clk (24 MHz) Dynamic Clock Gate Enable
> +#define R_RTC_PCR_RTCDCG_RTCROSIDEDCGEN BIT0 ///<
> rosc_side_clk (120 MHz) Dynamic Clock Gate Enable
> +#define R_RTC_PCR_PG1_CP_LO 0x3428
> +#define R_RTC_PCR_PG1_AC_LO 0x3438
> +#define R_RTC_PCR_3F00 0x3F00
> +#define R_RTC_PCR_UIPSMI 0x3F04 ///< RTC
> Update In Progress SMI Control
> +
> +//
> +// LPC PCR Registers
> +//
> +#define R_LPC_PCR_HVMTCTL 0x3410
> +#define R_LPC_PCR_GCFD 0x3418
> +#define B_LPC_PCR_GCFD_SRVR_CLKRUN_EN BIT2 ///<
> Enables the CLKRUN# logic to stop the PCI clocks
> +#define R_LPC_PCR_PRC 0x341C
> +#define R_LPC_PCR_PCT 0x3420
> +#define R_LPC_PCR_SCT 0x3424
> +#define R_LPC_PCR_LPCCT 0x3428
> +#define R_LPC_PCR_ULTOR 0x3500
> +
> +//
> +// eSPI PCR Registers
> +//
> +#define R_ESPI_PCR_SLV_CFG_REG_CTL 0x4000 ///<
> Slave Configuration Register and Link Control
> +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE BIT31 ///<
> Slave Configuration Register Access Enable
> +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28)
> ///< Slave Configuration Register Access Status
> +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS 28 ///<
> Slave Configuration Register Access Status bit position
> +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL BIT27 ///<
> IOSF-SB eSPI Link Configuration Lock
> +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR 7 ///<
> No errors (transaction completed successfully)
> +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) ///<
> Slave ID
> +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SID 19 ///<
> Slave ID bit position
> +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) ///<
> Slave Configuration Register Access Type
> +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT 16 ///<
> Slave Configuration Register Access Type bit position
> +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RD 0 ///<
> Slave Configuration register read from address SCRA[11:0]
> +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_WR 1 ///<
> Slave Configuration register write to address SCRA[11:0]
> +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_STS 2 ///<
> Slave Status register read
> +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RS 3 ///<
> In-Band reset
> +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA 0x00000FFF
> ///< Slave Configuration Register Address
> +#define R_ESPI_PCR_SLV_CFG_REG_DATA 0x4004 ///<
> Slave Configuration Register Data
> +
> +#define R_ESPI_PCR_PCERR_SLV0 0x4020 ///< Peripheral
> Channel Error for Slave 0
> +#define B_ESPI_PCR_PCERR_PCURD BIT24 ///< Peripheral
> Channel Unsupported Request Detected
> +#define R_ESPI_PCR_PCERR_SLV1 0x4024 ///< Peripheral
> Channel Error for Slave 1
> +#define R_ESPI_PCR_VWERR_SLV0 0x4030 ///< Virtual
> Wire Channel Error for Slave 0
> +#define R_ESPI_PCR_VWERR_SLV1 0x4034 ///< Virtual
> Wire Channel Error for Slave 1
> +#define R_ESPI_PCR_FCERR_SLV0 0x4040 ///< Flash Access
> Channel Error for Slave 0
> +#define B_ESPI_PCR_FCERR_SAFBLK BIT17 ///< SAF Blocked
> (SAFBLK)
> +#define B_ESPI_PCR_XERR_XNFEE (BIT14 | BIT13) ///< Non-Fatal
> Error Reporting Enable bits
> +#define N_ESPI_PCR_XERR_XNFEE 13 ///< Non-Fatal
> Error Reporting Enable bit position
> +#define V_ESPI_PCR_XERR_XNFEE_SMI 3 ///< Enable
> Non-Fatal Error Reporting as SMI
> +#define B_ESPI_PCR_XERR_XNFES BIT12 ///< Fatal Error
> Status
> +#define B_ESPI_PCR_XERR_XFEE (BIT6 | BIT5) ///< Fatal Error
> Reporting Enable bits
> +#define N_ESPI_PCR_XERR_XFEE 5 ///< Fatal Error
> Reporting Enable bit position
> +#define V_ESPI_PCR_XERR_XFEE_SMI 3 ///< Enable Fatal
> Error Reporting as SMI
> +#define B_ESPI_PCR_XERR_XFES BIT4 ///< Fatal Error
> Status
> +#define S_ESPI_PCR_XERR 4 ///< Channel register
> sizes
> +#define B_ESPI_PCR_PCERR_SLV0_PCURD BIT24 ///<
> Peripheral Channel Unsupported Request Detected
> +#define R_ESPI_PCR_LNKERR_SLV0 0x4050 ///< Link Error
> for Slave 0
> +#define S_ESPI_PCR_LNKERR_SLV0 4 ///< Link Error for
> Slave 0 register size
> +#define B_ESPI_PCR_LNKERR_SLV0_SLCRR BIT31 ///< eSPI Link
> and Slave Channel Recovery Required
> +#define B_ESPI_PCR_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fatal
> Error Type 1 Reporting Enable
> +#define N_ESPI_PCR_LNKERR_SLV0_LFET1E 21 ///< Fatal
> Error Type 1 Reporting Enable bit position
> +#define V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI 3 ///< Enable
> Fatal Error Type 1 Reporting as SMI
> +#define B_ESPI_PCR_LNKERR_SLV0_LFET1S BIT20 ///< Link Fatal
> Error Type 1 Status
> +#define R_ESPI_PCR_LNKERR_SLV1 0x4054 ///< Link Error
> for Slave 1
> +#define R_ESPI_PCR_CFG_VAL 0xC00C ///< ESPI Enabled
> Strap
> +#define B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0 ///< ESPI
> Enabled Strap bit position
> +#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI
> Sofstraps Register 0
> +#define R_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1#
> Enable
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> new file mode 100644
> index 0000000000..74789a87ce
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> @@ -0,0 +1,61 @@
> +/** @file
> + Register names for PCH LPC/eSPI device
> +
> + Conventions:
> +
> + - Prefixes:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register sizes
> + Definitions beginning with "N_" are the bit position
> + - In general, PCH registers are denoted by "_PCH_" in register names
> + - Registers / bits that are different between PCH generations are denoted by
> + "_PCH_[generation_name]_" in register/bit names.
> + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit
> names.
> + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit
> names.
> + e.g., "_PCH_H_", "_PCH_LP_"
> + Registers / bits names without _H_ or _LP_ apply for both H and LP.
> + - Registers / bits that are different between SKUs are denoted by
> "_[SKU_name]"
> + at the end of the register/bit names
> + - Registers / bits of new devices introduced in a PCH generation will be just
> named
> + as "_PCH_" without [generation_name] inserted.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_LPC_CNL_H_
> +#define _PCH_REGS_LPC_CNL_H_
> +
> +#define V_LPC_CFG_DID_CNL_H 0xA300
> +#define V_LPC_CFG_DID_CNL_LP 0x9D80
> +
> +//
> +// PCH-LP Device IDs
> +//
> +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_SUPER_SKU 0x9D80
> ///< PCH LP Mobile
> +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_0 0x9D81
> ///< PCH LP Mobile (U)
> +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_1 0x9D82
> ///< PCH LP Mobile Locked
> +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_2 0x9D83
> ///< PCH LP Mobile (Y)
> +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_3 0x9D84
> ///< PCH LP Mobile (U)
> +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_4 0x9D85
> ///< PCH LP Mobile (U)
> +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_5 0x9D86
> ///< PCH LP Mobile (Y)
> +
> +//
> +// PCH-H Desktop LPC Device IDs
> +//
> +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A300_SKU 0xA300
> ///< LPC/eSPI Controller
> +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A303_SKU 0xA303
> ///< PCH H Mobile H310
> +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A304_SKU 0xA304
> ///< PCH H Mobile H370
> +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A305_SKU 0xA305
> ///< PCH H Mobile Z390
> +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A306_SKU 0xA306
> ///< PCH H Mobile Q370
> +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A309_SKU 0xA309
> ///< PCH H Mobile C246
> +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30A_SKU 0xA30A
> ///< PCH H Mobile C242
> +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30B_SKU 0xA30B
> ///< PCH H Mobile X399
> +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30C_SKU 0xA30C
> ///< PCH H Mobile QM370
> +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30D_SKU 0xA30D
> ///< PCH H Mobile HM370
> +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30E_SKU 0xA30E
> ///< PCH H Mobile CM246
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsP2sb.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsP2sb.h
> new file mode 100644
> index 0000000000..db6a8c4e95
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsP2sb.h
> @@ -0,0 +1,116 @@
> +/** @file
> + Register names for PCH P2SB device
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_P2SB_H_
> +#define _PCH_REGS_P2SB_H_
> +
> +//
> +// PCI to P2SB Bridge Registers (D31:F1)
> +//
> +#define PCI_DEVICE_NUMBER_PCH_P2SB 31
> +#define PCI_FUNCTION_NUMBER_PCH_P2SB 1
> +
> +#define V_P2SB_CFG_VENDOR_ID
> V_PCH_INTEL_VENDOR_ID
> +#define R_P2SB_CFG_SBREG_BAR 0x10
> +#define B_P2SB_CFG_SBREG_RBA 0xFF000000
> +#define R_P2SB_CFG_SBREG_BARH 0x14
> +#define B_P2SB_CFG_SBREG_RBAH 0xFFFFFFFF
> +#define R_P2SB_CFG_VBDF 0x50
> +#define B_P2SB_CFG_VBDF_BUS 0xFF00
> +#define B_P2SB_CFG_VBDF_DEV 0x00F8
> +#define B_P2SB_CFG_VBDF_FUNC 0x0007
> +#define R_P2SB_CFG_ESMBDF 0x52
> +#define B_P2SB_CFG_ESMBDF_BUS 0xFF00
> +#define B_P2SB_CFG_ESMBDF_DEV 0x00F8
> +#define B_P2SB_CFG_ESMBDF_FUNC 0x0007
> +#define R_P2SB_CFG_RCFG 0x54
> +#define B_P2SB_CFG_RCFG_RPRID 0x0000FF00
> +#define B_P2SB_CFG_RCFG_RSE BIT0
> +#define R_P2SB_CFG_HPTC 0x60
> +#define B_P2SB_CFG_HPTC_AE BIT7
> +#define B_P2SB_CFG_HPTC_AS 0x0003
> +#define N_HPET_ADDR_ASEL 12
> +#define R_P2SB_CFG_IOAC 0x64
> +#define B_P2SB_CFG_IOAC_AE BIT8
> +#define B_P2SB_CFG_IOAC_ASEL 0x00FF
> +#define N_IO_APIC_ASEL 12
> +#define R_IO_APIC_INDEX_OFFSET 0x00
> +#define R_IO_APIC_DATA_OFFSET 0x10
> +#define R_IO_APIC_EOI_OFFSET 0x40
> +#define R_P2SB_CFG_IBDF 0x6C
> +#define B_P2SB_CFG_IBDF_BUS 0xFF00
> +#define B_P2SB_CFG_IBDF_DEV 0x00F8
> +#define B_P2SB_CFG_IBDF_FUNC 0x0007
> +#define V_P2SB_CFG_IBDF_BUS 0
> +#define V_P2SB_CFG_IBDF_DEV 30
> +#define V_P2SB_CFG_IBDF_FUNC 7
> +#define V_P2SB_CFG_HBDF_BUS 0
> +#define V_P2SB_CFG_HBDF_DEV 30
> +#define V_P2SB_CFG_HBDF_FUNC 6
> +
> +//
> +// Definition for SBI
> +//
> +#define R_P2SB_CFG_SBIADDR 0xD0
> +#define B_P2SB_CFG_SBIADDR_DESTID 0xFF000000
> +#define B_P2SB_CFG_SBIADDR_RS 0x000F0000
> +#define B_P2SB_CFG_SBIADDR_OFFSET 0x0000FFFF
> +#define R_P2SB_CFG_SBIDATA 0xD4
> +#define B_P2SB_CFG_SBIDATA_DATA 0xFFFFFFFF
> +#define R_P2SB_CFG_SBISTAT 0xD8
> +#define B_P2SB_CFG_SBISTAT_OPCODE 0xFF00
> +#define B_P2SB_CFG_SBISTAT_POSTED BIT7
> +#define B_P2SB_CFG_SBISTAT_RESPONSE 0x0006
> +#define N_P2SB_CFG_SBISTAT_RESPONSE 1
> +#define B_P2SB_CFG_SBISTAT_INITRDY BIT0
> +#define R_P2SB_CFG_SBIRID 0xDA
> +#define B_P2SB_CFG_SBIRID_FBE 0xF000
> +#define B_P2SB_CFG_SBIRID_BAR 0x0700
> +#define B_P2SB_CFG_SBIRID_FID 0x00FF
> +#define R_P2SB_CFG_SBIEXTADDR 0xDC
> +#define B_P2SB_CFG_SBIEXTADDR_ADDR 0xFFFFFFFF
> +
> +//
> +// Others
> +//
> +#define R_P2SB_CFG_E0 0xE0
> +#define R_P2SB_CFG_E4 0xE4
> +#define R_P2SB_CFG_E8 0xE8
> +#define R_P2SB_CFG_EA 0xEA
> +#define R_P2SB_CFG_F4 0xF4
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcie.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcie.h
> new file mode 100644
> index 0000000000..af19b93e2d
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcie.h
> @@ -0,0 +1,484 @@
> +/** @file
> + Register names for PCH PCI-E root port devices
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_PCIE_H_
> +#define _PCH_REGS_PCIE_H_
> +
> +//
> +// Number of PCIe ports per PCIe controller
> +//
> +#define PCH_PCIE_CONTROLLER_PORTS 4u
> +
> +//
> +// PCH PCI Express Root Ports (D28:F0..7, D29:F0..7, D27:F0..7)
> +//
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1 28
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2 29
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3 27
> +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5 4
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6 5
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7 6
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8 7
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9 0
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10 1
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11 2
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12 3
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13 4
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14 5
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15 6
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16 7
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17 0
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18 1
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19 2
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20 3
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_21 4
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_22 5
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_23 6
> +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_24 7
> +
> +#define V_PCH_PCIE_CFG_VENDOR_ID
> V_PCH_INTEL_VENDOR_ID
> +
> +
> +#define R_PCH_PCIE_CFG_CLIST 0x40
> +#define R_PCH_PCIE_CFG_XCAP (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_XCAP_OFFSET)
> +#define R_PCH_PCIE_CFG_DCAP (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_DCAP_OFFSET)
> +#define R_PCH_PCIE_CFG_DCTL (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_DCTL_OFFSET)
> +#define R_PCH_PCIE_CFG_DSTS (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_DSTS_OFFSET)
> +#define R_PCH_PCIE_CFG_LCAP (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_LCAP_OFFSET)
> +#define B_PCH_PCIE_CFG_LCAP_PN 0xFF000000
> +#define N_PCH_PCIE_CFG_LCAP_PN 24
> +#define R_PCH_PCIE_CFG_LCTL (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_LCTL_OFFSET)
> +#define R_PCH_PCIE_CFG_LSTS (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_LSTS_OFFSET)
> +#define R_PCH_PCIE_CFG_SLCAP (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_SLCAP_OFFSET)
> +#define R_PCH_PCIE_CFG_SLCTL (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_SLCTL_OFFSET)
> +#define R_PCH_PCIE_CFG_SLSTS (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_SLSTS_OFFSET)
> +#define R_PCH_PCIE_CFG_RCTL (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_RCTL_OFFSET)
> +#define R_PCH_PCIE_CFG_RSTS (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_RSTS_OFFSET)
> +#define R_PCH_PCIE_CFG_DCAP2
> (R_PCH_PCIE_CFG_CLIST + R_PCIE_DCAP2_OFFSET)
> +#define R_PCH_PCIE_CFG_DCTL2 (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_DCTL2_OFFSET)
> +#define R_PCH_PCIE_CFG_LCTL2 (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_LCTL2_OFFSET)
> +#define R_PCH_PCIE_CFG_LSTS2 (R_PCH_PCIE_CFG_CLIST
> + R_PCIE_LSTS2_OFFSET)
> +
> +#define R_PCH_PCIE_CFG_MID 0x80
> +#define S_PCH_PCIE_CFG_MID 2
> +#define R_PCH_PCIE_CFG_MC 0x82
> +#define S_PCH_PCIE_CFG_MC 2
> +#define R_PCH_PCIE_CFG_MA 0x84
> +#define S_PCH_PCIE_CFG_MA 4
> +#define R_PCH_PCIE_CFG_MD 0x88
> +#define S_PCH_PCIE_CFG_MD 2
> +
> +#define R_PCH_PCIE_CFG_SVCAP 0x90
> +#define S_PCH_PCIE_CFG_SVCAP 2
> +#define R_PCH_PCIE_CFG_SVID 0x94
> +#define S_PCH_PCIE_CFG_SVID 4
> +
> +#define R_PCH_PCIE_CFG_PMCAP 0xA0
> +#define R_PCH_PCIE_CFG_PMCS
> (R_PCH_PCIE_CFG_PMCAP + R_PCIE_PMCS_OFFST)
> +
> +#define R_PCH_PCIE_CFG_CCFG 0xD0
> +#define B_PCH_PCIE_CFG_CCFG_UNRS (BIT6 | BIT5 | BIT4)
> +#define N_PCH_PCIE_CFG_CCFG_UNRS 4
> +
> +#define R_PCH_PCIE_CFG_MPC2 0xD4
> +#define S_PCH_PCIE_CFG_MPC2 4
> +#define B_PCH_PCIE_CFG_MPC2_PTNFAE BIT12
> +#define B_PCH_PCIE_CFG_MPC2_LSTP BIT6
> +#define B_PCH_PCIE_CFG_MPC2_IEIME BIT5
> +#define B_PCH_PCIE_CFG_MPC2_ASPMCOEN BIT4
> +#define B_PCH_PCIE_CFG_MPC2_ASPMCO (BIT3 | BIT2)
> +#define V_PCH_PCIE_CFG_MPC2_ASPMCO_DISABLED 0
> +#define V_PCH_PCIE_CFG_MPC2_ASPMCO_L0S (1 << 2)
> +#define V_PCH_PCIE_CFG_MPC2_ASPMCO_L1 (2 << 2)
> +#define V_PCH_PCIE_CFG_MPC2_ASPMCO_L0S_L1 (3 << 2)
> +#define B_PCH_PCIE_CFG_MPC2_EOIFD BIT1
> +
> +#define R_PCH_PCIE_CFG_MPC 0xD8
> +#define S_PCH_PCIE_CFG_MPC 4
> +#define B_PCH_PCIE_CFG_MPC_PMCE BIT31
> +#define B_PCH_PCIE_CFG_MPC_HPCE BIT30
> +#define B_PCH_PCIE_CFG_MPC_MMBNCE BIT27
> +#define B_PCH_PCIE_CFG_MPC_P8XDE BIT26
> +#define B_PCH_PCIE_CFG_MPC_IRRCE BIT25
> +#define B_PCH_PCIE_CFG_MPC_SRL BIT23
> +#define B_PCH_PCIE_CFG_MPC_UCEL (BIT20 | BIT19 | BIT18)
> +#define N_PCH_PCIE_CFG_MPC_UCEL 18
> +#define B_PCH_PCIE_CFG_MPC_CCEL (BIT17 | BIT16 | BIT15)
> +#define N_PCH_PCIE_CFG_MPC_CCEL 15
> +#define B_PCH_PCIE_CFG_MPC_PCIESD (BIT14 | BIT13)
> +#define N_PCH_PCIE_CFG_MPC_PCIESD 13
> +#define V_PCH_PCIE_CFG_MPC_PCIESD_GEN1 1
> +#define V_PCH_PCIE_CFG_MPC_PCIESD_GEN2 2
> +#define B_PCH_PCIE_CFG_MPC_MCTPSE BIT3
> +#define B_PCH_PCIE_CFG_MPC_HPME BIT1
> +#define N_PCH_PCIE_CFG_MPC_HPME 1
> +#define B_PCH_PCIE_CFG_MPC_PMME BIT0
> +
> +#define R_PCH_PCIE_CFG_SMSCS 0xDC
> +#define S_PCH_PCIE_CFG_SMSCS 4
> +#define B_PCH_PCIE_CFG_SMSCS_PMCS BIT31
> +#define N_PCH_PCIE_CFG_SMSCS_LERSMIS 5
> +#define N_PCH_PCIE_CFG_SMSCS_HPLAS 4
> +#define N_PCH_PCIE_CFG_SMSCS_HPPDM 1
> +
> +#define R_PCH_PCIE_CFG_RPDCGEN 0xE1
> +#define S_PCH_PCIE_CFG_RPDCGEN 1
> +#define B_PCH_PCIE_CFG_RPDCGEN_RPSCGEN BIT7
> +#define B_PCH_PCIE_CFG_RPDCGEN_PTOCGE BIT6
> +#define B_PCH_PCIE_CFG_RPDCGEN_LCLKREQEN BIT5
> +#define B_PCH_PCIE_CFG_RPDCGEN_BBCLKREQEN BIT4
> +#define B_PCH_PCIE_CFG_RPDCGEN_SRDBCGEN BIT2
> +#define B_PCH_PCIE_CFG_RPDCGEN_RPDLCGEN BIT1
> +#define B_PCH_PCIE_CFG_RPDCGEN_RPDBCGEN BIT0
> +
> +
> +#define R_PCH_PCIE_CFG_PWRCTL 0xE8
> +#define B_PCH_PCIE_CFG_PWRCTL_LTSSMRTC BIT20
> +#define B_PCH_PCIE_CFG_PWRCTL_WPDMPGEP BIT17
> +#define B_PCH_PCIE_CFG_PWRCTL_DBUPI BIT15
> +#define B_PCH_PCIE_CFG_PWRCTL_TXSWING BIT13
> +#define B_PCH_PCIE_CFG_PWRCTL_RPL1SQPOL BIT1
> +#define B_PCH_PCIE_CFG_PWRCTL_RPDTSQPOL BIT0
> +
> +#define R_PCH_PCIE_CFG_DC 0xEC
> +#define B_PCH_PCIE_CFG_DC_PCIBEM BIT2
> +
> +#define R_PCH_PCIE_CFG_PHYCTL2 0xF5
> +#define B_PCH_PCIE_CFG_PHYCTL2_TDFT (BIT7 | BIT6)
> +#define B_PCH_PCIE_CFG_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4)
> +#define N_PCH_PCIE_CFG_PHYCTL2_TXCFGCHGWAIT 4
> +#define B_PCH_PCIE_CFG_PHYCTL2_PXPG3PLLOFFEN BIT1
> +#define B_PCH_PCIE_CFG_PHYCTL2_PXPG2PLLOFFEN BIT0
> +
> +#define R_PCH_PCIE_CFG_IOSFSBCS 0xF7
> +#define B_PCH_PCIE_CFG_IOSFSBCS_SCPTCGE BIT6
> +#define B_PCH_PCIE_CFG_IOSFSBCS_SIID (BIT3 | BIT2)
> +
> +#define R_PCH_PCIE_CFG_STRPFUSECFG 0xFC
> +#define B_PCH_PCIE_CFG_STRPFUSECFG_PXIP (BIT27 | BIT26 |
> BIT25 | BIT24)
> +#define N_PCH_PCIE_CFG_STRPFUSECFG_PXIP 24
> +#define B_PCH_PCIE_CFG_STRPFUSECFG_RPC (BIT15 | BIT14)
> +#define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_1_1_1_1 0
> +#define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_2_1_1 1
> +#define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_2_2 2
> +#define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_4 3
> +#define N_PCH_PCIE_CFG_STRPFUSECFG_RPC 14
> +#define B_PCH_PCIE_CFG_STRPFUSECFG_MODPHYIOPMDIS BIT9
> +#define B_PCH_PCIE_CFG_STRPFUSECFG_PLLSHTDWNDIS BIT8
> +#define B_PCH_PCIE_CFG_STRPFUSECFG_STPGATEDIS BIT7
> +#define B_PCH_PCIE_CFG_STRPFUSECFG_ASPMDIS BIT6
> +#define B_PCH_PCIE_CFG_STRPFUSECFG_LDCGDIS BIT5
> +#define B_PCH_PCIE_CFG_STRPFUSECFG_LTCGDIS BIT4
> +#define B_PCH_PCIE_CFG_STRPFUSECFG_CDCGDIS BIT3
> +#define B_PCH_PCIE_CFG_STRPFUSECFG_DESKTOPMOB BIT2
> +
> +//
> +//PCI Express Extended Capability Registers
> +//
> +
> +#define R_PCH_PCIE_CFG_EXCAP_OFFSET 0x100
> +
> +#define R_PCH_PCIE_CFG_EX_AECH 0x100 ///< Advanced
> Error Reporting Capability Header
> +#define V_PCH_PCIE_CFG_EX_AEC_CV 0x1
> +#define R_PCH_PCIE_CFG_EX_UEM
> (R_PCH_PCIE_CFG_EX_AECH + R_PCIE_EX_UEM_OFFSET) // Uncorrectable
> Error Mask
> +
> +#define R_PCH_PCIE_CFG_EX_CES 0x110 ///< Correctable
> Error Status
> +#define B_PCH_PCIE_CFG_EX_CES_BD BIT7 ///< Bad DLLP
> Status
> +#define B_PCH_PCIE_CFG_EX_CES_BT BIT6 ///< Bad TLP
> Status
> +#define B_PCH_PCIE_CFG_EX_CES_RE BIT0 ///< Receiver
> Error Status
> +
> +
> +//CES.RE, CES.BT, CES.BD
> +
> +#define R_PCH_PCIE_CFG_EX_ACSECH 0x140 ///< ACS
> Extended Capability Header
> +#define V_PCH_PCIE_CFG_EX_ACS_CV 0x1
> +#define R_PCH_PCIE_CFG_EX_ACSCAPR
> (R_PCH_PCIE_CFG_EX_ACSECH + R_PCIE_EX_ACSCAPR_OFFSET)
> +
> +#define R_PCH_PCIE_CFG_EX_L1SECH 0x200 ///< L1
> Sub-States Extended Capability Header
> +#define V_PCH_PCIE_CFG_EX_L1S_CV 0x1
> +#define R_PCH_PCIE_CFG_EX_L1SCAP
> (R_PCH_PCIE_CFG_EX_L1SECH + R_PCIE_EX_L1SCAP_OFFSET)
> +#define R_PCH_PCIE_CFG_EX_L1SCTL1
> (R_PCH_PCIE_CFG_EX_L1SECH + R_PCIE_EX_L1SCTL1_OFFSET)
> +#define R_PCH_PCIE_CFG_EX_L1SCTL2
> (R_PCH_PCIE_CFG_EX_L1SECH + R_PCIE_EX_L1SCTL2_OFFSET)
> +
> +#define R_PCH_PCIE_CFG_EX_SPEECH 0x220 ///< Secondary
> PCI Express Extended Capability Header
> +#define V_PCH_PCIE_CFG_EX_SPEECH_CV 0x1
> +#define R_PCH_PCIE_CFG_EX_LCTL3
> (R_PCH_PCIE_CFG_EX_SPEECH + R_PCIE_EX_LCTL3_OFFSET)
> +#define R_PCH_PCIE_CFG_EX_LES
> (R_PCH_PCIE_CFG_EX_SPEECH + R_PCIE_EX_LES_OFFSET)
> +#define R_PCH_PCIE_CFG_EX_LECTL
> (R_PCH_PCIE_CFG_EX_SPEECH + R_PCIE_EX_L01EC_OFFSET)
> +#define B_PCH_PCIE_CFG_EX_LECTL_UPTPH (BIT14 | BIT13 |
> BIT12)
> +#define N_PCH_PCIE_CFG_EX_LECTL_UPTPH 12
> +#define B_PCH_PCIE_CFG_EX_LECTL_UPTP 0x0F00
> +#define N_PCH_PCIE_CFG_EX_LECTL_UPTP 8
> +#define B_PCH_PCIE_CFG_EX_LECTL_DPTPH (BIT6 | BIT5 | BIT4)
> +#define N_PCH_PCIE_CFG_EX_LECTL_DPTPH 4
> +#define B_PCH_PCIE_CFG_EX_LECTL_DPTP 0x000F
> +#define N_PCH_PCIE_CFG_EX_LECTL_DPTP 0
> +
> +#define R_PCH_PCIE_CFG_EX_L01EC
> (R_PCH_PCIE_CFG_EX_SPEECH + R_PCIE_EX_L01EC_OFFSET)
> +#define R_PCH_PCIE_CFG_EX_L23EC
> (R_PCH_PCIE_CFG_EX_SPEECH + R_PCIE_EX_L23EC_OFFSET)
> +
> +#define R_PCH_PCIE_CFG_PCIERTP1 0x300
> +#define R_PCH_PCIE_CFG_PCIERTP2 0x304
> +#define R_PCH_PCIE_CFG_PCIENFTS 0x314
> +#define R_PCH_PCIE_CFG_PCIEL0SC 0x318
> +
> +#define R_PCH_PCIE_CFG_PCIECFG2 0x320
> +#define B_PCH_PCIE_CFG_PCIECFG2_LBWSSTE BIT30
> +#define B_PCH_PCIE_CFG_PCIECFG2_RLLG3R BIT27
> +#define B_PCH_PCIE_CFG_PCIECFG2_CROAOV BIT24
> +#define B_PCH_PCIE_CFG_PCIECFG2_CROAOE BIT23
> +#define B_PCH_PCIE_CFG_PCIECFG2_CRSREN BIT22
> +#define B_PCH_PCIE_CFG_PCIECFG2_PMET (BIT21 | BIT20)
> +#define V_PCH_PCIE_CFG_PCIECFG2_PMET 1
> +#define N_PCH_PCIE_CFG_PCIECFG2_PMET 20
> +
> +#define R_PCH_PCIE_CFG_PCIEDBG 0x324
> +#define B_PCH_PCIE_CFG_PCIEDBG_LBWSSTE BIT30
> +#define B_PCH_PCIE_CFG_PCIEDBG_USSP (BIT27 | BIT26)
> +#define B_PCH_PCIE_CFG_PCIEDBG_LGCLKSQEXITDBTIMERS (BIT25 |
> BIT24)
> +#define B_PCH_PCIE_CFG_PCIEDBG_CTONFAE BIT14
> +#define B_PCH_PCIE_CFG_PCIEDBG_SQOL0 BIT7
> +#define B_PCH_PCIE_CFG_PCIEDBG_SPCE BIT5
> +#define B_PCH_PCIE_CFG_PCIEDBG_LR BIT4
> +
> +#define R_PCH_PCIE_CFG_PCIESTS1 0x328
> +#define B_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE 0xFF000000
> +#define N_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE 24
> +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_DETRDY 0x01
> +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_DETRDYECINP1CG 0x0E
> +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_L0 0x33
> +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_DISWAIT 0x5E
> +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_DISWAITPG 0x60
> +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_RECOVERYSPEEDREADY
> 0x6C
> +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_RECOVERYLNK2DETECT
> 0x6F
> +
> +
> +#define B_PCH_PCIE_CFG_PCIESTS1_LNKSTAT (BIT22 | BIT21 |
> BIT20 | BIT19)
> +#define N_PCH_PCIE_CFG_PCIESTS1_LNKSTAT 19
> +#define V_PCH_PCIE_CFG_PCIESTS1_LNKSTAT_L0 0x7
> +
> +#define R_PCH_PCIE_CFG_PCIESTS2 0x32C
> +#define B_PCH_PCIE_CFG_PCIESTS2_P4PNCCWSSCMES BIT31
> +#define B_PCH_PCIE_CFG_PCIESTS2_P3PNCCWSSCMES BIT30
> +#define B_PCH_PCIE_CFG_PCIESTS2_P2PNCCWSSCMES BIT29
> +#define B_PCH_PCIE_CFG_PCIESTS2_P1PNCCWSSCMES BIT28
> +#define B_PCH_PCIE_CFG_PCIESTS2_CLRE 0x0000F000
> +#define N_PCH_PCIE_CFG_PCIESTS2_CLRE 12
> +
> +#define R_PCH_PCIE_CFG_PCIEALC 0x338
> +#define B_PCH_PCIE_CFG_PCIEALC_ITLRCLD BIT29
> +#define B_PCH_PCIE_CFG_PCIEALC_ILLRCLD BIT28
> +#define B_PCH_PCIE_CFG_PCIEALC_BLKDQDA BIT26
> +
> +
> +#define R_PCH_PCIE_CFG_LTROVR 0x400
> +#define B_PCH_PCIE_CFG_LTROVR_LTRNSROVR BIT31 ///< LTR
> Non-Snoop Requirement Bit Override
> +#define B_PCH_PCIE_CFG_LTROVR_LTRSROVR BIT15 ///< LTR
> Snoop Requirement Bit Override
> +
> +#define R_PCH_PCIE_CFG_LTROVR2 0x404
> +#define B_PCH_PCIE_CFG_LTROVR2_FORCE_OVERRIDE BIT3 ///< LTR
> Force Override Enable
> +#define B_PCH_PCIE_CFG_LTROVR2_LOCK BIT2 ///< LTR
> Override Lock
> +#define B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN BIT1 ///< LTR
> Non-Snoop Override Enable
> +#define B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN BIT0 ///< LTR
> Snoop Override Enable
> +
> +#define R_PCH_PCIE_CFG_PHYCTL4 0x408
> +#define B_PCH_PCIE_CFG_PHYCTL4_SQDIS BIT27
> +
> +#define R_PCH_PCIE_CFG_PCIEPMECTL 0x420
> +#define B_PCH_PCIE_CFG_PCIEPMECTL_DLSULPPGE BIT30
> +#define B_PCH_PCIE_CFG_PCIEPMECTL_L1LE BIT17
> +#define B_PCH_PCIE_CFG_PCIEPMECTL_L1FSOE BIT0
> +
> +#define R_PCH_PCIE_CFG_PCIEPMECTL2 0x424
> +#define B_PCH_PCIE_CFG_PCIEPMECTL2_PHYCLPGE BIT11
> +#define B_PCH_PCIE_CFG_PCIEPMECTL2_FDCPGE BIT8
> +#define B_PCH_PCIE_CFG_PCIEPMECTL2_DETSCPGE BIT7
> +#define B_PCH_PCIE_CFG_PCIEPMECTL2_L23RDYSCPGE BIT6
> +#define B_PCH_PCIE_CFG_PCIEPMECTL2_DISSCPGE BIT5
> +#define B_PCH_PCIE_CFG_PCIEPMECTL2_L1SCPGE BIT4
> +
> +#define R_PCH_PCIE_CFG_PCE 0x428
> +#define B_PCH_PCIE_CFG_PCE_HAE BIT5
> +#define B_PCH_PCIE_CFG_PCE_PMCRE BIT0
> +
> +#define R_PCH_PCIE_CFG_EQCFG1 0x450
> +#define S_PCH_PCIE_CFG_EQCFG1 4
> +#define B_PCH_PCIE_CFG_EQCFG1_REC 0xFF000000
> +#define N_PCH_PCIE_CFG_EQCFG1_REC 24
> +#define B_PCH_PCIE_CFG_EQCFG1_REIFECE BIT23
> +#define N_PCH_PCIE_CFG_EQCFG1_LERSMIE 21
> +#define B_PCH_PCIE_CFG_EQCFG1_LEP23B BIT18
> +#define B_PCH_PCIE_CFG_EQCFG1_LEP3B BIT17
> +#define B_PCH_PCIE_CFG_EQCFG1_RTLEPCEB BIT16
> +#define B_PCH_PCIE_CFG_EQCFG1_RTPCOE BIT15
> +#define B_PCH_PCIE_CFG_EQCFG1_HPCMQE BIT13
> +#define B_PCH_PCIE_CFG_EQCFG1_HAED BIT12
> +#define B_PCH_PCIE_CFG_EQCFG1_EQTS2IRRC BIT7
> +#define B_PCH_PCIE_CFG_EQCFG1_TUPP BIT1
> +
> +#define R_PCH_PCIE_CFG_RTPCL1 0x454
> +#define B_PCH_PCIE_CFG_RTPCL1_PCM BIT31
> +#define B_PCH_PCIE_CFG_RTPCL1_RTPRECL2PL4 0x3F000000
> +#define B_PCH_PCIE_CFG_RTPCL1_RTPOSTCL1PL3 0xFC0000
> +#define B_PCH_PCIE_CFG_RTPCL1_RTPRECL1PL2 0x3F000
> +#define B_PCH_PCIE_CFG_RTPCL1_RTPOSTCL0PL1 0xFC0
> +#define B_PCH_PCIE_CFG_RTPCL1_RTPRECL0PL0 0x3F
> +
> +#define R_PCH_PCIE_CFG_RTPCL2 0x458
> +#define B_PCH_PCIE_CFG_RTPCL2_RTPOSTCL3PL 0x3F000
> +#define B_PCH_PCIE_CFG_RTPCL2_RTPRECL3PL6 0xFC0
> +#define B_PCH_PCIE_CFG_RTPCL2_RTPOSTCL2PL5 0x3F
> +
> +#define R_PCH_PCIE_CFG_RTPCL3 0x45C
> +#define B_PCH_PCIE_CFG_RTPCL3_RTPRECL7 0x3F000000
> +#define B_PCH_PCIE_CFG_RTPCL3_RTPOSTCL6 0xFC0000
> +#define B_PCH_PCIE_CFG_RTPCL3_RTPRECL6 0x3F000
> +#define B_PCH_PCIE_CFG_RTPCL3_RTPOSTCL5 0xFC0
> +#define B_PCH_PCIE_CFG_RTPCL3_RTPRECL5PL10 0x3F
> +
> +#define R_PCH_PCIE_CFG_RTPCL4 0x460
> +#define B_PCH_PCIE_CFG_RTPCL4_RTPOSTCL9 0x3F000000
> +#define B_PCH_PCIE_CFG_RTPCL4_RTPRECL9 0xFC0000
> +#define B_PCH_PCIE_CFG_RTPCL4_RTPOSTCL8 0x3F000
> +#define B_PCH_PCIE_CFG_RTPCL4_RTPRECL8 0xFC0
> +#define B_PCH_PCIE_CFG_RTPCL4_RTPOSTCL7 0x3F
> +
> +#define R_PCH_PCIE_CFG_FOMS 0x464
> +#define B_PCH_PCIE_CFG_FOMS_I (BIT30 | BIT29)
> +#define N_PCH_PCIE_CFG_FOMS_I 29
> +#define B_PCH_PCIE_CFG_FOMS_LN 0x1F000000
> +#define N_PCH_PCIE_CFG_FOMS_LN 24
> +#define B_PCH_PCIE_CFG_FOMS_FOMSV 0x00FFFFFF
> +#define B_PCH_PCIE_CFG_FOMS_FOMSV0 0x000000FF
> +#define N_PCH_PCIE_CFG_FOMS_FOMSV0 0
> +#define B_PCH_PCIE_CFG_FOMS_FOMSV1 0x0000FF00
> +#define N_PCH_PCIE_CFG_FOMS_FOMSV1 8
> +#define B_PCH_PCIE_CFG_FOMS_FOMSV2 0x00FF0000
> +#define N_PCH_PCIE_CFG_FOMS_FOMSV2 16
> +
> +#define R_PCH_PCIE_CFG_HAEQ 0x468
> +#define B_PCH_PCIE_CFG_HAEQ_HAPCCPI (BIT31 | BIT30 |
> BIT29 | BIT28)
> +#define N_PCH_PCIE_CFG_HAEQ_HAPCCPI 28
> +#define B_PCH_PCIE_CFG_HAEQ_MACFOMC BIT19
> +
> +#define R_PCH_PCIE_CFG_LTCO1 0x470
> +#define B_PCH_PCIE_CFG_LTCO1_L1TCOE BIT25
> +#define B_PCH_PCIE_CFG_LTCO1_L0TCOE BIT24
> +#define B_PCH_PCIE_CFG_LTCO1_L1TPOSTCO 0xFC0000
> +#define N_PCH_PCIE_CFG_LTCO1_L1TPOSTCO 18
> +#define B_PCH_PCIE_CFG_LTCO1_L1TPRECO 0x3F000
> +#define N_PCH_PCIE_CFG_LTCO1_L1TPRECO 12
> +#define B_PCH_PCIE_CFG_LTCO1_L0TPOSTCO 0xFC0
> +#define N_PCH_PCIE_CFG_LTCO1_L0TPOSTCO 6
> +#define B_PCH_PCIE_CFG_LTCO1_L0TPRECO 0x3F
> +#define N_PCH_PCIE_CFG_LTCO1_L0TPRECO 0
> +
> +#define R_PCH_PCIE_CFG_LTCO2 0x474
> +#define B_PCH_PCIE_CFG_LTCO2_L3TCOE BIT25
> +#define B_PCH_PCIE_CFG_LTCO2_L2TCOE BIT24
> +#define B_PCH_PCIE_CFG_LTCO2_L3TPOSTCO 0xFC0000
> +#define B_PCH_PCIE_CFG_LTCO2_L3TPRECO 0x3F000
> +#define B_PCH_PCIE_CFG_LTCO2_L2TPOSTCO 0xFC0
> +#define B_PCH_PCIE_CFG_LTCO2_L2TPRECO 0x3F
> +
> +#define R_PCH_PCIE_CFG_G3L0SCTL 0x478
> +#define B_PCH_PCIE_CFG_G3L0SCTL_G3UCNFTS 0x0000FF00
> +#define B_PCH_PCIE_CFG_G3L0SCTL_G3CCNFTS 0x000000FF
> +
> +#define R_PCH_PCIE_CFG_EQCFG2 0x47C
> +#define B_PCH_PCIE_CFG_EQCFG2_NTIC 0xFF000000
> +#define B_PCH_PCIE_CFG_EQCFG2_EMD BIT23
> +#define B_PCH_PCIE_CFG_EQCFG2_NTSS (BIT22 | BIT21 |
> BIT20)
> +#define B_PCH_PCIE_CFG_EQCFG2_PCET (BIT19 | BIT18 | BIT17
> | BIT16)
> +#define N_PCH_PCIE_CFG_EQCFG2_PCET 16
> +#define B_PCH_PCIE_CFG_EQCFG2_HAPCSB (BIT15 | BIT14 |
> BIT13 | BIT12)
> +#define N_PCH_PCIE_CFG_EQCFG2_HAPCSB 12
> +#define B_PCH_PCIE_CFG_EQCFG2_NTEME BIT11
> +#define B_PCH_PCIE_CFG_EQCFG2_MPEME BIT10
> +#define B_PCH_PCIE_CFG_EQCFG2_REWMETM (BIT9 | BIT8)
> +#define B_PCH_PCIE_CFG_EQCFG2_REWMET 0xFF
> +
> +#define R_PCH_PCIE_CFG_MM 0x480
> +#define B_PCH_PCIE_CFG_MM_MSST 0xFFFFFF00
> +#define N_PCH_PCIE_CFG_MM_MSST 8
> +#define B_PCH_PCIE_CFG_MM_MSS 0xFF
> +
> +//
> +// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF)
> +//
> +#define R_SPX_PCR_PCD 0 ///< Port
> configuration and disable
> +#define B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///< Port
> 1 Function Number
> +#define B_SPX_PCR_PCD_RP1CH BIT3 ///< Port 1
> config hide
> +#define B_SPX_PCR_PCD_RP2FN (BIT6 | BIT5 | BIT4) ///< Port
> 2 Function Number
> +#define B_SPX_PCR_PCD_RP2CH BIT7 ///< Port 2
> config hide
> +#define B_SPX_PCR_PCD_RP3FN (BIT10 | BIT9 | BIT8) ///< Port
> 3 Function Number
> +#define B_SPX_PCR_PCD_RP3CH BIT11 ///< Port 3
> config hide
> +#define B_SPX_PCR_PCD_RP4FN (BIT14 | BIT13 | BIT12) ///<
> Port 4 Function Number
> +#define B_SPX_PCR_PCD_RP4CH BIT15 ///< Port 4
> config hide
> +#define S_SPX_PCR_PCD_RP_FIELD 4 ///< 4 bits
> for each RP FN
> +#define B_SPX_PCR_PCD_P1D BIT16 ///< Port 1
> disable
> +#define B_SPX_PCR_PCD_P2D BIT17 ///< Port 2
> disable
> +#define B_SPX_PCR_PCD_P3D BIT18 ///< Port 3
> disable
> +#define B_SPX_PCR_PCD_P4D BIT19 ///< Port 4
> disable
> +#define B_SPX_PCR_PCD_SRL BIT31 ///< Secured
> Register Lock
> +
> +#define R_SPX_PCR_PCIEHBP 0x0004 ///< PCI
> Express high-speed bypass
> +#define B_SPX_PCR_PCIEHBP_PCIEHBPME BIT0 ///<
> PCIe HBP mode enable
> +#define B_SPX_PCR_PCIEHBP_PCIEGMO (BIT2 | BIT1) ///<
> PCIe gen mode override
> +#define B_SPX_PCR_PCIEHBP_PCIETIL0O BIT3 ///< PCIe
> transmitter-in-L0 override
> +#define B_SPX_PCR_PCIEHBP_PCIERIL0O BIT4 ///< PCIe
> receiver-in-L0 override
> +#define B_SPX_PCR_PCIEHBP_PCIELRO BIT5 ///< PCIe
> link recovery override
> +#define B_SPX_PCR_PCIEHBP_PCIELDO BIT6 ///< PCIe
> link down override
> +#define B_SPX_PCR_PCIEHBP_PCIESSM BIT7 ///< PCIe
> SKP suppression mode
> +#define B_SPX_PCR_PCIEHBP_PCIESST BIT8 ///< PCIe
> suppress SKP transmission
> +#define B_SPX_PCR_PCIEHBP_PCIEHBPPS (BIT13 | BIT12) ///<
> PCIe HBP port select
> +#define B_SPX_PCR_PCIEHBP_CRCSEL (BIT15 | BIT14) ///<
> CRC select
> +#define B_SPX_PCR_PCIEHBP_PCIEHBPCRC 0xFFFF0000 ///<
> PCIe HBP CRC
> +
> +//
> +// ICC PCR (PID: ICC)
> +//
> +#define R_ICC_PCR_TMCSRCCLK 0x1000 ///<
> Timing Control SRC Clock Register
> +#define R_ICC_PCR_TMCSRCCLK2 0x1004 ///<
> Timing Control SRC Clock Register 2
> +#define R_ICC_PCR_MSKCKRQ 0x100C ///< Mask
> Control CLKREQ
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcr.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcr.h
> new file mode 100644
> index 0000000000..ed1668300a
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcr.h
> @@ -0,0 +1,73 @@
> +/** @file
> + Register names for PCH private chipset register
> +
> + Conventions:
> +
> + - Prefixes:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register sizes
> + Definitions beginning with "N_" are the bit position
> + - In general, PCH registers are denoted by "_PCH_" in register names
> + - Registers / bits that are different between PCH generations are denoted by
> + "_PCH_[generation_name]_" in register/bit names.
> + - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit
> names.
> + Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit
> names.
> + e.g., "_PCH_H_", "_PCH_LP_"
> + Registers / bits names without _H_ or _LP_ apply for both H and LP.
> + - Registers / bits that are different between SKUs are denoted by
> "_[SKU_name]"
> + at the end of the register/bit names
> + - Registers / bits of new devices introduced in a PCH generation will be just
> named
> + as "_PCH_" without [generation_name] inserted.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_PCR_H_
> +#define _PCH_REGS_PCR_H_
> +
> +/**
> + Definition for SBI PID
> + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI
> programming as well.
> +**/
> +#define PID_OPIPHY 0xAC
> +#define PID_MODPHY0 0xAB
> +#define PID_MODPHY1 0xAA
> +#define PID_USB2 0xCA
> +#define PID_DMI 0x88
> +#define PID_PSTH 0x89
> +#define PID_DSP 0xD7
> +#define PID_ESPISPI 0x72
> +#define PID_FIA 0xCF
> +#define PID_SPF 0x85
> +#define PID_SPE 0x84
> +#define PID_SPD 0x83
> +#define PID_SPC 0x82
> +#define PID_SPB 0x81
> +#define PID_SPA 0x80
> +#define PID_SERIALIO 0xCB
> +#define PID_LPC 0xC7
> +#define PID_SMB 0xC6
> +#define PID_ITSS 0xC4
> +#define PID_RTC_HOST 0xC3
> +#define PID_PSF6 0x7F
> +#define PID_PSF7 0x7E
> +#define PID_PSF8 0x7D
> +#define PID_PSF4 0xBD
> +#define PID_PSF3 0xBC
> +#define PID_PSF2 0xBB
> +#define PID_PSF1 0xBA
> +#define PID_GPIOCOM0 0x6E
> +#define PID_GPIOCOM1 0x6D
> +#define PID_GPIOCOM2 0x6C
> +#define PID_GPIOCOM3 0x6B
> +#define PID_GPIOCOM4 0x6A
> +#define PID_CSME12 0x9C
> +
> +#define PID_CSME0 0x90
> +#define PID_CSME_PSF 0x8F
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmc.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmc.h
> new file mode 100644
> index 0000000000..dcecc633a1
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmc.h
> @@ -0,0 +1,670 @@
> +/** @file
> + Register names for PCH PMC device
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_PMC_H_
> +#define _PCH_REGS_PMC_H_
> +
> +//
> +// PMC Registers (D31:F2)
> +//
> +#define PCI_DEVICE_NUMBER_PCH_PMC 31
> +#define PCI_FUNCTION_NUMBER_PCH_PMC 2
> +
> +#define R_PMC_CFG_BASE 0x10
> +#define B_PMC_CFG_PWRM_BASE_MASK 0xFFFF0000
> ///< PWRM must be 64KB alignment to align the source decode.
> +
> +//
> +// ACPI and legacy I/O register offsets from ACPIBASE
> +//
> +#define R_ACPI_IO_PM1_STS 0x00
> +#define S_ACPI_IO_PM1_STS 2
> +#define B_ACPI_IO_PM1_STS_WAK BIT15
> +#define B_ACPI_IO_PM1_STS_PCIEXP_WAKE_STS BIT14
> +#define B_ACPI_IO_PM1_STS_PRBTNOR BIT11
> +#define B_ACPI_IO_PM1_STS_RTC BIT10
> +#define B_ACPI_IO_PM1_STS_PWRBTN BIT8
> +#define B_ACPI_IO_PM1_STS_GBL BIT5
> +#define B_ACPI_IO_PM1_STS_BM BIT4
> +#define B_ACPI_IO_PM1_STS_TMROF BIT0
> +#define N_ACPI_IO_PM1_STS_WAK 15
> +#define N_ACPI_IO_PM1_STS_PCIEXP_WAKE_STS 14
> +#define N_ACPI_IO_PM1_STS_PRBTNOR 11
> +#define N_ACPI_IO_PM1_STS_RTC 10
> +#define N_ACPI_IO_PM1_STS_PWRBTN 8
> +#define N_ACPI_IO_PM1_STS_GBL 5
> +#define N_ACPI_IO_PM1_STS_BM 4
> +#define N_ACPI_IO_PM1_STS_TMROF 0
> +
> +#define R_ACPI_IO_PM1_EN 0x02
> +#define S_ACPI_IO_PM1_EN 2
> +#define B_ACPI_IO_PM1_EN_RTC BIT10
> +#define B_ACPI_IO_PM1_EN_PWRBTN BIT8
> +#define B_ACPI_IO_PM1_EN_GBL BIT5
> +#define B_ACPI_IO_PM1_EN_TMROF BIT0
> +#define N_ACPI_IO_PM1_EN_RTC 10
> +#define N_ACPI_IO_PM1_EN_PWRBTN 8
> +#define N_ACPI_IO_PM1_EN_GBL 5
> +#define N_ACPI_IO_PM1_EN_TMROF 0
> +
> +#define R_ACPI_IO_PM1_CNT 0x04
> +#define S_ACPI_IO_PM1_CNT 4
> +#define B_ACPI_IO_PM1_CNT_SLP_EN BIT13
> +#define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10)
> +#define V_ACPI_IO_PM1_CNT_S0 0
> +#define V_ACPI_IO_PM1_CNT_S1 BIT10
> +#define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10)
> +#define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11)
> +#define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
> +#define B_ACPI_IO_PM1_CNT_GBL_RLS BIT2
> +#define B_ACPI_IO_PM1_CNT_BM_RLD BIT1
> +#define B_ACPI_IO_PM1_CNT_SCI_EN BIT0
> +
> +#define R_ACPI_IO_PM1_TMR 0x08
> +#define V_ACPI_IO_PM1_TMR_FREQUENCY 3579545
> +#define B_ACPI_IO_PM1_TMR_VAL 0xFFFFFF
> +#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///<
> The timer is 24 bit overflow
> +
> +#define R_ACPI_IO_SMI_EN 0x30
> +#define S_ACPI_IO_SMI_EN 4
> +#define B_ACPI_IO_SMI_EN_LEGACY_USB3 BIT31
> +#define B_ACPI_IO_SMI_EN_GPIO_UNLOCK_SMI BIT27
> +#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17
> +#define B_ACPI_IO_SMI_EN_PERIODIC BIT14
> +#define B_ACPI_IO_SMI_EN_TCO BIT13
> +#define B_ACPI_IO_SMI_EN_MCSMI BIT11
> +#define B_ACPI_IO_SMI_EN_BIOS_RLS BIT7
> +#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6
> +#define B_ACPI_IO_SMI_EN_APMC BIT5
> +#define B_ACPI_IO_SMI_EN_ON_SLP_EN BIT4
> +#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3
> +#define B_ACPI_IO_SMI_EN_BIOS BIT2
> +#define B_ACPI_IO_SMI_EN_EOS BIT1
> +#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0
> +#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31
> +#define N_ACPI_IO_SMI_EN_ESPI 28
> +#define N_ACPI_IO_SMI_EN_GPIO_UNLOCK 27
> +#define N_ACPI_IO_SMI_EN_INTEL_USB2 18
> +#define N_ACPI_IO_SMI_EN_LEGACY_USB2 17
> +#define N_ACPI_IO_SMI_EN_PERIODIC 14
> +#define N_ACPI_IO_SMI_EN_TCO 13
> +#define N_ACPI_IO_SMI_EN_MCSMI 11
> +#define N_ACPI_IO_SMI_EN_BIOS_RLS 7
> +#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6
> +#define N_ACPI_IO_SMI_EN_APMC 5
> +#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4
> +#define N_ACPI_IO_SMI_EN_LEGACY_USB 3
> +#define N_ACPI_IO_SMI_EN_BIOS 2
> +#define N_ACPI_IO_SMI_EN_EOS 1
> +#define N_ACPI_IO_SMI_EN_GBL_SMI 0
> +
> +#define R_ACPI_IO_SMI_STS 0x34
> +#define S_ACPI_IO_SMI_STS 4
> +#define B_ACPI_IO_SMI_STS_LEGACY_USB3 BIT31
> +#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27
> +#define B_ACPI_IO_SMI_STS_SPI BIT26
> +#define B_ACPI_IO_SMI_STS_MONITOR BIT21
> +#define B_ACPI_IO_SMI_STS_PCI_EXP BIT20
> +#define B_ACPI_IO_SMI_STS_PATCH BIT19
> +#define B_ACPI_IO_SMI_STS_INTEL_USB2 BIT18
> +#define B_ACPI_IO_SMI_STS_LEGACY_USB2 BIT17
> +#define B_ACPI_IO_SMI_STS_SMBUS BIT16
> +#define B_ACPI_IO_SMI_STS_SERIRQ BIT15
> +#define B_ACPI_IO_SMI_STS_PERIODIC BIT14
> +#define B_ACPI_IO_SMI_STS_TCO BIT13
> +#define B_ACPI_IO_SMI_STS_DEVMON BIT12
> +#define B_ACPI_IO_SMI_STS_MCSMI BIT11
> +#define B_ACPI_IO_SMI_STS_GPIO_SMI BIT10
> +#define B_ACPI_IO_SMI_STS_GPE0 BIT9
> +#define B_ACPI_IO_SMI_STS_PM1_STS_REG BIT8
> +#define B_ACPI_IO_SMI_STS_SWSMI_TMR BIT6
> +#define B_ACPI_IO_SMI_STS_APM BIT5
> +#define B_ACPI_IO_SMI_STS_ON_SLP_EN BIT4
> +#define B_ACPI_IO_SMI_STS_LEGACY_USB BIT3
> +#define B_ACPI_IO_SMI_STS_BIOS BIT2
> +#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31
> +#define N_ACPI_IO_SMI_STS_ESPI 28
> +#define N_ACPI_IO_SMI_STS_GPIO_UNLOCK 27
> +#define N_ACPI_IO_SMI_STS_SPI 26
> +#define N_ACPI_IO_SMI_STS_MONITOR 21
> +#define N_ACPI_IO_SMI_STS_PCI_EXP 20
> +#define N_ACPI_IO_SMI_STS_PATCH 19
> +#define N_ACPI_IO_SMI_STS_INTEL_USB2 18
> +#define N_ACPI_IO_SMI_STS_LEGACY_USB2 17
> +#define N_ACPI_IO_SMI_STS_SMBUS 16
> +#define N_ACPI_IO_SMI_STS_SERIRQ 15
> +#define N_ACPI_IO_SMI_STS_PERIODIC 14
> +#define N_ACPI_IO_SMI_STS_TCO 13
> +#define N_ACPI_IO_SMI_STS_DEVMON 12
> +#define N_ACPI_IO_SMI_STS_MCSMI 11
> +#define N_ACPI_IO_SMI_STS_GPIO_SMI 10
> +#define N_ACPI_IO_SMI_STS_GPE0 9
> +#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8
> +#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6
> +#define N_ACPI_IO_SMI_STS_APM 5
> +#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4
> +#define N_ACPI_IO_SMI_STS_LEGACY_USB 3
> +#define N_ACPI_IO_SMI_STS_BIOS 2
> +
> +#define R_ACPI_IO_GPE_CNTL 0x40
> +#define B_ACPI_IO_GPE_CNTL_SWGPE_CTRL BIT17
> +
> +#define R_ACPI_IO_DEVACT_STS 0x44
> +#define S_ACPI_IO_DEVACT_STS 2
> +#define B_ACPI_IO_DEVACT_STS_MASK 0x13E1
> +#define B_ACPI_IO_DEVACT_STS_KBC BIT12
> +#define B_ACPI_IO_DEVACT_STS_PIRQDH BIT9
> +#define B_ACPI_IO_DEVACT_STS_PIRQCG BIT8
> +#define B_ACPI_IO_DEVACT_STS_PIRQBF BIT7
> +#define B_ACPI_IO_DEVACT_STS_PIRQAE BIT6
> +#define B_ACPI_IO_DEVACT_STS_D0_TRP BIT0
> +#define N_ACPI_IO_DEVACT_STS_KBC 12
> +#define N_ACPI_IO_DEVACT_STS_PIRQDH 9
> +#define N_ACPI_IO_DEVACT_STS_PIRQCG 8
> +#define N_ACPI_IO_DEVACT_STS_PIRQBF 7
> +#define N_ACPI_IO_DEVACT_STS_PIRQAE 6
> +
> +#define R_ACPI_IO_PM2_CNT 0x50
> +#define B_ACPI_IO_PM2_CNT_ARB_DIS BIT0
> +
> +#define R_ACPI_IO_OC_WDT_CTL 0x54
> +#define B_ACPI_IO_OC_WDT_CTL_RLD BIT31
> +#define B_ACPI_IO_OC_WDT_CTL_ICCSURV_STS BIT25
> +#define B_ACPI_IO_OC_WDT_CTL_NO_ICCSURV_STS BIT24
> +#define B_ACPI_IO_OC_WDT_CTL_FORCE_ALL BIT15
> +#define B_ACPI_IO_OC_WDT_CTL_EN BIT14
> +#define B_ACPI_IO_OC_WDT_CTL_ICCSURV BIT13
> +#define B_ACPI_IO_OC_WDT_CTL_LCK BIT12
> +#define B_ACPI_IO_OC_WDT_CTL_TOV_MASK 0x3FF
> +#define B_ACPI_IO_OC_WDT_CTL_FAILURE_STS BIT23
> +#define B_ACPI_IO_OC_WDT_CTL_UNXP_RESET_STS BIT22
> +#define B_ACPI_IO_OC_WDT_CTL_AFTER_POST 0x3F0000
> +#define V_ACPI_IO_OC_WDT_CTL_STATUS_FAILURE 1
> +#define V_ACPI_IO_OC_WDT_CTL_STATUS_OK 0
> +
> +#define R_ACPI_IO_GPE0_STS_31_0 0x60
> +#define R_ACPI_IO_GPE0_STS_63_32 0x64
> +#define R_ACPI_IO_GPE0_STS_95_64 0x68
> +#define R_ACPI_IO_GPE0_STS_127_96 0x6C
> +#define S_ACPI_IO_GPE0_STS_127_96 4
> +#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18
> +#define B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS BIT17
> +#define B_ACPI_IO_GPE0_STS_127_96_LAN_WAKE BIT16
> +#define B_ACPI_IO_GPE0_STS_127_96_GPIO_TIER_2 BIT15
> +#define B_ACPI_IO_GPE0_STS_127_96_PME_B0 BIT13
> +#define B_ACPI_IO_GPE0_STS_127_96_ME_SCI BIT12
> +#define B_ACPI_IO_GPE0_STS_127_96_PME BIT11
> +#define B_ACPI_IO_GPE0_STS_127_96_BATLOW BIT10
> +#define B_ACPI_IO_GPE0_STS_127_96_PCI_EXP BIT9
> +#define B_ACPI_IO_GPE0_STS_127_96_RI BIT8
> +#define B_ACPI_IO_GPE0_STS_127_96_SMB_WAK BIT7
> +#define B_ACPI_IO_GPE0_STS_127_96_TC0SCI BIT6
> +#define B_ACPI_IO_GPE0_STS_127_96_SWGPE BIT2
> +#define B_ACPI_IO_GPE0_STS_127_96_HOT_PLUG BIT1
> +#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13
> +#define N_ACPI_IO_GPE0_STS_127_96_PME 11
> +#define N_ACPI_IO_GPE0_STS_127_96_BATLOW 10
> +#define N_ACPI_IO_GPE0_STS_127_96_PCI_EXP 9
> +#define N_ACPI_IO_GPE0_STS_127_96_RI 8
> +#define N_ACPI_IO_GPE0_STS_127_96_SMB_WAK 7
> +#define N_ACPI_IO_GPE0_STS_127_96_TC0SCI 6
> +#define N_ACPI_IO_GPE0_STS_127_96_SWGPE 2
> +#define N_ACPI_IO_GPE0_STS_127_96_HOT_PLUG 1
> +
> +#define R_ACPI_IO_GPE0_EN_31_0 0x70
> +#define R_ACPI_IO_GPE0_EN_63_32 0x74
> +#define R_ACPI_IO_GPE0_EN_95_64 0x78
> +#define R_ACPI_IO_GPE0_EN_127_96 0x7C
> +#define S_ACPI_IO_GPE0_EN_127_96 4
> +#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18
> +#define B_ACPI_IO_GPE0_EN_127_96_USB_CON_DSX_EN BIT17
> +#define B_ACPI_IO_GPE0_EN_127_96_LAN_WAKE BIT16
> +#define B_ACPI_IO_GPE0_EN_127_96_PME_B0 BIT13
> +#define B_ACPI_IO_GPE0_EN_127_96_ME_SCI BIT12
> +#define B_ACPI_IO_GPE0_EN_127_96_PME BIT11
> +#define B_ACPI_IO_GPE0_EN_127_96_BATLOW BIT10
> +#define B_ACPI_IO_GPE0_EN_127_96_PCI_EXP BIT9
> +#define B_ACPI_IO_GPE0_EN_127_96_RI BIT8
> +#define B_ACPI_IO_GPE0_EN_127_96_TC0SCI BIT6
> +#define B_ACPI_IO_GPE0_EN_127_96_SWGPE BIT2
> +#define B_ACPI_IO_GPE0_EN_127_96_HOT_PLUG BIT1
> +#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13
> +#define N_ACPI_IO_GPE0_EN_127_96_USB3 12
> +#define N_ACPI_IO_GPE0_EN_127_96_PME 11
> +#define N_ACPI_IO_GPE0_EN_127_96_BATLOW 10
> +#define N_ACPI_IO_GPE0_EN_127_96_PCI_EXP 9
> +#define N_ACPI_IO_GPE0_EN_127_96_RI 8
> +#define N_ACPI_IO_GPE0_EN_127_96_TC0SCI 6
> +#define N_ACPI_IO_GPE0_EN_127_96_SWGPE 2
> +#define N_ACPI_IO_GPE0_EN_127_96_HOT_PLUG 1
> +
> +
> +//
> +// TCO register I/O map
> +//
> +#define R_TCO_IO_RLD 0x0
> +#define R_TCO_IO_DAT_IN 0x2
> +#define R_TCO_IO_DAT_OUT 0x3
> +#define R_TCO_IO_TCO1_STS 0x04
> +#define S_TCO_IO_TCO1_STS 2
> +#define B_TCO_IO_TCO1_STS_DMISERR BIT12
> +#define B_TCO_IO_TCO1_STS_DMISMI BIT10
> +#define B_TCO_IO_TCO1_STS_DMISCI BIT9
> +#define B_TCO_IO_TCO1_STS_BIOSWR BIT8
> +#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7
> +#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3
> +#define B_TCO_IO_TCO1_STS_TCO_INT BIT2
> +#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1
> +#define N_TCO_IO_TCO1_STS_DMISMI 10
> +#define N_TCO_IO_TCO1_STS_BIOSWR 8
> +#define N_TCO_IO_TCO1_STS_NEWCENTURY 7
> +#define N_TCO_IO_TCO1_STS_TIMEOUT 3
> +#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1
> +
> +#define R_TCO_IO_TCO2_STS 0x06
> +#define S_TCO_IO_TCO2_STS 2
> +#define B_TCO_IO_TCO2_STS_SMLINK_SLV_SMI BIT4
> +#define B_TCO_IO_TCO2_STS_BAD_BIOS BIT3
> +#define B_TCO_IO_TCO2_STS_BOOT BIT2
> +#define B_TCO_IO_TCO2_STS_SECOND_TO BIT1
> +#define B_TCO_IO_TCO2_STS_INTRD_DET BIT0
> +#define N_TCO_IO_TCO2_STS_INTRD_DET 0
> +
> +#define R_TCO_IO_TCO1_CNT 0x08
> +#define S_TCO_IO_TCO1_CNT 2
> +#define B_TCO_IO_TCO1_CNT_LOCK BIT12
> +#define B_TCO_IO_TCO1_CNT_TMR_HLT BIT11
> +#define B_TCO_IO_TCO1_CNT_NR_MSUS BIT0 //NO_REBOOT
> +
> +#define R_TCO_IO_TCO2_CNT 0x0A
> +#define S_TCO_IO_TCO2_CNT 2
> +#define B_TCO_IO_TCO2_CNT_OS_POLICY 0x0030
> +#define B_TCO_IO_TCO2_CNT_GPI11_ALERT_DISABLE 0x0008
> +#define B_TCO_IO_TCO2_CNT_INTRD_SEL 0x0006
> +#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2
> +
> +#define R_TCO_IO_MESSAGE1 0x0C
> +#define R_TCO_IO_MESSAGE2 0x0D
> +#define R_TCO_IO_TWDS 0x0E ///<
> TCO_WDSTATUS register.
> +#define R_TCO_IO_LE 0x10 ///<
> LEGACY_ELIM register
> +#define B_TCO_IO_LE_IRQ12_CAUSE BIT1
> +#define B_TCO_IO_LE_IRQ1_CAUSE BIT0
> +#define R_TCO_IO_TMR 0x12
> +
> +//
> +// PWRM Registers for IPC interface
> +//
> +#define R_PMC_PWRM_IPC_CMD 0x00
> ///< IPC command
> +#define N_PMC_PWRM_IPC_CMD_CMD_ID 12
> ///< IPC command.cmd.ID
> +#define N_PMC_PWRM_IPC_CMD_SIZE 16
> ///< IPC command.size
> +#define B_PMC_PWRM_IPC_CMD_SIZE_MASK 0x00FF0000
> ///< IPC command.size mask Bits[23:16]
> +#define N_PMC_PWRM_IPC_CMD_COMMAND 0
> ///< IPC command.cmd.Command
> +#define B_PMC_PWRM_IPC_CMD_COMMAND_MASK
> 0x000000FF ///< IPC command.size mask Bits[07:00]
> +#define V_PMC_PWRM_IPC_CMD_COMMAND_SLP_CTRL 0xA1
> ///< IPC commmand to control S0ix policies RCOMP
> +#define V_PMC_PWRM_IPC_CMD_COMMAND_NPK_STATE 0xA4
> ///< IPC commmand to control NPK Power State
> +#define V_PMC_PWRM_IPC_CMD_COMMAND_PROXY 0xAA
> ///< Proxy access to SOC registers
> +#define V_PMC_PWRM_IPC_CMD_CMD_ID_PROXY_READ 0
> ///< Read command
> +#define V_PMC_PWRM_IPC_CMD_CMD_ID_PROXY_WRITE 1
> ///< Write command
> +#define V_PMC_PWRM_IPC_CMD_WBUF0_PROXY_NMI 2
> ///< parameter to access NMI control register
> +#define R_PMC_PWRM_IPC_STS 0x04
> ///< IPC Status
> +#define B_PMC_PWRM_IPC_STS_BUSY BIT0
> ///< IPC Status Busy Bit
> +#define B_PMC_PWRM_IPC_STS_ERROR BIT1
> ///< IPC Status Error Bit
> +#define N_PMC_PWRM_IPC_STS_ERR_CODE BIT16
> ///< IPC Status Error status
> +#define B_PMC_PWRM_IPC_STS_ERR_CODE_MASK
> 0x00FF0000 ///< IPC Status Error status mask[23:16]
> +#define R_PMC_PWRM_IPC_SPTR 0x08
> ///< IPC Source Pointer
> +#define R_PMC_PWRM_IPC_DPTR 0x0C
> ///< IPC Destination Pointer
> +#define R_PMC_PWRM_IPC_WBUF0 0x80
> ///< IPC Write Buffer
> +#define R_PMC_PWRM_IPC_WBUF1 0x84
> ///< IPC Write Buffer
> +#define R_PMC_PWRM_IPC_WBUF2 0x88
> ///< IPC Write Buffer
> +#define R_PMC_PWRM_IPC_WBUF3 0x8C
> ///< IPC Write Buffer
> +#define R_PMC_PWRM_IPC_RBUF0 0x90
> ///< IPC Read Buffer
> +#define R_PMC_PWRM_IPC_RBUF1 0x94
> ///< IPC Read Buffer
> +#define R_PMC_PWRM_IPC_RBUF2 0x98
> ///< IPC Read Buffer
> +#define R_PMC_PWRM_IPC_RBUF3 0x9C
> ///< IPC Read Buffer
> +//
> +// PWRM Registers
> +//
> +#define R_PMC_PWRM_GEN_PMCON_A 0x1020
> +#define B_PMC_PWRM_GEN_PMCON_A_DC_PP_DIS BIT30
> +#define B_PMC_PWRM_GEN_PMCON_A_DSX_PP_DIS BIT29
> +#define B_PMC_PWRM_GEN_PMCON_A_AG3_PP_EN BIT28
> +#define B_PMC_PWRM_GEN_PMCON_A_SX_PP_EN BIT27
> +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_ICLK_PLL BIT26
> +#define B_PMC_PWRM_GEN_PMCON_A_MPHY_CRICLK_GATE_OVR
> BIT25
> +#define B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS BIT24
> +#define B_PMC_PWRM_GEN_PMCON_A_DISB BIT23
> +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_OPI_PLL_SD_INC0
> BIT22
> +#define B_PMC_PWRM_GEN_PMCON_A_MEM_SR BIT21
> +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_SPXB_CG_INC0
> BIT20
> +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_C0
> BIT19
> +#define B_PMC_PWRM_GEN_PMCON_A_MS4V BIT18
> +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON
> BIT17
> +#define B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR BIT16
> +#define B_PMC_PWRM_GEN_PMCON_A_PME_B0_S5_DIS BIT15
> +#define B_PMC_PWRM_GEN_PMCON_A_PWR_FLR BIT14
> +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON
> BIT13
> +#define B_PMC_PWRM_GEN_PMCON_A_DISABLE_SX_STRETCH
> BIT12
> +#define B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS BIT9
> +#define B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK BIT8
> +#define B_PMC_PWRM_GEN_PMCON_A_SLP_S4_ASE BIT3
> +#define B_PMC_PWRM_GEN_PMCON_A_AFTERG3_EN BIT0
> +#define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0
> +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0
> +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80
> +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40
> +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS
> 0x00
> +#define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL 0x6
> +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000
> +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002
> +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004
> +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006
> +
> +#define R_PMC_PWRM_GEN_PMCON_B 0x1024
> +#define B_PMC_PWRM_GEN_PMCON_B_SLPSX_STR_POL_LOCK
> BIT18 ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width
> +#define B_PMC_PWRM_GEN_PMCON_B_WOL_EN_OVRD BIT13
> +#define B_PMC_PWRM_GEN_PMCON_B_BIOS_PCI_EXP_EN BIT10
> +#define B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL BIT9
> +#define B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK BIT4
> +#define B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS BIT2
> +
> +#define R_PMC_PWRM_CRID 0x1030 ///<
> Configured Revision ID
> +#define B_PMC_PWRM_CRID_RID_SEL (BIT0 | BIT1)
> ///< RID Select
> +#define V_PMC_PWRM_CRID_RID_SEL_REVISIONID 0
> +#define V_PMC_PWRM_CRID_RID_SEL_CRID0 1
> +#define B_PMC_PWRM_CRID_CRID_LK BIT31
> ///< CRID Lock
> +
> +#define R_PMC_PWRM_ETR3 0x1048 ///<
> this is PWRM register
> +#define B_PMC_PWRM_ETR3_CF9LOCK BIT31
> ///< CF9h Lockdown
> +#define B_PMC_PWRM_ETR3_LATCH_EVENTS_C10_EXIT BIT30
> +#define B_PMC_PWRM_ETR3_USB_CACHE_DIS BIT21
> +#define B_PMC_PWRM_ETR3_CF9GR BIT20
> ///< CF9h Global Reset
> +#define B_PMC_PWRM_ETR3_SKIP_HOST_RST_HS BIT19
> +#define B_PMC_PWRM_ETR3_CWORWRE BIT18
> +#define B_PMC_PWRM_THROT_1_VR_ALERT BIT0
> +
> +#define R_PMC_PWRM_SSML 0x104C ///<
> Set Strap Msg Lock
> +#define B_PMC_PWRM_SSML_SSL BIT0 ///<
> Set_Strap Lock
> +#define R_PMC_PWRM_SSMC 0x1050 ///<
> Set Strap Msg Control
> +#define B_PMC_PWRM_SSMC_SSMS BIT0
> ///< Set_Strap Mux Select
> +#define R_PMC_PWRM_SSMD 0x1054 ///<
> Set Strap Msg Data
> +
> +#define R_PMC_PWRM_MODPHY_PM_CFG5 0x10D0
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_UFS2
> BIT26
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_DMI
> BIT25
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_E3
> BIT24
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_E2
> BIT23
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_E1
> BIT22
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_E0
> BIT21
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_D3
> BIT20
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_D2
> BIT19
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_D1
> BIT18
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_D0
> BIT17
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_UFS
> BIT16 ///< UFS ModPHY SPD RT Request
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XDCI
> BIT15 ///< xDCI ModPHY SPD RT Request
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XHCI
> BIT14 ///< xHCI ModPHY SPD RT Request
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_GBE
> BIT13 ///< GbE ModPHY SPD RT Request
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_SATA
> BIT12 ///< SATA ModPHY SPD RT Request
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_C3
> BIT11
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_C2
> BIT10
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_C1 BIT9
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_C0 BIT8
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_B3 BIT7
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_B2 BIT6
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_B1 BIT5
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_B0 BIT4
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_A3 BIT3
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_A2 BIT2
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_A1 BIT1
> +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_A0 BIT0
> +#define R_PMC_PWRM_WADT_AC 0x1800
> +#define R_PMC_PWRM_PRSTS 0x1810
> ///< Power and Reset Status
> +#define B_PMC_PWRM_PRSTS_VE_WD_TMR_STS BIT7
> ///< VE Watchdog Timer Status
> +#define B_PMC_PWRM_PRSTS_WOL_OVR_WK_STS BIT5
> +#define B_PMC_PWRM_PRSTS_FIELD_1 BIT4
> +#define B_PMC_PWRM_PRSTS_ME_WAKE_STS BIT0
> +
> +#define R_PMC_PWRM_1814 0x1814
> +#define R_PMC_PWRM_CFG 0x1818
> ///< Power Management Configuration
> +#define B_PMC_PWRM_CFG_ALLOW_24_OSC_SD BIT29
> ///< Allow 24MHz Crystal Oscillator Shutdown
> +#define B_PMC_PWRM_CFG_DBG_MODE_LOCK BIT27
> ///< Debug Mode Lock
> +#define B_PMC_PWRM_CFG_ALLOW_USB2_CORE_PG BIT25
> ///< Allow USB2 Core Power Gating
> +#define B_PMC_PWRM_CFG_ER_LOCK BIT24
> ///< Energy Reporting Lock
> +#define B_PMC_PWRM_CFG_EN_PMC_UNC_ERR BIT23
> ///< Enable Global Reset on Uncorrectable Parity Error on PMC SRAM Interface
> +#define B_PMC_PWRM_CFG_PMCREAD_DISABLE BIT22
> ///< Disable Reads to PMC
> +#define B_PMC_PWRM_CFG_RTC_DS_WAKE_DIS BIT21
> ///< RTC Wake from Deep S4/S5 Disable
> +#define B_PMC_PWRM_CFG_SSMAW_MASK (BIT19 |
> BIT18) ///< SLP_SUS# Min Assertion Width
> +#define V_PMC_PWRM_CFG_SSMAW_4S (BIT19 | BIT18)
> ///< 4 seconds
> +#define V_PMC_PWRM_CFG_SSMAW_1S BIT19
> ///< 1 second
> +#define V_PMC_PWRM_CFG_SSMAW_0_5S BIT18
> ///< 0.5 second (500ms)
> +#define V_PMC_PWRM_CFG_SSMAW_0S 0
> ///< 0 second
> +#define B_PMC_PWRM_CFG_SAMAW_MASK (BIT17 |
> BIT16) ///< SLP_A# Min Assertion Width
> +#define V_PMC_PWRM_CFG_SAMAW_2S (BIT17 | BIT16)
> ///< 2 seconds
> +#define V_PMC_PWRM_CFG_SAMAW_98ms BIT17
> ///< 98ms
> +#define V_PMC_PWRM_CFG_SAMAW_4S BIT16
> ///< 4 seconds
> +#define V_PMC_PWRM_CFG_SAMAW_0S 0
> ///< 0 second
> +#define B_PMC_PWRM_CFG_RPCD_MASK (BIT9 | BIT8)
> ///< Reset Power Cycle Duration
> +#define V_PMC_PWRM_CFG_RPCD_1S (BIT9 | BIT8)
> ///< 1-2 seconds
> +#define V_PMC_PWRM_CFG_RPCD_2S BIT9
> ///< 2-3 seconds
> +#define V_PMC_PWRM_CFG_RPCD_3S BIT8
> ///< 3-4 seconds
> +#define V_PMC_PWRM_CFG_RPCD_4S 0
> ///< 4-5 seconds (Default)
> +#define B_PMC_PWRM_CFG_COCS BIT5
> ///< CPU OC Strap
> +#define B_PMC_PWRM_CFG_ER_EN BIT2
> ///< Energy Reporting Enable
> +#define B_PMC_PWRM_CFG_TIMING_TPCH25 (BIT1 | BIT0)
> ///< tPCH25 timing
> +
> +#define R_PMC_PWRM_S3_PWRGATE_POL 0x1828
> ///< S3 Power Gating Policies
> +#define B_PMC_PWRM_S3_PWRGATE_POL_S3DC_GATE_SUS BIT1
> ///< Deep S3 Enable in DC Mode
> +#define B_PMC_PWRM_S3_PWRGATE_POL_S3AC_GATE_SUS BIT0
> ///< Deep S3 Enable in AC Mode
> +
> +#define R_PMC_PWRM_S4_PWRGATE_POL 0x182C
> ///< Deep S4 Power Policies
> +#define B_PMC_PWRM_S4_PWRGATE_POL_S4DC_GATE_SUS BIT1
> ///< Deep S4 Enable in DC Mode
> +#define B_PMC_PWRM_S4_PWRGATE_POL_S4AC_GATE_SUS BIT0
> ///< Deep S4 Enable in AC Mode
> +
> +#define R_PMC_PWRM_S5_PWRGATE_POL 0x1830
> ///< Deep S5 Power Policies
> +#define B_PMC_PWRM_S5_PWRGATE_POL_S5DC_GATE_SUS BIT15
> ///< Deep S5 Enable in DC Mode
> +#define B_PMC_PWRM_S5_PWRGATE_POL_S5AC_GATE_SUS BIT14
> ///< Deep S5 Enable in AC Mode
> +
> +#define R_PMC_PWRM_DSX_CFG 0x1834
> ///< Deep SX Configuration
> +#define B_PMC_PWRM_DSX_CFG_WAKE_PIN_DSX_EN BIT2
> ///< WAKE# Pin DeepSx Enable
> +#define B_PMC_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS BIT1
> ///< AC_PRESENT pin pulldown in DeepSx disable
> +#define B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN BIT0
> ///< LAN_WAKE Pin DeepSx Enable
> +
> +#define R_PMC_PWRM_CFG2 0x183C
> ///< Power Management Configuration Reg 2
> +#define B_PMC_PWRM_CFG2_PBOP (BIT31 | BIT30 |
> BIT29) ///< Power Button Override Period (PBOP)
> +#define N_PMC_PWRM_CFG2_PBOP 29
> ///< Power Button Override Period (PBOP)
> +#define B_PMC_PWRM_CFG2_PB_DIS BIT28
> ///< Power Button Native Mode Disable (PB_DIS)
> +#define B_PMC_PWRM_CFG2_EN_DBG_MSG BIT27
> ///< Enable PMC Debug Messages
> +#define B_PMC_PWRM_CFG2_DRAM_RESET_CTL BIT26
> ///< DRAM RESET# control
> +#define N_PMC_PWRM_CFG2_DRAM_RESET_CTL 26
> +
> +#define R_PMC_PWRM_EN_SN_SLOW_RING 0x1848
> ///< Enable Snoop Request to SLOW_RING
> +#define R_PMC_PWRM_EN_SN_SLOW_RING2 0x184C
> ///< Enable Snoop Request to SLOW_RING 2nd Reg
> +#define R_PMC_PWRM_EN_SN_SA 0x1850
> ///< Enable Snoop Request to SA
> +#define R_PMC_PWRM_EN_SN_SA2 0x1854
> ///< Enable Snoop Request to SA 2nd Reg
> +#define R_PMC_PWRM_EN_SN_SLOW_RING_CF 0x1858
> ///< Enable Snoop Request to SLOW_RING_CF
> +#define R_PMC_PWRM_EN_NS_SA 0x1868
> ///< Enable Non-Snoop Request to SA
> +#define R_PMC_PWRM_EN_CW_SLOW_RING 0x1880
> ///< Enable Clock Wake to SLOW_RING
> +#define R_PMC_PWRM_EN_CW_SLOW_RING2 0x1884
> ///< Enable Clock Wake to SLOW_RING 2nd Reg
> +#define R_PMC_PWRM_EN_CW_SA 0x1888
> ///< Enable Clock Wake to SA
> +#define R_PMC_PWRM_EN_CW_SA2 0x188C
> ///< Enable Clock Wake to SA 2nd Reg
> +#define R_PMC_PWRM_EN_CW_SLOW_RING_CF 0x1898
> ///< Enable Clock Wake to SLOW_RING_CF
> +#define R_PMC_PWRM_EN_PA_SLOW_RING 0x18A8
> ///< Enable Pegged Active to SLOW_RING
> +#define R_PMC_PWRM_EN_PA_SLOW_RING2 0x18AC
> ///< Enable Pegged Active to SLOW_RING 2nd Reg
> +#define R_PMC_PWRM_EN_PA_SA 0x18B0
> ///< Enable Pegged Active to SA
> +#define R_PMC_PWRM_EN_PA_SA2 0x18B4
> ///< Enable Pegged Active to SA 2nd Reg
> +#define R_PMC_PWRM_EN_MISC_EVENT 0x18C0
> ///< Enable Misc PM_SYNC Events
> +#define R_PMC_PWRM_PMSYNC_TPR_CONFIG 0x18C4
> +#define B_PMC_PWRM_PMSYNC_TPR_CONFIG_LOCK BIT31
> +#define B_PMC_PWRM_PMSYNC_PCH2CPU_TT_EN BIT26
> +#define B_PMC_PWRM_PMSYNC_PCH2CPU_TT_STATE (BIT25 |
> BIT24)
> +#define N_PMC_PWRM_PMSYNC_PCH2CPU_TT_STATE 24
> +#define V_PMC_PWRM_PMSYNC_PCH2CPU_TT_STATE_1 1
> +#define B_PMC_PWRM_PMSYNC_PM_SYNC_LOCK BIT15
> ///< PM_SYNC Configuration Lock
> +#define B_PMC_PWRM_PMSYNC_GPIO_D_SEL BIT11
> +#define B_PMC_PWRM_PMSYNC_GPIO_C_SEL BIT10
> +
> +#define R_PMC_PWRM_PM_SYNC_STATE_HYS 0x18D0
> ///< PM_SYNC State Hysteresis
> +#define R_PMC_PWRM_PM_SYNC_MODE 0x18D4
> ///< PM_SYNC Pin Mode
> +
> +#define R_PMC_PWRM_CFG3 0x18E0
> ///< Power Management Configuration Reg 3
> +#define B_PMC_PWRM_CFG3_HOST_WLAN_PP_EN BIT17
> ///< Host Wireless LAN Phy Power Enable
> +#define B_PMC_PWRM_CFG3_DSX_WLAN_PP_EN BIT16
> ///< Deep-Sx WLAN Phy Power Enable
> +
> +#define R_PMC_PWRM_PM_DOWN_PPB_CFG 0x18E4
> ///< PM_DOWN PCH_POWER_BUDGET CONFIGURATION
> +
> +#define R_PMC_PWRM_CFG4 0x18E8
> ///< Power Management Configuration Reg 4
> +#define B_PMC_PWRM_CFG4_U2_PHY_PG_EN BIT30
> ///< USB2 PHY SUS Well Power Gating Enable
> +#define B_PMC_PWRM_CFG4_CPU_IOVR_RAMP_DUR
> (0x000001FF) ///< CPU I/O VR Ramp Duration, [8:0]
> +#define N_PMC_PWRM_CFG4_CPU_IOVR_RAMP_DUR 0
> +#define V_PMC_PWRM_CFG4_CPU_IOVR_RAMP_DUR_70US 0x007
> +#define V_PMC_PWRM_CFG4_CPU_IOVR_RAMP_DUR_240US
> 0x018
> +
> +#define R_PMC_PWRM_CPU_EPOC 0x18EC
> +
> +#define R_PMC_PWRM_GPIO_CFG 0x1920
> +#define B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 |
> BIT10 | BIT9 | BIT8)
> +#define N_PMC_PWRM_GPIO_CFG_GPE0_DW2 8
> +#define B_PMC_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6
> | BIT5 | BIT4)
> +#define N_PMC_PWRM_GPIO_CFG_GPE0_DW1 4
> +#define B_PMC_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2
> | BIT1 | BIT0)
> +#define N_PMC_PWRM_GPIO_CFG_GPE0_DW0 0
> +
> +
> +#define R_PMC_PWRM_CS_SD_CTL1 0x1BE8
> ///< Clock Source Shutdown Control Reg 1
> +#define B_PMC_PWRM_CS_SD_CTL1_CS5_CTL_CFG (BIT22 |
> BIT21 | BIT20) ///< Clock Source 5 Control Configuration
> +#define N_PMC_PWRM_CS_SD_CTL1_CS5_CTL_CFG 20
> +#define B_PMC_PWRM_CS_SD_CTL1_CS1_CTL_CFG (BIT2 | BIT1
> | BIT0) ///< Clock Source 1 Control Configuration
> +#define N_PMC_PWRM_CS_SD_CTL1_CS1_CTL_CFG 0
> +
> +#define R_PMC_PWRM_CS_SD_CTL2 0x1BEC ///<
> Clock Source Shutdown Control Reg 2
> +
> +#define R_PMC_PWRM_HSWPGCR1 0x1DD0
> +#define B_PMC_PWRM_SW_PG_CTRL_LOCK BIT31
> +#define B_PMC_PWRM_NPK_VNN_SW_PG_CTRL BIT0
> +
> +#define R_PMC_PWRM_1E00 0x1E00
> +#define R_PMC_PWRM_1E04 0x1E04
> +
> +#define R_PMC_PWRM_ST_PG_FDIS_PMC_1 0x1E20 ///<
> Static PG Related Function Disable Register 1
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_CNVI_FDIS_PMC BIT1
> ///< CNVi Function Disable (PMC Version) (CNVI_FDIS_PMC)
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31
> ///< Static Function Disable Lock (ST_FDIS_LK)
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_CAM_FDIS_PMC BIT6
> ///< Camera Function Disable (PMC Version) (CAM_FDIS_PMC)
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_ISH_FDIS_PMC BIT5
> ///< SH Function Disable (PMC Version) (ISH_FDIS_PMC)
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_GBE_FDIS_PMC BIT0
> ///< GBE Function Disable (PMC Version) (GBE_FDIS_PMC)
> +
> +#define R_PMC_PWRM_ST_PG_FDIS_PMC_2 0x1E24 ///<
> Static Function Disable Control Register 2
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI2_FDIS_PMC
> BIT11 ///< SerialIo Controller GSPI Device 2 Function Disable
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI1_FDIS_PMC
> BIT10 ///< SerialIo Controller GSPI Device 1 Function Disable
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI0_FDIS_PMC
> BIT9 ///< SerialIo Controller GSPI Device 0 Function Disable
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART2_FDIS_PMC
> BIT8 ///< SerialIo Controller UART Device 2 Function Disable
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART1_FDIS_PMC
> BIT7 ///< SerialIo Controller UART Device 1 Function Disable
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART0_FDIS_PMC
> BIT6 ///< SerialIo Controller UART Device 0 Function Disable
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C5_FDIS_PMC
> BIT5 ///< SerialIo Controller I2C Device 5 Function Disable
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C4_FDIS_PMC
> BIT4 ///< SerialIo Controller I2C Device 4 Function Disable
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C3_FDIS_PMC
> BIT3 ///< SerialIo Controller I2C Device 3 Function Disable
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C2_FDIS_PMC
> BIT2 ///< SerialIo Controller I2C Device 2 Function Disable
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C1_FDIS_PMC
> BIT1 ///< SerialIo Controller I2C Device 1 Function Disable
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C0_FDIS_PMC
> BIT0 ///< SerialIo Controller I2C Device 0 Function Disable
> +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO 0xFFF
> ///< SerialIo Devices Disable Mask
> +
> +#define R_PMC_PWRM_NST_PG_FDIS_1 0x1E28
> +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_F3_FDIS_PMC
> BIT31 ///< PCIe Controller F Port 3 Function Disable
> +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_F2_FDIS_PMC
> BIT30 ///< PCIe Controller F Port 2 Function Disable
> +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_F1_FDIS_PMC
> BIT29 ///< PCIe Controller F Port 1 Function Disable
> +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_F0_FDIS_PMC
> BIT28 ///< PCIe Controller F Port 0 Function Disable
> +#define B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_SDCARD_FDIS_PMC
> BIT29 ///< SD Card Function Disable
> +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_SDCARD_FDIS_PMC
> BIT27 ///< SD Card Function Disable
> +#define B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_EMMC_FDIS_PMC
> BIT28 ///< eMMC Function Disable
> +#define B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_UFS_FDIS_PMC BIT27
> ///< UFS Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_XDCI_FDIS_PMC BIT26
> ///< XDCI Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_SMBUS_FDIS_PMC BIT25
> ///< Smbus Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_ADSP_FDIS_PMC BIT23
> ///< ADSP Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_SATA_FDIS_PMC BIT22
> ///< SATA Function Disable
> +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_E3_FDIS_PMC
> BIT21 ///< PCIe Controller E Port 3 Function Disable
> +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_E2_FDIS_PMC
> BIT20 ///< PCIe Controller E Port 2 Function Disable
> +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_E1_FDIS_PMC
> BIT19 ///< PCIe Controller E Port 1 Function Disable
> +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_E0_FDIS_PMC
> BIT18 ///< PCIe Controller E Port 0 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_D3_FDIS_PMC BIT17
> ///< PCIe Controller D Port 3 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_D2_FDIS_PMC BIT16
> ///< PCIe Controller D Port 2 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_D1_FDIS_PMC BIT15
> ///< PCIe Controller D Port 1 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_D0_FDIS_PMC BIT14
> ///< PCIe Controller D Port 0 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_C3_FDIS_PMC BIT13
> ///< PCIe Controller C Port 3 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_C2_FDIS_PMC BIT12
> ///< PCIe Controller C Port 2 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_C1_FDIS_PMC BIT11
> ///< PCIe Controller C Port 1 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_C0_FDIS_PMC BIT10
> ///< PCIe Controller C Port 0 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_B3_FDIS_PMC BIT9
> ///< PCIe Controller B Port 3 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_B2_FDIS_PMC BIT8
> ///< PCIe Controller B Port 2 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_B1_FDIS_PMC BIT7
> ///< PCIe Controller B Port 1 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_B0_FDIS_PMC BIT6
> ///< PCIe Controller B Port 0 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_A3_FDIS_PMC BIT5
> ///< PCIe Controller A Port 3 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_A2_FDIS_PMC BIT4
> ///< PCIe Controller A Port 2 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_A1_FDIS_PMC BIT3
> ///< PCIe Controller A Port 1 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_A0_FDIS_PMC BIT2
> ///< PCIe Controller A Port 0 Function Disable
> +#define B_PMC_PWRM_NST_PG_FDIS_1_XHCI_FDIS_PMC BIT0
> ///< XHCI Function Disable
> +
> +#define R_PMC_PWRM_FUSE_DIS_RD_2 0x1E44 ///<
> Fuse Disable Read 2 Register
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_SPC_SS_DIS BIT25 ///<
> SPC Fuse Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_SPB_SS_DIS BIT24 ///<
> SPB Fuse Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_SPA_SS_DIS BIT23 ///<
> SPA Fuse Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_PSTH_FUSE_SS_DIS BIT21
> ///< PSTH Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_DMI_FUSE_SS_DIS BIT20
> ///< DMI Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS BIT19
> ///< OTG Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_XHCI_SS_DIS BIT18 ///<
> XHCI Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_FIA_FUSE_SS_DIS BIT17
> ///< FIA Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_DSP_FUSE_SS_DIS BIT16
> ///< DSP Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS BIT15
> ///< SATA Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_ICC_FUSE_SS_DIS BIT14
> ///< ICC Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_LPC_FUSE_SS_DIS BIT13
> ///< LPC Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_RTC_FUSE_SS_DIS BIT12
> ///< RTC Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_P2S_FUSE_SS_DIS BIT11
> ///< P2S Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_TRSB_FUSE_SS_DIS BIT10
> ///< TRSB Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_SMB_FUSE_SS_DIS BIT9
> ///< SMB Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_ITSS_FUSE_SS_DIS BIT8
> ///< ITSS Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_UFSX2_FUSE_SS_DIS BIT7
> ///< UFSX2 Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_SERIALIO_FUSE_SS_DIS BIT6
> ///< SerialIo Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_EMMC_FUSE_SS_DIS BIT5
> ///< EMMC Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_CNVI_FUSE_SS_DIS BIT4
> ///< CNVi Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_P2D_FUSE_SS_DIS BIT3
> ///< P2D Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_SDX_FUSE_SS_DIS BIT2
> ///< SD Conroller Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_ISH_FUSE_SS_DIS BIT1
> ///< ISH Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0
> ///< GBE Fuse or Soft Strap Disable
> +
> +#define R_PMC_PWRM_FUSE_DIS_RD_3 0x1E48 ///<
> Static PG Fuse and Soft Strap Disable Read Register 3
> +#define B_PMC_PWRM_FUSE_DIS_RD_3_PNCRA3_FUSE_SS_DIS BIT3
> ///< PNCRA3 Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_3_PNCRA2_FUSE_SS_DIS BIT2
> ///< PNCRA2 Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_3_PNCRA1_FUSE_SS_DIS BIT1
> ///< PNCRA1 Fuse or Soft Strap Disable
> +#define B_PMC_PWRM_FUSE_DIS_RD_3_PNCRA_FUSE_SS_DIS BIT0
> ///< PNCRA Fuse or Soft Strap Disable
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmcCnl.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmcCnl.h
> new file mode 100644
> index 0000000000..bd0c2574f2
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmcCnl.h
> @@ -0,0 +1,72 @@
> +/** @file
> + Register names for PCH PMC device
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_PMC_CNL_H_
> +#define _PCH_REGS_PMC_CNL_H_
> +
> +//
> +// PWRM Registers
> +//
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_A
> 0x0
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_B
> 0x1
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_C
> 0xD
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_D
> 0x4
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_E
> 0xE
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_F
> 0x5
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_G
> 0x2
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_H
> 0x6
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPD 0xA
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_VGPIO
> 0x7
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_SPI 0x3
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_AZA 0xB
> +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_JTAG 0xF
> +
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_A
> 0x0
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_B
> 0x1
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_C
> 0x2
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_D
> 0x3
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_E
> 0xA
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_F
> 0xB
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_G
> 0x4
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_H
> 0x9
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_I
> 0xC
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_J
> 0xD
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_K
> 0x8
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPD 0x7
> +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_VGPIO
> 0x5
> +
> +#endif // _PCH_REGS_PMC_CNL_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h
> new file mode 100644
> index 0000000000..5c4d583904
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h
> @@ -0,0 +1,104 @@
> +/** @file
> + Register definition for PSF component
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_PSF_H_
> +#define _PCH_REGS_PSF_H_
> +
> +//
> +// Private chipset register (Memory space) offset definition
> +// The PCR register defines is used for PCR MMIO programming and PCH SBI
> programming as well.
> +//
> +
> +//
> +// PSFx segment registers
> +//
> +#define R_PCH_PSF_PCR_GLOBAL_CONFIG 0x4000
> ///< PSF Segment Global Configuration Register
> +#define B_PCH_PSF_PCR_ROOTSPACE_CONFIG_RSX_ENADDRP2P BIT1
> +#define B_PCH_PSF_PCR_ROOTSPACE_CONFIG_RSX_VTDEN BIT0
> +
> +#define S_PCH_PSFX_PCR_DEV_GNTCNT_RELOAD_DGCR 4
> +#define S_PCH_PSFX_PCR_TARGET_GNTCNT_RELOAD 4
> +#define
> B_PCH_PSFX_PCR_DEV_GNTCNT_RELOAD_DGCR_GNT_CNT_RELOAD 0x1F
> +#define B_PCH_PSFX_PCR_TARGET_GNTCNT_RELOAD_GNT_CNT_RELOAD
> 0x1F
> +
> +#define N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMMC 1
> +#define B_PCH_PSFX_PCR_MC_CONTROL_MCASTX_MULTCEN BIT0
> +
> +//
> +// PSFx PCRs definitions
> +//
> +#define R_PCH_PSFX_PCR_T0_SHDW_BAR0 0
> ///< PCI BAR0
> +#define R_PCH_PSFX_PCR_T0_SHDW_BAR1 0x04
> ///< PCI BAR1
> +#define R_PCH_PSFX_PCR_T0_SHDW_BAR2 0x08
> ///< PCI BAR2
> +#define R_PCH_PSFX_PCR_T0_SHDW_BAR3 0x0C
> ///< PCI BAR3
> +#define R_PCH_PSFX_PCR_T0_SHDW_BAR4 0x10
> ///< PCI BAR4
> +#define R_PCH_PSFX_PCR_T0_SHDW_PCIEN 0x1C
> ///< PCI configuration space enable bits
> +#define N_PCH_PSFX_PCR_T0_SHDW_PCIEN_BARXDIS 16
> +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR0DIS BIT16
> ///< Disable BAR0
> +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR1DIS BIT17
> ///< Disable BAR1
> +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR2DIS BIT18
> ///< Disable BAR2
> +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR3DIS BIT19
> ///< Disable BAR3
> +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR4DIS BIT20
> ///< Disable BAR4
> +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR5DIS BIT21
> ///< Disable BAR5
> +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS BIT8
> ///< Function disable
> +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_MEMEN BIT1
> ///< Memory decoding enable
> +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_IOEN BIT0
> ///< IO decoding enable
> +#define R_PCH_PSFX_PCR_T0_SHDW_PMCSR 0x20
> ///< PCI power management configuration
> +#define B_PCH_PSFX_PCR_T0_SHDW_PMCSR_PWRST (BIT1 | BIT0)
> ///< Power status
> +#define R_PCH_PSFX_PCR_T0_SHDW_CFG_DIS 0x38
> ///< PCI configuration disable
> +#define B_PCH_PSFX_PCR_T0_SHDW_CFG_DIS_CFGDIS BIT0
> ///< config disable
> +
> +#define R_PCH_PSFX_PCR_T1_SHDW_PCIEN 0x3C
> ///< PCI configuration space enable bits
> +#define B_PCH_PSFX_PCR_T1_SHDW_PCIEN_FUNDIS BIT8
> ///< Function disable
> +#define B_PCH_PSFX_PCR_T1_SHDW_PCIEN_MEMEN BIT1
> ///< Memory decoding enable
> +#define B_PCH_PSFX_PCR_T1_SHDW_PCIEN_IOEN BIT0
> ///< IO decoding enable
> +
> +#define B_PCH_PSFX_PCR_TX_AGENT_FUNCTION_CONFIG_DEVICE 0x01F0
> ///< device number
> +#define N_PCH_PSFX_PCR_TX_AGENT_FUNCTION_CONFIG_DEVICE 4
> +#define B_PCH_PSFX_PCR_TX_AGENT_FUNCTION_CONFIG_FUNCTION (BIT3
> | BIT2 | BIT1) ///< function number
> +#define N_PCH_PSFX_PCR_TX_AGENT_FUNCTION_CONFIG_FUNCTION 1
> +
> +#define B_PCH_PSFX_PCR_TARGET_CHANNELID 0xFF
> +#define B_PCH_PSFX_PCR_TARGET_PORTID 0x7F00
> +#define N_PCH_PSFX_PCR_TARGET_PORTID 8
> +#define B_PCH_PSFX_PCR_TARGET_PORTGROUPID BIT15
> +#define N_PCH_PSFX_PCR_TARGET_PORTGROUPID 15
> +#define B_PCH_PSFX_PCR_TARGET_PSFID 0xFF0000
> +#define N_PCH_PSFX_PCR_TARGET_PSFID 16
> +#define B_PCH_PSFX_PCR_TARGET_CHANMAP BIT31
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsfCnl.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsfCnl.h
> new file mode 100644
> index 0000000000..9a5e536f18
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsfCnl.h
> @@ -0,0 +1,113 @@
> +/** @file
> + Register definition for PSF component
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_PSF_CNL_H_
> +#define _PCH_REGS_PSF_CNL_H_
> +
> +//PSF 1 Multicast Message Configuration
> +#define R_CNL_PCH_LP_PSF1_PCR_PSF_MC_CONTROL_MCAST0_EOI
> 0x404C ///< Multicast Control Register
> +#define R_CNL_PCH_LP_PSF1_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI
> 0x4064 ///< Destination ID
> +#define R_CNL_PCH_H_PSF1_PCR_PSF_MC_CONTROL_MCAST0_EOI
> 0x403C ///< Multicast Control Register
> +#define R_CNL_PCH_H_PSF1_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI
> 0x4054 ///< Destination ID
> +
> +//
> +// PSF3 PCRs (PID:PSF3)
> +//
> +// PSF3 PCH-LP Specific Base Address
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI2_REG_BASE 0x0100
> ///< D18F6 PSF base address (SerialIo: SPI2)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_ISH_REG_BASE 0x0200
> ///< D19F0 PSF base address (ISH)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_CNVI_REG_BASE
> 0x0400 ///< D20F3 PSF base address (CNVi)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SDCARD_REG_BASE
> 0x0500 ///< D20F5 PSF base address (SCC: SDCard)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C0_REG_BASE 0x0600
> ///< D21F0 PSF base address (SerialIo: I2C0)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C1_REG_BASE 0x0700
> ///< D21F1 PSF base address (SerialIo: I2C1)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C2_REG_BASE 0x0800
> ///< D21F2 PSF base address (SerialIo: I2C2)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C3_REG_BASE 0x0900
> ///< D21F3 PSF base address (SerialIo: I2C3)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C4_REG_BASE 0x0A00
> ///< D25F0 PSF base address (SerialIo: I2C4)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C5_REG_BASE 0x0B00
> ///< D25F1 PSF base address (SerialIo: I2C5)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_UART2_REG_BASE
> 0x0C00 ///< D25F2 PSF base address (SerialIo: UART2)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_UART0_REG_BASE
> 0x0D00 ///< D30F0 PSF base address (SerialIo: UART0)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_UART1_REG_BASE
> 0x0E00 ///< D30F1 PSF base address (SerialIo: UART1)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI0_REG_BASE 0x0F00
> ///< D30F2 PSF base address (SerialIo: SPI0)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI1_REG_BASE 0x1000
> ///< D30F3 PSF base address (SerialIo: SPI1)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_LPC_REG_BASE 0x1100
> ///< D31F0 PSF base address (LPC)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_P2SB_REG_BASE
> 0x1300 ///< D31F1 PSF base address (P2SB)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_PMC_REG_BASE
> 0x1400 ///< D31F2 PSF base address (PMC)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_AUD_REG_BASE
> 0x1500 ///< D31F3 PSF base address (HDA, ADSP)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SMBUS_REG_BASE
> 0x1600 ///< D31F4 PSF base address (SMBUS)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI_SPI_REG_BASE
> 0x1700 ///< D31F5 PSF base address (SPI SPI)
> +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_GBE_REG_BASE
> 0x1800 ///< D31F6 PSF base address (GBE)
> +// PSF3 PCH-H Specific Base Address
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI2_REG_BASE 0x0100
> ///< D18F6 PSF base address (SerialIo: SPI2)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_ISH_REG_BASE 0x0180
> ///< D19F0 PSF base address (ISH)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_CNVI_REG_BASE
> 0x0280 ///< D20F3 PSF base address (CNVi)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SDCARD_REG_BASE
> 0x0300 ///< D20F5 PSF base address (SCC: SDCard)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C0_REG_BASE 0x0380
> ///< D21F0 PSF base address (SerialIo: I2C0)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C1_REG_BASE 0x0400
> ///< D21F1 PSF base address (SerialIo: I2C1)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C2_REG_BASE 0x0480
> ///< D21F2 PSF base address (SerialIo: I2C2)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C3_REG_BASE 0x0500
> ///< D21F3 PSF base address (SerialIo: I2C3)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_UART2_REG_BASE
> 0x0580 ///< D25F2 PSF base address (SerialIo: UART2)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_UART0_REG_BASE
> 0x0600 ///< D30F0 PSF base address (SerialIo: UART0)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_UART1_REG_BASE
> 0x0680 ///< D30F1 PSF base address (SerialIo: UART1)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI0_REG_BASE 0x0700
> ///< D30F2 PSF base address (SerialIo: SPI0)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI1_REG_BASE 0x0780
> ///< D30F3 PSF base address (SerialIo: SPI1)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_LPC_REG_BASE 0x0800
> ///< D31F0 PSF base address (LPC)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_P2SB_REG_BASE
> 0x0900 ///< D31F1 PSF base address (P2SB)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_PMC_REG_BASE
> 0x0980 ///< D31F2 PSF base address (PMC)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_AUD_REG_BASE
> 0x0A00 ///< D31F3 PSF base address (HDA, ADSP)H
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SMBUS_REG_BASE
> 0x0A80 ///< D31F4 PSF base address (SMBUS)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI_SPI_REG_BASE
> 0x0B00 ///< D31F5 PSF base address (SPI SPI)
> +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_GBE_REG_BASE
> 0x0B80 ///< D31F6 PSF base address (GBE)
> +
> +// Other PSF3 PCRs definition
> +#define R_CNL_PCH_PSF3_PCR_PSF_MC_CONTROL_MCAST0_EOI
> 0x4058 ///< Multicast Control Register // LP&H
> +#define R_CNL_PCH_PSF3_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI
> 0x4064 ///< Destination ID // LP&H
> +
> +#define R_CNL_PCH_H_PSF6_PCR_PSF_MC_CONTROL_MCAST0_EOI
> 0x4030 ///< Multicast Control Register
> +#define R_CNL_PCH_H_PSF6_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI
> 0x4048 ///< Destination ID
> +#define R_CNL_PCH_H_PSF6_PCR_PSF_MC_CONTROL_MCAST1_RS0_MCTP1
> 0x403C ///< Multicast Control Register
> +#define
> R_CNL_PCH_H_PSF6_PCR_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1
> 0x4070 ///< Destination ID
> +
> +#define R_CNL_PCH_H_PSF7_PCR_PSF_MC_CONTROL_MCAST0_EOI
> 0x4030 ///< Multicast Control Register
> +#define R_CNL_PCH_H_PSF7_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI
> 0x4048 ///< Destination ID
> +#define R_CNL_PCH_H_PSF7_PCR_PSF_MC_CONTROL_MCAST1_RS0_MCTP1
> 0x403C ///< Multicast Control Register
> +#define
> R_CNL_PCH_H_PSF7_PCR_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1
> 0x4070 ///< Destination ID
> +
> +#define R_CNL_PCH_H_PSF8_PCR_PSF_MC_CONTROL_MCAST0_EOI
> 0x4030 ///< Multicast Control Register
> +#define R_CNL_PCH_H_PSF8_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI
> 0x4048 ///< Destination ID
> +#define R_CNL_PCH_H_PSF8_PCR_PSF_MC_CONTROL_MCAST1_RS0_MCTP1
> 0x403C ///< Multicast Control Register
> +#define
> R_CNL_PCH_H_PSF8_PCR_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1
> 0x4070 ///< Destination ID
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h
> new file mode 100644
> index 0000000000..d6030ed10d
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h
> @@ -0,0 +1,77 @@
> +/** @file
> + Register definition for PSTH component
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_PSTH_H_
> +#define _PCH_REGS_PSTH_H_
> +
> +//
> +// Private chipset register (Memory space) offset definition
> +// The PCR register defines is used for PCR MMIO programming and PCH SBI
> programming as well.
> +//
> +
> +//
> +// PSTH and IO Trap PCRs (PID:PSTH)
> +//
> +#define R_PSTH_PCR_PSTHCTL 0x1D00 ///< PSTH control
> register
> +#define B_PSTH_PCR_PSTHIOSFPTCGE BIT2 ///< PSTH IOSF
> primary trunk clock gating enable
> +#define B_PSTH_PCR_PSTHIOSFSTCGE BIT1 ///< PSTH IOSF
> sideband trunk clock gating enable
> +#define B_PSTH_PCR_PSTHDCGE BIT0 ///< PSTH dynamic
> clock gating enable
> +#define R_PSTH_PCR_TRPST 0x1E00 ///< Trap status
> register
> +#define B_PSTH_PCR_TRPST_CTSS 0x0000000F ///< Cycle Trap
> SMI# Status mask
> +#define R_PSTH_PCR_TRPC 0x1E10 ///< Trapped cycle
> +#define B_PSTH_PCR_TRPC_RW BIT24 ///< Read/Write#:
> 1=Read, 0=Write
> +#define B_PSTH_PCR_TRPC_AHBE 0x00000000000F0000 ///< Active
> high byte enables
> +#define B_PSTH_PCR_TRPC_IOA 0x000000000000FFFC ///< Trap
> cycle I/O address
> +#define R_PSTH_PCR_TRPD 0x1E18 ///< Trapped write
> data
> +#define B_PSTH_PCR_TRPD_IOD 0x00000000FFFFFFFF ///< Trap cycle
> I/O data
> +#define R_PSTH_PCR_TRPREG0 0x1E80 ///< IO Tarp 0
> register
> +#define R_PSTH_PCR_TRPREG1 0x1E88 ///< IO Tarp 1
> register
> +#define R_PSTH_PCR_TRPREG2 0x1E90 ///< IO Tarp 2
> register
> +#define R_PSTH_PCR_TRPREG3 0x1E98 ///< IO Tarp 3
> register
> +#define B_PSTH_PCR_TRPREG_RWM BIT17 ///< 49 - 32 for 32
> bit access, Read/Write mask
> +#define B_PSTH_PCR_TRPREG_RWIO BIT16 ///< 48 - 32 for 32
> bit access, Read/Write#, 1=Read, 0=Write
> +#define N_PSTH_PCR_TRPREG_RWIO 16 ///< 48 - 32 for 32
> bit access, 16bit shift for Read/Write field
> +#define N_PSTH_PCR_TRPREG_BEM 36
> +#define B_PSTH_PCR_TRPREG_BEM 0x000000F000000000 ///< Byte
> enable mask
> +#define N_PSTH_PCR_TRPREG_BE 32
> +#define B_PSTH_PCR_TRPREG_BE 0x0000000F00000000 ///< Byte
> enable
> +#define B_PSTH_PCR_TRPREG_AM 0x0000000000FC0000 ///< IO
> Address mask
> +#define B_PSTH_PCR_TRPREG_AD 0x000000000000FFFC ///< IO
> Address
> +#define B_PSTH_PCR_TRPREG_TSE BIT0 ///< Trap and SMI#
> Enable
> +
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSata.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSata.h
> new file mode 100644
> index 0000000000..d98ce39df6
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSata.h
> @@ -0,0 +1,668 @@
> +/** @file
> + Register names for PCH SATA controllers
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_SATA_H_
> +#define _PCH_REGS_SATA_H_
> +
> +//
> +// SATA Controller Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SATA 23
> +#define PCI_FUNCTION_NUMBER_PCH_SATA 0
> +
> +#define PCI_DEVICE_NUMBER_CDF_PCH_SATA_1 7
> +#define PCI_FUNCTION_NUMBER_CDF_PCH_SATA_1 0
> +
> +#define PCI_DEVICE_NUMBER_CDF_PCH_SATA_2 8
> +#define PCI_FUNCTION_NUMBER_CDF_PCH_SATA_2 0
> +
> +#define PCI_DEVICE_NUMBER_CDF_PCH_SATA_3 14
> +#define PCI_FUNCTION_NUMBER_CDF_PCH_SATA_3 0
> +
> +//
> +// PCH-LP SATA Device ID's
> +//
> +#define V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_AHCI 0x9DD3 ///<
> SATA Controller (AHCI) - Mobile
> +#define V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_RAID 0x9DD5 ///<
> SATA Controller (RAID 0/1/5/10) - NOT premium - Mobile
> +#define V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_RAID_PREM 0x9DD7
> ///< SATA Controller (RAID 0/1/5/10) - premium - Mobile
> +#define V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_RAID_IBC 0x282A ///<
> SATA Controller (RAID 0/1/5/10) - In-box compatible - Mobile
> +
> +//
> +// PCH-H SATA Device ID's
> +//
> +#define V_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_ALTDIS 0x2822 ///<
> SATA Controller (RAID 0/1/5/10) - premium - Alternate ID
> +#define V_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_RSTE 0x2826 ///< SATA
> Controller (RAID 0/1/5/10) - RSTe of Server SKU
> +
> +//
> +// PCH-H SATA Device ID's
> +//
> +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_AHCI 0xA352 ///<
> SATA Controller (AHCI) Desktop/Server
> +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_MH_AHCI 0xA353 ///<
> SATA Controller (AHCI) Mobile Halo
> +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID 0xA354 ///<
> SATA Controller (RAID 0/1/5/10) - NOT premium Desktop/Server
> +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_MH_RAID 0xA355 ///<
> SATA Controller (RAID 0/1/5/10) - NOT premium Mobile Halo
> +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_PREM 0xA356
> ///< SATA Controller (RAID 0/1/5/10) - premium Desktop/Server
> +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_MH_RAID_PREM 0xA357
> ///< SATA Controller (RAID 0/1/5/10) - premium Mobile Halo
> +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_OP_AHCI 0xA35E ///<
> SATA Controller (AHCI) Optane Caching - Desktop
> +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_IBC 0x2822 ///<
> SATA Controller (RAID 0/1/5/10) - In-box compatible
> +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_IBC_RST 0x2826 ///<
> SATA Controller (RAID 0/1/5/10) - In-box compatible (RSTe)
> +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_IBC_2 0x282A ///<
> SATA Controller (RAID 0/1/5/10) - In-box compatible (Alternate)
> +
> +
> +//
> +// SATA Controller common Registers
> +//
> +#define V_SATA_CFG_SUB_CLASS_CODE_AHCI 0x06
> +#define V_SATA_CFG_SUB_CLASS_CODE_RAID 0x04
> +#define R_SATA_CFG_AHCI_BAR 0x24
> +#define B_SATA_CFG_AHCI_BAR_BA 0xFFFFF800
> +#define V_SATA_CFG_AHCI_BAR_LENGTH 0x800
> +#define N_SATA_CFG_AHCI_BAR_ALIGNMENT 11
> +#define V_SATA_CFG_AHCI_BAR_LENGTH_512K 0x80000
> +#define N_SATA_CFG_AHCI_BAR_ALIGNMENT_512K 19
> +#define B_SATA_CFG_AHCI_BAR_PF BIT3
> +#define B_SATA_CFG_AHCI_BAR_TP (BIT2 | BIT1)
> +#define B_SATA_CFG_AHCI_BAR_RTE BIT0
> +#define R_SATA_CFG_PID 0x70
> +#define B_SATA_CFG_PID_NEXT 0xFF00
> +#define V_SATA_CFG_PID_NEXT_0 0xB000
> +#define V_SATA_CFG_PID_NEXT_1 0xA800
> +#define B_SATA_CFG_PID_CID 0x00FF
> +#define R_SATA_CFG_PC 0x72
> +#define S_SATA_CFG_PC 2
> +#define B_SATA_CFG_PC_PME (BIT15 | BIT14 | BIT13 | BIT12 |
> BIT11)
> +#define V_SATA_CFG_PC_PME_0 0x0000
> +#define V_SATA_CFG_PC_PME_1 0x4000
> +#define B_SATA_CFG_PC_D2_SUP BIT10
> +#define B_SATA_CFG_PC_D1_SUP BIT9
> +#define B_SATA_CFG_PC_AUX_CUR (BIT8 | BIT7 | BIT6)
> +#define B_SATA_CFG_PC_DSI BIT5
> +#define B_SATA_CFG_PC_PME_CLK BIT3
> +#define B_SATA_CFG_PC_VER (BIT2 | BIT1 | BIT0)
> +#define R_SATA_CFG_PMCS 0x74
> +#define B_SATA_CFG_PMCS_PMES BIT15
> +#define B_SATA_CFG_PMCS_PMEE BIT8
> +#define B_SATA_CFG_PMCS_NSFRST BIT3
> +#define V_SATA_CFG_PMCS_NSFRST_1 0x01
> +#define V_SATA_CFG_PMCS_NSFRST_0 0x00
> +#define B_SATA_CFG_PMCS_PS (BIT1 | BIT0)
> +#define V_SATA_CFG_PMCS_PS_3 0x03
> +#define V_SATA_CFG_PMCS_PS_0 0x00
> +#define R_SATA_CFG_MID 0x80
> +#define B_SATA_CFG_MID_NEXT 0xFF00
> +#define B_SATA_CFG_MID_CID 0x00FF
> +#define R_SATA_CFG_MC 0x82
> +#define B_SATA_CFG_MC_C64 BIT7
> +#define B_SATA_CFG_MC_MME (BIT6 | BIT5 | BIT4)
> +#define V_SATA_CFG_MC_MME_4 0x04
> +#define V_SATA_CFG_MC_MME_2 0x02
> +#define V_SATA_CFG_MC_MME_1 0x01
> +#define V_SATA_CFG_MC_MME_0 0x00
> +#define B_SATA_CFG_MC_MMC (BIT3 | BIT2 | BIT1)
> +#define V_SATA_CFG_MC_MMC_4 0x04
> +#define V_SATA_CFG_MC_MMC_0 0x00
> +#define B_SATA_CFG_MC_MSIE BIT0
> +#define V_SATA_CFG_MC_MSIE_1 0x01
> +#define V_SATA_CFG_MC_MSIE_0 0x00
> +#define R_SATA_CFG_MA 0x84
> +#define B_SATA_CFG_MA 0xFFFFFFFC
> +#define R_SATA_CFG_MD 0x88
> +#define B_SATA_CFG_MD_MSIMD 0xFFFF
> +
> +#define R_SATA_CFG_MAP 0x90
> +#define B_SATA_CFG_MAP_PCD 0xFF
> +#define N_SATA_CFG_MAP_SPD 16
> +#define B_SATA_CFG_MAP_SPD7 BIT23
> +#define B_SATA_CFG_MAP_SPD6 BIT22
> +#define B_SATA_CFG_MAP_SPD5 BIT21
> +#define B_SATA_CFG_MAP_SPD4 BIT20
> +#define B_SATA_CFG_MAP_SPD3 BIT19
> +#define B_SATA_CFG_MAP_SPD2 BIT18
> +#define B_SATA_CFG_MAP_SPD1 BIT17
> +#define B_SATA_CFG_MAP_SPD0 BIT16
> +#define B_SATA_CFG_MAP_PORT7_PCD BIT7
> +#define B_SATA_CFG_MAP_PORT6_PCD BIT6
> +#define B_SATA_CFG_MAP_PORT5_PCD BIT5
> +#define B_SATA_CFG_MAP_PORT4_PCD BIT4
> +#define B_SATA_CFG_MAP_PORT3_PCD BIT3
> +#define B_SATA_CFG_MAP_PORT2_PCD BIT2
> +#define B_SATA_CFG_MAP_PORT1_PCD BIT1
> +#define B_SATA_CFG_MAP_PORT0_PCD BIT0
> +#define R_SATA_CFG_PCS 0x94
> +#define B_SATA_CFG_PCS_P7P BIT23
> +#define B_SATA_CFG_PCS_P6P BIT22
> +#define B_SATA_CFG_PCS_P5P BIT21
> +#define B_SATA_CFG_PCS_P4P BIT20
> +#define B_SATA_CFG_PCS_P3P BIT19
> +#define B_SATA_CFG_PCS_P2P BIT18
> +#define B_SATA_CFG_PCS_P1P BIT17
> +#define B_SATA_CFG_PCS_P0P BIT16
> +#define B_SATA_CFG_PCS_P7E BIT7
> +#define B_SATA_CFG_PCS_P6E BIT6
> +#define B_SATA_CFG_PCS_P5E BIT5
> +#define B_SATA_CFG_PCS_P4E BIT4
> +#define B_SATA_CFG_PCS_P3E BIT3
> +#define B_SATA_CFG_PCS_P2E BIT2
> +#define B_SATA_CFG_PCS_P1E BIT1
> +#define B_SATA_CFG_PCS_P0E BIT0
> +#define R_SATA_CFG_SATAGC 0x9C
> +#define B_SATA_CFG_SATAGC_SMS_MASK BIT16
> +#define N_SATA_CFG_SATAGC_SMS_MASK 16
> +#define V_SATA_CFG_SATAGC_SMS_AHCI 0x0
> +#define V_SATA_CFG_SATAGC_SMS_RAID 0x1
> +#define B_SATA_CFG_SATAGC_AIE BIT7
> +#define B_SATA_CFG_SATAGC_AIES BIT6
> +#define B_SATA_CFG_SATAGC_MSS (BIT4 | BIT3)
> +#define V_SATA_CFG_SATAGC_MSS_8K 0x2
> +#define N_SATA_CFG_SATAGC_MSS 3
> +#define B_SATA_CFG_SATAGC_ASSEL (BIT2 | BIT1 | BIT0)
> +
> +#define V_SATA_CFG_SATAGC_ASSEL_2K 0x0
> +#define V_SATA_CFG_SATAGC_ASSEL_16K 0x1
> +#define V_SATA_CFG_SATAGC_ASSEL_32K 0x2
> +#define V_SATA_CFG_SATAGC_ASSEL_64K 0x3
> +#define V_SATA_CFG_SATAGC_ASSEL_128K 0x4
> +#define V_SATA_CFG_SATAGC_ASSEL_256K 0x5
> +#define V_SATA_CFG_SATAGC_ASSEL_512K 0x6
> +
> +#define R_SATA_CFG_SIRI 0xA0
> +#define R_SATA_CFG_STRD 0xA4
> +#define R_SATA_CFG_SIR_0C 0x0C
> +#define R_SATA_CFG_SIR_50 0x50
> +#define R_SATA_CFG_SIR_54 0x54
> +#define R_SATA_CFG_SIR_58 0x58
> +#define R_SATA_CFG_SIR_5C 0x5C
> +#define R_SATA_CFG_SIR_60 0x60
> +#define R_SATA_CFG_SIR_64 0x64
> +#define R_SATA_CFG_SIR_68 0x68
> +#define R_SATA_CFG_SIR_6C 0x6C
> +#define R_SATA_CFG_SIR_70 0x70
> +#define R_SATA_CFG_SIR_80 0x80
> +#define R_SATA_CFG_SIR_84 0x84
> +#define R_SATA_CFG_SIR_8C 0x8C
> +#define R_SATA_CFG_SIR_90 0x90
> +#define R_SATA_CFG_SIR_98 0x98
> +#define R_SATA_CFG_SIR_9C 0x9C
> +#define R_SATA_CFG_SIR_A0 0xA0
> +#define R_SATA_CFG_SIR_A4 0xA4
> +#define R_SATA_CFG_SIR_A8 0xA8
> +#define R_SATA_CFG_SIR_C8 0xC8
> +#define R_SATA_CFG_SIR_CC 0xCC
> +#define R_SATA_CFG_SIR_D0 0xD0
> +#define R_SATA_CFG_SIR_D4 0xD4
> +#define B_SATA_CFG_STRD_DTA 0xFFFFFFFF
> +#define R_SATA_CFG_CR0 0xA8
> +#define B_SATA_CFG_CR0_MAJREV 0x00F00000
> +#define B_SATA_CFG_CR0_MINREV 0x000F0000
> +#define B_SATA_CFG_CR0_NEXT 0x0000FF00
> +#define B_SATA_CFG_CR0_CAP 0x000000FF
> +#define R_SATA_CFG_CR1 0xAC
> +#define B_SATA_CFG_CR1_BAROFST 0xFFF0
> +#define B_SATA_CFG_CR1_BARLOC 0x000F
> +#define R_SATA_CFG_FLR_CID 0xB0
> +#define B_SATA_CFG_FLR_CID_NEXT 0xFF00
> +#define B_SATA_CFG_FLR_CID 0x00FF
> +#define V_SATA_CFG_FLR_CID_1 0x0009
> +#define V_SATA_CFG_FLR_CID_0 0x0013
> +#define R_SATA_CFG_FLR_CLV 0xB2
> +#define B_SATA_CFG_FLR_CLV_FLRC_FLRCSSEL_0 BIT9
> +#define B_SATA_CFG_FLR_CLV_TXPC_FLRCSSEL_0 BIT8
> +#define B_SATA_CFG_FLR_CLV_VSCID_FLRCSSEL_0 0x00FF
> +#define B_SATA_CFG_FLR_CLV_VSCID_FLRCSSEL_1 0x00FF
> +#define V_SATA_CFG_FLR_CLV_VSCID_FLRCSSEL 0x0006
> +#define R_SATA_CFG_FLRC 0xB4
> +#define B_SATA_CFG_FLRC_TXP BIT8
> +#define B_SATA_CFG_FLRC_INITFLR BIT0
> +#define R_SATA_CFG_SP 0xC0
> +#define B_SATA_CFG_SP 0xFFFFFFFF
> +#define R_SATA_CFG_MXID 0xD0
> +#define N_SATA_CFG_MXID_NEXT 8
> +
> +#define R_SATA_CFG_BFCS 0xE0
> +#define B_SATA_CFG_BFCS_P7BFI BIT17
> +#define B_SATA_CFG_BFCS_P6BFI BIT16
> +#define B_SATA_CFG_BFCS_P5BFI BIT15
> +#define B_SATA_CFG_BFCS_P4BFI BIT14
> +#define B_SATA_CFG_BFCS_P3BFI BIT13
> +#define B_SATA_CFG_BFCS_P2BFI BIT12
> +#define B_SATA_CFG_BFCS_P2BFS BIT11
> +#define B_SATA_CFG_BFCS_P2BFF BIT10
> +#define B_SATA_CFG_BFCS_P1BFI BIT9
> +#define B_SATA_CFG_BFCS_P0BFI BIT8
> +#define B_SATA_CFG_BFCS_BIST_FIS_T BIT7
> +#define B_SATA_CFG_BFCS_BIST_FIS_A BIT6
> +#define B_SATA_CFG_BFCS_BIST_FIS_S BIT5
> +#define B_SATA_CFG_BFCS_BIST_FIS_L BIT4
> +#define B_SATA_CFG_BFCS_BIST_FIS_F BIT3
> +#define B_SATA_CFG_BFCS_BIST_FIS_P BIT2
> +#define R_SATA_CFG_BFTD1 0xE4
> +#define B_SATA_CFG_BFTD1 0xFFFFFFFF
> +#define R_SATA_CFG_BFTD2 0xE8
> +#define B_SATA_CFG_BFTD2 0xFFFFFFFF
> +
> +#define R_SATA_CFG_VS_CAP 0xA4
> +#define B_SATA_CFG_VS_CAP_NRMBE BIT0 ///<
> NVM Remap Memory BAR Enable
> +#define B_SATA_CFG_VS_CAP_MSL 0x1FFE ///<
> Memory Space Limit
> +#define N_SATA_CFG_VS_CAP_MSL 1
> +#define V_SATA_CFG_VS_CAP_MSL 0x1EF ///<
> Memory Space Limit Field Value
> +#define B_SATA_CFG_VS_CAP_NRMO 0xFFF0000
> ///< NVM Remapped Memory Offset
> +#define N_SATA_CFG_VS_CAP_NRMO 16
> +#define V_SATA_CFG_VS_CAP_NRMO 0x10 ///<
> NVM Remapped Memory Offset Field Value
> +
> +//
> +// RST PCIe Storage Remapping Registers
> +//
> +#define R_SATA_CFG_RST_PCIE_STORAGE_RCR 0x800
> ///< Remap Capability Register
> +#define B_SATA_CFG_RST_PCIE_STORAGE_RCR_NRS
> (BIT2|BIT1|BIT0) ///< Number of Remapping Supported
> +#define B_SATA_CFG_RST_PCIE_STORAGE_RCR_NRS_CR1 BIT0
> ///< Number of Remapping Supported (RST PCIe Storage Cycle Router #1)
> +#define R_SATA_CFG_RST_PCIE_STORAGE_SPR 0x80C
> ///< Scratch Pad Register
> +#define R_SATA_CFG_RST_PCIE_STORAGE_CR1_DCC 0x880
> ///< CR#1 Device Class Code
> +#define N_SATA_CFG_RST_PCIE_STORAGE_CR1_DCC_SCC 8
> +#define N_SATA_CFG_RST_PCIE_STORAGE_CR1_DCC_BCC 16
> +#define B_SATA_CFG_RST_PCIE_STORAGE_CR1_DCC_DT BIT31
> ///< Device Type
> +#define V_SATA_CFG_RST_PCIE_STORAGE_REMAP_CONFIG_CR 0x80
> ///< Remapped Configuration for RST PCIe Storage Cycle Router #n
> +#define V_SATA_CFG_RST_PCIE_STORAGE_REMAP_RP_OFFSET 0x100
> ///< Remapped Root Port Offset Value
> +#define R_SATA_CFG_RST_PCIE_STORAGE_CCFG 0x1D0
> ///< Port Configuration Register
> +//
> +// AHCI BAR Area related Registers
> +//
> +#define R_SATA_MEM_AHCI_CAP 0x0
> +#define B_SATA_MEM_AHCI_CAP_S64A BIT31
> +#define B_SATA_MEM_AHCI_CAP_SCQA BIT30
> +#define B_SATA_MEM_AHCI_CAP_SSNTF BIT29
> +#define B_SATA_MEM_AHCI_CAP_SMPS BIT28 ///< Supports
> Interlock Switch
> +#define B_SATA_MEM_AHCI_CAP_SSS BIT27 ///< Supports Stagger
> Spin-up
> +#define B_SATA_MEM_AHCI_CAP_SALP BIT26
> +#define B_SATA_MEM_AHCI_CAP_SAL BIT25
> +#define B_SATA_MEM_AHCI_CAP_SCLO BIT24 ///< Supports
> Command List Override
> +#define B_SATA_MEM_AHCI_CAP_ISS_MASK (BIT23 | BIT22 | BIT21 |
> BIT20)
> +#define N_SATA_MEM_AHCI_CAP_ISS 20 ///< Interface Speed
> Support
> +#define V_SATA_MEM_AHCI_CAP_ISS_1_5_G 0x01
> +#define V_SATA_MEM_AHCI_CAP_ISS_3_0_G 0x02
> +#define V_SATA_MEM_AHCI_CAP_ISS_6_0_G 0x03
> +#define B_SATA_MEM_AHCI_CAP_SNZO BIT19
> +#define B_SATA_MEM_AHCI_CAP_SAM BIT18
> +#define B_SATA_MEM_AHCI_CAP_SPM BIT17 ///< Supports Port
> Multiplier
> +#define B_SATA_MEM_AHCI_CAP_PMD BIT15 ///< PIO Multiple DRQ
> Block
> +#define B_SATA_MEM_AHCI_CAP_SSC BIT14
> +#define B_SATA_MEM_AHCI_CAP_PSC BIT13
> +#define B_SATA_MEM_AHCI_CAP_NCS 0x1F00
> +#define B_SATA_MEM_AHCI_CAP_CCCS BIT7
> +#define B_SATA_MEM_AHCI_CAP_EMS BIT6
> +#define B_SATA_MEM_AHCI_CAP_SXS BIT5 ///< External SATA is
> supported
> +#define B_SATA_MEM_AHCI_CAP_NPS 0x001F
> +
> +#define R_SATA_MEM_AHCI_GHC 0x04
> +#define B_SATA_MEM_AHCI_GHC_AE BIT31
> +#define B_SATA_MEM_AHCI_GHC_MRSM BIT2
> +#define B_SATA_MEM_AHCI_GHC_IE BIT1
> +#define B_SATA_MEM_AHCI_GHC_HR BIT0
> +
> +#define R_SATA_MEM_AHCI_IS 0x08
> +#define B_SATA_MEM_AHCI_IS_PORT7 BIT7
> +#define B_SATA_MEM_AHCI_IS_PORT6 BIT6
> +#define B_SATA_MEM_AHCI_IS_PORT5 BIT5
> +#define B_SATA_MEM_AHCI_IS_PORT4 BIT4
> +#define B_SATA_MEM_AHCI_IS_PORT3 BIT3
> +#define B_SATA_MEM_AHCI_IS_PORT2 BIT2
> +#define B_SATA_MEM_AHCI_IS_PORT1 BIT1
> +#define B_SATA_MEM_AHCI_IS_PORT0 BIT0
> +#define R_SATA_MEM_AHCI_PI 0x0C
> +#define B_SATA_MEM_AHCI_PI_PORT_MASK 0xFF
> +#define B_SATA_MEM_PORT7_IMPLEMENTED BIT7
> +#define B_SATA_MEM_PORT6_IMPLEMENTED BIT6
> +#define B_SATA_MEM_PORT5_IMPLEMENTED BIT5
> +#define B_SATA_MEM_PORT4_IMPLEMENTED BIT4
> +#define B_SATA_MEM_PORT3_IMPLEMENTED BIT3
> +#define B_SATA_MEM_PORT2_IMPLEMENTED BIT2
> +#define B_SATA_MEM_PORT1_IMPLEMENTED BIT1
> +#define B_SATA_MEM_PORT0_IMPLEMENTED BIT0
> +#define R_SATA_MEM_AHCI_VS 0x10
> +#define B_SATA_MEM_AHCI_VS_MJR 0xFFFF0000
> +#define B_SATA_MEM_AHCI_VS_MNR 0x0000FFFF
> +#define R_SATA_MEM_AHCI_EM_LOC 0x1C
> +#define B_SATA_MEM_AHCI_EM_LOC_OFST 0xFFFF0000
> +#define B_SATA_MEM_AHCI_EM_LOC_SZ 0x0000FFFF
> +#define R_SATA_MEM_AHCI_EM_CTRL 0x20
> +#define B_SATA_MEM_AHCI_EM_CTRL_ATTR_ALHD BIT26
> +#define B_SATA_MEM_AHCI_EM_CTRL_ATTR_XMT BIT25
> +#define B_SATA_MEM_AHCI_EM_CTRL_ATTR_SMB BIT24
> +#define B_SATA_MEM_AHCI_EM_CTRL_SUPP_SGPIO BIT19
> +#define B_SATA_MEM_AHCI_EM_CTRL_SUPP_SES2 BIT18
> +#define B_SATA_MEM_AHCI_EM_CTRL_SUPP_SAFTE BIT17
> +#define B_SATA_MEM_AHCI_EM_CTRL_SUPP_LED BIT16
> +#define B_SATA_MEM_AHCI_EM_CTRL_RST BIT9
> +#define B_SATA_MEM_AHCI_EM_CTRL_CTL_TM BIT8
> +#define B_SATA_MEM_AHCI_EM_CTRL_STS_MR BIT0
> +#define R_SATA_MEM_AHCI_CAP2 0x24
> +#define B_SATA_MEM_AHCI_CAP2_DESO BIT5
> +#define B_SATA_MEM_AHCI_CAP2_SADM BIT4
> +#define B_SATA_MEM_AHCI_CAP2_SDS BIT3
> +#define B_SATA_MEM_AHCI_CAP2_APST BIT2 ///< Automatic Partial
> to Slumber Transitions
> +#define R_SATA_MEM_AHCI_VSP 0xA0
> +#define B_SATA_MEM_AHCI_VSP_SLPD BIT0
> +#define R_SATA_MEM_AHCI_SFM 0xC8 ///< RST Feature
> Capabilities
> +#define B_SATA_MEM_AHCI_SFM_LEGACY BIT12
> +#define B_SATA_MEM_AHCI_SFM_OUD (BIT11 | BIT10)
> +#define N_SATA_MEM_AHCI_SFM_OUD 10
> +#define B_SATA_MEM_AHCI_SFM_SEREQ BIT9
> +#define B_SATA_MEM_AHCI_SFM_IROES BIT8
> +#define B_SATA_MEM_AHCI_SFM_LEDL BIT7
> +#define B_SATA_MEM_AHCI_SFM_HDDLK BIT6
> +#define B_SATA_MEM_AHCI_SFM_IRSTOROM BIT5
> +#define B_SATA_MEM_AHCI_SFM_RSTE BIT4
> +#define B_SATA_MEM_AHCI_SFM_R5E BIT3
> +#define B_SATA_MEM_AHCI_SFM_R10E BIT2
> +#define B_SATA_MEM_AHCI_SFM_R1E BIT1
> +#define B_SATA_MEM_AHCI_SFM_R0E BIT0
> +#define B_SATA_MEM_AHCI_SFM_LOWBYTES 0x1FF
> +#define R_SATA_MEM_AHCI_P0CLB 0x100
> +#define R_SATA_MEM_AHCI_P1CLB 0x180
> +#define R_SATA_MEM_AHCI_P2CLB 0x200
> +#define R_SATA_MEM_AHCI_P3CLB 0x280
> +#define R_SATA_MEM_AHCI_P4CLB 0x300
> +#define R_SATA_MEM_AHCI_P5CLB 0x380
> +#define R_SATA_MEM_AHCI_P6CLB 0x400
> +#define R_SATA_MEM_AHCI_P7CLB 0x480
> +#define B_SATA_MEM_AHCI_PXCLB 0xFFFFFC00
> +#define R_SATA_MEM_AHCI_P0CLBU 0x104
> +#define R_SATA_MEM_AHCI_P1CLBU 0x184
> +#define R_SATA_MEM_AHCI_P2CLBU 0x204
> +#define R_SATA_MEM_AHCI_P3CLBU 0x284
> +#define R_SATA_MEM_AHCI_P4CLBU 0x304
> +#define R_SATA_MEM_AHCI_P5CLBU 0x384
> +#define R_SATA_MEM_AHCI_P6CLBU 0x404
> +#define R_SATA_MEM_AHCI_P7CLBU 0x484
> +#define B_SATA_MEM_AHCI_PXCLBU 0xFFFFFFFF
> +#define R_SATA_MEM_AHCI_P0FB 0x108
> +#define R_SATA_MEM_AHCI_P1FB 0x188
> +#define R_SATA_MEM_AHCI_P2FB 0x208
> +#define R_SATA_MEM_AHCI_P3FB 0x288
> +#define R_SATA_MEM_AHCI_P4FB 0x308
> +#define R_SATA_MEM_AHCI_P5FB 0x388
> +#define R_SATA_MEM_AHCI_P6FB 0x408
> +#define R_SATA_MEM_AHCI_P7FB 0x488
> +#define B_SATA_MEM_AHCI_PXFB 0xFFFFFF00
> +#define R_SATA_MEM_AHCI_P0FBU 0x10C
> +#define R_SATA_MEM_AHCI_P1FBU 0x18C
> +#define R_SATA_MEM_AHCI_P2FBU 0x20C
> +#define R_SATA_MEM_AHCI_P3FBU 0x28C
> +#define R_SATA_MEM_AHCI_P4FBU 0x30C
> +#define R_SATA_MEM_AHCI_P5FBU 0x38C
> +#define R_SATA_MEM_AHCI_P6FBU 0x40C
> +#define R_SATA_MEM_AHCI_P7FBU 0x48C
> +#define B_SATA_MEM_AHCI_PXFBU 0xFFFFFFFF
> +#define R_SATA_MEM_AHCI_P0IS 0x110
> +#define R_SATA_MEM_AHCI_P1IS 0x190
> +#define R_SATA_MEM_AHCI_P2IS 0x210
> +#define R_SATA_MEM_AHCI_P3IS 0x290
> +#define R_SATA_MEM_AHCI_P4IS 0x310
> +#define R_SATA_MEM_AHCI_P5IS 0x390
> +#define R_SATA_MEM_AHCI_P6IS 0x410
> +#define R_SATA_MEM_AHCI_P7IS 0x490
> +#define B_SATA_MEM_AHCI_PXIS_CPDS BIT31
> +#define B_SATA_MEM_AHCI_PXIS_TFES BIT30
> +#define B_SATA_MEM_AHCI_PXIS_HBFS BIT29
> +#define B_SATA_MEM_AHCI_PXIS_HBDS BIT28
> +#define B_SATA_MEM_AHCI_PXIS_IFS BIT27
> +#define B_SATA_MEM_AHCI_PXIS_INFS BIT26
> +#define B_SATA_MEM_AHCI_PXIS_OFS BIT24
> +#define B_SATA_MEM_AHCI_PXIS_IPMS BIT23
> +#define B_SATA_MEM_AHCI_PXIS_PRCS BIT22
> +#define B_SATA_MEM_AHCI_PXIS_DIS BIT7
> +#define B_SATA_MEM_AHCI_PXIS_PCS BIT6
> +#define B_SATA_MEM_AHCI_PXIS_DPS BIT5
> +#define B_SATA_MEM_AHCI_PXIS_UFS BIT4
> +#define B_SATA_MEM_AHCI_PXIS_SDBS BIT3
> +#define B_SATA_MEM_AHCI_PXIS_DSS BIT2
> +#define B_SATA_MEM_AHCI_PXIS_PSS BIT1
> +#define B_SATA_MEM_AHCI_PXIS_DHRS BIT0
> +#define R_SATA_MEM_AHCI_P0IE 0x114
> +#define R_SATA_MEM_AHCI_P1IE 0x194
> +#define R_SATA_MEM_AHCI_P2IE 0x214
> +#define R_SATA_MEM_AHCI_P3IE 0x294
> +#define R_SATA_MEM_AHCI_P4IE 0x314
> +#define R_SATA_MEM_AHCI_P5IE 0x394
> +#define R_SATA_MEM_AHCI_P6IE 0x414
> +#define R_SATA_MEM_AHCI_P7IE 0x494
> +#define B_SATA_MEM_AHCI_PXIE_CPDE BIT31
> +#define B_SATA_MEM_AHCI_PXIE_TFEE BIT30
> +#define B_SATA_MEM_AHCI_PXIE_HBFE BIT29
> +#define B_SATA_MEM_AHCI_PXIE_HBDE BIT28
> +#define B_SATA_MEM_AHCI_PXIE_IFE BIT27
> +#define B_SATA_MEM_AHCI_PXIE_INFE BIT26
> +#define B_SATA_MEM_AHCI_PXIE_OFE BIT24
> +#define B_SATA_MEM_AHCI_PXIE_IPME BIT23
> +#define B_SATA_MEM_AHCI_PXIE_PRCE BIT22
> +#define B_SATA_MEM_AHCI_PXIE_DIE BIT7
> +#define B_SATA_MEM_AHCI_PXIE_PCE BIT6
> +#define B_SATA_MEM_AHCI_PXIE_DPE BIT5
> +#define B_SATA_MEM_AHCI_PXIE_UFIE BIT4
> +#define B_SATA_MEM_AHCI_PXIE_SDBE BIT3
> +#define B_SATA_MEM_AHCI_PXIE_DSE BIT2
> +#define B_SATA_MEM_AHCI_PXIE_PSE BIT1
> +#define B_SATA_MEM_AHCI_PXIE_DHRE BIT0
> +#define R_SATA_MEM_AHCI_P0CMD 0x118
> +#define R_SATA_MEM_AHCI_P1CMD 0x198
> +#define R_SATA_MEM_AHCI_P2CMD 0x218
> +#define R_SATA_MEM_AHCI_P3CMD 0x298
> +#define R_SATA_MEM_AHCI_P4CMD 0x318
> +#define R_SATA_MEM_AHCI_P5CMD 0x398
> +#define R_SATA_MEM_AHCI_P6CMD 0x418
> +#define R_SATA_MEM_AHCI_P7CMD 0x498
> +#define B_SATA_MEM_AHCI_PxCMD_ESP BIT21 ///< Used with an
> external SATA device
> +#define B_SATA_MEM_AHCI_PxCMD_MPSP BIT19 ///< Mechanical
> Switch Attached to Port
> +#define B_SATA_MEM_AHCI_PxCMD_HPCP BIT18 ///< Hotplug
> capable
> +#define B_SATA_MEM_AHCI_PxCMD_CR BIT15
> +#define B_SATA_MEM_AHCI_PxCMD_FR BIT14
> +#define B_SATA_MEM_AHCI_PxCMD_ISS BIT13
> +#define B_SATA_MEM_AHCI_PxCMD_CCS 0x00001F00
> +#define B_SATA_MEM_AHCI_PxCMD_FRE BIT4
> +#define B_SATA_MEM_AHCI_PxCMD_CLO BIT3
> +#define B_SATA_MEM_AHCI_PxCMD_POD BIT2
> +#define B_SATA_MEM_AHCI_PxCMD_SUD BIT1
> +#define B_SATA_MEM_AHCI_PxCMD_ST BIT0
> +#define R_SATA_MEM_AHCI_P0TFD 0x120
> +#define R_SATA_MEM_AHCI_P1TFD 0x1A0
> +#define R_SATA_MEM_AHCI_P2TFD 0x220
> +#define R_SATA_MEM_AHCI_P3TFD 0x2A0
> +#define R_SATA_MEM_AHCI_P4TFD 0x320
> +#define R_SATA_MEM_AHCI_P5TFD 0x3A0
> +#define R_SATA_MEM_AHCI_P6TFD 0x420
> +#define B_SATA_MEM_AHCI_PXTFD_ERR 0x0000FF00
> +#define B_SATA_MEM_AHCI_PXTFD_STS 0x000000FF
> +#define R_SATA_MEM_AHCI_P0SIG 0x124
> +#define R_SATA_MEM_AHCI_P1SIG 0x1A4
> +#define R_SATA_MEM_AHCI_P2SIG 0x224
> +#define R_SATA_MEM_AHCI_P3SIG 0x2A4
> +#define R_SATA_MEM_AHCI_P4SIG 0x324
> +#define R_SATA_MEM_AHCI_P5SIG 0x3A4
> +#define R_SATA_MEM_AHCI_P6SIG 0x424
> +#define B_SATA_MEM_AHCI_PXSIG_LBA_HR 0xFF000000
> +#define B_SATA_MEM_AHCI_PXSIG_LBA_MR 0x00FF0000
> +#define B_SATA_MEM_AHCI_PXSIG_LBA_LR 0x0000FF00
> +#define B_SATA_MEM_AHCI_PXSIG_SCR 0x000000FF
> +#define R_SATA_MEM_AHCI_P0SSTS 0x128
> +#define R_SATA_MEM_AHCI_P1SSTS 0x1A8
> +#define R_SATA_MEM_AHCI_P2SSTS 0x228
> +#define R_SATA_MEM_AHCI_P3SSTS 0x2A8
> +#define R_SATA_MEM_AHCI_P4SSTS 0x328
> +#define R_SATA_MEM_AHCI_P5SSTS 0x3A8
> +#define R_SATA_MEM_AHCI_P6SSTS 0x428
> +#define B_SATA_MEM_AHCI_PXSSTS_IPM_0 0x00000000
> +#define B_SATA_MEM_AHCI_PXSSTS_IPM_1 0x00000100
> +#define B_SATA_MEM_AHCI_PXSSTS_IPM_2 0x00000200
> +#define B_SATA_MEM_AHCI_PXSSTS_IPM_6 0x00000600
> +#define B_SATA_MEM_AHCI_PXSSTS_SPD_0 0x00000000
> +#define B_SATA_MEM_AHCI_PXSSTS_SPD_1 0x00000010
> +#define B_SATA_MEM_AHCI_PXSSTS_SPD_2 0x00000020
> +#define B_SATA_MEM_AHCI_PXSSTS_SPD_3 0x00000030
> +#define B_SATA_MEM_AHCI_PXSSTS_DET_0 0x00000000
> +#define B_SATA_MEM_AHCI_PXSSTS_DET_1 0x00000001
> +#define B_SATA_MEM_AHCI_PXSSTS_DET_3 0x00000003
> +#define B_SATA_MEM_AHCI_PXSSTS_DET_4 0x00000004
> +#define R_SATA_MEM_AHCI_P0SCTL 0x12C
> +#define R_SATA_MEM_AHCI_P1SCTL 0x1AC
> +#define R_SATA_MEM_AHCI_P2SCTL 0x22C
> +#define R_SATA_MEM_AHCI_P3SCTL 0x2AC
> +#define R_SATA_MEM_AHCI_P4SCTL 0x32C
> +#define R_SATA_MEM_AHCI_P5SCTL 0x3AC
> +#define R_SATA_MEM_AHCI_P6SCTL 0x42C
> +#define B_SATA_MEM_AHCI_PXSCTL_IPM 0x00000F00
> +#define V_SATA_MEM_AHCI_PXSCTL_IPM_0 0x00000000
> +#define V_SATA_MEM_AHCI_PXSCTL_IPM_1 0x00000100
> +#define V_SATA_MEM_AHCI_PXSCTL_IPM_2 0x00000200
> +#define V_SATA_MEM_AHCI_PXSCTL_IPM_3 0x00000300
> +#define B_SATA_MEM_AHCI_PXSCTL_SPD 0x000000F0
> +#define V_SATA_MEM_AHCI_PXSCTL_SPD_0 0x00000000
> +#define V_SATA_MEM_AHCI_PXSCTL_SPD_1 0x00000010
> +#define V_SATA_MEM_AHCI_PXSCTL_SPD_2 0x00000020
> +#define V_SATA_MEM_AHCI_PXSCTL_SPD_3 0x00000030
> +#define B_SATA_MEM_AHCI_PXSCTL_DET 0x0000000F
> +#define V_SATA_MEM_AHCI_PXSCTL_DET_0 0x00000000
> +#define V_SATA_MEM_AHCI_PXSCTL_DET_1 0x00000001
> +#define V_SATA_MEM_AHCI_PXSCTL_DET_4 0x00000004
> +#define R_SATA_MEM_AHCI_P0SERR 0x130
> +#define R_SATA_MEM_AHCI_P1SERR 0x1B0
> +#define R_SATA_MEM_AHCI_P2SERR 0x230
> +#define R_SATA_MEM_AHCI_P3SERR 0x2B0
> +#define R_SATA_MEM_AHCI_P4SERR 0x330
> +#define R_SATA_MEM_AHCI_P5SERR 0x3B0
> +#define R_SATA_MEM_AHCI_P6SERR 0x430
> +#define B_SATA_MEM_AHCI_PXSERR_EXCHG BIT26
> +#define B_SATA_MEM_AHCI_PXSERR_UN_FIS_TYPE BIT25
> +#define B_SATA_MEM_AHCI_PXSERR_TRSTE_24 BIT24
> +#define B_SATA_MEM_AHCI_PXSERR_TRSTE_23 BIT23
> +#define B_SATA_MEM_AHCI_PXSERR_HANDSHAKE BIT22
> +#define B_SATA_MEM_AHCI_PXSERR_CRC_ERROR BIT21
> +#define B_SATA_MEM_AHCI_PXSERR_10B8B_DECERR BIT19
> +#define B_SATA_MEM_AHCI_PXSERR_COMM_WAKE BIT18
> +#define B_SATA_MEM_AHCI_PXSERR_PHY_ERROR BIT17
> +#define B_SATA_MEM_AHCI_PXSERR_PHY_RDY_CHG BIT16
> +#define B_SATA_MEM_AHCI_PXSERR_INTRNAL_ERR BIT11
> +#define B_SATA_MEM_AHCI_PXSERR_PROTOCOL_ERR BIT10
> +#define B_SATA_MEM_AHCI_PXSERR_PCDIE BIT9
> +#define B_SATA_MEM_AHCI_PXSERR_TDIE BIT8
> +#define B_SATA_MEM_AHCI_PXSERR_RCE BIT1
> +#define B_SATA_MEM_AHCI_PXSERR_RDIE BIT0
> +#define R_SATA_MEM_AHCI_P0SACT 0x134
> +#define R_SATA_MEM_AHCI_P1SACT 0x1B4
> +#define R_SATA_MEM_AHCI_P2SACT 0x234
> +#define R_SATA_MEM_AHCI_P3SACT 0x2B4
> +#define R_SATA_MEM_AHCI_P4SACT 0x334
> +#define R_SATA_MEM_AHCI_P5SACT 0x3B4
> +#define R_SATA_MEM_AHCI_P6SACT 0x434
> +#define B_SATA_MEM_AHCI_PXSACT_DS 0xFFFFFFFF
> +#define R_SATA_MEM_AHCI_P0CI 0x138
> +#define R_SATA_MEM_AHCI_P1CI 0x1B8
> +#define R_SATA_MEM_AHCI_P2CI 0x238
> +#define R_SATA_MEM_AHCI_P3CI 0x2B8
> +#define R_SATA_MEM_AHCI_P4CI 0x338
> +#define R_SATA_MEM_AHCI_P5CI 0x3B8
> +#define R_SATA_MEM_AHCI_P6CI 0x438
> +#define B_SATA_MEM_AHCI_PXCI 0xFFFFFFFF
> +
> +//
> +// SATA AHCI Device ID macros
> +//
> +#define IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) \
> + ( \
> + (DeviceId == V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_AHCI) || \
> + (DeviceId == V_CNL_PCH_H_SATA_CFG_DEVICE_ID_MH_AHCI) || \
> + (DeviceId == V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_OP_AHCI) \
> + )
> +
> +#define IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) \
> + ( \
> + (DeviceId == V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_AHCI) \
> + )
> +
> +#define IS_PCH_SATA_AHCI_DEVICE_ID(DeviceId) \
> + ( \
> + IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) || \
> + IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) \
> + )
> +
> +//
> +// SATA RAID Device ID macros
> +//
> +#define IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) \
> + ( \
> + (DeviceId == V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID) || \
> + (DeviceId == V_CNL_PCH_H_SATA_CFG_DEVICE_ID_MH_RAID) || \
> + (DeviceId == V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_PREM) || \
> + (DeviceId == V_CNL_PCH_H_SATA_CFG_DEVICE_ID_MH_RAID_PREM) ||
> \
> + (DeviceId == V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_IBC) || \
> + (DeviceId == V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_IBC_RST) ||
> \
> + (DeviceId == V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_IBC_2) || \
> + (DeviceId == V_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_ALTDIS) || \
> + (DeviceId == V_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_RSTE) \
> + )
> +
> +#define IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \
> + ( \
> + (DeviceId == V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_RAID) || \
> + (DeviceId == V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_RAID_PREM) || \
> + (DeviceId == V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_RAID_IBC) \
> + )
> +
> +#define IS_PCH_SATA_RAID_DEVICE_ID(DeviceId) \
> + ( \
> + IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) || \
> + IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \
> + )
> +
> +//
> +// Combined SATA IDE/AHCI/RAID Device ID macros
> +//
> +#define IS_PCH_H_SATA_DEVICE_ID(DeviceId) \
> + ( \
> + IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) || \
> + IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) \
> + )
> +
> +#define IS_PCH_LP_SATA_DEVICE_ID(DeviceId) \
> + ( \
> + IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) || \
> + IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \
> + )
> +#define IS_PCH_SATA_DEVICE_ID(DeviceId) \
> + ( \
> + IS_PCH_H_SATA_DEVICE_ID(DeviceId) || \
> + IS_PCH_LP_SATA_DEVICE_ID(DeviceId) \
> + )
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScs.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScs.h
> new file mode 100644
> index 0000000000..00e7881408
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScs.h
> @@ -0,0 +1,52 @@
> +/** @file
> + Register names for PCH Storage and Communication Subsystem
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_SCS_H_
> +#define _PCH_REGS_SCS_H_
> +
> +//
> +// SCS Devices proprietary PCI Config Space Registers
> +//
> +#define R_SCS_CFG_PCS 0x84 ///< PME
> Control Status
> +#define B_SCS_CFG_PCS_PMESTS BIT15 ///< PME
> Status
> +#define B_SCS_CFG_PCS_PMEEN BIT8 ///< PME
> Enable
> +#define B_SCS_CFG_PCS_NSS BIT3 ///< No Soft
> Reset
> +#define B_SCS_CFG_PCS_PS (BIT1 | BIT0) ///< Power
> State
> +#define B_SCS_CFG_PCS_PS_D3HOT (BIT1 | BIT0) ///<
> Power State: D3Hot State
> +#define R_SCS_CFG_PG_CONFIG 0xA2 ///< PG
> Config
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScsCnl.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScsCnl.h
> new file mode 100644
> index 0000000000..c18e1ef38c
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScsCnl.h
> @@ -0,0 +1,48 @@
> +/** @file
> + Project specific SCS register definitions.
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_SCS_CNL_H_
> +#define _PCH_REGS_SCS_CNL_H_
> +
> +//
> +// SCS SDCARD Controller PCI config
> +//
> +#define PCI_DEVICE_NUMBER_PCH_CNL_SCS_SDCARD 20
> +#define PCI_FUNCTION_NUMBER_PCH_CNL_SCS_SDCARD 5
> +
> +#endif
> +
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h
> new file mode 100644
> index 0000000000..449335b073
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h
> @@ -0,0 +1,232 @@
> +/** @file
> + Register names for PCH Serial IO Controllers
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_SERIAL_IO_
> +#define _PCH_REGS_SERIAL_IO_
> +
> +//
> +// Serial IO Controllers General PCI Configuration Registers
> +// registers accessed using PciD21FxRegBase + offset
> +//
> +#define R_SERIAL_IO_CFG_BAR0_LOW 0x10
> +#define B_SERIAL_IO_CFG_BAR0_LOW_BAR 0xFFFFF000
> +#define R_SERIAL_IO_CFG_BAR0_HIGH 0x14
> +#define R_SERIAL_IO_CFG_BAR1_LOW 0x18
> +#define B_SERIAL_IO_CFG_BAR1_LOW_BAR 0xFFFFF000
> +#define R_SERIAL_IO_CFG_BAR1_HIGH 0x1C
> +#define V_SERIAL_IO_CFG_BAR_SIZE (4 * 1024)
> +#define N_SERIAL_IO_CFG_BAR_ALIGNMENT 12
> +
> +#define R_SERIAL_IO_CFG_PME_CTRL_STS 0x84
> +#define B_SERIAL_IO_CFG_PME_CTRL_STS_PWR_ST (BIT1| BIT0)
> +
> +#define R_SERIAL_IO_CFG_D0I3MAXDEVPG 0xA0
> +#define B_SERIAL_IO_CFG_D0I3MAXDEVPG_PMCRE BIT16
> +#define B_SERIAL_IO_CFG_D0I3MAXDEVPG_I3E BIT17
> +#define B_SERIAL_IO_CFG_D0I3MAXDEVPG_PGE BIT18
> +
> +#define R_SERIAL_IO_CFG_INTERRUPTREG 0x3C
> +#define B_SERIAL_IO_CFG_INTERRUPTREG_INTLINE 0x000000FF
> +
> +//
> +// Serial IO Controllers MMIO Registers
> +// registers accessed : BAR0 + offset
> +//
> +#define R_SERIAL_IO_MEM_SSCR1 0x4
> +#define B_SERIAL_IO_MEM_SSCR1_IFS BIT16
> +
> +#define R_SERIAL_IO_MEM_PPR_CLK 0x200
> +#define B_SERIAL_IO_MEM_PPR_CLK_EN BIT0
> +#define B_SERIAL_IO_MEM_PPR_CLK_UPDATE BIT31
> +#define V_SERIAL_IO_MEM_PPR_CLK_M_DIV 0x30
> +#define V_SERIAL_IO_MEM_PPR_CLK_N_DIV 0xC35
> +
> +#define R_SERIAL_IO_MEM_PPR_RESETS 0x204
> +#define B_SERIAL_IO_MEM_PPR_RESETS_FUNC BIT0
> +#define B_SERIAL_IO_MEM_PPR_RESETS_APB BIT1
> +#define B_SERIAL_IO_MEM_PPR_RESETS_IDMA BIT2
> +
> +#define R_SERIAL_IO_MEM_ACTIVE_LTR 0x210
> +#define R_SERIAL_IO_MEM_IDLE_LTR 0x214
> +#define B_SERIAL_IO_MEM_LTR_SNOOP_VALUE 0x000003FF
> +#define B_SERIAL_IO_MEM_LTR_SNOOP_SCALE 0x00001C00
> +#define B_SERIAL_IO_MEM_LTR_SNOOP_REQUIREMENT BIT15
> +
> +#define R_SERIAL_IO_MEM_SPI_CS_CONTROL 0x224
> +#define B_SERIAL_IO_MEM_SPI_CS_CONTROL_STATE BIT1
> +#define B_SERIAL_IO_MEM_SPI_CS_CONTROL_MODE BIT0
> +
> +#define R_SERIAL_IO_MEM_REMAP_ADR_LOW 0x240
> +#define R_SERIAL_IO_MEM_REMAP_ADR_HIGH 0x244
> +
> +#define R_SERIAL_IO_MEM_I2C_SDA_HOLD 0x7C
> +#define V_SERIAL_IO_MEM_I2C_SDA_HOLD_VALUE 0x002C002C
> +
> +//
> +// I2C Controller
> +// Registers accessed through BAR0 + offset
> +//
> +#define R_IC_CON 0x00 // I2c Control
> +#define B_IC_MASTER_MODE BIT0
> +#define B_IC_RESTART_EN BIT5
> +#define B_IC_SLAVE_DISABLE BIT6
> +#define V_IC_SPEED_STANDARD 0x02
> +#define V_IC_SPEED_FAST 0x04
> +#define V_IC_SPEED_HIGH 0x06
> +
> +#define R_IC_TAR 0x04 // I2c Target Address
> +#define B_IC_TAR_10BITADDR_MASTER BIT12
> +
> +#define R_IC_DATA_CMD 0x10 // I2c Rx/Tx Data Buffer
> and Command
> +#define B_IC_CMD_READ BIT8 // 1 = read, 0 = write
> +#define B_IC_CMD_STOP BIT9 // 1 = STOP
> +#define B_IC_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
> +#define V_IC_WRITE_CMD_MASK 0xFF
> +
> +#define R_IC_SS_SCL_HCNT 0x14 // Standard Speed I2c Clock
> SCL High Count
> +#define R_IC_SS_SCL_LCNT 0x18 // Standard Speed I2c Clock
> SCL Low Count
> +#define R_IC_FS_SCL_HCNT 0x1C // Full Speed I2c Clock SCL
> High Count
> +#define R_IC_FS_SCL_LCNT 0x20 // Full Speed I2c Clock SCL
> Low Count
> +#define R_IC_HS_SCL_HCNT 0x24 // High Speed I2c Clock SCL
> High Count
> +#define R_IC_HS_SCL_LCNT 0x28 // High Speed I2c Clock SCL
> Low Count
> +#define R_IC_INTR_STAT 0x2C // I2c Inetrrupt Status
> +#define R_IC_INTR_MASK 0x30 // I2c Interrupt Mask
> +#define B_IC_INTR_GEN_CALL BIT11 // General call received
> +#define B_IC_INTR_START_DET BIT10
> +#define B_IC_INTR_STOP_DET BIT9
> +#define B_IC_INTR_ACTIVITY BIT8
> +#define B_IC_INTR_TX_ABRT BIT6 // Set on NACK
> +#define B_IC_INTR_TX_EMPTY BIT4
> +#define B_IC_INTR_TX_OVER BIT3
> +#define B_IC_INTR_RX_FULL BIT2 // Data bytes in RX FIFO
> over threshold
> +#define B_IC_INTR_RX_OVER BIT1
> +#define B_IC_INTR_RX_UNDER BIT0
> +#define R_IC_RAW_INTR_STAT ( 0x34) // I2c Raw Interrupt
> Status
> +#define R_IC_RX_TL ( 0x38) // I2c Receive FIFO Threshold
> +#define R_IC_TX_TL ( 0x3C) // I2c Transmit FIFO Threshold
> +#define R_IC_CLR_INTR ( 0x40) // Clear Combined and
> Individual Interrupts
> +#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER
> Interrupt
> +#define R_IC_CLR_RX_OVER ( 0x48) // Clear
> RX_OVERinterrupt
> +#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER
> interrupt
> +#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt
> +#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt
> +#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE
> interrupt
> +#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt
> +#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET
> interrupt
> +#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET
> interrupt
> +#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL
> interrupt
> +#define R_IC_ENABLE ( 0x6C) // I2c Enable
> +
> +#define R_IC_STATUS 0x70 // I2c Status
> +#define B_IC_STATUS_RFF BIT4 // RX FIFO is completely
> full
> +#define B_IC_STATUS_RFNE BIT3 // RX FIFO is not empty
> +#define B_IC_STATUS_TFE BIT2 // TX FIFO is completely
> empty
> +#define B_IC_STATUS_TFNF BIT1 // TX FIFO is not full
> +#define B_IC_STATUS_ACTIVITY BIT0 // Controller Activity
> Status.
> +
> +#define R_IC_TXFL R ( 0x74) // Transmit FIFO Level Register
> +#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register
> +#define R_IC_SDA_HOLD ( 0x7C)
> +#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2c Transmit Abort
> Status Register
> +#define B_IC_TX_ABRT_7B_ADDR_NACK BIT0 // NACK on 7-bit
> address
> +
> +#define R_IC_SDA_SETUP ( 0x94) // I2c SDA Setup Register
> +#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2c ACK General Call
> Register
> +#define R_IC_ENABLE_STATUS ( 0x9C) // I2c Enable Status
> Register
> +#define B_IC_EN BIT0 // I2c enable status
> +
> +#define R_IC_CLK_GATE ( 0xC0)
> +#define R_IC_COMP_PARAM ( 0xF4) // Component
> Parameter Register
> +#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID
> +#define R_IC_COMP_TYPE ( 0xFC) // Component Type
> +
> +//
> +// Bridge Private Configuration Registers
> +// accessed only through SB messaging. SB access = SerialIo IOSF2OCP Bridge
> Port ID + offset
> +//
> +#define R_SERIAL_IO_PCR_PMCTL 0x1D0
> +#define V_SERIAL_IO_PCR_PMCTL_PWR_GATING 0x3F
> +
> +#define R_SERIAL_IO_PCR_PCICFGCTRLx 0x200
> +#define V_SERIAL_IO_PCR_PCICFGCTRL_N_OFFS 0x04
> +#define R_SERIAL_IO_PCR_PCICFGCTRL1 0x200 //I2C0
> +#define R_SERIAL_IO_PCR_PCICFGCTRL2 0x204 //I2C1
> +#define R_SERIAL_IO_PCR_PCICFGCTRL3 0x208 //I2C2
> +#define R_SERIAL_IO_PCR_PCICFGCTRL4 0x20C //I2C3
> +#define R_SERIAL_IO_PCR_PCICFGCTRL5 0x210 //I2C4
> +#define R_SERIAL_IO_PCR_PCICFGCTRL6 0x214 //I2C5
> +#define R_SERIAL_IO_PCR_PCICFGCTRL9 0x218 //UA00
> +#define R_SERIAL_IO_PCR_PCICFGCTRL10 0x21C //UA01
> +#define R_SERIAL_IO_PCR_PCICFGCTRL11 0x220 //UA02
> +#define R_SERIAL_IO_PCR_PCICFGCTRL13 0x224 //SPI0
> +#define R_SERIAL_IO_PCR_PCICFGCTRL14 0x228 //SPI1
> +
> +#define B_SERIAL_IO_PCR_PCICFGCTRL_PCI_CFG_DIS BIT0
> +#define B_SERIAL_IO_PCR_PCICFGCTRL_ACPI_INTR_EN BIT1
> +#define B_SERIAL_IO_PCR_PCICFGCTRL_BAR1_DIS BIT7
> +#define B_SERIAL_IO_PCR_PCICFGCTRL_INT_PIN (BIT11 | BIT10 | BIT9
> | BIT8)
> +#define N_SERIAL_IO_PCR_PCICFGCTRL_INT_PIN 8
> +#define V_SERIAL_IO_PCR_PCICFGCTRL_INTA 0x01
> +#define V_SERIAL_IO_PCR_PCICFGCTRL_INTB 0x02
> +#define V_SERIAL_IO_PCR_PCICFGCTRL_INTC 0x03
> +#define V_SERIAL_IO_PCR_PCICFGCTRL_INTD 0x04
> +#define B_SERIAL_IO_PCR_PCICFGCTRL_ACPI_IRQ 0x000FF000
> +#define N_SERIAL_IO_PCR_PCICFGCTRL_ACPI_IRQ 12
> +#define B_SERIAL_IO_PCR_PCICFGCTRL_PCI_IRQ 0x0FF00000
> +#define N_SERIAL_IO_PCR_PCICFGCTRL_PCI_IRQ 20
> +
> +#define R_SERIAL_IO_PCR_GPPRVRW2 0x604
> +#define B_SERIAL_IO_PCR_GPPRVRW2_PGCB_FRC_CLK_CP_EN BIT1
> +#define B_SERIAL_IO_PCR_GPPRVRW2_CDC_SIDE_CFG_CG_EN BIT5
> +#define B_SERIAL_IO_PCR_GPPRVRW2_CDC_SIDE_CFG_CLKREQ_CTL_EN
> BIT11
> +#define V_SERIAL_IO_PCR_GPPRVRW2_CLK_GATING
> (B_SERIAL_IO_PCR_GPPRVRW2_PGCB_FRC_CLK_CP_EN |
> B_SERIAL_IO_PCR_GPPRVRW2_CDC_SIDE_CFG_CG_EN |
> B_SERIAL_IO_PCR_GPPRVRW2_CDC_SIDE_CFG_CLKREQ_CTL_EN)
> +
> +
> +#define R_SERIAL_IO_PCR_GPPRVRW7 0x618
> +#define B_SERIAL_IO_PCR_GPPRVRW7_UART0_BYTE_ADDR_EN BIT0
> +#define B_SERIAL_IO_PCR_GPPRVRW7_UART1_BYTE_ADDR_EN BIT1
> +#define B_SERIAL_IO_PCR_GPPRVRW7_UART2_BYTE_ADDR_EN BIT2
> +
> +//
> +// Number of pins used by SerialIo controllers
> +//
> +#define PCH_SERIAL_IO_PINS_PER_I2C_CONTROLLER 2
> +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4
> +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2
> +#define PCH_SERIAL_IO_PINS_PER_SPI_CONTROLLER 4
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSerialIoCnl
> .h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSerialIoCn
> l.h
> new file mode 100644
> index 0000000000..62b859dc99
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSerialIoCn
> l.h
> @@ -0,0 +1,138 @@
> +/** @file
> + Device IDs for PCH Serial IO Controllers for PCH
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_SERIAL_IO_CNL_
> +#define _PCH_REGS_SERIAL_IO_CNL_
> +
> +//
> +// Serial IO I2C0 Controller Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0 21
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0 0
> +
> +#define V_CNL_PCH_LP_SERIAL_IO_CFG_I2C0_DEVICE_ID 0x9DE8
> +#define V_CNL_PCH_H_SERIAL_IO_CFG_I2C0_DEVICE_ID 0xA368
> +
> +//
> +// Serial IO I2C1 Controller Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1 21
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1 1
> +
> +#define V_CNL_PCH_LP_SERIAL_IO_CFG_I2C1_DEVICE_ID 0x9DE9
> +#define V_CNL_PCH_H_SERIAL_IO_CFG_I2C1_DEVICE_ID 0xA369
> +
> +//
> +// Serial IO I2C2 Controller Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2 21
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2 2
> +
> +#define V_CNL_PCH_LP_SERIAL_IO_CFG_I2C2_DEVICE_ID 0x9DEA
> +#define V_CNL_PCH_H_SERIAL_IO_CFG_I2C2_DEVICE_ID 0xA36A
> +
> +//
> +// Serial IO I2C3 Controller Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3 21
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3 3
> +
> +#define V_CNL_PCH_LP_SERIAL_IO_CFG_I2C3_DEVICE_ID 0x9DEB
> +#define V_CNL_PCH_H_SERIAL_IO_CFG_I2C3_DEVICE_ID 0xA36B
> +
> +//
> +// Serial IO I2C4 Controller Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4 25
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4 0
> +
> +#define V_CNL_PCH_LP_SERIAL_IO_CFG_I2C4_DEVICE_ID 0x9DC5
> +
> +//
> +// Serial IO I2C5 Controller Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5 25
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5 1
> +
> +#define V_CNL_PCH_LP_SERIAL_IO_CFG_I2C5_DEVICE_ID 0x9DC6
> +
> +//
> +// Serial IO SPI0 Controller Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0 30
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0 2
> +
> +#define V_CNL_PCH_LP_SERIAL_IO_CFG_SPI0_DEVICE_ID 0x9DAA
> +#define V_CNL_PCH_H_SERIAL_IO_CFG_SPI0_DEVICE_ID 0xA32A
> +
> +//
> +// Serial IO SPI1 Controller Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1 30
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1 3
> +
> +#define V_CNL_PCH_LP_SERIAL_IO_CFG_SPI1_DEVICE_ID 0x9DAB
> +#define V_CNL_PCH_H_SERIAL_IO_CFG_SPI1_DEVICE_ID 0xA32B
> +
> +//
> +// Serial IO UART0 Controller Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0 30
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0 0
> +
> +#define V_CNL_PCH_LP_SERIAL_IO_CFG_UART0_DEVICE_ID 0x9DA8
> +#define V_CNL_PCH_H_SERIAL_IO_CFG_UART0_DEVICE_ID 0xA328
> +
> +//
> +// Serial IO UART1 Controller Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1 30
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1 1
> +
> +#define V_CNL_PCH_LP_SERIAL_IO_CFG_UART1_DEVICE_ID 0x9DA9
> +#define V_CNL_PCH_H_SERIAL_IO_CFG_UART1_DEVICE_ID 0xA329
> +
> +//
> +// Serial IO UART2 Controller Registers
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2 25
> +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2 2
> +
> +#define V_CNL_PCH_LP_SERIAL_IO_CFG_UART2_DEVICE_ID 0x9DC7
> +#define V_CNL_PCH_H_SERIAL_IO_CFG_UART2_DEVICE_ID 0xA347
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSmbus.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSmbus.h
> new file mode 100644
> index 0000000000..e571a6a127
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSmbus.h
> @@ -0,0 +1,151 @@
> +/** @file
> + Register names for PCH Smbus Device.
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used .
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_SMBUS_H_
> +#define _PCH_REGS_SMBUS_H_
> +
> +//
> +// SMBus Controller Registers (D31:F4)
> +//
> +#define PCI_DEVICE_NUMBER_PCH_SMBUS 31
> +#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4
> +#define R_SMBUS_CFG_BASE 0x20
> +#define V_SMBUS_CFG_BASE_SIZE (1 << 5)
> +#define B_SMBUS_CFG_BASE_BAR 0x0000FFE0
> +#define R_SMBUS_CFG_HOSTC 0x40
> +#define B_SMBUS_CFG_HOSTC_SPDWD BIT4
> +#define B_SMBUS_CFG_HOSTC_SSRESET BIT3
> +#define B_SMBUS_CFG_HOSTC_I2C_EN BIT2
> +#define B_SMBUS_CFG_HOSTC_SMI_EN BIT1
> +#define B_SMBUS_CFG_HOSTC_HST_EN BIT0
> +#define R_SMBUS_CFG_TCOBASE 0x50
> +#define B_SMBUS_CFG_TCOBASE_BAR 0x0000FFE0
> +#define R_SMBUS_CFG_TCOCTL 0x54
> +#define B_SMBUS_CFG_TCOCTL_TCO_BASE_EN BIT8
> +#define B_SMBUS_CFG_TCOCTL_TCO_BASE_LOCK BIT0
> +#define R_SMBUS_CFG_64 0x64
> +#define R_SMBUS_CFG_80 0x80
> +
> +//
> +// SMBus I/O Registers
> +//
> +#define R_SMBUS_IO_HSTS 0x00 ///< Host Status Register R/W
> +#define B_SMBUS_IO_HBSY 0x01
> +#define B_SMBUS_IO_INTR 0x02
> +#define B_SMBUS_IO_DERR 0x04
> +#define B_SMBUS_IO_BERR 0x08
> +#define B_SMBUS_IO_FAIL 0x10
> +#define B_SMBUS_IO_SMBALERT_STS 0x20
> +#define B_SMBUS_IO_IUS 0x40
> +#define B_SMBUS_IO_BYTE_DONE_STS 0x80
> +#define B_SMBUS_IO_ERROR (B_SMBUS_IO_DERR |
> B_SMBUS_IO_BERR | B_SMBUS_IO_FAIL)
> +#define B_SMBUS_IO_HSTS_ALL 0xFF
> +#define R_SMBUS_IO_HCTL 0x02 ///< Host Control Register
> R/W
> +#define B_SMBUS_IO_INTREN 0x01
> +#define B_SMBUS_IO_KILL 0x02
> +#define B_SMBUS_IO_SMB_CMD 0x1C
> +#define V_SMBUS_IO_SMB_CMD_QUICK 0x00
> +#define V_SMBUS_IO_SMB_CMD_BYTE 0x04
> +#define V_SMBUS_IO_SMB_CMD_BYTE_DATA 0x08
> +#define V_SMBUS_IO_SMB_CMD_WORD_DATA 0x0C
> +#define V_SMBUS_IO_SMB_CMD_PROCESS_CALL 0x10
> +#define V_SMBUS_IO_SMB_CMD_BLOCK 0x14
> +#define V_SMBUS_IO_SMB_CMD_IIC_READ 0x18
> +#define V_SMBUS_IO_SMB_CMD_BLOCK_PROCESS 0x1C
> +#define B_SMBUS_IO_LAST_BYTE 0x20
> +#define B_SMBUS_IO_START 0x40
> +#define B_SMBUS_IO_PEC_EN 0x80
> +#define R_SMBUS_IO_HCMD 0x03 ///< Host Command Register
> R/W
> +#define R_SMBUS_IO_TSA 0x04 ///< Transmit Slave Address
> Register R/W
> +#define B_SMBUS_IO_RW_SEL 0x01
> +#define B_SMBUS_IO_READ 0x01 // RW
> +#define B_SMBUS_IO_WRITE 0x00 // RW
> +#define B_SMBUS_IO_ADDRESS 0xFE
> +#define R_SMBUS_IO_HD0 0x05 ///< Data 0 Register R/W
> +#define R_SMBUS_IO_HD1 0x06 ///< Data 1 Register R/W
> +#define R_SMBUS_IO_HBD 0x07 ///< Host Block Data Register
> R/W
> +#define R_SMBUS_IO_PEC 0x08 ///< Packet Error Check Data
> Register R/W
> +#define R_SMBUS_IO_RSA 0x09 ///< Receive Slave Address
> Register R/W
> +#define B_SMBUS_IO_SLAVE_ADDR 0x7F
> +#define R_SMBUS_IO_SD 0x0A ///< Receive Slave Data
> Register R/W
> +#define R_SMBUS_IO_AUXS 0x0C ///< Auxiliary Status Register
> R/WC
> +#define B_SMBUS_IO_CRCE 0x01
> +#define B_SMBUS_IO_STCO 0x02 ///< SMBus TCO Mode
> +#define R_SMBUS_IO_AUXC 0x0D ///< Auxiliary Control
> Register R/W
> +#define B_SMBUS_IO_AAC 0x01
> +#define B_SMBUS_IO_E32B 0x02
> +#define R_SMBUS_IO_SMLC 0x0E ///< SMLINK Pin Control
> Register R/W
> +#define B_SMBUS_IO_SMLINK0_CUR_STS 0x01
> +#define B_SMBUS_IO_SMLINK1_CUR_STS 0x02
> +#define B_SMBUS_IO_SMLINK_CLK_CTL 0x04
> +#define R_SMBUS_IO_SMBC 0x0F ///< SMBus Pin Control
> Register R/W
> +#define B_SMBUS_IO_SMBCLK_CUR_STS 0x01
> +#define B_SMBUS_IO_SMBDATA_CUR_STS 0x02
> +#define B_SMBUS_IO_SMBCLK_CTL 0x04
> +#define R_SMBUS_IO_SSTS 0x10 ///< Slave Status Register
> R/WC
> +#define B_SMBUS_IO_HOST_NOTIFY_STS 0x01
> +#define R_SMBUS_IO_SCMD 0x11 ///< Slave Command Register
> R/W
> +#define B_SMBUS_IO_HOST_NOTIFY_INTREN 0x01
> +#define B_SMBUS_IO_HOST_NOTIFY_WKEN 0x02
> +#define B_SMBUS_IO_SMBALERT_DIS 0x04
> +#define R_SMBUS_IO_NDA 0x14 ///< Notify Device Address
> Register RO
> +#define B_SMBUS_IO_DEVICE_ADDRESS 0xFE
> +#define R_SMBUS_IO_NDLB 0x16 ///< Notify Data Low Byte
> Register RO
> +#define R_SMBUS_IO_NDHB 0x17 ///< Notify Data High Byte
> Register RO
> +
> +//
> +// SMBus Private Config Registers
> +// (PID:SMB)
> +//
> +#define R_SMBUS_PCR_TCOCFG 0x00 ///< TCO
> Configuration register
> +#define B_SMBUS_PCR_TCOCFG_IE BIT7 ///< TCO
> IRQ Enable
> +#define B_SMBUS_PCR_TCOCFG_IS (BIT2 | BIT1 | BIT0) ///<
> TCO IRQ Select
> +#define V_SMBUS_PCR_TCOCFG_IRQ_9 0x00
> +#define V_SMBUS_PCR_TCOCFG_IRQ_10 0x01
> +#define V_SMBUS_PCR_TCOCFG_IRQ_11 0x02
> +#define V_SMBUS_PCR_TCOCFG_IRQ_20 0x04 ///<
> only if APIC enabled
> +#define V_SMBUS_PCR_TCOCFG_IRQ_21 0x05 ///<
> only if APIC enabled
> +#define V_SMBUS_PCR_TCOCFG_IRQ_22 0x06 ///<
> only if APIC enabled
> +#define V_SMBUS_PCR_TCOCFG_IRQ_23 0x07 ///<
> only if APIC enabled
> +#define R_SMBUS_PCR_SMBTM 0x04 ///<
> SMBus Test Mode
> +#define B_SMBUS_PCR_SMBTM_SMBCT BIT1 ///<
> SMBus Counter
> +#define B_SMBUS_PCR_SMBTM_SMBDG BIT0 ///<
> SMBus Deglitch
> +#define R_SMBUS_PCR_SCTM 0x08 ///< Short
> Counter Test Mode
> +#define B_SMBUS_PCR_SCTM_SSU BIT31 ///<
> Simulation Speed-Up
> +#define R_SMBUS_PCR_GC 0x0C ///< General
> Control
> +#define B_SMBUS_PCR_GC_FD BIT0 ///<
> Function Disable
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSpi.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSpi.h
> new file mode 100644
> index 0000000000..013603ca25
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSpi.h
> @@ -0,0 +1,295 @@
> +/** @file
> + Register names for PCH SPI device.
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_SPI_H_
> +#define _PCH_REGS_SPI_H_
> +
> +//
> +// SPI Registers (D31:F5)
> +//
> +
> +#define PCI_DEVICE_NUMBER_PCH_SPI 31
> +#define PCI_FUNCTION_NUMBER_PCH_SPI 5
> +
> +#define R_SPI_CFG_BAR0 0x10
> +#define B_SPI_CFG_BAR0_MASK 0x0FFF
> +
> +#define R_SPI_CFG_BDE 0xD8
> +#define B_SPI_CFG_BDE_F8 0x8000
> +#define B_SPI_CFG_BDE_F0 0x4000
> +#define B_SPI_CFG_BDE_E8 0x2000
> +#define B_SPI_CFG_BDE_E0 0x1000
> +#define B_SPI_CFG_BDE_D8 0x0800
> +#define B_SPI_CFG_BDE_D0 0x0400
> +#define B_SPI_CFG_BDE_C8 0x0200
> +#define B_SPI_CFG_BDE_C0 0x0100
> +#define B_SPI_CFG_BDE_LEG_F 0x0080
> +#define B_SPI_CFG_BDE_LEG_E 0x0040
> +#define B_SPI_CFG_BDE_70 0x0008
> +#define B_SPI_CFG_BDE_60 0x0004
> +#define B_SPI_CFG_BDE_50 0x0002
> +#define B_SPI_CFG_BDE_40 0x0001
> +
> +#define R_SPI_CFG_BC 0xDC
> +#define S_SPI_CFG_BC 4
> +#define N_SPI_CFG_BC_ASE_BWP 11
> +#define B_SPI_CFG_BC_ASE_BWP BIT11
> +#define N_SPI_CFG_BC_ASYNC_SS 10
> +#define B_SPI_CFG_BC_ASYNC_SS BIT10
> +#define B_SPI_CFG_BC_OSFH BIT9 ///< OS Function
> Hide
> +#define N_SPI_CFG_BC_SYNC_SS 8
> +#define B_SPI_CFG_BC_SYNC_SS BIT8
> +#define B_SPI_CFG_BC_BILD BIT7
> +#define B_SPI_CFG_BC_BBS BIT6 ///< Boot BIOS strap
> +#define N_SPI_CFG_BC_BBS 6
> +#define V_SPI_CFG_BC_BBS_SPI 0 ///< Boot BIOS
> strapped to SPI
> +#define V_SPI_CFG_BC_BBS_LPC 1 ///< Boot BIOS
> strapped to LPC
> +#define B_SPI_CFG_BC_EISS BIT5 ///< Enable
> InSMM.STS
> +#define B_SPI_CFG_BC_TSS BIT4
> +#define B_SPI_CFG_BC_SRC (BIT3 | BIT2)
> +#define N_SPI_CFG_BC_SRC 2
> +#define V_SPI_CFG_BC_SRC_PREF_EN_CACHE_EN 0x02 ///<
> Prefetching and Caching enabled
> +#define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No
> prefetching and no caching
> +#define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_EN 0x00 ///< No
> prefetching, but caching enabled
> +#define B_SPI_CFG_BC_LE BIT1 ///< Lock Enable
> +#define N_SPI_CFG_BC_BLE 1
> +#define B_SPI_CFG_BC_WPD BIT0 ///< Write Protect
> Disable
> +
> +//
> +// BIOS Flash Program Registers (based on SPI_BAR0)
> +//
> +#define R_SPI_MEM_BFPR 0x00 ///< BIOS
> Flash Primary Region Register(32bits), which is RO and contains the same value
> from FREG1
> +#define B_SPI_MEM_BFPR_PRL 0x7FFF0000 ///<
> BIOS Flash Primary Region Limit mask
> +#define N_SPI_MEM_BFPR_PRL 16 ///< BIOS
> Flash Primary Region Limit bit position
> +#define B_SPI_MEM_BFPR_PRB 0x00007FFF ///<
> BIOS Flash Primary Region Base mask
> +#define N_SPI_MEM_BFPR_PRB 0 ///< BIOS
> Flash Primary Region Base bit position
> +#define R_SPI_MEM_HSFSC 0x04 ///<
> Hardware Sequencing Flash Status and Control Register(32bits)
> +#define B_SPI_MEM_HSFSC_FSMIE BIT31 ///<
> Flash SPI SMI# Enable
> +#define B_SPI_MEM_HSFSC_FDBC_MASK 0x3F000000
> ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
> +#define N_SPI_MEM_HSFSC_FDBC 24
> +#define B_SPI_MEM_HSFSC_CYCLE_MASK 0x001E0000
> ///< Flash Cycle.
> +#define N_SPI_MEM_HSFSC_CYCLE 17
> +#define V_SPI_MEM_HSFSC_CYCLE_READ 0 ///<
> Flash Cycle Read
> +#define V_SPI_MEM_HSFSC_CYCLE_WRITE 2 ///<
> Flash Cycle Write
> +#define V_SPI_MEM_HSFSC_CYCLE_4K_ERASE 3 ///<
> Flash Cycle 4K Block Erase
> +#define V_SPI_MEM_HSFSC_CYCLE_64K_ERASE 4
> ///< Flash Cycle 64K Sector Erase
> +#define V_SPI_MEM_HSFSC_CYCLE_READ_SFDP 5
> ///< Flash Cycle Read SFDP
> +#define V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID 6
> ///< Flash Cycle Read JEDEC ID
> +#define V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS 7
> ///< Flash Cycle Write Status
> +#define V_SPI_MEM_HSFSC_CYCLE_READ_STATUS 8
> ///< Flash Cycle Read Status
> +#define B_SPI_MEM_HSFSC_CYCLE_FGO BIT16 ///<
> Flash Cycle Go.
> +#define B_SPI_MEM_HSFSC_FLOCKDN BIT15 ///<
> Flash Configuration Lock-Down
> +#define B_SPI_MEM_HSFSC_FDV BIT14 ///<
> Flash Descriptor Valid, once valid software can use hareware sequencing regs
> +#define B_SPI_MEM_HSFSC_FDOPSS BIT13 ///<
> Flash Descriptor Override Pin-Strap Status
> +#define B_SPI_MEM_HSFSC_PRR34_LOCKDN BIT12
> ///< PRR3 PRR4 Lock-Down
> +#define B_SPI_MEM_HSFSC_WRSDIS BIT11 ///<
> Write Status Disable
> +#define B_SPI_MEM_HSFSC_SAF_CE BIT8 ///<
> SAF ctype error
> +#define B_SPI_MEM_HSFSC_SAF_MODE_ACTIVE BIT7
> ///< Indicates flash is attached either directly to the PCH via the SPI bus or
> EC/BMC
> +#define B_SPI_MEM_HSFSC_SAF_LE BIT6 ///<
> SAF link error
> +#define B_SPI_MEM_HSFSC_SCIP BIT5 ///< SPI
> cycle in progress
> +#define B_SPI_MEM_HSFSC_SAF_DLE BIT4 ///<
> SAF Data length error
> +#define B_SPI_MEM_HSFSC_SAF_ERROR BIT3 ///<
> SAF Error
> +#define B_SPI_MEM_HSFSC_AEL BIT2 ///<
> Access Error Log
> +#define B_SPI_MEM_HSFSC_FCERR BIT1 ///<
> Flash Cycle Error
> +#define B_SPI_MEM_HSFSC_FDONE BIT0 ///<
> Flash Cycle Done
> +#define R_SPI_MEM_FADDR 0x08 ///< SPI
> Flash Address
> +#define B_SPI_MEM_FADDR_MASK 0x07FFFFFF ///<
> SPI Flash Address Mask (0~26bit)
> +#define R_SPI_MEM_DLOCK 0x0C ///<
> Discrete Lock Bits
> +#define B_SPI_MEM_DLOCK_PR0LOCKDN BIT8 ///<
> PR0LOCKDN
> +#define R_SPI_MEM_FDATA00 0x10 ///< SPI
> Data 00 (32 bits)
> +#define R_SPI_MEM_FDATA01 0x14 ///< SPI
> Data 01
> +#define R_SPI_MEM_FDATA02 0x18 ///< SPI
> Data 02
> +#define R_SPI_MEM_FDATA03 0x1C ///< SPI
> Data 03
> +#define R_SPI_MEM_FDATA04 0x20 ///< SPI
> Data 04
> +#define R_SPI_MEM_FDATA05 0x24 ///< SPI
> Data 05
> +#define R_SPI_MEM_FDATA06 0x28 ///< SPI
> Data 06
> +#define R_SPI_MEM_FDATA07 0x2C ///< SPI
> Data 07
> +#define R_SPI_MEM_FDATA08 0x30 ///< SPI
> Data 08
> +#define R_SPI_MEM_FDATA09 0x34 ///< SPI
> Data 09
> +#define R_SPI_MEM_FDATA10 0x38 ///< SPI
> Data 10
> +#define R_SPI_MEM_FDATA11 0x3C ///< SPI
> Data 11
> +#define R_SPI_MEM_FDATA12 0x40 ///< SPI
> Data 12
> +#define R_SPI_MEM_FDATA13 0x44 ///< SPI
> Data 13
> +#define R_SPI_MEM_FDATA14 0x48 ///< SPI
> Data 14
> +#define R_SPI_MEM_FDATA15 0x4C ///< SPI
> Data 15
> +#define R_SPI_MEM_FRAP 0x50 ///< Flash
> Region Access Permisions Register
> +#define B_SPI_MEM_FRAP_BRWA_MASK 0x0000FF00
> ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS;
> 2: ME; 3: GbE; 4: PlatformData
> +#define N_SPI_MEM_FRAP_BRWA 8 ///<
> BIOS Region Write Access bit position
> +#define B_SPI_MEM_FRAP_BRRA_MASK 0x000000FF
> ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2:
> ME; 3: GbE; 4: PlatformData
> +#define B_SPI_MEM_FRAP_BMRAG_MASK 0x00FF0000
> ///< BIOS Master Read Access Grant
> +#define B_SPI_MEM_FRAP_BMWAG_MASK 0xFF000000
> ///< BIOS Master Write Access Grant
> +#define R_SPI_MEM_FREG0_FLASHD 0x54 ///<
> Flash Region 0(Flash Descriptor)(32bits)
> +#define R_SPI_MEM_FREG1_BIOS 0x58 ///<
> Flash Region 1(BIOS)(32bits)
> +#define R_SPI_MEM_FREG2_ME 0x5C ///<
> Flash Region 2(ME)(32bits)
> +#define R_SPI_MEM_FREG3_GBE 0x60 ///<
> Flash Region 3(GbE)(32bits)
> +#define R_SPI_MEM_FREG4_PLATFORM_DATA 0x64
> ///< Flash Region 4(Platform Data)(32bits)
> +#define R_SPI_MEM_FREG5_DER 0x68 ///<
> Flash Region 5(Device Expansion Region)(32bits)
> +#define S_SPI_MEM_FREGX 4 ///< Size of
> Flash Region register
> +#define B_SPI_MEM_FREGX_LIMIT_MASK 0x7FFF0000
> ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be
> FFFh
> +#define N_SPI_MEM_FREGX_LIMIT 16 ///<
> Region limit bit position
> +#define N_SPI_MEM_FREGX_LIMIT_REPR 12 ///<
> Region limit bit represents position
> +#define B_SPI_MEM_FREGX_BASE_MASK 0x00007FFF
> ///< Flash Region Base, [14:0] represents [26:12]
> +#define N_SPI_MEM_FREGX_BASE 0 ///<
> Region base bit position
> +#define N_SPI_MEM_FREGX_BASE_REPR 12 ///<
> Region base bit represents position
> +#define R_SPI_MEM_PR0 0x84 ///<
> Protected Region 0 Register
> +#define R_SPI_MEM_PR1 0x88 ///<
> Protected Region 1 Register
> +#define R_SPI_MEM_PR2 0x8C ///<
> Protected Region 2 Register
> +#define R_SPI_MEM_PR3 0x90 ///<
> Protected Region 3 Register
> +#define R_SPI_MEM_PR4 0x94 ///<
> Protected Region 4 Register
> +#define S_SPI_MEM_PRX 4 ///<
> Protected Region X Register size
> +#define B_SPI_MEM_PRX_WPE BIT31 ///<
> Write Protection Enable
> +#define B_SPI_MEM_PRX_PRL_MASK 0x7FFF0000
> ///< Protected Range Limit Mask, [30:16] here represents upper limit of
> address [26:12]
> +#define N_SPI_MEM_PRX_PRL 16 ///<
> Protected Range Limit bit position
> +#define B_SPI_MEM_PRX_RPE BIT15 ///<
> Read Protection Enable
> +#define B_SPI_MEM_PRX_PRB_MASK 0x00007FFF
> ///< Protected Range Base Mask, [14:0] here represents base limit of address
> [26:12]
> +#define N_SPI_MEM_PRX_PRB 0 ///<
> Protected Range Base bit position
> +#define R_SPI_MEM_SFRAP 0xB0 ///<
> Secondary Flash Regions Access Permisions Register
> +#define R_SPI_MEM_FDOC 0xB4 ///< Flash
> Descriptor Observability Control Register(32 bits)
> +#define B_SPI_MEM_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12)
> ///< Flash Descritor Section Select
> +#define V_SPI_MEM_FDOC_FDSS_FSDM 0x0000
> ///< Flash Signature and Descriptor Map
> +#define V_SPI_MEM_FDOC_FDSS_COMP 0x1000
> ///< Component
> +#define V_SPI_MEM_FDOC_FDSS_REGN 0x2000
> ///< Region
> +#define V_SPI_MEM_FDOC_FDSS_MSTR 0x3000
> ///< Master
> +#define V_SPI_MEM_FDOC_FDSS_PCHS 0x4000 ///<
> PCH soft straps
> +#define V_SPI_MEM_FDOC_FDSS_SFDP 0x5000 ///<
> SFDP Parameter Table
> +#define B_SPI_MEM_FDOC_FDSI_MASK 0x0FFC ///<
> Flash Descriptor Section Index
> +#define R_SPI_MEM_FDOD 0xB8 ///< Flash
> Descriptor Observability Data Register(32 bits)
> +#define R_SPI_MEM_SFDP0_VSCC0 0xC4 ///<
> Vendor Specific Component Capabilities Register(32 bits)
> +#define B_SPI_MEM_SFDPX_VSCCX_CPPTV BIT31
> ///< Component Property Parameter Table Valid
> +#define B_SPI_MEM_SFDP0_VSCC0_VCL BIT30 ///<
> Vendor Component Lock
> +#define B_SPI_MEM_SFDPX_VSCCX_EO_64K BIT29
> ///< 64k Erase valid (EO_64k_valid)
> +#define B_SPI_MEM_SFDPX_VSCCX_EO_4K BIT28
> ///< 4k Erase valid (EO_4k_valid)
> +#define B_SPI_MEM_SFDPX_VSCCX_RPMC BIT27
> ///< RPMC Supported
> +#define B_SPI_MEM_SFDPX_VSCCX_DPD BIT26 ///<
> Deep Powerdown Supported
> +#define B_SPI_MEM_SFDPX_VSCCX_SUSRES BIT25
> ///< Suspend/Resume Supported
> +#define B_SPI_MEM_SFDPX_VSCCX_SOFTRES BIT24
> ///< Soft Reset Supported
> +#define B_SPI_MEM_SFDPX_VSCCX_64k_EO_MASK 0x00FF0000
> ///< 64k Erase Opcode (EO_64k)
> +#define B_SPI_MEM_SFDPX_VSCCX_4k_EO_MASK 0x0000FF00
> ///< 4k Erase Opcode (EO_4k)
> +#define B_SPI_MEM_SFDPX_VSCCX_QER (BIT7 | BIT6 | BIT5)
> ///< Quad Enable Requirements
> +#define B_SPI_MEM_SFDPX_VSCCX_WEWS BIT4
> ///< Write Enable on Write Status
> +#define B_SPI_MEM_SFDPX_VSCCX_WSR BIT3 ///<
> Write Status Required
> +#define B_SPI_MEM_SFDPX_VSCCX_WG_64B BIT2
> ///< Write Granularity, 0: 1 Byte; 1: 64 Bytes
> +#define R_SPI_MEM_SFDP1_VSCC1 0xC8 ///<
> Vendor Specific Component Capabilities Register(32 bits)
> +#define R_SPI_MEM_PINTX 0xCC ///<
> Parameter Table Index
> +#define N_SPI_MEM_PINTX_SPT 14
> +#define V_SPI_MEM_PINTX_SPT_CPT0 0x0 ///<
> Component 0 Property Parameter Table
> +#define V_SPI_MEM_PINTX_SPT_CPT1 0x1 ///<
> Component 1 Property Parameter Table
> +#define N_SPI_MEM_PINTX_HORD 12
> +#define V_SPI_MEM_PINTX_HORD_SFDP 0x0 ///<
> SFDP Header
> +#define V_SPI_MEM_PINTX_HORD_PT 0x1 ///<
> Parameter Table Header
> +#define V_SPI_MEM_PINTX_HORD_DATA 0x2 ///<
> Data
> +#define R_SPI_MEM_PTDATA 0xD0 ///<
> Parameter Table Data
> +#define R_SPI_MEM_SBRS 0xD4 ///< SPI
> Bus Requester Status
> +
> +//
> +// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
> +//
> +#define R_SPI_FLASH_FDBAR_FLVALSIG 0x00 ///<
> Flash Valid Signature
> +#define V_SPI_FLASH_FDBAR_FLVALSIG 0x0FF0A55A
> +#define R_SPI_FLASH_FDBAR_FLASH_MAP0 0x04
> +#define B_SPI_FLASH_FDBAR_FCBA 0x000000FF
> ///< Flash Component Base Address
> +#define B_SPI_FLASH_FDBAR_NC 0x00000300
> ///< Number Of Components
> +#define N_SPI_FLASH_FDBAR_NC 8 ///<
> Number Of Components
> +#define V_SPI_FLASH_FDBAR_NC_1 0x00000000
> +#define V_SPI_FLASH_FDBAR_NC_2 0x00000100
> +#define B_SPI_FLASH_FDBAR_FRBA 0x00FF0000
> ///< Flash Region Base Address
> +#define B_SPI_FLASH_FDBAR_NR 0x07000000
> ///< Number Of Regions
> +#define R_SPI_FLASH_FDBAR_FLASH_MAP1 0x08
> +#define B_SPI_FLASH_FDBAR_FMBA 0x000000FF
> ///< Flash Master Base Address
> +#define B_SPI_FLASH_FDBAR_NM 0x00000700
> ///< Number Of Masters
> +#define B_SPI_FLASH_FDBAR_FPSBA 0x00FF0000
> ///< PCH Strap Base Address, [23:16] represents [11:4]
> +#define N_SPI_FLASH_FDBAR_FPSBA 16 ///<
> PCH Strap base Address bit position
> +#define N_SPI_FLASH_FDBAR_FPSBA_REPR 4 ///<
> PCH Strap base Address bit represents position
> +#define B_SPI_FLASH_FDBAR_PCHSL 0xFF000000
> ///< PCH Strap Length, [31:24] represents number of Dwords
> +#define N_SPI_FLASH_FDBAR_PCHSL 24 ///<
> PCH Strap Length bit position
> +#define R_SPI_FLASH_FDBAR_FLASH_MAP2 0x0C
> +#define B_SPI_FLASH_FDBAR_FCPUSBA 0x000000FF
> ///< CPU Strap Base Address, [7:0] represents [11:4]
> +#define N_SPI_FLASH_FDBAR_FCPUSBA 0 ///<
> CPU Strap Base Address bit position
> +#define N_SPI_FLASH_FDBAR_FCPUSBA_REPR 4
> ///< CPU Strap Base Address bit represents position
> +#define B_SPI_FLASH_FDBAR_CPUSL 0x0000FF00
> ///< CPU Strap Length, [15:8] represents number of Dwords
> +#define N_SPI_FLASH_FDBAR_CPUSL 8 ///<
> CPU Strap Length bit position
> +//
> +// Flash Component Base Address (FCBA) from Flash Region 0
> +//
> +#define R_SPI_FLASH_FCBA_FLCOMP 0x00 ///<
> Flash Components Register
> +#define B_SPI_FLASH_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27)
> ///< Read ID and Read Status Clock Frequency
> +#define B_SPI_FLASH_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24)
> ///< Write and Erase Clock Frequency
> +#define B_SPI_FLASH_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21)
> ///< Fast Read Clock Frequency
> +#define B_SPI_FLASH_FLCOMP_FR_SUP BIT20 ///<
> Fast Read Support.
> +#define B_SPI_FLASH_FLCOMP_RC_FREQ (BIT19 | BIT18 | BIT17)
> ///< Read Clock Frequency.
> +#define V_SPI_FLASH_FLCOMP_FREQ_48MHZ 0x02
> +#define V_SPI_FLASH_FLCOMP_FREQ_30MHZ 0x04
> +#define V_SPI_FLASH_FLCOMP_FREQ_17MHZ 0x06
> +#define B_SPI_FLASH_FLCOMP_COMP1_MASK 0xF0
> ///< Flash Component 1 Size MASK
> +#define N_SPI_FLASH_FLCOMP_COMP1 4 ///<
> Flash Component 1 Size bit position
> +#define B_SPI_FLASH_FLCOMP_COMP0_MASK 0x0F
> ///< Flash Component 0 Size MASK
> +#define V_SPI_FLASH_FLCOMP_COMP_512KB 0x80000
> +//
> +// Descriptor Upper Map Section from Flash Region 0
> +//
> +#define R_SPI_FLASH_UMAP1 0xEFC ///<
> Flash Upper Map 1
> +#define B_SPI_FLASH_UMAP1_VTBA 0x000000FF
> ///< VSCC Table Base Address
> +#define B_SPI_FLASH_UMAP1_VTL 0x0000FF00
> ///< VSCC Table Length
> +
> +//
> +// SPI Private Configuration Space Registers
> +//
> +#define R_SPI_PCR_CLK_CTL 0xC004
> +#define R_SPI_PCR_PWR_CTL 0xC008
> +#define R_SPI_PCR_ESPI_SOFTSTRAPS 0xC210
> +#define B_SPI_PCR_ESPI_SLAVE BIT12
> +
> +//
> +// MMP0
> +//
> +#define R_PCH_SPI_STRP_MMP0 0xC4 ///< MMP0 Soft strap
> offset
> +#define B_PCH_SPI_STRP_MMP0 0x10 ///< MMP0 Soft strap
> bit
> +
> +
> +#define R_PCH_SPI_STRP_SFDP 0xF0 ///< PCH Soft Strap SFDP
> +#define B_PCH_SPI_STRP_SFDP_QIORE BIT3 ///< Quad IO Read
> Enable
> +#define B_PCH_SPI_STRP_SFDP_QORE BIT2 ///< Quad Output
> Read Enable
> +#define B_PCH_SPI_STRP_SFDP_DIORE BIT1 ///< Dual IO Read
> Enable
> +#define B_PCH_SPI_STRP_SFDP_DORE BIT0 ///< Dual Output Read
> Enable
> +
> +//
> +// Descriptor Record 0
> +//
> +#define R_PCH_SPI_STRP_DSCR_0 0x00 ///< PCH Soft Strap 0
> +#define B_PCH_SPI_STRP_DSCR_0_PTT_SUPP BIT22 ///< PTT Supported
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsThermalC
> nl.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsThermalC
> nl.h
> new file mode 100644
> index 0000000000..fb93a62364
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsThermalC
> nl.h
> @@ -0,0 +1,49 @@
> +/** @file
> + Register names for PCH Thermal Device
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_THERMAL_H_
> +#define _PCH_REGS_THERMAL_H_
> +
> +//
> +// Thermal Device Registers (D18:0)
> +//
> +#define PCI_DEVICE_NUMBER_PCH_THERMAL 18
> +#define PCI_FUNCTION_NUMBER_PCH_THERMAL 0
> +#define R_THERMAL_CFG_MEM_TBAR 0x10
> +#define B_THERMAL_CFG_MEM_TBAR_MASK 0xFFFFF000
> +#define R_THERMAL_CFG_MEM_TBARH 0x14
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsTraceHub.
> h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsTraceHub.
> h
> new file mode 100644
> index 0000000000..21f9839546
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsTraceHub.
> h
> @@ -0,0 +1,134 @@
> +/** @file
> + Register names for PCH TraceHub device
> +
> + Conventions:
> +
> + - Register definition format:
> +
> Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpa
> ce_RegisterName
> + - Prefix:
> + Definitions beginning with "R_" are registers
> + Definitions beginning with "B_" are bits within registers
> + Definitions beginning with "V_" are meaningful values within the bits
> + Definitions beginning with "S_" are register size
> + Definitions beginning with "N_" are the bit position
> + - [GenerationName]:
> + Three letter acronym of the generation is used
> + Register name without GenerationName applies to all generations.
> + - [ComponentName]:
> + This field indicates the component name that the register belongs to (e.g.
> PCH, SA etc.)
> + Register name without ComponentName applies to all components.
> + Register that is specific to -H denoted by "_PCH_H_" in component name.
> + Register that is specific to -LP denoted by "_PCH_LP_" in component name.
> + - SubsystemName:
> + This field indicates the subsystem name of the component that the
> register belongs to
> + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
> + - RegisterSpace:
> + MEM - MMIO space register of subsystem.
> + IO - IO space register of subsystem.
> + PCR - Private configuration register of subsystem.
> + CFG - PCI configuration space register of subsystem.
> + - RegisterName:
> + Full register name.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_REGS_TRACE_HUB_H_
> +#define _PCH_REGS_TRACE_HUB_H_
> +
> +//
> +// TraceHub Registers (D31:F7)
> +//
> +#define PCI_DEVICE_NUMBER_PCH_TRACE_HUB 31
> +#define PCI_FUNCTION_NUMBER_PCH_TRACE_HUB 7
> +
> +#define R_TRACE_HUB_CFG_CSR_MTB_LBAR 0x10
> +#define B_TRACE_HUB_CFG_CSR_MTB_RBAL 0xFFF00000
> +#define R_TRACE_HUB_CFG_CSR_MTB_UBAR 0x14
> +#define B_TRACE_HUB_CFG_CSR_MTB_RBAU 0xFFFFFFFF
> +#define R_TRACE_HUB_CFG_SW_LBAR 0x18
> +#define R_TRACE_HUB_CFG_SW_UBAR 0x1C
> +#define B_TRACE_HUB_CFG_SW_RBAU 0xFFFFFFFF
> +#define R_TRACE_HUB_CFG_RTIT_LBAR 0x20
> +#define B_TRACE_HUB_CFG_RTIT_RBAL 0xFFFFFF00
> +#define R_TRACE_HUB_CFG_RTIT_UBAR 0x24
> +#define B_TRACE_HUB_CFG_RTIT_RBAU 0xFFFFFFFF
> +#define R_TRACE_HUB_CFG_MSICID 0x40
> +#define R_TRACE_HUB_CFG_MSINCP 0x41
> +#define R_TRACE_HUB_CFG_MSIMC 0x42
> +#define R_TRACE_HUB_CFG_MSILMA 0x44
> +#define R_TRACE_HUB_CFG_MSIUMA 0x48
> +#define R_TRACE_HUB_CFG_MSIMD 0x4C
> +#define B_TRACE_HUB_CFG_FW_RBAU 0xFFFFFFFF
> +#define R_TRACE_HUB_CFG_DSC 0x80
> +#define B_TRACE_HUB_CFG_BYP BIT0 //< TraceHub
> Bypass
> +#define R_TRACE_HUB_CFG_DSS 0x81
> +#define R_TRACE_HUB_CFG_ISTOT 0x84
> +#define R_TRACE_HUB_CFG_ICTOT 0x88
> +#define R_TRACE_HUB_CFG_IPAD 0x8C
> +#define R_TRACE_HUB_CFG_DSD 0x90
> +
> +//
> +// Offsets from CSR_MTB_BAR
> +//
> +#define R_TRACE_HUB_MEM_MTB_GTHOPT0 0x00
> +#define B_TRACE_HUB_MEM_MTB_GTHOPT0_P0FLUSH BIT7
> +#define B_TRACE_HUB_MEM_MTB_GTHOPT0_P1FLUSH BIT15
> +#define V_TRACE_HUB_MEM_MTB_SWDEST_PTI 0x0A
> +#define V_TRACE_HUB_MEM_MTB_SWDEST_MEMEXI 0x08
> +#define V_TRACE_HUB_MEM_MTB_SWDEST_DISABLE 0x00
> +#define R_TRACE_HUB_MEM_MTB_SWDEST_1 0x0C
> +#define B_TRACE_HUB_MEM_MTB_SWDEST_CSE_1 0x0000000F
> +#define B_TRACE_HUB_MEM_MTB_SWDEST_CSE_2 0x000000F0
> +#define B_TRACE_HUB_MEM_MTB_SWDEST_CSE_3 0x00000F00
> +#define B_TRACE_HUB_MEM_MTB_SWDEST_ISH_1 0x0000F000
> +#define B_TRACE_HUB_MEM_MTB_SWDEST_ISH_2 0x000F0000
> +#define B_TRACE_HUB_MEM_MTB_SWDEST_ISH_3 0x00F00000
> +#define B_TRACE_HUB_MEM_MTB_SWDEST_AUDIO 0x0F000000
> +#define B_TRACE_HUB_MEM_MTB_SWDEST_PMC 0xF0000000
> +#define R_TRACE_HUB_MEM_MTB_SWDEST_2 0x10
> +#define B_TRACE_HUB_MEM_MTB_SWDEST_FTH 0x0000000F
> +#define R_TRACE_HUB_MEM_MTB_SWDEST_3 0x14
> +#define B_TRACE_HUB_MEM_MTB_SWDEST_MAESTRO 0x00000F00
> +#define B_TRACE_HUB_MEM_MTB_SWDEST_MIPICAM 0x0F000000
> +#define B_TRACE_HUB_MEM_MTB_SWDEST_AET 0xF0000000
> +#define R_TRACE_HUB_MEM_MTB_SWDEST_4 0x18
> +#define R_TRACE_HUB_MEM_MTB_MSC0CTL 0xA0100
> +#define R_TRACE_HUB_MEM_MTB_MSC1CTL 0xA0200
> +#define V_TRACE_HUB_MEM_MTB_MSCNMODE_DCI 0x2
> +#define V_TRACE_HUB_MEM_MTB_MSCNMODE_DEBUG 0x3
> +#define B_TRACE_HUB_MEM_MTB_MSCNLEN (BIT10 | BIT9 |
> BIT8)
> +#define B_TRACE_HUB_MEM_MTB_MSCNMODE (BIT5 | BIT4)
> +#define N_TRACE_HUB_MEM_MTB_MSCNMODE 0x4
> +#define B_TRACE_HUB_MEM_MTB_MSCN_RD_HDR_OVRD BIT2
> +#define B_TRACE_HUB_MEM_MTB_WRAPENN BIT1
> +#define B_TRACE_HUB_MEM_MTB_MSCNEN BIT0
> +#define R_TRACE_HUB_MEM_MTB_GTHSTAT 0xD4
> +#define R_TRACE_HUB_MEM_MTB_SCR2 0xD8
> +#define B_TRACE_HUB_MEM_MTB_SCR2_FCD BIT0
> +#define B_TRACE_HUB_MEM_MTB_SCR2_FSEOFF2 BIT2
> +#define B_TRACE_HUB_MEM_MTB_SCR2_FSEOFF3 BIT3
> +#define B_TRACE_HUB_MEM_MTB_SCR2_FSEOFF4 BIT4
> +#define B_TRACE_HUB_MEM_MTB_SCR2_FSEOFF5 BIT5
> +#define B_TRACE_HUB_MEM_MTB_SCR2_FSEOFF6 BIT6
> +#define B_TRACE_HUB_MEM_MTB_SCR2_FSEOFF7 BIT7
> +#define R_TRACE_HUB_MEM_MTB_MSC0BAR 0xA0108
> +#define R_TRACE_HUB_MEM_MTB_MSC0SIZE 0xA010C
> +#define R_TRACE_HUB_MEM_MTB_MSC1BAR 0xA0208
> +#define R_TRACE_HUB_MEM_MTB_MSC1SIZE 0xA020C
> +#define R_TRACE_HUB_MEM_MTB_STREAMCFG1 0xA1000
> +#define R_TRACE_HUB_MEM_MTB_SCR 0xC8
> +#define R_TRACE_HUB_MEM_MTB_GTH_FREQ 0xCC
> +#define V_TRACE_HUB_MEM_MTB_SCR 0x00130000
> +#define R_TRACE_HUB_MEM_CSR_MTB_SCRATCHPAD0 0xE0
> +#define R_TRACE_HUB_MEM_CSR_MTB_SCRATCHPAD1 0xE4
> +#define R_TRACE_HUB_MEM_CSR_MTB_SCRATCHPAD10 0xE40
> +#define R_TRACE_HUB_MEM_MTB_CTPGCS 0x1C14
> +#define B_TRACE_HUB_MEM_MTB_CTPEN BIT0
> +#define V_TRACE_HUB_MEM_MTB_CHLCNT 0x80
> +#define R_TRACE_HUB_MEM_CSR_MTB_TSUCTRL 0x2000
> +#define B_TRACE_HUB_MEM_CSR_MTB_TSUCTRL_CTCRESYNC BIT0
> +
> +#endif
> --
> 2.16.2.windows.1
next prev parent reply other threads:[~2019-08-17 1:09 UTC|newest]
Thread overview: 121+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-17 0:15 [edk2-platforms][PATCH V1 00/37] Coffee Lake and Whiskey Lake support Kubacki, Michael A
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and Include headers Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:08 ` Chiu, Chasel
2019-08-17 1:18 ` Chaganty, Rangasai V
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:08 ` Chiu, Chasel
2019-08-17 6:58 ` Chaganty, Rangasai V
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:08 ` Chiu, Chasel
2019-08-17 7:04 ` Chaganty, Rangasai V
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add include headers Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:08 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add ConfigBlock headers Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add Library include headers Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI and Protocol " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 08/37] CoffeelakeSiliconPkg/Pch: Add Register " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel [this message]
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add Private " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add Private/Library " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:10 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode: Add Include headers Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 13/37] CoffeelakeSiliconPkg/SystemAgent: " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 14/37] CoffeelakeSiliconPkg: Add package common library instances Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:15 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 16/37] CoffeelakeSiliconPkg/Me: " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 17/37] CoffeelakeSiliconPkg/Pch: Add Base " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 18/37] CoffeelakeSiliconPkg/Pch: Add DXE " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 19/37] CoffeelakeSiliconPkg/Pch: Add PEI " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 20/37] CoffeelakeSiliconPkg/Pch: Add SMM " Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 21/37] CoffeelakeSiliconPkg/Pch: Add Base " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 22/37] CoffeelakeSiliconPkg/Pch: Add DXE private " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 23/37] CoffeelakeSiliconPkg/Pch: Add PEI " Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 24/37] CoffeelakeSiliconPkg/Pch: Add SMM " Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 25/37] CoffeelakeSiliconPkg/SystemAgent: Add " Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 26/37] CoffeelakeSiliconPkg/Pch: Add modules Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 27/37] CoffeelakeSiliconPkg/Pch: Add PchSmiDispatcher Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:15 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 28/37] CoffeelakeSiliconPkg/SystemAgent: Add modules Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:15 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package DSC files Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 30/37] Maintainers.txt: Add CoffeelakeSiliconPkg maintainers Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:15 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 31/37] WhiskeylakeOpenBoardPkg: Add package and headers Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-19 18:09 ` Sinha, Ankit
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 32/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 33/37] WhiskeylakeOpenBoardPkg: Add library instances Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-17 0:16 ` [edk2-platforms][PATCH V1 34/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: " Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:17 ` Chiu, Chasel
2019-08-17 20:08 ` Chaganty, Rangasai V
2019-08-17 0:16 ` [edk2-platforms][PATCH V1 35/37] WhiskeylakeOpenBoardPkg: Add modules Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:17 ` Chiu, Chasel
2019-08-17 7:50 ` Chaganty, Rangasai V
2019-08-17 0:16 ` [edk2-platforms][PATCH V1 36/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-17 20:11 ` Chaganty, Rangasai V
2019-08-17 0:16 ` [edk2-platforms][PATCH V1 37/37] Add WhiskeylakeOpenBoardPkg to global build config and documentation Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:17 ` Chiu, Chasel
2019-08-17 20:00 ` Chaganty, Rangasai V
2019-08-19 18:14 ` [edk2-platforms][PATCH V1 00/37] Coffee Lake and Whiskey Lake support Sinha, Ankit
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