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From: "Chiu, Chasel" <chasel.chiu@intel.com>
To: "Kubacki, Michael A" <michael.a.kubacki@intel.com>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>,
	"Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>,
	"Gao, Liming" <liming.gao@intel.com>,
	"Kinney, Michael D" <michael.d.kinney@intel.com>,
	"Sinha, Ankit" <ankit.sinha@intel.com>
Subject: Re: [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add Private/Library include headers
Date: Sat, 17 Aug 2019 01:09:55 +0000	[thread overview]
Message-ID: <3C3EFB470A303B4AB093197B6777CCEC504622A4@PGSMSX111.gar.corp.intel.com> (raw)
In-Reply-To: <20190817001603.30632-11-michael.a.kubacki@intel.com>


Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>


> -----Original Message-----
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>;
> Kinney, Michael D <michael.d.kinney@intel.com>; Sinha, Ankit
> <ankit.sinha@intel.com>
> Subject: [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add
> Private/Library include headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds the following header files:
>  * Pch/Include/Private/Library
> 
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHdaNh
> lt.h           |  134 +++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioHelpersLi
> b.h          |   97 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioNameBuf
> ferLib.h       |   25 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioPrivateLi
> b.h          | 1061 ++++++++++++++++++++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/I2cMasterCo
> mmonLib.h      |  288 ++++++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchDmiLib.h
> |  344 +++++++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchHdaLib.h
> |   56 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchInitComm
> onLib.h        |  100 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPciExpress
> HelpersLib.h |  371 +++++++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPsfPrivate
> Lib.h        |  578 +++++++++++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSmbusCo
> mmonLib.h       |   98 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSpiComm
> onLib.h         |  366 +++++++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PeiPchDmiLib.
> h            |   25 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PmcPrivateLib
> .h           |  706 +++++++++++++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SiScheduleRes
> etLib.h      |   48 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SmmPchPrivat
> eLib.h        |   28 +
>  16 files changed, 4325 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHda
> Nhlt.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHda
> Nhlt.h
> new file mode 100644
> index 0000000000..9d8e34eb0d
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHda
> Nhlt.h
> @@ -0,0 +1,134 @@
> +/** @file
> +  Header file for DxePchHdaLib - NHLT structure definitions.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _DXE_PCH_HDA_NHLT_H_
> +#define _DXE_PCH_HDA_NHLT_H_
> +
> +#include <IndustryStandard/Acpi.h>
> +
> +//
> +// ACPI support protocol instance signature definition.
> +//
> +#define NHLT_ACPI_TABLE_SIGNATURE  SIGNATURE_32 ('N', 'H', 'L', 'T')
> +
> +// MSFT defined structures
> +#define SPEAKER_FRONT_LEFT      0x1
> +#define SPEAKER_FRONT_RIGHT     0x2
> +#define SPEAKER_FRONT_CENTER    0x4
> +#define SPEAKER_BACK_LEFT       0x10
> +#define SPEAKER_BACK_RIGHT      0x20
> +
> +#define KSAUDIO_SPEAKER_MONO   (SPEAKER_FRONT_CENTER)
> +#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT |
> SPEAKER_FRONT_RIGHT)
> +#define KSAUDIO_SPEAKER_QUAD   (SPEAKER_FRONT_LEFT |
> SPEAKER_FRONT_RIGHT | SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT)
> +
> +#define WAVE_FORMAT_EXTENSIBLE    0xFFFE /* Microsoft */
> +#define KSDATAFORMAT_SUBTYPE_PCM \
> +        {0x00000001, 0x0000, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b,
> 0x71}}
> +
> +#pragma pack (push, 1)
> +
> +typedef struct {
> +  UINT16  wFormatTag;
> +  UINT16  nChannels;
> +  UINT32  nSamplesPerSec;
> +  UINT32  nAvgBytesPerSec;
> +  UINT16  nBlockAlign;
> +  UINT16  wBitsPerSample;
> +  UINT16  cbSize;
> +} WAVEFORMATEX;
> +
> +typedef struct {
> +  WAVEFORMATEX Format;
> +  union {
> +    UINT16 wValidBitsPerSample;
> +    UINT16 wSamplesPerBlock;
> +    UINT16 wReserved;
> +  } Samples;
> +  UINT32       dwChannelMask;
> +  GUID         SubFormat;
> +} WAVEFORMATEXTENSIBLE;
> +
> +//
> +// List of supported link type.
> +//
> +enum NHLT_LINK_TYPE
> +{
> +  HdaNhltLinkHd   = 0,
> +  HdaNhltLinkDsp  = 1,
> +  HdaNhltLinkDmic = 2,
> +  HdaNhltLinkSsp  = 3,
> +  HdaNhltLinkInvalid
> +};
> +
> +//
> +// List of supported device type.
> +//
> +enum NHLT_DEVICE_TYPE
> +{
> +  HdaNhltDeviceBt   = 0,
> +  HdaNhltDeviceDmic = 1,
> +  HdaNhltDeviceI2s  = 4,
> +  HdaNhltDeviceInvalid
> +};
> +
> +typedef struct {
> +  UINT32    CapabilitiesSize;
> +  UINT8     Capabilities[1];
> +} SPECIFIC_CONFIG;
> +
> +typedef struct {
> +  WAVEFORMATEXTENSIBLE Format;
> +  SPECIFIC_CONFIG      FormatConfiguration;
> +} FORMAT_CONFIG;
> +
> +typedef struct {
> +  UINT8           FormatsCount;
> +  FORMAT_CONFIG   FormatsConfiguration[1];
> +} FORMATS_CONFIG;
> +
> +typedef struct {
> +  UINT8           DeviceId[16];
> +  UINT8           DeviceInstanceId;
> +  UINT8           DevicePortId;
> +} DEVICE_INFO;
> +
> +typedef struct {
> +  UINT8           DeviceInfoCount;
> +  DEVICE_INFO     DeviceInformation[1];
> +} DEVICES_INFO;
> +
> +typedef struct {
> +  UINT32          EndpointDescriptorLength;
> +  UINT8           LinkType;
> +  UINT8           InstanceId;
> +  UINT16          HwVendorId;
> +  UINT16          HwDeviceId;
> +  UINT16          HwRevisionId;
> +  UINT32          HwSubsystemId;
> +  UINT8           DeviceType;
> +  UINT8           Direction;
> +  UINT8           VirtualBusId;
> +  SPECIFIC_CONFIG EndpointConfig;
> +  FORMATS_CONFIG  FormatsConfig;
> +  DEVICES_INFO    DevicesInformation;
> +} ENDPOINT_DESCRIPTOR;
> +
> +//
> +// High Level Table structure
> +//
> +typedef struct {
> +  EFI_ACPI_DESCRIPTION_HEADER Header; //{'N', 'H', 'L', 'T'}
> +  UINT8                       EndpointCount;   // Actual number of endpoints
> +  ENDPOINT_DESCRIPTOR         EndpointDescriptors[1];
> +  SPECIFIC_CONFIG             OedConfiguration;
> +} NHLT_ACPI_TABLE;
> +
> +#pragma pack (pop)
> +
> +#endif // _DXE_PCH_HDA_NHLT_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioHelper
> sLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioHelper
> sLib.h
> new file mode 100644
> index 0000000000..9e0658331f
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioHelper
> sLib.h
> @@ -0,0 +1,97 @@
> +/** @file
> +  Header file for GPIO Helpers Lib implementation.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _GPIO_HELPERS_LIB_H_
> +#define _GPIO_HELPERS_LIB_H_
> +
> +#include <GpioConfig.h>
> +
> +/**
> +  This procedure stores GPIO pad unlock information
> +
> +  @param[in] GpioPad         GPIO pad
> +  @param[in] GpioLockConfig  GPIO Lock Configuration
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioStoreUnlockData (
> +  IN GPIO_PAD             GpioPad,
> +  IN GPIO_LOCK_CONFIG     GpioLockConfig
> +  );
> +
> +/**
> +  This procedure stores GPIO group data about pads which PadConfig needs
> to be unlocked.
> +
> +  @param[in]  GroupIndex          GPIO group index
> +  @param[in]  DwNum               DWORD index for a group.
> +                                  For group which has less then 32 pads per group
> DwNum must be 0.
> +  @param[in]  PadsToLock          DWORD bitmask for pads which are going
> to be left unlocked
> +                                  Bit position - PadNumber
> +                                  Bit value - 0: Skip, 1: Leave unlocked
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioStoreGroupDwUnlockPadConfigData (
> +  IN UINT32                       GroupIndex,
> +  IN UINT32                       DwNum,
> +  IN UINT32                       UnlockedPads
> +  );
> +
> +/**
> +  This procedure stores GPIO group data about pads which Output state
> needs to be unlocked.
> +
> +  @param[in]  GroupIndex          GPIO group index
> +  @param[in]  DwNum               DWORD index for a group.
> +                                  For group which has less then 32 pads per group
> DwNum must be 0.
> +  @param[in]  PadsToLock          DWORD bitmask for pads which are going
> to be left unlocked
> +                                  Bit position - PadNumber
> +                                  Bit value - 0: Skip, 1: Leave unlocked
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioStoreGroupDwUnlockOutputData (
> +  IN UINT32                       GroupIndex,
> +  IN UINT32                       DwNum,
> +  IN UINT32                       UnlockedPads
> +  );
> +
> +/**
> +  This procedure will get GPIO group data with pads, which PadConfig is
> supposed to be left unlock
> +
> +  @param[in]  GroupIndex          GPIO group index
> +  @param[in]  DwNum               DWORD index for a group.
> +                                  For group which has less then 32 pads per group
> DwNum must be 0.
> +  @retval     UnlockedPads        DWORD bitmask for pads which are going to
> be left unlocked
> +                                  Bit position - PadNumber
> +                                  Bit value - 0: to be locked, 1: Leave unlocked
> +**/
> +UINT32
> +GpioGetGroupDwUnlockPadConfigMask (
> +  IN UINT32                       GroupIndex,
> +  IN UINT32                       DwNum
> +  );
> +
> +/**
> +  This procedure will get GPIO group data with pads, which Output is
> supposed to be left unlock
> +
> +  @param[in]  GroupIndex          GPIO group index
> +  @param[in]  DwNum               DWORD index for a group.
> +                                  For group which has less then 32 pads per group
> DwNum must be 0.
> +  @retval     UnlockedPads        DWORD bitmask for pads which are going to
> be left unlocked
> +                                  Bit position - PadNumber
> +                                  Bit value - 0: to be locked, 1: Leave unlocked
> +**/
> +UINT32
> +GpioGetGroupDwUnlockOutputMask (
> +  IN UINT32                       GroupIndex,
> +  IN UINT32                       DwNum
> +  );
> +#endif // _GPIO_HELPERS_LIB_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioNameB
> ufferLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioName
> BufferLib.h
> new file mode 100644
> index 0000000000..a6ab42e4d5
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioName
> BufferLib.h
> @@ -0,0 +1,25 @@
> +/** @file
> +  Header file for GpioMemLib. This library provides GpioLib with static
> memory to hold GpioName.
> +  Static memory is handled differently in PEI and DXE phase. For PEI pre mem
> we use private HOB to store
> +  gpio name since .data section is read only. For PEI post mem and DXE simple
> static buffer is used.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _GPIO_NAME_BUFFER_LIB_H_
> +#define _GPIO_NAME_BUFFER_LIB_H_
> +
> +#define GPIO_NAME_LENGTH_MAX  32
> +
> +/**
> +  Returns pointer to the global buffer to be used by GpioNamesLib
> +
> +  @retval CHAR8*  Pointer to the buffer
> +**/
> +CHAR8*
> +GpioGetStaticNameBuffer (
> +  VOID
> +  );
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioPrivate
> Lib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioPrivate
> Lib.h
> new file mode 100644
> index 0000000000..245618ff6d
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioPrivate
> Lib.h
> @@ -0,0 +1,1061 @@
> +/** @file
> +  Header file for GpioPrivateLib.
> +  All function in this library is available for PEI, DXE, and SMM,
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _GPIO_PRIVATE_LIB_H_
> +#define _GPIO_PRIVATE_LIB_H_
> +
> +#include <GpioConfig.h>
> +#include <Library/PchPcrLib.h>
> +
> +//
> +// Structure for native pin data
> +//
> +typedef struct {
> +  GPIO_PAD       Pad;
> +  GPIO_PAD_MODE  Mode;
> +} GPIO_PAD_NATIVE_FUNCTION;
> +
> +//
> +// Below defines are based on GPIO_CONFIG structure fields
> +//
> +#define B_GPIO_PAD_MODE_MASK                            0xF
> +#define N_GPIO_PAD_MODE_BIT_POS                         0
> +#define B_GPIO_HOSTSW_OWN_MASK                          0x3
> +#define N_GPIO_HOSTSW_OWN_BIT_POS                       0
> +#define B_GPIO_DIRECTION_MASK                           0x1F
> +#define B_GPIO_DIRECTION_DIR_MASK                       0x7
> +#define N_GPIO_DIRECTION_DIR_BIT_POS                    0
> +#define B_GPIO_DIRECTION_INV_MASK                       0x18
> +#define N_GPIO_DIRECTION_INV_BIT_POS                    3
> +#define B_GPIO_OUTPUT_MASK                              0x3
> +#define N_GPIO_OUTPUT_BIT_POS                           0
> +#define N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS            0
> +#define N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS              5
> +#define B_GPIO_RESET_CONFIG_RESET_MASK                  0x3F
> +#define N_GPIO_RESET_CONFIG_OLD_RESET_TYPE              BIT1
> +#define B_GPIO_RESET_CONFIG_OLD_RESET_MASK              0xF
> +#define N_GPIO_RESET_CONFIG_RESET_BIT_POS               0
> +#define B_GPIO_RESET_CONFIG_GPD_RESET_MASK              (BIT5 | BIT4)
> +#define B_GPIO_RESET_CONFIG_GPP_RESET_MASK              (BIT3 | BIT2)
> +#define N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS    0
> +#define N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS               0
> +
> +//
> +// Structure for storing information about registers offset, community,
> +// maximal pad number for available groups
> +//
> +typedef struct {
> +  PCH_SBI_PID  Community;
> +  UINT16       PadOwnOffset;
> +  UINT16       HostOwnOffset;
> +  UINT16       GpiIsOffset;
> +  UINT16       GpiIeOffset;
> +  UINT16       GpiGpeStsOffset;
> +  UINT16       GpiGpeEnOffset;
> +  UINT16       SmiStsOffset;
> +  UINT16       SmiEnOffset;
> +  UINT16       NmiStsOffset;
> +  UINT16       NmiEnOffset;
> +  UINT16       PadCfgLockOffset;
> +  UINT16       PadCfgLockTxOffset;
> +  UINT16       PadCfgOffset;
> +  UINT16       PadPerGroup;
> +} GPIO_GROUP_INFO;
> +
> +//
> +// If in GPIO_GROUP_INFO structure certain register doesn't exist
> +// it will have value equal to NO_REGISTER_FOR_PROPERTY
> +//
> +#define NO_REGISTER_FOR_PROPERTY 0xFFFF
> +
> +/**
> +  This procedure will retrieve address and length of GPIO info table
> +
> +  @param[out]  GpioGroupInfoTableLength   Length of GPIO group table
> +
> +  @retval Pointer to GPIO group table
> +**/
> +CONST GPIO_GROUP_INFO*
> +GpioGetGroupInfoTable (
> +  OUT UINT32              *GpioGroupInfoTableLength
> +  );
> +
> +typedef struct {
> +  CONST CHAR8*    GpioGroupPrefix;
> +  CONST GPIO_PAD  FirstUniqueGpio;
> +  CONST CHAR8**   GroupUniqueNames;
> +  CONST UINT32    UniqueNamesTableSize;
> +} GPIO_GROUP_NAME_INFO;
> +
> +//
> +// Helper macros for initializing GPIO_GROUP_NAME_INFO structures
> +//
> +#define
> GPIO_GROUP_NAME(GroupName,FirstUniqueGpio,GroupUniqueNamesTabl
> e) \
> +  {GroupName, FirstUniqueGpio, GroupUniqueNamesTable, ARRAY_SIZE
> (GroupUniqueNamesTable)}
> +
> +#define GPIO_GROUP_NAME_BASIC(GroupName) \
> +  {GroupName, 0, NULL, 0}
> +
> +/**
> +  Returns GPIO_GROUP_NAME_INFO corresponding to the give GpioPad
> +
> +  @param[in]  GroupIndex  Group index
> +
> +  @retval  GPIO_GROUP_NAME_INFO*  Pointer to the
> GPIO_GROUP_NAME_INFO
> +  @retval  NULL                   If no group descriptor was found
> +**/
> +CONST
> +GPIO_GROUP_NAME_INFO*
> +GpioGetGroupNameInfo (
> +  IN UINT32  GroupIndex
> +  );
> +
> +/**
> +  Get GPIO Chipset ID specific to PCH generation and series
> +**/
> +UINT32
> +GpioGetThisChipsetId (
> +  VOID
> +  );
> +
> +/**
> +  This procedure is used to check if GpioPad is valid for certain chipset
> +
> +  @param[in]  GpioPad             GPIO pad
> +
> +  @retval TRUE                    This pin is valid on this chipset
> +          FALSE                   Incorrect pin
> +**/
> +BOOLEAN
> +GpioIsCorrectPadForThisChipset (
> +  IN  GPIO_PAD        GpioPad
> +  );
> +
> +/**
> +  Generates GPIO name from GpioPad
> +  This function returns pointer to the static buffer.
> +
> +  @param[in] GpioPad  GpioPad
> +
> +  @retval CHAR8*  Pointer to the GPIO name
> +**/
> +CHAR8*
> +GpioName (
> +  IN GPIO_PAD  GpioPad
> +  );
> +
> +/**
> +  This procedure will get value of selected gpio register
> +
> +  @param[in]  Group               GPIO group number
> +  @param[in]  Offset              GPIO register offset
> +  @param[out] RegVal              Value of gpio register
> +
> +  @retval EFI_SUCCESS             The function completed successfully
> +  @retval EFI_INVALID_PARAMETER   Invalid group or pad number
> +**/
> +EFI_STATUS
> +GpioGetReg (
> +  IN  GPIO_GROUP              Group,
> +  IN  UINT32                  Offset,
> +  OUT UINT32                  *RegVal
> +  );
> +
> +/**
> +  This procedure will set value of selected gpio register
> +
> +  @param[in] Group               GPIO group number
> +  @param[in] Offset              GPIO register offset
> +  @param[in] RegVal              Value of gpio register
> +
> +  @retval EFI_SUCCESS            The function completed successfully
> +  @retval EFI_INVALID_PARAMETER  Invalid group or pad number
> +**/
> +EFI_STATUS
> +GpioSetReg (
> +  IN GPIO_GROUP              Group,
> +  IN UINT32                  Offset,
> +  IN UINT32                  RegVal
> +  );
> +
> +/**
> +  This procedure is used by PchSmiDispatcher and will return information
> +  needed to register GPI SMI.
> +
> +  @param[in]  Index                   GPI SMI number
> +  @param[out] GpioPin                 GPIO pin
> +  @param[out] GpiSmiBitOffset         GPI SMI bit position within GpiSmi
> Registers
> +  @param[out] GpiHostSwOwnRegAddress  Address of HOSTSW_OWN
> register
> +  @param[out] GpiSmiStsRegAddress     Address of GPI SMI status register
> +
> +  @retval EFI_SUCCESS             The function completed successfully
> +  @retval EFI_INVALID_PARAMETER   Invalid group or pad number
> +**/
> +EFI_STATUS
> +GpioGetPadAndSmiRegs (
> +  IN UINT32            Index,
> +  OUT GPIO_PAD         *GpioPin,
> +  OUT UINT8            *GpiSmiBitOffset,
> +  OUT UINT32           *GpiHostSwOwnRegAddress,
> +  OUT UINT32           *GpiSmiStsRegAddress
> +  );
> +
> +/**
> +  This procedure will set GPIO Driver IRQ number
> +
> +  @param[in]  Irq                 Irq number
> +
> +  @retval EFI_SUCCESS             The function completed successfully
> +  @retval EFI_INVALID_PARAMETER   Invalid IRQ number
> +**/
> +EFI_STATUS
> +GpioSetIrq (
> +  IN  UINT8          Irq
> +  );
> +
> +/**
> +  This function provides GPIO Community PortIDs
> +
> +  @param[out] NativePinsTable                Table with GPIO COMMx SBI
> PortIDs
> +
> +  @retval      Number of communities
> +**/
> +UINT32
> +GpioGetComSbiPortIds (
> +  OUT PCH_SBI_PID    **GpioComSbiIds
> +  );
> +
> +/**
> +  This procedure will perform special handling of GPP_A_12.
> +
> +  @param[in]  None
> +
> +  @retval None
> +**/
> +VOID
> +GpioA12SpecialHandling (
> +  VOID
> +  );
> +
> +//
> +// Structure which stores information needed to map GPIO Group
> +// to 1-Tier GPE. Configuration is needed both in PMC and GPIO IP.
> +// Because GPE_DWx can handle only 32 pins only single double word can
> +// be mapped at a time. Each DW for a group has different configuration in
> PMC and GPIO
> +//
> +typedef struct {
> +  GPIO_GROUP  Group;
> +  UINT8       GroupDw;
> +  UINT8       PmcGpeDwxVal;
> +  UINT8       GpioGpeDwxVal;
> +} GPIO_GROUP_TO_GPE_MAPPING;
> +
> +/**
> +  Get information for GPIO Group required to program GPIO and PMC for
> desired 1-Tier GPE mapping
> +
> +  @param[out] GpioGroupToGpeMapping        Table with GPIO Group to
> GPE mapping
> +  @param[out] GpioGroupToGpeMappingLength  GPIO Group to GPE
> mapping table length
> +**/
> +VOID
> +GpioGetGroupToGpeMapping (
> +  OUT GPIO_GROUP_TO_GPE_MAPPING  **GpioGroupToGpeMapping,
> +  OUT UINT32                     *GpioGroupToGpeMappingLength
> +  );
> +
> +/**
> +  This procedure will return Port ID of GPIO Community from GpioPad
> +
> +  @param[in] GpioPad            GpioPad
> +
> +  @retval GpioCommunityPortId   Port ID of GPIO Community
> +**/
> +UINT8
> +GpioGetGpioCommunityPortIdFromGpioPad (
> +  IN GPIO_PAD        GpioPad
> +  );
> +
> +/**
> +  This procedure will return PadCfg address from GpioPad
> +
> +  @param[in] GpioPad            GpioPad
> +
> +  @retval GpioPadCfgAddress     PadCfg Address of GpioPad
> +**/
> +UINT32
> +GpioGetGpioPadCfgAddressFromGpioPad (
> +  IN GPIO_PAD        GpioPad
> +  );
> +
> +/**
> +  This procedure is used to unlock all GPIO pads.
> +  This function can only be called when platform is still in HOSTIA_BOOT_SAI.
> +**/
> +VOID
> +GpioUnlockAllPads (
> +  VOID
> +  );
> +
> +/**
> +  This procedure will check if GpioPad is owned by host.
> +
> +  @param[in] GpioPad       GPIO pad
> +
> +  @retval TRUE             GPIO pad is owned by host
> +  @retval FALSE            GPIO pad is not owned by host and should not be
> used with GPIO lib API
> +**/
> +BOOLEAN
> +GpioIsPadHostOwned (
> +  IN GPIO_PAD             GpioPad
> +  );
> +
> +
> +/**
> +  This procedure will check if GpioPad argument is valid.
> +  Function will check below conditions:
> +   - GpioPad represents a pad for current PCH
> +   - GpioPad belongs to valid GpioGroup
> +   - GPIO PadNumber is not greater than number of pads for this group
> +
> +  @param[in] GpioPad       GPIO pad
> +
> +  @retval TRUE             GPIO pad is valid and can be used with GPIO lib API
> +  @retval FALSE            GPIO pad is invalid and cannot be used with GPIO lib
> API
> +**/
> +BOOLEAN
> +GpioIsPadValid (
> +  IN GPIO_PAD             GpioPad
> +  );
> +
> +/**
> +  This procedure will read GPIO Pad Configuration register
> +
> +  @param[in] GpioPad          GPIO pad
> +  @param[in] DwReg            Choose PADCFG register: 0:DW0, 1:DW1
> +
> +  @retval PadCfgRegValue      PADCFG_DWx value
> +**/
> +UINT32
> +GpioReadPadCfgReg (
> +  IN GPIO_PAD             GpioPad,
> +  IN UINT8                DwReg
> +  );
> +
> +/**
> +  This procedure will write or read GPIO Pad Configuration register
> +
> +  @param[in] GpioPad              GPIO pad
> +  @param[in] DwReg                Choose PADCFG register: 0:DW0, 1:DW1
> +  @param[in] PadCfgAndMask        Mask to be AND'ed with PADCFG reg
> value
> +  @param[in] PadCfgOrMask         Mask to be OR'ed with PADCFG reg value
> +
> +  @retval none
> +**/
> +VOID
> +GpioWritePadCfgReg (
> +  IN GPIO_PAD             GpioPad,
> +  IN UINT8                DwReg,
> +  IN UINT32               PadCfgAndMask,
> +  IN UINT32               PadCfgOrMask
> +  );
> +
> +/**
> +  This procedure will set GPIO mode
> +
> +  @param[in]  GpioPad             GPIO pad
> +  @param[out] PadModeValue        GPIO pad mode value
> +
> +  @retval EFI_SUCCESS             The function completed successfully
> +  @retval EFI_INVALID_PARAMETER   Invalid group or pad number
> +**/
> +EFI_STATUS
> +GpioSetPadMode (
> +  IN GPIO_PAD                GpioPad,
> +  IN GPIO_PAD_MODE           PadModeValue
> +  );
> +
> +/**
> +  This procedure will get GPIO mode
> +
> +  @param[in]  GpioPad             GPIO pad
> +  @param[out] PadModeValue        GPIO pad mode value
> +
> +  @retval EFI_SUCCESS             The function completed successfully
> +  @retval EFI_INVALID_PARAMETER   Invalid group or pad number
> +**/
> +EFI_STATUS
> +GpioGetPadMode (
> +  IN  GPIO_PAD                 GpioPad,
> +  OUT GPIO_PAD_MODE            *PadModeValue
> +  );
> +
> +/**
> +  This procedure will check if group is within DeepSleepWell.
> +
> +  @param[in]  Group               GPIO Group
> +
> +  @retval GroupWell               TRUE:  This is DSW Group
> +                                  FALSE: This is not DSW Group
> +**/
> +BOOLEAN
> +GpioIsDswGroup (
> +  IN  GPIO_GROUP         Group
> +  );
> +
> +/**
> +  The function performs GPIO Power Management programming.
> +**/
> +VOID
> +GpioConfigurePm (
> +  VOID
> +  );
> +
> +/**
> +  This function sets SerialIo I2C controller pins into native mode
> +
> +  @param[in]  SerialIoI2cControllerNumber   I2C controller
> +  @param[in]  GpioTermination               GPIO termination type
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableSerialIoI2c (
> +  IN  UINT32                  SerialIoI2cControllerNumber,
> +  IN  GPIO_ELECTRICAL_CONFIG  GpioTermination
> +  );
> +
> +/**
> +  This function sets SerialIo UART controller pins into native mode
> +
> +  @param[in]  SerialIoUartControllerNumber   UART controller
> +  @param[in]  HardwareFlowControl            Hardware Flow control
> +  @param[in]  PinMuxing                      UART controller pin muxing
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableSerialIoUart (
> +  IN  UINT32            SerialIoUartControllerNumber,
> +  IN  BOOLEAN           HardwareFlowControl,
> +  IN  UINT32            PinMuxing
> +  );
> +
> +/**
> +  This function sets SerialIo SPI controller pins into native mode
> +
> +  @param[in]  SerialIoSpiControllerNumber   SPI controller
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableSerialIoSpi (
> +  IN  UINT32            SerialIoSpiControllerNumber
> +  );
> +
> +/**
> +  This function sets ISH I2C controller pins into native mode
> +
> +  @param[in]  IshI2cControllerNumber   I2C controller
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableIshI2c (
> +  IN  UINT32            IshI2cControllerNumber
> +  );
> +
> +/**
> +  This function sets ISH UART controller pins into native mode
> +
> +  @param[in]  IshUartControllerNumber   UART controller
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableIshUart (
> +  IN  UINT32            IshUartControllerNumber
> +  );
> +
> +/**
> +  This function sets ISH SPI controller pins into native mode
> +
> +  @param[in]  IshSpiControllerNumber   SPI controller
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableIshSpi (
> +  IN  UINT32            IshSpiControllerNumber
> +  );
> +
> +/**
> +  This function sets ISH GP pin into native mode
> +
> +  @param[in]  IshGpPinNumber   ISH GP pin number
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableIshGpPin (
> +  IN  UINT32            IshGpPinNumber
> +  );
> +
> +/**
> +  This function sets SCS SD card controller pins into native mode
> +
> +  @param[in]  none
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableScsSdCard (
> +  VOID
> +  );
> +
> +/**
> +  This function enables SCS SD Card controller card detect pin
> +
> +  @param[in]  none
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableScsSdCardDetect (
> +  VOID
> +  );
> +
> +/**
> +  This function sets SCS eMMC controller pins into native mode
> +
> +  @param[in]  none
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableScsEmmc (
> +  VOID
> +  );
> +
> +/**
> +  This function sets HDA Link pins into native mode
> +
> +  @param[in]  none
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableHdaLink (
> +  VOID
> +  );
> +
> +/**
> +  This function sets HDA DMIC pins into native mode
> +
> +  @param[in]  DmicNumber   DMIC number
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableHdaDmic (
> +  IN  UINT32            DmicNumber
> +  );
> +
> +/**
> +  This function sets HDA SSP interface pins into native mode
> +
> +  @param[in]  SspInterfaceNumber   SSPx interface number
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableHdaSsp (
> +  IN  UINT32            SspInterfaceNumber
> +  );
> +
> +/**
> +  This function sets HDA SSP Master Clock into native mode
> +
> +  @param[in]  none
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableHdaSspMasterClock (
> +  VOID
> +  );
> +
> +/**
> +  This function sets HDA SoundWire interface pins into native mode
> +
> +  @param[in]  SndwInterfaceNumber   SNDWx interface number
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableHdaSndw (
> +  IN  UINT32            SndwInterfaceNumber
> +  );
> +
> +/**
> +  This function sets SMBUS controller pins into native mode
> +
> +  @param[in]  none
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableSmbus (
> +  VOID
> +  );
> +
> +/**
> +  This function sets SMBUS ALERT pins into native mode
> +
> +  @param[in]  none
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableSmbusAlert (
> +  VOID
> +  );
> +
> +/**
> +  This function enables USB OverCurrent pins by setting
> +  USB2 OCB pins into native mode
> +
> +  @param[in]  OcPinNumber            USB OC pin number
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableUsbOverCurrent (
> +  IN  UINTN   OcPinNumber
> +  );
> +
> +/**
> +  This function sets SATA DevSlp pins into native mode
> +
> +  @param[in]  SataCtrlIndex       SATA controller index
> +  @param[in]  SataPort            SATA port number
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableSataDevSlpPin (
> +  IN  UINT32  SataCtrlIndex,
> +  IN  UINTN   SataPort
> +  );
> +
> +/**
> +  This function checks if SataDevSlp pin is in native mode
> +
> +  @param[in]  SataCtrlIndex       SATA controller index
> +  @param[in]  SataPort            SATA port
> +  @param[out] DevSlpPad           DevSlpPad
> +                                  This is an optional parameter and may be NULL.
> +
> +  @retval TRUE                    DevSlp is in native mode
> +          FALSE                   DevSlp is not in native mode
> +**/
> +BOOLEAN
> +GpioIsSataDevSlpPinEnabled (
> +  IN  UINT32          SataCtrlIndex,
> +  IN  UINTN           SataPort,
> +  OUT GPIO_PAD        *DevSlpPad  OPTIONAL
> +  );
> +
> +/**
> +  This function sets SATAGPx pin into native mode
> +
> +  @param[in]  SataCtrlIndex       SATA controller index
> +  @param[in]  SataPort            SATA port number
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableSataGpPin (
> +  IN  UINT32  SataCtrlIndex,
> +  IN  UINTN   SataPort
> +  );
> +
> +/**
> +  This function provides SATA GP pin data
> +
> +  @param[in]  SataCtrlIndex       SATA controller index
> +  @param[in]  SataPort            SATA port number
> +  @param[out] NativePin           SATA GP pin
> +**/
> +VOID
> +GpioGetSataGpPin (
> +  IN  UINT32                    SataCtrlIndex,
> +  IN  UINTN                     SataPort,
> +  OUT GPIO_PAD_NATIVE_FUNCTION  *NativePin
> +  );
> +
> +/**
> +  This function sets SATA LED pin into native mode. SATA LED indicates
> +  SATA controller activity
> +
> +  @param[in]  none
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableSataLed (
> +  VOID
> +  );
> +
> +/**
> +  Returns pad for given CLKREQ# index.
> +
> +  @param[in]  ClkreqIndex       CLKREQ# number
> +
> +  @return CLKREQ# pad.
> +**/
> +GPIO_PAD
> +GpioGetClkreqPad (
> +  IN     UINT32   ClkreqIndex
> +  );
> +
> +/**
> +  Enables CLKREQ# pad in native mode.
> +
> +  @param[in]  ClkreqIndex       CLKREQ# number
> +
> +  @return none
> +**/
> +VOID
> +GpioEnableClkreq (
> +  IN     UINT32   ClkreqIndex
> +  );
> +
> +/**
> +  This function sets PCHHOT pin into native mode
> +
> +  @param[in]  none
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnablePchHot (
> +  VOID
> +  );
> +
> +/**
> +  This function sets VRALERTB pin into native mode
> +
> +  @param[in]  none
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableVrAlert (
> +  VOID
> +  );
> +
> +/**
> +  This function sets CPU GP pins into native mode
> +
> +  @param[in]  CpuGpPinNum               CPU GP pin number
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableCpuGpPin (
> +  IN  UINT32                            CpuGpPinNum
> +  );
> +
> +/**
> +This function sets CPU C10 Gate pins into native mode
> +
> +@retval Status
> +**/
> +EFI_STATUS
> +GpioEnableCpuC10GatePin (
> +  VOID
> +  );
> +
> +//
> +// DDSP_HPD pins
> +//
> +typedef enum {
> +  GpioDdspHpd0 = 0x00,
> +  GpioDdspHpd1 = 0x01,
> +  GpioDdspHpd2 = 0x02,
> +  GpioDdspHpd3 = 0x03,
> +  GpioDdspHpd4 = 0x04,
> +  GpioDdspHpdA = 0x10,
> +  GpioDdspHpdB = 0x11,
> +  GpioDdspHpdC = 0x12
> +} GPIO_DDSP_HPD;
> +
> +/**
> +  This function sets DDSP_HPDx pin into native mode
> +
> +  @param[in]  DdspHpdPin     DDSP_HPDx pin
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableDpHotPlugDetect (
> +  IN GPIO_DDSP_HPD  DdspHpdPin
> +  );
> +
> +/**
> +  This function sets HPD, VDDEN, BKLTEN and BKLTCTL pins into native mode
> for eDP Panel
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableEdpPins (
> +  VOID
> +  );
> +
> +//
> +// DDPx pins
> +//
> +typedef enum {
> +  GpioDdp1 = 0x01,
> +  GpioDdp2 = 0x02,
> +  GpioDdp3 = 0x03,
> +  GpioDdp4 = 0x04,
> +  GpioDdpA = 0x10,
> +  GpioDdpB = 0x11,
> +  GpioDdpC = 0x12,
> +  GpioDdpD = 0x13,
> +  GpioDdpF = 0x15,
> +} GPIO_DDP;
> +
> +/**
> +  This function sets DDP pins into native mode
> +
> +  @param[in]  DdpInterface   DDPx interface
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableDpInterface (
> +  IN  GPIO_DDP            DdpInterface
> +  );
> +
> +/**
> +  This function configures GPIO connection between CNVi and CRF
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioConfigureCnviCrfConnection (
> +  VOID
> +  );
> +
> +/**
> +  This function enables CNVi RF Reset pin
> +**/
> +VOID
> +GpioEnableCnviRfResetPin (
> +  VOID
> +  );
> +
> +/**
> +  This function enables CNVi MODEM CLKREQ pin
> +**/
> +VOID
> +GpioEnableCnviModemClkReqPin (
> +  VOID
> +  );
> +
> +/**
> +  CNVi Bluetooth UART connection options
> +**/
> +typedef enum {
> +  GpioCnviBtUartNotConnected,
> +  GpioCnviBtUartToSerialIoUart0,
> +  GpioCnviBtUartToIshUart0,
> +  GpioCnviBtUartToExternalPads
> +} VGPIO_CNVI_BT_UART_CONNECTION_TYPE;
> +
> +/**
> +  This function configures virtual GPIO connection for CNVi Bluetooth UART
> +
> +  @param[in]  ConnectionType
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioConfigureCnviBtUartConnection (
> +  IN  VGPIO_CNVI_BT_UART_CONNECTION_TYPE  ConnectionType
> +  );
> +
> +/**
> +  CNVi Bluetooth I2S connection options
> +**/
> +typedef enum {
> +  GpioCnviBtI2sNotConnected,
> +  GpioCnviBtI2sToSsp0,
> +  GpioCnviBtI2sToSsp1,
> +  GpioCnviBtI2sToSsp2,
> +  GpioCnviBtI2sToExternalPads
> +} VGPIO_CNVI_BT_I2S_CONNECTION_TYPE;
> +
> +/**
> +  This function configures virtual GPIO connection for CNVi Bluetooth I2S
> +
> +  @param[in]  ConnectionType
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioConfigureCnviBtI2sConnection (
> +  IN  VGPIO_CNVI_BT_I2S_CONNECTION_TYPE  ConnectionType
> +  );
> +
> +/**
> +  CNVi MultiFunction UART connection options
> +**/
> +typedef enum {
> +  GpioCnviMfUart1NotConnected,
> +  GpioCnviMfUart1ToSerialIoUart2,
> +  GpioCnviMfUart1ToIshUart0,
> +  GpioCnviMfUart1ToExternalPads
> +} VGPIO_CNVI_MF_UART1_CONNECTION_TYPE;
> +
> +/**
> +  This function configures virtual GPIO connection for CNVi MFUART1
> +
> +  @param[in]  ConnectionType
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioConfigureCnviMfUart1Connection (
> +  IN  VGPIO_CNVI_MF_UART1_CONNECTION_TYPE  ConnectionType
> +  );
> +
> +
> +/**
> +  This function sets CNVi Bluetooth Enable value
> +
> +  @param[in] Value                CNVi BT enable value
> +                                  0: Disable, 1: Enable
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioSetCnviBtEnState (
> +   IN  UINT32  Value
> +  );
> +
> +/**
> +  CNVi Bluetooth UART connection options
> +**/
> +typedef enum {
> +  GpioCnviBtIfUart = 0,
> +  GpioCnviBtIfUsb,
> +} VGPIO_CNVI_BT_INTERFACE;
> +
> +/**
> +  This function sets CNVi Bluetooth main host interface
> +
> +  @param[in] BtInterface          CNVi BT Interface Select value
> +                                  GpioCnviBtIfUart: UART, GpioCnviBtIfUsb: USB
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioSetCnviBtInterface (
> +  IN  VGPIO_CNVI_BT_INTERFACE  BtInterface
> +  );
> +
> +/**
> +  This function sets CNVi Bluetooth Wireless Charging support
> +
> +  @param[in] BtWirelessCharging   CNVi BT Wireless Charging support
> +                                  0: Normal BT operation (no Wireless Charging
> support)
> +                                  1: Enable BT Wireless Charging
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioSetCnviBtWirelessCharging (
> +  IN  UINT32  BtWirelessCharging
> +  );
> +
> +/**
> +  This function enables and configures CNVi Bluetooth Host wake-up
> interrupt
> +
> +  @param[in] None
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioConfigureCnviBtHostWakeInt (
> +  VOID
> +  );
> +
> +/**
> +  CNVi WiFi mode
> +**/
> +typedef enum {
> +  GpioCnviWiFiEnabled,
> +  GpioCnviWiFiAuto
> +} VGPIO_CNVI_WIFI_MODE;
> +
> +/**
> +  This function sets CNVi WiFi mode
> +
> +  @param[in] Value                CNVi WiFi Mode value
> +                                  GpioCnviWiFiAuto: WiFi is automatically
> enabled/disabled by WiFi core
> +                                  GpioCnviWiFiEnabled: WiFi is enabled regardless of
> WiFi core decision
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioSetCnviWifiMode (
> +  IN  VGPIO_CNVI_WIFI_MODE  WiFiMode
> +  );
> +
> +/**
> +  This function enables IMGU CLKOUT native pin
> +
> +  @param[in] None
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +GpioEnableImguClkOut (
> +  VOID
> +  );
> +
> +/**
> +  Power button debounce configuration
> +  Debounce time can be specified in microseconds. Only certain values
> according
> +  to below formula are supported:
> +   DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock period).
> +  RTC clock with f = 32 KHz is used for glitch filter.
> +   DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us).
> +  Supported DebounceTime values are following:
> +   DebounceTime = 0 -> Debounce feature disabled
> +   DebounceTime > 0 && < 250us -> Not supported
> +   DebounceTime = 250us - 1024000us -> Supported range (DebounceTime =
> 250us * 2^n)
> +  For values not supported by HW, they will be rounded down to closest
> supported one
> +
> +  @param[in] DebounceTime    Debounce Time in microseconds
> +                             If Debounce Time = 0, Debouncer feature will be
> disabled
> +                             Function will set DebounceTime argument to rounded
> supported value
> +**/
> +VOID
> +GpioSetPwrBtnDebounceTimer (
> +  IN UINT32                DebounceTime
> +  );
> +
> +/**
> +  Configure LPC GPIO
> +**/
> +VOID
> +LpcConfigureGpio (
> +  VOID
> +  );
> +
> +#endif // _GPIO_PRIVATE_LIB_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/I2cMasterC
> ommonLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/I2cMasterC
> ommonLib.h
> new file mode 100644
> index 0000000000..a4bd42f420
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/I2cMasterC
> ommonLib.h
> @@ -0,0 +1,288 @@
> +/** @file
> + Implement the I2C port control.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _I2C_MASTER_COMMON_LIB_H_
> +#define _I2C_MASTER_COMMON_LIB_H_
> +
> +///
> +/// Each I2C port instance uses an I2C_MASTER_CONTEXT structure
> +/// to maintain its context.
> +///
> +typedef struct {
> +  EFI_I2C_CONTROLLER_CAPABILITIES Capabilities;
> +  //
> +  // I2C master's mmio addresses cached to speed up operation
> +  //
> +  UINTN                           MmioAddress;
> +  UINTN                           ConfigAddress;
> +  //
> +  // copy of all pointers and data provided in StartRequest call
> +  // if transfer didn't finish in one go, those will be needed to continue it
> +  //
> +  EFI_I2C_REQUEST_PACKET          *Request;
> +  //
> +  // Internal copy of Transfer status, to be returned from StartRequest()
> +  //
> +  EFI_STATUS                      TransferStatus;
> +  //
> +  // Index (Operation:Postition in Buffer) of next operation to be performed
> +  // Write is for both R/W operations as both need to be put in fifo
> +  // Read is for Read only, for filling buffer with data retrieved from bus
> +  //
> +  UINTN                           WriteOp;
> +  UINTN                           WritePos;
> +  UINTN                           ReadOp;
> +  UINTN                           ReadPos;
> +  BOOLEAN                         TransferInProgress;
> +} I2C_MASTER_CONTEXT;
> +
> +/**
> +  Prepare I2c controller for use: enable its mmio range, put in D0, get out of
> reset
> +  Verifies I2C Line SDA and SCL states
> +
> +  @param[in] Context - driver context
> +
> +  @retval EFI_SUCCESS         Controller prepared
> +  @retval EFI_DEVICE_ERROR    SCL and/or SDA lines are not pulled up
> +**/
> +EFI_STATUS
> +PrepareController (
> +  I2C_MASTER_CONTEXT  *Context
> +  );
> +
> +/**
> +  Determine the state of the I2C controller
> +
> +  @param[in] Context - driver context
> +
> +  @retval TRUE              The I2C controller is active
> +  @retval FALSE             The I2C controller is idle
> +**/
> +BOOLEAN
> +IsHardwareActive (
> +  I2C_MASTER_CONTEXT  *Context
> +  );
> +
> +/**
> +  Updates WriteOperation and WritePosition, two variables that determine
> +  which part of Request is being committed to I2C bus.
> +  This iterates over both Read and Write operations from a request, because
> +  things that need to be written to WriteFifo are both I2c bus writes
> +  and I2c bus reads (the command to perform bus read needs to be put into
> Write Fifo)
> +
> +  @param[in] Context - driver context
> +**/
> +VOID
> +UpdateWritePosition (
> +  I2C_MASTER_CONTEXT *Context
> +  );
> +
> +/**
> +  FindReadOp checks if current Operation is of Read type. If so, returns.
> +  If not, increases ReadOp until it finds one or goes beyond Request's
> OperationCount
> +
> +  @param[in] Context - driver context
> +**/
> +VOID
> +FindReadOp (
> +  I2C_MASTER_CONTEXT *Context
> +  );
> +
> +/**
> +  Updates ReadOperation and ReadPosition, two variables that determine
> +  which part of Request is being filled with data incoming from I2C reads.
> +  This iterates only over Read operations from a request.
> +
> +  @param[in] Context - driver context
> +**/
> +VOID
> +UpdateReadPosition (
> +  I2C_MASTER_CONTEXT *Context
> +  );
> +
> +/**
> +  ValidateRequest checks if Request is valid and can be started
> +
> +  @param[in] Context            driver context
> +  @param[in] RequestPacket      content of I2C request package
> +
> +  @retval EFI_SUCCESS           Request is valid and can be started
> +  @retval EFI_ALREADY_STARTED   The controller is busy with another
> transfer
> +  @retval EFI_BAD_BUFFER_SIZE   Transfer size too big
> +  @retval EFI_INVALID_PARAMETER RequestPacket is NULL, invalid Operation
> flags
> +  @retval EFI_UNSUPPORTED       10bit I2C address or "ping" operation
> attempted (0-byte transfer, address byte not followed by any data)
> +**/
> +EFI_STATUS
> +ValidateRequest (
> +  I2C_MASTER_CONTEXT           *Context,
> +  CONST EFI_I2C_REQUEST_PACKET *RequestPacket
> +  );
> +
> +/**
> +  IsLastFromRequest checks if WritePos and WriteOp point to the last byte of
> the request
> +
> +  @param[in] Context - driver context
> +**/
> +BOOLEAN
> +IsLastFromRequest (
> +  I2C_MASTER_CONTEXT *Context
> +  );
> +
> +/**
> +  IsLastFromRequest checks if WritePos and WriteOp point to the first byte of
> an operation
> +
> +  @param[in] Context - driver context
> +
> +  @retval Boolean
> +**/
> +BOOLEAN
> +IsFirstFromOperation (
> +  I2C_MASTER_CONTEXT *Context
> +  );
> +
> +/**
> +  InitializeTransfer checks if HW is ready to accept new transfer.
> +  If so, sets up slave address
> +
> +  @param[in] Context - driver context
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +InitializeTransfer (
> +  I2C_MASTER_CONTEXT           *Context,
> +  UINTN                        SlaveAddress,
> +  CONST EFI_I2C_REQUEST_PACKET *RequestPacket
> +  );
> +
> +/**
> +  WriteFifo writes to I2c controller's transmit Fifo. Data written to Fifo could
> be
> +  - data bytes to be written to an I2C slave
> +  - read requests that trigger I2C bus reads
> +  First transfer from each operation adds Restart bit which triggers Restart
> condition on bus
> +  Last transfer from the whole Request adds Stop bit which triggers Stop
> condtion on bus
> +  Driver keeps track of which parts of Request were already committed to
> hardware using
> +  pointer consisting of WritePosition and WriteOperation variables. This
> pointer is updated
> +  every time data byte/read request is committed to FIFO
> +  WriteFifo executes while there's anything more to write and the write fifo
> isn't full
> +
> +  @param[in] Context - driver context
> +**/
> +VOID
> +WriteFifo (
> +  I2C_MASTER_CONTEXT *Context
> +  );
> +
> +/**
> +  ReadFifo reads from I2c controller's receive Fifo. It contains data retrieved
> +  from slave device as a result of executing read transfers, which were
> +  triggered by putting read requests into Write Fifo. Retrieved data is copied
> into buffers
> +  pointed to by Request structure.
> +  Driver keeps track where to copy incoming data using pointer consisting of
> +  ReadPosition and ReadOperation variables. This pointer is updated
> +  every time data was retrieved from hardware
> +  ReadFifo executes while there's data available and receive buffers were not
> filled
> +
> +  @param[in] Context - driver context
> +**/
> +VOID
> +ReadFifo (
> +  I2C_MASTER_CONTEXT *Context
> +  );
> +
> +/**
> +  CheckErrors checks if there were any transfer errors.
> +
> +  @param[in] Context - driver context
> +**/
> +VOID
> +CheckErrors (
> +  I2C_MASTER_CONTEXT *Context
> +  );
> +
> +/**
> +  Transfer is finished when all requested operations were placed in fifo,
> +  all read requests were filled and hardware is inactive
> +  The last part is necessary for write-only transfers where after
> +  placing all writes in fifo sw needs to wait until they flush down the bus
> +
> +  @param[in] Context - driver context
> +
> +  @retval Boolean
> +**/
> +BOOLEAN
> +IsTransferFinished (
> +  I2C_MASTER_CONTEXT *Context
> +  );
> +
> +/**
> +  Clean up Hw activity and errors
> +  Return status to Request's submitter and signal the event that tells
> +  it that the request is complete
> +  Clear up Sw context to allow new request to start
> +
> +  @param[in] Context - driver context
> +**/
> +VOID
> +FinishTransfer (
> +  I2C_MASTER_CONTEXT *Context
> +  );
> +
> +/**
> +  PerformTransfer. For synchronous transfer this function is called in a loop
> +  and for asynchronous transfers, as a timer callback. It writes data and/or
> +  read requests to hadrware, copies read data to destination buffers. When
> +  transfer completes, it cleans up Sw context and Hw registers in preparation
> +  for new transfer
> +
> +  @param[in] Context - driver context
> +**/
> +VOID
> +PerformTransfer (
> +  IN I2C_MASTER_CONTEXT *Context
> +  );
> +
> +/**
> +  Set the I2C controller bus clock frequency.
> +
> +  This routine must be called at or below TPL_NOTIFY.
> +
> +  The software and controller do a best case effort of using the specified
> +  frequency for the I2C bus.  If the frequency does not match exactly then
> +  the controller will use lower frequency for the I2C to avoid exceeding
> +  the operating conditions for any of the I2C devices on the bus.
> +  For example if 400 KHz was specified and the controller's divide network
> +  only supports 402 KHz or 398 KHz then the controller would be set to 398
> +  KHz.
> +
> +  @param[in] MmioAddress    Address of I2C controller
> +  @param[in] BusClockHertz  New I2C bus clock frequency in Hertz
> +
> +  @retval EFI_SUCCESS       The bus frequency was set successfully.
> +  @retval EFI_UNSUPPORTED   The controller does not support this
> frequency.
> +**/
> +
> +EFI_STATUS
> +FrequencySet (
> +  IN UINTN     MmioAddress,
> +  IN OUT UINTN *BusClockHertz
> +  );
> +
> +/**
> +  Reset the I2C controller
> +
> +  @param[in] MmioAddress    Address of I2C controller
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +I2cReset (
> +  IN UINTN     MmioAddress
> +  );
> +
> +#endif // _I2C_MASTER_COMMON_LIB_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchDmiLib.
> h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchDmiLib.
> h
> new file mode 100644
> index 0000000000..d17b65c598
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchDmiLib.
> h
> @@ -0,0 +1,344 @@
> +/** @file
> +  Header file for PchDmiLib.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_DMI_LIB_H_
> +#define _PCH_DMI_LIB_H_
> +
> +/**
> +  This function checks if DMI Secured Register Lock (SRL) is set
> +
> +  @retval SRL state
> +**/
> +BOOLEAN
> +IsPchDmiLocked (
> +  VOID
> +  );
> +
> +/**
> +  Set ACPI base address decoding in DMI
> +
> +  @param[in] Address                    Address for ACPI base.
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_INVALID_PARAMETER         Invalid base address passed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PchDmiSetAcpiBase (
> +  IN  UINT16                            Address
> +  );
> +
> +/**
> +  Set PWRM base address decoding in DMI
> +
> +  @param[in] Address                    Address for PWRM base.
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_INVALID_PARAMETER         Invalid base address passed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PchDmiSetPwrmBase (
> +  IN  UINT32                            Address
> +  );
> +
> +/**
> +  Set PCH TCO base address decoding in DMI
> +
> +  @param[in] Address                    Address for TCO base address.
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_INVALID_PARAMETER         Invalid base address passed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PchDmiSetTcoBase (
> +  IN  UINT16                            Address
> +  );
> +
> +/**
> +  Get PCH TCO base address.
> +
> +  @retval Address                   Address of TCO base address.
> +**/
> +UINT16
> +PchDmiGetTcoBase (
> +  VOID
> +  );
> +
> +/**
> +  Set PCH LPC/eSPI generic IO range decoding in DMI
> +
> +  @param[in] Address                    Address for generic IO range base
> address.
> +  @param[in] Length                     Length of generic IO range.
> +  @param[in] RangeIndex                 Index of choosen range
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PchDmiSetLpcGenIoRange (
> +  IN  UINT32                            Address,
> +  IN  UINT32                            Length,
> +  IN  UINT32                            RangeIndex
> +  );
> +
> +/**
> +  Set PCH eSPI eSPI CS1# generic IO range decoding in DMI
> +
> +  @param[in] Address                    Address for generic IO range base
> address.
> +  @param[in] Length                     Length of generic IO range.
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PchDmiSetEspiCs1GenIoRange (
> +  IN  UINT32                            Address,
> +  IN  UINT32                            Length
> +  );
> +
> +/**
> +  Clear PCH LPC/eSPI generic IO range decoding in DMI
> +
> +  @param[in] RangeIndex                 Index of chosen range
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PchDmiClearLpcGenIoRange (
> +  IN  UINTN                             RangeIndex
> +  );
> +
> +/**
> +  Clear PCH eSPI CS1# generic IO range decoding in DMI
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PchDmiClearEspiCs1GenIoRange (
> +  VOID
> +  );
> +
> +/**
> +  Set PCH LPC/eSPI memory range decoding in DMI
> +
> +  @param[in] Address                    Address for memory base address.
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PchDmiSetLpcMemRange (
> +  IN  UINT32                            Address
> +  );
> +
> +/**
> +  Set PCH eSPI CS1# memory range decoding in DMI
> +
> +  @param[in] Address                    Address for memory base address.
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PchDmiSetEspiCs1MemRange (
> +  IN  UINT32                            Address
> +  );
> +
> +/**
> +  Check if Boot BIOS Strap is set for SPI.
> +
> +  @retval TRUE                Boot BIOS Strap set for SPI
> +  @retval FALSE               Boot BIOS Strap set for LPC/eSPI
> +**/
> +BOOLEAN
> +PchDmiIsBootBiosStrapSetForSpi (
> +  VOID
> +  );
> +
> +/**
> +  Set PCH BIOS range decoding in DMI
> +  Please check EDS for detail of BiosDecodeEnable bit definition.
> +    bit 15: F8-FF Enable
> +    bit 14: F0-F8 Enable
> +    bit 13: E8-EF Enable
> +    bit 12: E0-E8 Enable
> +    bit 11: D8-DF Enable
> +    bit 10: D0-D7 Enable
> +    bit  9: C8-CF Enable
> +    bit  8: C0-C7 Enable
> +    bit  7: Legacy F Segment Enable
> +    bit  6: Legacy E Segment Enable
> +    bit  5: Reserved
> +    bit  4: Reserved
> +    bit  3: 70-7F Enable
> +    bit  2: 60-6F Enable
> +    bit  1: 50-5F Enable
> +    bit  0: 40-4F Enable
> +
> +  @param[in] BiosDecodeEnable           Bios decode enable setting.
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PchDmiSetBiosDecodeEnable (
> +  IN  UINT16                            BiosDecodeEnable
> +  );
> +
> +/**
> +  Set PCH LPC/eSPI IO decode ranges in DMI
> +  Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
> +  Bit  12: FDD range
> +  Bit 9:8: LPT range
> +  Bit 6:4: ComB range
> +  Bit 2:0: ComA range
> +
> +  @param[in] LpcIoDecodeRanges          LPC/eSPI IO decode ranges bit
> settings.
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PchDmiSetLpcIoDecodeRanges (
> +  IN  UINT16                            LpcIoDecodeRanges
> +  );
> +
> +/**
> +  Set PCH LPC/eSPI IO enable decoding in DMI
> +
> +  @param[in] LpcIoEnableDecoding        LPC/eSPI IO enable decoding bit
> settings.
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PchDmiSetLpcIoEnable (
> +  IN  UINT16                            LpcIoEnableDecoding
> +  );
> +
> +/**
> +  Set PCH IO port 80h cycle decoding to PCIE root port in DMI
> +
> +  @param[in] RpNumber                   PCIE root port physical number.
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +**/
> +EFI_STATUS
> +PchDmiSetIoPort80Decode (
> +  IN  UINTN                             RpNumber
> +  );
> +
> +/**
> +  Set DMI thermal throttling to recommended configuration
> +**/
> +VOID
> +PchDmiSetRecommendedThermalThrottling (
> +  VOID
> +  );
> +
> +//
> +// Thermal Sensor Target Width structure
> +// Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values
> +//
> +typedef struct {
> +  UINT32  ThermalSensor0TargetWidth :3;
> +  UINT32  ThermalSensor1TargetWidth :3;
> +  UINT32  ThermalSensor2TargetWidth :3;
> +  UINT32  ThermalSensor3TargetWidth :3;
> +  UINT32  Rsvd                      :20;
> +} DMI_THERMAL_THROTTLING;
> +
> +/**
> +  Set DMI thermal throttling to custom configuration.
> +  This function will configure Thermal Sensor 0/1/2/3 TargetWidth and set
> +  DMI Thermal Sensor Autonomous Width Enable.
> +
> +  @param[in] DmiThermalThrottling        DMI Thermal Throttling structure.
> +**/
> +VOID
> +PchDmiSetCustomThermalThrottling (
> +  IN DMI_THERMAL_THROTTLING      DmiThermalThrottling
> +  );
> +
> +/**
> +  Determines where to send the reserved page registers
> +  Accesses to the I/O ranges 80h - 8Fh will be forwarded to PCIe Root Port
> +  with the destination ID specified in GCS.RPRDID using DMI source decode.
> +**/
> +VOID
> +PchDmiSetReservedPageRegToPcieRootPort (
> +  VOID
> +  );
> +
> +/**
> +  Determines where to send the reserved page registers
> +  DMI will not perform source decode on the I/O ranges 80h - 8Fh. The cycles
> hitting these ranges will
> +  end up in P2SB which will then forward the cycle to LPC or eSPI through IOSF
> Sideband.
> +**/
> +VOID
> +PchDmiSetReservedPageRegToLpc (
> +  VOID
> +  );
> +
> +/**
> +  uCode Patch Region Enable (UPRE). Enables memory access targeting the
> uCode patch region (0xFEF00000 to 0xFEFFFFFF)
> +  to be forwarded to SPI Flash. This can only be set if the boot flash is on SPI.
> +**/
> +VOID
> +PchDmiEnableUCodePatchRegion (
> +  VOID
> +  );
> +
> +/**
> +  Enable PCIe Relaxed Order
> +**/
> +VOID
> +PchDmiEnablePcieRelaxedOrder (
> +  VOID
> +  );
> +
> +/**
> +  This function will switch SAI value to be driven to IOSF Primary Fabric
> +  for cycles with Core BDF from HOSTIA_BOOT_SAI to HOSTIA_POSTBOOT_SAI.
> +  To be used when PCH is paired with CFL CPU.
> +**/
> +VOID
> +PchDmiEnablePostBootSai (
> +  VOID
> +  );
> +
> +/**
> +  This function will do necessary configuration after platform
> +  should have switched to POSTBOOT_SAI. It needs to be called even if
> +  POSTBOOT_SAI was not set.
> +**/
> +VOID
> +PchDmiConfigAfterPostBootSai (
> +  VOID
> +  );
> +
> +/**
> +  Configure PCH DMI Lock
> +**/
> +VOID
> +PchDmiSetLockWithS3BootScript (
> +  VOID
> +  );
> +
> +/**
> +  Set BIOS interface Lock-Down
> +**/
> +VOID
> +PchDmiSetBiosLockDownWithS3BootScript (
> +  VOID
> +  );
> +#endif // _PCH_DMI_LIB_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchHdaLib.
> h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchHdaLib.
> h
> new file mode 100644
> index 0000000000..e53ed881df
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchHdaLib.
> h
> @@ -0,0 +1,56 @@
> +/** @file
> +  This library provides PCH HD Audio functions.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_HDA_LIB_H_
> +#define _PCH_HDA_LIB_H_
> +
> +#include <Private/Library/DxePchHdaNhlt.h>
> +#include <Private/PchHdaEndpoints.h>
> +
> +/**
> +  Prints NHLT (Non HDA-Link Table) to be exposed via ACPI (aka. OED (Offload
> Engine Driver) Configuration Table).
> +
> +  @param[in] *NhltAcpiTable    The NHLT table to print
> +**/
> +VOID
> +NhltAcpiTableDump(
> +  IN NHLT_ACPI_TABLE           *NhltTable
> +  );
> +
> +/**
> +  Constructs EFI_ACPI_DESCRIPTION_HEADER structure for NHLT table.
> +
> +  @param[in][out] *NhltTable            NHLT table for which header will be
> created
> +  @param[in]      NhltTableSize         Size of NHLT table
> +
> +  @retval None
> +**/
> +VOID
> +NhltAcpiHeaderConstructor (
> +  IN OUT NHLT_ACPI_TABLE        *NhltTable,
> +  IN UINT32                     NhltTableSize
> +  );
> +
> +/**
> +  Constructs NHLT_ACPI_TABLE structure based on given Endpoints list.
> +
> +  @param[in]      *EndpointTable List of endpoints for NHLT
> +  @param[in][out] **NhltTable    NHLT table to be created
> +  @param[in][out] *NhltTableSize Size of created NHLT table
> +
> +  @retval EFI_SUCCESS            NHLT created successfully
> +  @retval EFI_BAD_BUFFER_SIZE    Not enough resources to allocate NHLT
> +**/
> +EFI_STATUS
> +NhltConstructor(
> +  IN PCH_HDA_NHLT_ENDPOINTS    *EndpointTable,
> +  IN OUT NHLT_ACPI_TABLE       **NhltTable,
> +  IN OUT UINT32                *NhltTableSize
> +  );
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchInitCom
> monLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchInitCom
> monLib.h
> new file mode 100644
> index 0000000000..6d71504772
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchInitCom
> monLib.h
> @@ -0,0 +1,100 @@
> +/** @file
> +  Header file for PCH Init Common Lib
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_INIT_COMMON_LIB_H_
> +#define _PCH_INIT_COMMON_LIB_H_
> +
> +#include <Library/PchPcrLib.h>
> +
> +/**
> +  This function returns PID according to PCIe controller index
> +
> +  @param[in] ControllerIndex     PCIe controller index
> +
> +  @retval PCH_SBI_PID    Returns PID for SBI Access
> +**/
> +PCH_SBI_PID
> +PchGetPcieControllerSbiPid (
> +  IN  UINT32  ControllerIndex
> +  );
> +
> +/**
> +  This function returns PID according to Root Port Number
> +
> +  @param[in] RpPort             Root Port Number
> +
> +  @retval PCH_SBI_PID    Returns PID for SBI Access
> +**/
> +PCH_SBI_PID
> +GetRpSbiPid (
> +  IN  UINTN  RpPort
> +  );
> +
> +/**
> +  Calculate root port device number based on physical port index.
> +
> +  @param[in]  RpIndex              Root port index (0-based).
> +
> +  @retval     Root port device number.
> +**/
> +UINT32
> +PchGetPcieRpDevice (
> +  IN  UINT32   RpIndex
> +  );
> +
> +/**
> +  This function reads Pci Config register via SBI Access
> +
> +  @param[in]  RpIndex             Root Port Index (0-based)
> +  @param[in]  Offset              Offset of Config register
> +  @param[out] *Data32             Value of Config register
> +
> +  @retval EFI_SUCCESS             SBI Read successful.
> +**/
> +EFI_STATUS
> +PchSbiRpPciRead32 (
> +  IN    UINT32  RpIndex,
> +  IN    UINT32  Offset,
> +  OUT   UINT32  *Data32
> +  );
> +
> +/**
> +  This function And then Or Pci Config register via SBI Access
> +
> +  @param[in]  RpIndex             Root Port Index (0-based)
> +  @param[in]  Offset              Offset of Config register
> +  @param[in]  Data32And           Value of Config register to be And-ed
> +  @param[in]  Data32AOr           Value of Config register to be Or-ed
> +
> +  @retval EFI_SUCCESS             SBI Read and Write successful.
> +**/
> +EFI_STATUS
> +PchSbiRpPciAndThenOr32 (
> +  IN  UINT32  RpIndex,
> +  IN  UINT32  Offset,
> +  IN  UINT32  Data32And,
> +  IN  UINT32  Data32Or
> +  );
> +
> +/**
> +  Print registers value
> +
> +  @param[in] PrintMmioBase       Mmio base address
> +  @param[in] PrintSize           Number of registers
> +  @param[in] OffsetFromBase      Offset from mmio base address
> +
> +  @retval None
> +**/
> +VOID
> +PrintRegisters (
> +  IN  UINTN        PrintMmioBase,
> +  IN  UINT32       PrintSize,
> +  IN  UINT32       OffsetFromBase
> +  );
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPciExpre
> ssHelpersLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPciExpre
> ssHelpersLib.h
> new file mode 100644
> index 0000000000..b0e4eb64c2
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPciExpre
> ssHelpersLib.h
> @@ -0,0 +1,371 @@
> +/** @file
> +  Header file for PCH PCI Express helpers library
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_PCI_EXPRESS_HELPERS_LIB_H_
> +#define _PCH_PCI_EXPRESS_HELPERS_LIB_H_
> +
> +#include <PchPolicyCommon.h>
> +
> +typedef enum {
> +  TpoScale2us,
> +  TpoScale10us,
> +  TpoScale100us,
> +  TpoScaleMax
> +} T_PO_SCALE;
> +
> +typedef struct {
> +  UINT32     Value;
> +  T_PO_SCALE Scale;
> +} T_POWER_ON;
> +
> +//
> +// Function prototypes
> +//
> +
> +/**
> +  Get PCIe port number for enabled port.
> +  @param[in] RpBase    Root Port pci segment base address
> +  @return Root Port number (1 based)
> +**/
> +UINT32
> +PciePortNum (
> +  IN     UINT64  RpBase
> +  );
> +
> +/**
> +  Get PCIe root port index
> +  @param[in] RpBase    Root Port pci segment base address
> +  @return Root Port index (0 based)
> +**/
> +UINT32
> +PciePortIndex (
> +  IN     UINT64  RpBase
> +  );
> +
> +/**
> +  Translate PCIe Port/Lane pair to 0-based PCIe lane number.
> +
> +  @param[in] RpIndex    Root Port index
> +  @param[in] RpLane     Root Port Lane (0-3)
> +
> +  @retval PCIe lane number (0-based)
> +**/
> +UINT32
> +PchPciePhysicalLane (
> +  UINT32 RpIndex,
> +  UINT32 RpLane
> +  );
> +
> +/**
> +  Checks if lane reversal is enabled on a given root port
> +
> +  @param[in] RpIndex  Root port index (0-based)
> +
> +  @retval TRUE if lane reversal is enbabled, FALSE otherwise
> +**/
> +BOOLEAN
> +IsPcieLaneReversalEnabled (
> +  IN     UINT32  RpIndex
> +  );
> +
> +/**
> +  Calculates the index of the first port on the same controller.
> +
> +  @param[in] RpIndex     Root Port Number (0-based)
> +
> +  @retval Index of the first port on the first controller.
> +**/
> +UINT32
> +PchGetPcieFirstPortIndex (
> +  IN     UINT32  RpIndex
> +  );
> +
> +/*
> +  Returns Tpower_on capability of device
> +
> +  @param[in] DeviceBase       device's PCI segment base address
> +  @param[in] L1ssCapOffset    offset to L1substates capability in device's
> extended config space
> +
> +  @retval                     structure containing Tpoweron scale and value
> +*/
> +T_POWER_ON
> +GetTpoCapability (
> +  UINT64 DeviceBase,
> +  UINT32 L1ssCapOffset
> +  );
> +
> +/*
> +  Converts Tpower_on from value:scale notation to microseconds
> +
> +  @param[in] TpoScale   T power on scale
> +  @param[in] TpoValue   T power on value
> +
> +  @retval    number of microseconds
> +*/
> +UINT32
> +TpoToUs (
> +  UINT32 TpoScale,
> +  UINT32 TpoValue
> +  );
> +
> +/**
> +  Find the Offset to a given Capabilities ID
> +  CAPID list:
> +    0x01 = PCI Power Management Interface
> +    0x04 = Slot Identification
> +    0x05 = MSI Capability
> +    0x10 = PCI Express Capability
> +
> +  @param[in] DeviceBase           device's base address
> +  @param[in] CapId                CAPID to search for
> +
> +  @retval 0                       CAPID not found
> +  @retval Other                   CAPID found, Offset of desired CAPID
> +**/
> +UINT8
> +PcieBaseFindCapId (
> +  IN UINT64  DeviceBase,
> +  IN UINT8   CapId
> +  );
> +
> +/**
> +  Find the Offset to a given Capabilities ID
> +  CAPID list:
> +    0x01 = PCI Power Management Interface
> +    0x04 = Slot Identification
> +    0x05 = MSI Capability
> +    0x10 = PCI Express Capability
> +
> +  @param[in] Segment              Pci Segment Number
> +  @param[in] Bus                  Pci Bus Number
> +  @param[in] Device               Pci Device Number
> +  @param[in] Function             Pci Function Number
> +  @param[in] CapId                CAPID to search for
> +
> +  @retval 0                       CAPID not found
> +  @retval Other                   CAPID found, Offset of desired CAPID
> +**/
> +UINT8
> +PcieFindCapId (
> +  IN UINT8   Segment,
> +  IN UINT8   Bus,
> +  IN UINT8   Device,
> +  IN UINT8   Function,
> +  IN UINT8   CapId
> +  );
> +
> +/**
> +  Search and return the offset of desired Pci Express Capability ID
> +  CAPID list:
> +    0x0001 = Advanced Error Reporting Capability
> +    0x0002 = Virtual Channel Capability
> +    0x0003 = Device Serial Number Capability
> +    0x0004 = Power Budgeting Capability
> +
> +  @param[in] DeviceBase           device base address
> +  @param[in] CapId                Extended CAPID to search for
> +
> +  @retval 0                       CAPID not found, this includes situation where
> device doesn't exist
> +  @retval Other                   CAPID found, Offset of desired CAPID
> +**/
> +UINT16
> +PcieBaseFindExtendedCapId (
> +  IN UINT64  DeviceBase,
> +  IN UINT16  CapId
> +  );
> +
> +/**
> +  Search and return the offset of desired Pci Express Capability ID
> +  CAPID list:
> +    0x0001 = Advanced Error Rreporting Capability
> +    0x0002 = Virtual Channel Capability
> +    0x0003 = Device Serial Number Capability
> +    0x0004 = Power Budgeting Capability
> +
> +  @param[in] Segment              Pci Segment Number
> +  @param[in] Bus                  Pci Bus Number
> +  @param[in] Device               Pci Device Number
> +  @param[in] Function             Pci Function Number
> +  @param[in] CapId                Extended CAPID to search for
> +
> +  @retval 0                       CAPID not found
> +  @retval Other                   CAPID found, Offset of desired CAPID
> +**/
> +UINT16
> +PcieFindExtendedCapId (
> +  IN UINT8   Segment,
> +  IN UINT8   Bus,
> +  IN UINT8   Device,
> +  IN UINT8   Function,
> +  IN UINT16  CapId
> +  );
> +
> +/*
> +  Checks device's Slot Clock Configuration
> +
> +  @param[in] Base            device's base address
> +
> +  @retval TRUE when device device uses slot clock, FALSE otherwise
> +*/
> +BOOLEAN
> +GetScc (
> +  UINT64    Base,
> +  UINT8     PcieCapOffset
> +  );
> +
> +/*
> +  Sets Common Clock Configuration bit for given device.
> +
> +  @param[in] Base            device's base address
> +*/
> +VOID
> +EnableCcc (
> +  UINT64    Base,
> +  UINT8     PcieCapOffset
> +  );
> +
> +/*
> +  Retrains link behind given device.
> +  It only makes sense to call it for downstream ports.
> +  If called for upstream port nothing will happen, it won't enter infinite loop.
> +
> +  @param[in] Base            device's base address
> +*/
> +VOID
> +RetrainLink (
> +  UINT64  Base,
> +  UINT8   PcieCapOffset,
> +  BOOLEAN WaitUntilDone
> +  );
> +
> +/*
> +  Checks if device at given address exists
> +
> +  @retval TRUE when device exists; FALSE otherwise
> +*/
> +BOOLEAN
> +IsDevicePresent (
> +  UINT64 Base
> +  );
> +
> +/*
> +  Checks if device is a multifunction device
> +
> +  @param[in] Base            device's base address
> +
> +  @retval TRUE if multifunction; FALSE otherwise
> +*/
> +BOOLEAN
> +IsMultifunctionDevice (
> +  UINT64 Base
> +  );
> +
> +/*
> +  Initializes the following features in rootport and devices behind it:
> +  Maximum Payload Size (generic)
> +  Rootport packet split (proprietary)
> +  EonOfInterrupt forwarding (proprietary)
> +  Common Clock Configuration (generic)
> +
> +  Generic: any code written according to PCIE Express base specification can
> do that.
> +  Proprietary: code uses registers and features that are specific to Intel silicon
> +  and probably only this Reference Code knows how to handle that.
> +
> +  If OEM implemented generic feature enabling in his platform code or trusts
> Operating System
> +  to do it, then those features can be deleted from here.
> +
> +  CCC requires link retrain, which takes a while. CCC must happen before
> L0s/L1 programming.
> +  If there was guarantee no code would access PCI while links retrain, it would
> be possible to skip this waiting
> +
> +  @param[in] RpSegment  address of rootport on PCIe
> +  @param[in] RpBus      address of rootport on PCIe
> +  @param[in] RpDevice   address of rootport on PCIe
> +  @param[in] RpFunction address of rootport on PCIe
> +  @param[in] BusMin     minimum Bus number that can be assigned below
> this rootport
> +  @param[in] BusMax     maximum Bus number that can be assigned below
> this rootport
> +*/
> +VOID
> +RootportDownstreamConfiguration (
> +  UINT8                     RpSegment,
> +  UINT8                     RpBus,
> +  UINT8                     RpDevice,
> +  UINT8                     RpFunction,
> +  UINT8                     BusMin,
> +  UINT8                     BusMax
> +  );
> +
> +/*
> +  Configures the following power-management related features in rootport
> and devices behind it:
> +  LTR limit (generic)
> +  LTR override (proprietary)
> +  Clock Power Management (generic)
> +  L1 substates (generic except for the override table)
> +  L1.LOW substate (proprietary)
> +  L0s and L1 (generic)
> +
> +  Generic: any code written according to PCIE Express base specification can
> do that.
> +  Proprietary: code uses registers and features that are specific to Intel silicon
> +  and probably only this Reference Code knows how to handle that.
> +
> +  If OEM implemented generic feature enabling in his platform code or trusts
> Operating System
> +  to do it, then those features can be deleted from here.
> +
> +  @param[in] RpSegment                address of rootport on PCIe
> +  @param[in] RpBus                    address of rootport on PCIe
> +  @param[in] RpDevice                 address of rootport on PCIe
> +  @param[in] RpFunction               address of rootport on PCIe
> +  @param[in] BusLimit                 maximum Bus number that can be
> assigned below this rootport
> +  @param[in] AspmOverrideTableSize    size of override array
> +  @param[in] AspmOverrideTable        array of device that need exceptions
> in configuration
> +*/
> +VOID
> +RootportDownstreamPmConfiguration (
> +  UINT8                     RpSegment,
> +  UINT8                     RpBus,
> +  UINT8                     RpDevice,
> +  UINT8                     RpFunction,
> +  UINT8                     BusMin,
> +  UINT8                     BusMax,
> +  PCH_PCIE_ROOT_PORT_CONFIG *RpConfig,
> +  UINT32                    AspmOverrideTableSize,
> +  PCH_PCIE_DEVICE_OVERRIDE  *AspmOverrideTable
> +  );
> +
> +/**
> +  Get current PCIe link speed.
> +
> +  @param[in] RpBase    Root Port base address
> +  @return Link speed
> +**/
> +UINT32
> +GetLinkSpeed (
> +  UINT64  RpBase
> +  );
> +
> +/**
> +  Get max PCIe link speed supported by the root port.
> +
> +  @param[in] RpBase    Root Port pci segment base address
> +  @return Max link speed
> +**/
> +UINT32
> +GetMaxLinkSpeed (
> +  UINT64 RpBase
> +  );
> +
> +/**
> +  PCIe controller configuration.
> +**/
> +typedef enum {
> +  Pcie4x1      = 0,
> +  Pcie1x2_2x1  = 1,
> +  Pcie2x2      = 2,
> +  Pcie1x4      = 3
> +} PCIE_CONTROLLER_CONFIG;
> +
> +#endif // _PEI_DXE_SMM_PCH_PCI_EXPRESS_HELPERS_LIB_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPsfPriva
> teLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPsfPriva
> teLib.h
> new file mode 100644
> index 0000000000..9e68615717
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPsfPriva
> teLib.h
> @@ -0,0 +1,578 @@
> +/** @file
> +  Header file for PchPsfPrivateLib.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_PSF_PRIVATE_LIB_H_
> +#define _PCH_PSF_PRIVATE_LIB_H_
> +
> +#include <Library/PchPcrLib.h>
> +#include <Register/PchRegsPcr.h>
> +
> +//
> +// Structure for storing data on both PSF SideBand Port ID and
> +// PSF port register offset for specific device
> +//
> +typedef struct {
> +  PCH_SBI_PID  PsfPid;
> +  UINT16       RegBase;
> +} PSF_PORT;
> +
> +/**
> +  Disable device at PSF level
> +  Method not for bridges (e.g. PCIe Root Port)
> +
> +  @param[in] PsfPort  PSF PORT data structure
> +**/
> +VOID
> +PsfDisableDevice (
> +  IN PSF_PORT  PsfPort
> +  );
> +
> +/**
> +  Enable device at PSF level
> +  Method not for bridges (e.g. PCIe Root Port)
> +
> +  @param[in] PsfPort  PSF PORT data structure
> +**/
> +VOID
> +PsfEnableDevice (
> +  IN PSF_PORT  PsfPort
> +  );
> +
> +/**
> +  Hide PciCfgSpace of device at PSF level
> +  Method not for bridges (e.g. PCIe Root Port)
> +
> +  @param[in] PsfPort  PSF PORT data structure
> +**/
> +VOID
> +PsfHideDevice (
> +  IN PSF_PORT  PsfPort
> +  );
> +
> +/**
> +  Unhide PciCfgSpace of device at PSF level
> +  Method not for bridges (e.g. PCIe Root Port)
> +
> +  @param[in] PsfPort  PSF PORT data structure
> +**/
> +VOID
> +PsfUnhideDevice (
> +  IN PSF_PORT  PsfPort
> +  );
> +
> +/**
> +  Disable device BARs at PSF level
> +  Method not for bridges (e.g. PCIe Root Port)
> +
> +  @param[in] PsfPort     PSF PORT data structure
> +  @param[in] BarDisMask  BIT0-BAR0, BIT1-BAR1,...
> +                         Mask corresponds to 32bit wide BARs
> +**/
> +VOID
> +PsfDisableDeviceBar (
> +  IN PSF_PORT  PsfPort,
> +  IN UINT32    BarDisMask
> +  );
> +
> +/**
> +  Enable device BARs at PSF level
> +  Method not for bridges (e.g. PCIe Root Port)
> +
> +  @param[in] PsfPort     PSF PORT data structure
> +  @param[in] BarEnMask   BIT0-BAR0, BIT1-BAR1,...
> +                         Mask corresponds to 32bit wide BARs
> +**/
> +VOID
> +PsfEnableDeviceBar (
> +  IN PSF_PORT  PsfPort,
> +  IN UINT32    BarEnMask
> +  );
> +
> +/**
> +  Return PSF_PORT for SerialIO I2C device
> +
> +  @param[in] I2cNum  Serial IO I2C device (I2C0, I2C1, ....)
> +
> +  @retval  PsfPort   PSF PORT structure for SerialIO I2C device
> +**/
> +PSF_PORT
> +PsfSerialIoI2cPort (
> +  IN UINT32  I2cNum
> +  );
> +
> +/**
> +  Return PSF_PORT for SerialIO SPI device
> +
> +  @param[in] SpiNum  Serial IO SPI device (SPI0, SPI1, ....)
> +
> +  @retval  PsfPort   PSF PORT structure for SerialIO SPI device
> +**/
> +PSF_PORT
> +PsfSerialIoSpiPort (
> +  IN UINT32  SpiNum
> +  );
> +
> +/**
> +  Return PSF_PORT for SerialIO UART device
> +
> +  @param[in] UartNum  Serial IO UART device (UART0, UART1, ....)
> +
> +  @retval  PsfPort    PSF PORT structure for SerialIO UART device
> +**/
> +PSF_PORT
> +PsfSerialIoUartPort (
> +  IN UINT32  UartNum
> +  );
> +
> +/**
> +  This procedure will set BARx value for TraceHub ACPI device at PSF level
> +
> +  @param[in] BarNum          BAR Number (0:BAR0, 1:BAR1)
> +  @param[in] BarValue        32bit BAR value
> +**/
> +VOID
> +PsfSetTraceHubAcpiDeviceBarValue (
> +  IN UINT8   BarNum,
> +  IN UINT32  BarValue
> +  );
> +
> +/**
> +  This procedure will enable MSE for TraceHub ACPI device at PSF level
> +**/
> +VOID
> +PsfEnableTraceHubAcpiDeviceMemorySpace (
> +  VOID
> +  );
> +
> +/**
> +  Enable HECI device at PSF level
> +
> +  @param[in] HeciDevice       HECIx Device (HECI1-4)
> +**/
> +VOID
> +PsfEnableHeciDevice (
> +  IN UINT8      HeciDevice
> +  );
> +
> +/**
> +  Disable HECI device at PSF level
> +
> +  @param[in] HeciDevice       HECIx Device (HECI1-4)
> +**/
> +VOID
> +PsfDisableHeciDevice (
> +  IN UINT8      HeciDevice
> +  );
> +
> +/**
> +  Disable IDER device at PSF level
> +**/
> +VOID
> +PsfDisableIderDevice (
> +  VOID
> +  );
> +
> +/**
> +  Enable SOL device at PSF level
> +**/
> +VOID
> +PsfEnableSolDevice (
> +  VOID
> +  );
> +
> +/**
> +  Disable SOL device at PSF level
> +**/
> +VOID
> +PsfDisableSolDevice (
> +  VOID
> +  );
> +
> +/**
> +  Set PMC ABASE value in PSF
> +
> +  @param[in] Address     Address for ACPI base.
> +**/
> +VOID
> +PsfSetPmcAbase (
> +  IN  UINT16       Address
> +  );
> +
> +/**
> +  Get PMC ABASE value from PSF
> +
> +  @retval Address     Address for ACPI base.
> +**/
> +UINT16
> +PsfGetPmcAbase (
> +  VOID
> +  );
> +
> +/**
> +  Get PMC PWRMBASE value from PSF
> +
> +  @retval Address     Address for PWRM base.
> +**/
> +UINT32
> +PsfGetPmcPwrmBase (
> +  VOID
> +  );
> +
> +/**
> +  Hide Cnvi WiFi device's PciCfgSpace at PSF level
> +**/
> +VOID
> +PsfHideCnviWifiDevice (
> +  VOID
> +  );
> +
> +/**
> +  Disable Cnvi Wifi device at PSF level
> +**/
> +VOID
> +PsfDisableCnviWifiDevice (
> +  VOID
> +  );
> +
> +/**
> +  Disable HDAudio device at PSF level
> +**/
> +VOID
> +PsfDisableHdaDevice (
> +  VOID
> +  );
> +
> +/**
> +  Disable xDCI device at PSF level
> +**/
> +VOID
> +PsfDisableXdciDevice (
> +  VOID
> +  );
> +
> +/**
> +  Disable xHCI device at PSF level
> +**/
> +VOID
> +PsfDisableXhciDevice (
> +  VOID
> +  );
> +
> +/**
> +  Disable xHCI VTIO Phantom device at PSF level
> +**/
> +VOID
> +PsfDisableXhciVtioDevice (
> +  VOID
> +  );
> +
> +/**
> +  Disable SATA device at PSF level
> +
> +  @param[in]  SataCtrlIndex     SATA controller index
> +**/
> +VOID
> +PsfDisableSataDevice (
> +  IN UINT32     SataCtrlIndex
> +  );
> +
> +/**
> +  Return PSF_PORT for SCS eMMC device
> +
> +  @retval    PsfPort      PSF PORT structure for SCS eMMC device
> +**/
> +PSF_PORT
> +PsfScsEmmcPort (
> +  VOID
> +  );
> +
> +/**
> +  Return PSF_PORT for SCS SD Card device
> +
> +  @retval    PsfPort      PSF PORT structure for SCS SD Card device
> +**/
> +PSF_PORT
> +PsfScsSdCardPort (
> +  VOID
> +  );
> +
> +/**
> +  Return PSF_PORT for SCS UFS device
> +
> +  @param[in] UfsNum       UFS Device
> +
> +  @retval    PsfPort      PSF PORT structure for SCS UFS device
> +**/
> +PSF_PORT
> +PsfScsUfsPort (
> +  IN UINT32  UfsNum
> +  );
> +
> +/**
> +  Disable ISH device at PSF level
> +**/
> +VOID
> +PsfDisableIshDevice (
> +  VOID
> +  );
> +
> +/**
> +  Disable ISH BAR1 at PSF level
> +**/
> +VOID
> +PsfDisableIshBar1 (
> +  VOID
> +  );
> +
> +/**
> +  Disable GbE device at PSF level
> +**/
> +VOID
> +PsfDisableGbeDevice (
> +  VOID
> +  );
> +
> +/**
> +  Disable SMBUS device at PSF level
> +**/
> +VOID
> +PsfDisableSmbusDevice (
> +  VOID
> +  );
> +
> +/**
> +  Disable TraceHub ACPI devices at PSF level
> +**/
> +VOID
> +PsfDisableTraceHubAcpiDevice (
> +  VOID
> +  );
> +
> +/**
> +  Hide TraceHub ACPI devices PciCfgSpace at PSF level
> +**/
> +VOID
> +PsfHideTraceHubAcpiDevice (
> +  VOID
> +  );
> +
> +/**
> +  This procedure will hide TraceHub PciCfgSpace at PSF level
> +**/
> +VOID
> +PsfHideTraceHubDevice (
> +  VOID
> +  );
> +
> +/**
> +  This procedure will unhide TraceHub PciCfgSpace at PSF level
> +**/
> +VOID
> +PsfUnhideTraceHubDevice (
> +  VOID
> +  );
> +
> +/**
> +  This procedure will disable TraceHub device at PSF level
> +**/
> +VOID
> +PsfDisableTraceHubDevice (
> +  VOID
> +  );
> +
> +/**
> +  Configures rootspace 3 bus number for PCIe IMR use
> +
> +  @param[in] Rs3Bus        bus number
> +**/
> +VOID
> +PsfSetRs3Bus (
> +  UINT8 Rs3Bus
> +  );
> +
> +/**
> +  Disable PCIe Root Port at PSF level
> +
> +  @param[in] RpIndex        PCIe Root Port Index (0 based)
> +**/
> +VOID
> +PsfDisablePcieRootPort (
> +  IN UINT32  RpIndex
> +  );
> +
> +/**
> +  Program PSF grant counts for SATA
> +  Call this before SATA ports are accessed for enumeration
> +**/
> +VOID
> +PsfConfigureSataGrantCounts (
> +  VOID
> +  );
> +
> +typedef enum {
> +  PsfPcieCtrl4x1,
> +  PsfPcieCtrl1x2_2x1,
> +  PsfPcieCtrl2x2,
> +  PsfPcieCtrl1x4
> +} PSF_PCIE_CTRL_CONFIG;
> +
> +/**
> +  Program PSF grant counts for PCI express depending on controllers
> configuration
> +
> +  @param[in] PsfPcieCtrlConfigTable   Table with PCIe controllers
> configuration
> +  @param[in] NumberOfPcieControllers  Number of PCIe controllers. This is
> also the size of PsfPcieCtrlConfig table
> +**/
> +VOID
> +PsfConfigurePcieGrantCounts (
> +  IN PSF_PCIE_CTRL_CONFIG  *PsfPcieCtrlConfigTable,
> +  IN UINT32                NumberOfPcieControllers
> +  );
> +
> +/**
> +  Program PSF EOI Multicast configuration for ITSS
> +**/
> +VOID
> +PsfConfigurEoiForItss (
> +  VOID
> +  );
> +
> +/**
> +  This function enables EOI message forwarding in PSF for PCIe ports
> +  for cases where IOAPIC is present behind this root port.
> +
> +  @param[in] RpIndex        Root port index (0 based)
> +
> +  @retval Status
> +**/
> +EFI_STATUS
> +PsfConfigurEoiForPciePort (
> +  IN  UINT32   RpIndex
> +  );
> +
> +//
> +// Structure for PSF Port Destination ID
> +//
> +typedef union {
> +  UINT32 RegVal;
> +  struct {
> +    UINT32  ChannelId   : 8;  // Channel ID
> +    UINT32  PortId      : 7;  // Port ID
> +    UINT32  PortGroupId : 1;  // Port Group ID
> +    UINT32  PsfId       : 8;  // PSF ID
> +    UINT32  Rsvd        : 7;  // Reserved
> +    UINT32  ChanMap     : 1;  // Channel map
> +  } Fields;
> +} PSF_PORT_DEST_ID;
> +
> +/**
> +  PCIe PSF port destination ID (psf_id:port_group_id:port_id:channel_id)
> +
> +  @param[in] RpIndex        PCIe Root Port Index (0 based)
> +
> +  @retval Destination ID
> +**/
> +PSF_PORT_DEST_ID
> +PsfPcieDestinationId (
> +  IN UINT32 RpIndex
> +  );
> +
> +/**
> +  PSF early initialization.
> +**/
> +VOID
> +PsfEarlyInit (
> +  VOID
> +  );
> +
> +/**
> +  Assign new function number for PCIe Port Number.
> +
> +  @param[in] RpIndex        PCIe Root Port Index (0 based)
> +  @param[in] NewFunction    New Function number
> +**/
> +VOID
> +PsfSetPcieFunction (
> +  IN UINT32  RpIndex,
> +  IN UINT32  NewFunction
> +  );
> +
> +/**
> +  This function enables PCIe Relaxed Order in PSF
> +**/
> +VOID
> +PsfEnablePcieRelaxedOrder (
> +  VOID
> +  );
> +
> +/**
> +  Configure PSF power management.
> +  Must be called after all PSF configuration is completed.
> +**/
> +VOID
> +PsfConfigurePowerManagement (
> +  VOID
> +  );
> +
> +/**
> +  Enable VTd support in PSF.
> +**/
> +VOID
> +PchPsfEnableVtd (
> +  VOID
> +  );
> +
> +/**
> +  Disable PSF address-based peer-to-peer decoding.
> +**/
> +VOID
> +PchPsfDisableP2pDecoding (
> +  VOID
> +  );
> +
> +/**
> +  Perform registers programming required for
> +  Management Component Transport Protocol Broadcast Cycle.
> +
> +  Agent Destination Addresses are being programmed only when adequate
> +  PCIe root port controllers are function enabled.
> +
> +  Function sets CSME PMT as a message broadcaster and programs the targets
> +  of the message in registers only if adequate PCIe root port controllers
> +  are function enabled. Conditionally, if the CPU PEG exist and is function
> +  enabled, DMI is also a target.
> +**/
> +VOID
> +PsfConfigureMctpCycle (
> +  VOID
> +  );
> +
> +/**
> +  This procedure will hide PMC device at PSF level
> +**/
> +VOID
> +PsfHidePmcDevice (
> +  VOID
> +  );
> +
> +/**
> +  This procedure will disable D3:F0 device at PSF level for PCH-LP
> +**/
> +VOID
> +PsfDisableD3F0 (
> +  VOID
> +  );
> +
> +/**
> +  This procedure will disable PSF upstream completion tracking for HDAudio
> on PCH-LP
> +**/
> +VOID
> +PsfDisableUpstreamCompletionTrackingForHda (
> +  VOID
> +  );
> +
> +#endif // _PCH_PSF_PRIVATE_LIB_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSmbusC
> ommonLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSmbusC
> ommonLib.h
> new file mode 100644
> index 0000000000..313b13060f
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSmbusC
> ommonLib.h
> @@ -0,0 +1,98 @@
> +/** @file
> +  PCH Smbus Protocol
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_SMBUS_COMMON_LIB_H
> +#define _PCH_SMBUS_COMMON_LIB_H
> +
> +//
> +// Definitions
> +//
> +#define SMBUS_NUM_RESERVED          38      ///< Number of device
> addresses that are reserved by the SMBus spec.
> +#define SMBUS_ADDRESS_ARP           0xC2 >> 1
> +#define SMBUS_DATA_PREPARE_TO_ARP   0x01
> +#define SMBUS_DATA_RESET_DEVICE     0x02
> +#define SMBUS_DATA_GET_UDID_GENERAL 0x03
> +#define SMBUS_DATA_ASSIGN_ADDRESS   0x04
> +#define SMBUS_GET_UDID_LENGTH       17      ///< 16 byte UDID + 1 byte
> address
> +//
> +// Private data and functions
> +//
> +
> +#define PCH_SMBUS_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('p', 's', 'm',
> 'b')
> +
> +/**
> +  This function provides a standard way to read PCH Smbus IO registers.
> +
> +  @param[in] Offset               Register offset from Smbus base IO address.
> +
> +  @retval UINT8                   Returns data read from IO.
> +**/
> +UINT8
> +SmbusIoRead (
> +  IN      UINT8           Offset
> +  );
> +
> +/**
> +  This function provides a standard way to write PCH Smbus IO registers.
> +
> +  @param[in] Offset               Register offset from Smbus base IO address.
> +  @param[in] Data                 Data to write to register.
> +
> +**/
> +VOID
> +SmbusIoWrite (
> +  IN      UINT8           Offset,
> +  IN      UINT8           Data
> +  );
> +
> +/**
> +  This function provides a standard way to execute Smbus protocols
> +  as defined in the SMBus Specification. The data can either be of
> +  the Length byte, word, or a block of data. The resulting transaction will be
> +  either the SMBus Slave Device accepts this transaction or this function
> +  returns with an error
> +
> +  @param[in] SlaveAddress         Smbus Slave device the command is
> directed at
> +  @param[in] Command              Slave Device dependent
> +  @param[in] Operation            Which SMBus protocol will be used
> +  @param[in] PecCheck             Defines if Packet Error Code Checking is to be
> used
> +  @param[in, out] Length          How many bytes to read. Must be 0 <=
> Length <= 32 depending on Operation
> +                                  It will contain the actual number of bytes
> read/written.
> +  @param[in, out] Buffer          Contain the data read/written.
> +
> +  @retval EFI_SUCCESS             The operation completed successfully.
> +  @exception EFI_UNSUPPORTED      The operation is unsupported.
> +
> +  @retval EFI_INVALID_PARAMETER   Length or Buffer is NULL for any
> operation besides
> +                                  quick read or quick write.
> +  @retval EFI_TIMEOUT             The transaction did not complete within an
> internally
> +                                  specified timeout period, or the controller is not
> +                                  available for use.
> +  @retval EFI_DEVICE_ERROR        There was an Smbus error (NACK) during
> the operation.
> +                                  This could indicate the slave device is not present
> +                                  or is in a hung condition.
> +**/
> +EFI_STATUS
> +SmbusExec (
> +  IN      EFI_SMBUS_DEVICE_ADDRESS  SlaveAddress,
> +  IN      EFI_SMBUS_DEVICE_COMMAND  Command,
> +  IN      EFI_SMBUS_OPERATION       Operation,
> +  IN      BOOLEAN                   PecCheck,
> +  IN OUT  UINTN                     *Length,
> +  IN OUT  VOID                      *Buffer
> +  );
> +
> +/**
> +  This function initializes the Smbus Registers.
> +
> +**/
> +VOID
> +InitializeSmbusRegisters (
> +  VOID
> +  );
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSpiCom
> monLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSpiCom
> monLib.h
> new file mode 100644
> index 0000000000..0a973a77a3
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSpiCom
> monLib.h
> @@ -0,0 +1,366 @@
> +/** @file
> +  Header file for the PCH SPI Common Driver.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_SPI_COMMON_LIB_H_
> +#define _PCH_SPI_COMMON_LIB_H_
> +
> +#include <Protocol/Spi.h>
> +
> +//
> +// Maximum time allowed while waiting the SPI cycle to complete
> +//  Wait Time = 6 seconds = 6000000 microseconds
> +//  Wait Period = 10 microseconds
> +//
> +#define SPI_WAIT_TIME   6000000     ///< Wait Time = 6 seconds = 6000000
> microseconds
> +#define SPI_WAIT_PERIOD 10          ///< Wait Period = 10 microseconds
> +
> +///
> +/// Flash cycle Type
> +///
> +typedef enum {
> +  FlashCycleRead,
> +  FlashCycleWrite,
> +  FlashCycleErase,
> +  FlashCycleReadSfdp,
> +  FlashCycleReadJedecId,
> +  FlashCycleWriteStatus,
> +  FlashCycleReadStatus,
> +  FlashCycleMax
> +} FLASH_CYCLE_TYPE;
> +
> +///
> +/// Flash Component Number
> +///
> +typedef enum {
> +  FlashComponent0,
> +  FlashComponent1,
> +  FlashComponentMax
> +} FLASH_COMPONENT_NUM;
> +
> +///
> +/// Private data structure definitions for the driver
> +///
> +#define PCH_SPI_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('P', 'S', 'P', 'I')
> +
> +typedef struct {
> +  UINT32                Signature;
> +  EFI_HANDLE            Handle;
> +  PCH_SPI_PROTOCOL      SpiProtocol;
> +  UINT16                PchAcpiBase;
> +  UINT64                PchSpiBase;
> +  UINT8                 ReadPermission;
> +  UINT8                 WritePermission;
> +  UINT32                SfdpVscc0Value;
> +  UINT32                SfdpVscc1Value;
> +  UINT16                PchStrapBaseAddr;
> +  UINT16                PchStrapSize;
> +  UINT16                CpuStrapBaseAddr;
> +  UINT16                CpuStrapSize;
> +  UINT8                 NumberOfComponents;
> +  UINT32                Component1StartAddr;
> +  UINT32                TotalFlashSize;
> +} SPI_INSTANCE;
> +
> +#define SPI_INSTANCE_FROM_SPIPROTOCOL(a)  CR (a, SPI_INSTANCE,
> SpiProtocol, PCH_SPI_PRIVATE_DATA_SIGNATURE)
> +
> +//
> +// Function prototypes used by the SPI protocol.
> +//
> +
> +/**
> +  Initialize an SPI protocol instance.
> +
> +  @param[in] SpiInstance          Pointer to SpiInstance to initialize
> +
> +  @retval EFI_SUCCESS             The protocol instance was properly
> initialized
> +  @exception EFI_UNSUPPORTED      The PCH is not supported by this
> module
> +**/
> +EFI_STATUS
> +SpiProtocolConstructor (
> +  IN     SPI_INSTANCE       *SpiInstance
> +  );
> +
> +/**
> +  This function is a hook for Spi to disable BIOS Write Protect
> +
> +  @retval EFI_SUCCESS             The protocol instance was properly
> initialized
> +  @retval EFI_ACCESS_DENIED       The BIOS Region can only be updated in
> SMM phase
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +DisableBiosWriteProtect (
> +  VOID
> +  );
> +
> +/**
> +  This function is a hook for Spi to enable BIOS Write Protect
> +
> +
> +**/
> +VOID
> +EFIAPI
> +EnableBiosWriteProtect (
> +  VOID
> +  );
> +
> +/**
> +  Acquire pch spi mmio address.
> +
> +  @param[in] SpiInstance          Pointer to SpiInstance to initialize
> +
> +  @retval PchSpiBar0              return SPI MMIO address
> +**/
> +UINTN
> +AcquireSpiBar0 (
> +  IN  SPI_INSTANCE                *SpiInstance
> +  );
> +
> +/**
> +  Release pch spi mmio address.
> +
> +  @param[in] SpiInstance          Pointer to SpiInstance to initialize
> +
> +  @retval None
> +**/
> +VOID
> +ReleaseSpiBar0 (
> +  IN  SPI_INSTANCE                *SpiInstance
> +  );
> +
> +/**
> +  Check if it's granted to do flash write.
> +
> +  @retval TRUE    It's secure to do flash write.
> +  @retval FALSE   It's not secure to do flash write.
> +**/
> +BOOLEAN
> +IsSpiFlashWriteGranted (
> +  VOID
> +  );
> +
> +/**
> +  Read data from the flash part.
> +
> +  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
> +  @param[in] FlashRegionType      The Flash Region type for flash cycle
> which is listed in the Descriptor.
> +  @param[in] Address              The Flash Linear Address must fall within a
> region for which BIOS has access permissions.
> +  @param[in] ByteCount            Number of bytes in the data portion of the
> SPI cycle.
> +  @param[out] Buffer              The Pointer to caller-allocated buffer
> containing the dada received.
> +                                  It is the caller's responsibility to make sure Buffer is
> large enough for the total number of bytes read.
> +
> +  @retval EFI_SUCCESS             Command succeed.
> +  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
> +  @retval EFI_DEVICE_ERROR        Device error, command aborts
> abnormally.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiProtocolFlashRead (
> +  IN     PCH_SPI_PROTOCOL   *This,
> +  IN     FLASH_REGION_TYPE  FlashRegionType,
> +  IN     UINT32             Address,
> +  IN     UINT32             ByteCount,
> +  OUT    UINT8              *Buffer
> +  );
> +
> +/**
> +  Write data to the flash part.
> +
> +  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
> +  @param[in] FlashRegionType      The Flash Region type for flash cycle
> which is listed in the Descriptor.
> +  @param[in] Address              The Flash Linear Address must fall within a
> region for which BIOS has access permissions.
> +  @param[in] ByteCount            Number of bytes in the data portion of the
> SPI cycle.
> +  @param[in] Buffer               Pointer to caller-allocated buffer containing
> the data sent during the SPI cycle.
> +
> +  @retval EFI_SUCCESS             Command succeed.
> +  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
> +  @retval EFI_DEVICE_ERROR        Device error, command aborts
> abnormally.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiProtocolFlashWrite (
> +  IN     PCH_SPI_PROTOCOL   *This,
> +  IN     FLASH_REGION_TYPE  FlashRegionType,
> +  IN     UINT32             Address,
> +  IN     UINT32             ByteCount,
> +  IN     UINT8              *Buffer
> +  );
> +
> +/**
> +  Erase some area on the flash part.
> +
> +  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
> +  @param[in] FlashRegionType      The Flash Region type for flash cycle
> which is listed in the Descriptor.
> +  @param[in] Address              The Flash Linear Address must fall within a
> region for which BIOS has access permissions.
> +  @param[in] ByteCount            Number of bytes in the data portion of the
> SPI cycle.
> +
> +  @retval EFI_SUCCESS             Command succeed.
> +  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
> +  @retval EFI_DEVICE_ERROR        Device error, command aborts
> abnormally.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiProtocolFlashErase (
> +  IN     PCH_SPI_PROTOCOL   *This,
> +  IN     FLASH_REGION_TYPE  FlashRegionType,
> +  IN     UINT32             Address,
> +  IN     UINT32             ByteCount
> +  );
> +
> +/**
> +  Read SFDP data from the flash part.
> +
> +  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
> +  @param[in] ComponentNumber      The Componen Number for chip select
> +  @param[in] Address              The starting byte address for SFDP data read.
> +  @param[in] ByteCount            Number of bytes in SFDP data portion of the
> SPI cycle
> +  @param[out] SfdpData            The Pointer to caller-allocated buffer
> containing the SFDP data received
> +                                  It is the caller's responsibility to make sure Buffer is
> large enough for the total number of bytes read
> +
> +  @retval EFI_SUCCESS             Command succeed.
> +  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
> +  @retval EFI_DEVICE_ERROR        Device error, command aborts
> abnormally.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiProtocolFlashReadSfdp (
> +  IN     PCH_SPI_PROTOCOL   *This,
> +  IN     UINT8              ComponentNumber,
> +  IN     UINT32             Address,
> +  IN     UINT32             ByteCount,
> +  OUT    UINT8              *SfdpData
> +  );
> +
> +/**
> +  Read Jedec Id from the flash part.
> +
> +  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
> +  @param[in] ComponentNumber      The Componen Number for chip select
> +  @param[in] ByteCount            Number of bytes in JedecId data portion of
> the SPI cycle, the data size is 3 typically
> +  @param[out] JedecId             The Pointer to caller-allocated buffer
> containing JEDEC ID received
> +                                  It is the caller's responsibility to make sure Buffer is
> large enough for the total number of bytes read.
> +
> +  @retval EFI_SUCCESS             Command succeed.
> +  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
> +  @retval EFI_DEVICE_ERROR        Device error, command aborts
> abnormally.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiProtocolFlashReadJedecId (
> +  IN     PCH_SPI_PROTOCOL   *This,
> +  IN     UINT8              ComponentNumber,
> +  IN     UINT32             ByteCount,
> +  OUT    UINT8              *JedecId
> +  );
> +
> +/**
> +  Write the status register in the flash part.
> +
> +  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
> +  @param[in] ByteCount            Number of bytes in Status data portion of
> the SPI cycle, the data size is 1 typically
> +  @param[in] StatusValue          The Pointer to caller-allocated buffer
> containing the value of Status register writing
> +
> +  @retval EFI_SUCCESS             Command succeed.
> +  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
> +  @retval EFI_DEVICE_ERROR        Device error, command aborts
> abnormally.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiProtocolFlashWriteStatus (
> +  IN     PCH_SPI_PROTOCOL   *This,
> +  IN     UINT32             ByteCount,
> +  IN     UINT8              *StatusValue
> +  );
> +
> +/**
> +  Read status register in the flash part.
> +
> +  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
> +  @param[in] ByteCount            Number of bytes in Status data portion of
> the SPI cycle, the data size is 1 typically
> +  @param[out] StatusValue         The Pointer to caller-allocated buffer
> containing the value of Status register received.
> +
> +  @retval EFI_SUCCESS             Command succeed.
> +  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
> +  @retval EFI_DEVICE_ERROR        Device error, command aborts
> abnormally.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiProtocolFlashReadStatus (
> +  IN     PCH_SPI_PROTOCOL   *This,
> +  IN     UINT32             ByteCount,
> +  OUT    UINT8              *StatusValue
> +  );
> +
> +/**
> +  Get the SPI region base and size, based on the enum type
> +
> +  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
> +  @param[in] FlashRegionType      The Flash Region type for for the base
> address which is listed in the Descriptor.
> +  @param[out] BaseAddress         The Flash Linear Address for the Region 'n'
> Base
> +  @param[out] RegionSize          The size for the Region 'n'
> +
> +  @retval EFI_SUCCESS             Read success
> +  @retval EFI_INVALID_PARAMETER   Invalid region type given
> +  @retval EFI_DEVICE_ERROR        The region is not used
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiProtocolGetRegionAddress (
> +  IN     PCH_SPI_PROTOCOL   *This,
> +  IN     FLASH_REGION_TYPE  FlashRegionType,
> +  OUT    UINT32             *BaseAddress,
> +  OUT    UINT32             *RegionSize
> +  );
> +
> +/**
> +  Read PCH Soft Strap Values
> +
> +  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
> +  @param[in] SoftStrapAddr        PCH Soft Strap address offset from FPSBA.
> +  @param[in] ByteCount            Number of bytes in SoftStrap data portion
> of the SPI cycle
> +  @param[out] SoftStrapValue      The Pointer to caller-allocated buffer
> containing PCH Soft Strap Value.
> +                                  If the value of ByteCount is 0, the data type of
> SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap
> Length
> +                                  It is the caller's responsibility to make sure Buffer is
> large enough for the total number of bytes read.
> +
> +  @retval EFI_SUCCESS             Command succeed.
> +  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
> +  @retval EFI_DEVICE_ERROR        Device error, command aborts
> abnormally.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiProtocolReadPchSoftStrap (
> +  IN     PCH_SPI_PROTOCOL   *This,
> +  IN     UINT32             SoftStrapAddr,
> +  IN     UINT32             ByteCount,
> +  OUT    VOID               *SoftStrapValue
> +  );
> +
> +/**
> +  Read CPU Soft Strap Values
> +
> +  @param[in] This                 Pointer to the PCH_SPI_PROTOCOL instance.
> +  @param[in] SoftStrapAddr        CPU Soft Strap address offset from
> FCPUSBA.
> +  @param[in] ByteCount            Number of bytes in SoftStrap data portion
> of the SPI cycle.
> +  @param[out] SoftStrapValue      The Pointer to caller-allocated buffer
> containing CPU Soft Strap Value.
> +                                  If the value of ByteCount is 0, the data type of
> SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap
> Length
> +                                  It is the caller's responsibility to make sure Buffer is
> large enough for the total number of bytes read.
> +
> +  @retval EFI_SUCCESS             Command succeed.
> +  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.
> +  @retval EFI_DEVICE_ERROR        Device error, command aborts
> abnormally.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SpiProtocolReadCpuSoftStrap (
> +  IN     PCH_SPI_PROTOCOL   *This,
> +  IN     UINT32             SoftStrapAddr,
> +  IN     UINT32             ByteCount,
> +  OUT    VOID               *SoftStrapValue
> +  );
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PeiPchDmiLi
> b.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PeiPchDmiL
> ib.h
> new file mode 100644
> index 0000000000..301ec3dd48
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PeiPchDmiL
> ib.h
> @@ -0,0 +1,25 @@
> +/** @file
> +  This file contains PEI DMI methods
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PEI_PCH_DMI_LIB_H_
> +#define _PEI_PCH_DMI_LIB_H_
> +
> +#include <Ppi/SiPolicy.h>
> +
> +//
> +// Data structure definitions
> +//
> +typedef enum {
> +  DmiVcTypeVc0,
> +  DmiVcTypeVc1,
> +  DmiVcTypeVcm,
> +  DmiVcTypeMax
> +} PCH_DMI_VC_TYPE;
> +
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PmcPrivateL
> ib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PmcPrivate
> Lib.h
> new file mode 100644
> index 0000000000..44e7567e0f
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PmcPrivate
> Lib.h
> @@ -0,0 +1,706 @@
> +/** @file
> +  Header file for private PmcLib.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PMC_PRIVATE_LIB_H_
> +#define _PMC_PRIVATE_LIB_H_
> +
> +#include <Library/PmcLib.h>
> +#include <Register/PchRegsPmc.h>
> +
> +/**
> +  Send PMC IPC1 Normal Read/Write command
> +
> +  @param[in]  Command           Command to be issued to PMC IPC 1
> interface
> +  @param[in]  SubCmdId          SUB_CMD_ID for provided Command
> +  @param[in]  CmdSize           Total size in byte to be sent via PMC IPC 1
> interface
> +  @param[in]  WriteBufPtr       Pointer to Structure of 4 DWORDs to be
> issued to PMC IPC 1 interface
> +  @param[out] ReadBufPtr        Pointer to Structure of 4 DWORDs to be
> filled by PMC IPC 1 interface
> +
> +  @retval EFI_SUCCESS             Command was executed successfully
> +  @retval EFI_INVALID_PARAMETER   Invalid command size
> +  @retval EFI_DEVICE_ERROR        IPC command failed with an error
> +  @retval EFI_TIMEOUT             IPC command did not complete after 1s
> +**/
> +EFI_STATUS
> +PmcSendCommand (
> +  IN  UINT8                    Command,
> +  IN  UINT8                    SubCmdId,
> +  IN  UINT8                    CmdSize,
> +  IN  PMC_IPC_COMMAND_BUFFER   *WriteBufPtr,
> +  OUT PMC_IPC_COMMAND_BUFFER   *ReadBufPtr
> +  );
> +
> +/**
> +  Set PCH ACPI base address.
> +  The Address should not be 0 and should be 256 bytes alignment, and it is IO
> space, so must not exceed 0xFFFF.
> +
> +  @param[in] Address                    Address for ACPI base address.
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_INVALID_PARAMETER         Invalid base address passed.
> +**/
> +EFI_STATUS
> +PmcSetAcpiBase (
> +  IN  UINT16                            Address
> +  );
> +
> +/**
> +  Set PCH PWRM base address.
> +  Only 0xFE000000 (PCH_PWRM_BASE_ADDRESS) is the acceptable value for
> PWRMBASE
> +
> +  @param[in] Address                    Address for PWRM base address.
> +
> +  @retval EFI_SUCCESS                   Successfully completed.
> +  @retval EFI_UNSUPPORTED               DMIC.SRL is set.
> +**/
> +EFI_STATUS
> +PmcSetPwrmBase (
> +  IN  UINT32                            Address
> +  );
> +
> +/**
> +  This function checks if function disable (static and non-static power gating)
> +  configuration is locked
> +
> +  @retval lock state
> +**/
> +BOOLEAN
> +PmcIsFunctionDisableConfigLocked (
> +  VOID
> +  );
> +
> +/**
> +  This function locks static power gating configuration with S3 Boot Script
> programming
> +**/
> +VOID
> +PmcLockFunctionDisableConfigWithS3BootScript (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if ISH is function disabled
> +  by static power gating
> +
> +  @retval ISH device state
> +**/
> +BOOLEAN
> +PmcIsIshFunctionDisabled (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if ISH device is supported (not disabled by fuse)
> +
> +  @retval ISH support state
> +**/
> +BOOLEAN
> +PmcIsIshSupported (
> +  VOID
> +  );
> +
> +/**
> +  This function disables ISH device by static power gating
> +  For static power gating to take place Global Reset, G3 or DeepSx transition
> must happen.
> +**/
> +VOID
> +PmcStaticDisableIsh (
> +  VOID
> +  );
> +
> +/**
> +  This function enables ISH device by disabling static power gating
> +**/
> +VOID
> +PmcEnableIsh (
> +  VOID
> +  );
> +
> +/**
> +  This function enables GBE ModPHY SPD gating.
> +**/
> +VOID
> +PmcGbeModPhyPowerGating (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if GbE is function disabled
> +  by static power gating
> +
> +  @retval GbE device state
> +**/
> +BOOLEAN
> +PmcIsGbeFunctionDisabled (
> +  VOID
> +  );
> +
> +/**
> +  This function disables GbE device by static power gating
> +  For static power gating to take place Global Reset, G3 or DeepSx transition
> must happen.
> +**/
> +VOID
> +PmcStaticDisableGbe (
> +  VOID
> +  );
> +
> +/**
> +  This function enables GbE device by disabling static power gating
> +  Static power gating disabling takes place after Global Reset, G3 or DeepSx
> transition.
> +**/
> +VOID
> +PmcEnableGbe (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if GbE device is supported (not disabled by fuse)
> +
> +  @retval GbE support state
> +**/
> +BOOLEAN
> +PmcIsGbeSupported (
> +  VOID
> +  );
> +
> +/**
> +  This function enables all SerailIo devices
> +  Static power gating disabling takes place after Global Reset, G3 or DeepSx
> transition.
> +**/
> +VOID
> +PmcEnableSerialIo (
> +  VOID
> +  );
> +
> +/**
> +  This function disables (static power gating) all SerailIo devices.
> +  For SerialIo controllers they can be power gated only if all of them are to be
> disabled.
> +  They cannot be statically power gated separately.
> +  For static power gating to take place Global Reset, G3 or DeepSx transition
> must happen.
> +**/
> +VOID
> +PmcStaticDisableSerialIo (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if all SerialIo devices are statically disabled (static
> power gating)
> +
> +  @retval SerialIo disable state
> +**/
> +BOOLEAN
> +PmcIsSerialIoStaticallyDisabled (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if SerialIo device is supported (not disabled by fuse)
> +
> +  @retval SerialIo support state
> +**/
> +BOOLEAN
> +PmcIsSerialIoSupported (
> +  VOID
> +  );
> +
> +/**
> +  This function disables (non-static power gating) HDA device
> +**/
> +VOID
> +PmcDisableHda (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if Cnvi device is supported (not disabled by fuse)
> +
> +  @retval Cnvi support state
> +**/
> +BOOLEAN
> +PmcIsCnviSupported (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if CNVi is function disabled
> +  by static power gating
> +
> +  @retval GbE device state
> +**/
> +BOOLEAN
> +PmcIsCnviFunctionDisabled (
> +  VOID
> +  );
> +
> +/**
> +  This function enables CNVi device by disabling static power gating.
> +  Static power gating disabling takes place after Global Reset, G3 or DeepSx
> transition.
> +**/
> +VOID
> +PmcEnableCnvi (
> +  VOID
> +  );
> +
> +/**
> +  This function disables CNVi device by static power gating
> +  For static power gating to take place Global Reset, G3 or DeepSx transition
> must happen.
> +**/
> +VOID
> +PmcStaticDisableCnvi (
> +  VOID
> +  );
> +
> +/**
> +  This function disables (non-static power gating) PCIe Root Port
> +
> +  @param[in] RpIndex        PCIe Root Port Index (0 based)
> +**/
> +VOID
> +PmcDisablePcieRootPort (
> +  IN UINT32  RpIndex
> +  );
> +
> +/**
> +  This function disables (non-static power gating) SATA
> +
> +  @param[in]  SataCtrlIndex     SATA controller index
> +**/
> +VOID
> +PmcDisableSata (
> +  IN UINT32     SataCtrlIndex
> +  );
> +
> +/**
> +  This function checks if SATA device is supported (not disabled by fuse)
> +
> +  @param[in] SataCtrlIndex SATA controller index
> +
> +  @retval SATA support state
> +**/
> +BOOLEAN
> +PmcIsSataSupported (
> +  IN UINT32  SataCtrlIndex
> +  );
> +
> +/**
> +  This function gets NMI regsiter.
> +
> +  @retval  NMI register setting
> +**/
> +UINT32
> +PmcGetNmiControl (
> +  VOID
> +  );
> +
> +/**
> +  This function sets the NMI register
> +
> +  @param[in]  NmiRegister    The whole NMI register
> +**/
> +VOID
> +PmcSetNmiControl (
> +  UINT32   NmiRegister
> +  );
> +
> +/**
> +  This function disables (non-static power gating) xHCI
> +**/
> +VOID
> +PmcDisableXhci (
> +  VOID
> +  );
> +
> +/**
> +  This function disables (non-static power gating) XDCI
> +**/
> +VOID
> +PmcDisableXdci (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if XDCI device is supported (not disabled by fuse)
> +
> +  @retval XDCI support state
> +**/
> +BOOLEAN
> +PmcIsXdciSupported (
> +  VOID
> +  );
> +
> +/**
> +  This function disables (non-static power gating) SCS eMMC controller and
> enables ModPHY SPD gating (PCH-LP only).
> +**/
> +VOID
> +PmcDisableScsEmmc (
> +  VOID
> +  );
> +
> +/**
> +  This function disables (non-static power gating) SCS SD Card controller and
> enables ModPHY SPD gating (PCH-LP only).
> +**/
> +VOID
> +PmcDisableScsSdCard (
> +  VOID
> +  );
> +
> +/**
> +  This function disables (non-static power gating) SCS UFS controller and
> enables ModPHY SPD gating (PCH-LP only).
> +
> +  @param[in] UfsNum     SCS UFS Device
> +**/
> +VOID
> +PmcDisableScsUfs (
> +  IN UINT32   UfsNum
> +  );
> +
> +/**
> +  This function checks if SCS eMMC device is supported (not disabled by fuse)
> +
> +  @retval SCS device support state
> +**/
> +BOOLEAN
> +PmcIsScsEmmcSupported (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if SCS SD Card device is supported (not disabled by fuse)
> +
> +  @retval SCS device support state
> +**/
> +BOOLEAN
> +PmcIsScsSdCardSupported (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if SCS UFS device is supported (not disabled by fuse)
> +
> +  @param[in] UfsNum     SCS UFS Device
> +
> +  @retval SCS device support state
> +**/
> +BOOLEAN
> +PmcIsScsUfsSupported (
> +  IN UINT32   UfsNum
> +  );
> +
> +
> +/**
> +  This function locks HOST SW power gating control
> +**/
> +VOID
> +PmcLockHostSwPgCtrl (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if HOST SW Power Gating Control is locked
> +
> +  @retval lock state
> +**/
> +BOOLEAN
> +PmcIsHostSwPgCtrlLocked (
> +  VOID
> +  );
> +
> +/**
> +  This function disables Trace Hub by enabling power gating
> +**/
> +VOID
> +PmcDisableTraceHub (
> +  VOID
> +  );
> +
> +/**
> +  This function enables Trace Hub by disabling power gating
> +**/
> +VOID
> +PmcEnableTraceHub (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if LAN wake from DeepSx is enabled
> +
> +  @retval Lan Wake state
> +**/
> +BOOLEAN
> +PmcIsLanDeepSxWakeEnabled (
> +  VOID
> +  );
> +
> +/**
> +  This function locks down PMC (DebugModeLock)
> +**/
> +VOID
> +PmcLockWithS3BootScript (
> +  VOID
> +  );
> +
> +/**
> +  Checks if conditions for proper USB2 PHY AFE programming are met
> +**/
> +VOID
> +PmcUsb2CorePhyPowerGatingDisable (
> +  VOID
> +  );
> +
> +/**
> +  This function reads CPU Early Power-on Configuration (EPOC)
> +
> +  @retval CPU EPOC value
> +**/
> +UINT32
> +PmcGetCpuEpoc (
> +  VOID
> +  );
> +
> +/**
> +  This function sets CPU Early Power-on Configuration (EPOC)
> +
> +  @param[in] CpuEpocValue      CPU EPOC value
> +**/
> +VOID
> +PmcSetCpuEpoc (
> +  IN UINT32     CpuEpocValue
> +  );
> +
> +/**
> +  This function sets DRAM_RESET# Control Pin value
> +
> +  @param[in] DramResetVal      0: Pin output is low
> +                               1: Pin output is tri-stated
> +**/
> +VOID
> +PmcSetDramResetCtlState (
> +  IN UINT32     DramResetVal
> +  );
> +
> +/**
> +  This function enables triggering Global Reset of both
> +  the Host and the ME partitions after CF9h write of 6h or Eh
> +**/
> +VOID
> +PmcEnableCf9GlobalReset (
> +  VOID
> +  );
> +
> +/**
> +  This function disables triggering Global Reset of both
> +  the Host and the ME partitions after CF9h write of 6h or Eh.
> +**/
> +VOID
> +PmcDisableCf9GlobalReset (
> +  VOID
> +  );
> +
> +/**
> +  This function disables triggering Global Reset of both
> +  the Host and the ME partitions after CF9h write of 6h or Eh.
> +  Global Reset configuration is locked after programming
> +**/
> +VOID
> +PmcDisableCf9GlobalResetWithLock (
> +  VOID
> +  );
> +
> +/**
> +  This S3 BootScript only function disables triggering Global Reset of both
> +  the Host and the ME partitions after CF9h write of 6h or Eh.
> +**/
> +VOID
> +PmcDisableCf9GlobalResetInS3BootScript (
> +  VOID
> +  );
> +
> +/**
> +  This S3 BootScript only function disables triggering Global Reset of both
> +  the Host and the ME partitions after CF9h write of 6h or Eh.
> +  Global Reset configuration is locked after programming
> +**/
> +VOID
> +PmcDisableCf9GlobalResetWithLockInS3BootScript (
> +  VOID
> +  );
> +
> +/**
> +  This function disables CF9 reset without Resume Well reset.
> +  Cf9 0x6/0xE reset will also reset resume well logic.
> +**/
> +VOID
> +PmcDisableCf9ResetWithoutResumeWell (
> +  VOID
> +  );
> +
> +/**
> +  This function locks PMC Set Strap Message interface with S3 Boot Script
> programming
> +**/
> +VOID
> +PmcLockSetStrapMsgInterfaceWithS3BootScript (
> +  VOID
> +  );
> +
> +/**
> +  This function clears RTC Power Failure status (RTC_PWR_FLR)
> +**/
> +VOID
> +PmcClearRtcPowerFailureStatus (
> +  VOID
> +  );
> +
> +/**
> +  This function enables PCI Express* PME events
> +**/
> +VOID
> +PmcEnablePciExpressPmeEvents (
> +  VOID
> +  );
> +
> +/**
> +  This function sets SLP_SX Stretching Policy and adds
> +  lock setting to S3 Boot Script
> +**/
> +VOID
> +PmcLockSlpSxStretchingPolicyWithS3BootScript (
> +  VOID
> +  );
> +
> +/**
> +  This function sets SMI Lock with S3 Boot Script programming
> +**/
> +VOID
> +PmcLockSmiWithS3BootScript (
> +  VOID
> +  );
> +
> +/**
> +  This function sets eSPI SMI Lock
> +**/
> +VOID
> +PmcLockEspiSmi (
> +  VOID
> +  );
> +
> +/**
> +  This function checks if eSPI SMI Lock is set
> +
> +  @retval eSPI SMI Lock state
> +**/
> +BOOLEAN
> +PmcIsEspiSmiLockSet (
> +  VOID
> +  );
> +
> +typedef enum {
> +  PmcSwSmiRate1p5ms = 0,
> +  PmcSwSmiRate16ms,
> +  PmcSwSmiRate32ms,
> +  PmcSwSmiRate64ms
> +} PMC_SWSMI_RATE;
> +
> +/**
> +  This function sets SW SMI Rate.
> +
> +  @param[in] SwSmiRate        Refer to PMC_SWSMI_RATE for possible
> values
> +**/
> +VOID
> +PmcSetSwSmiRate (
> +  IN PMC_SWSMI_RATE          SwSmiRate
> +  );
> +
> +typedef enum {
> +  PmcPeriodicSmiRate8s = 0,
> +  PmcPeriodicSmiRate16s,
> +  PmcPeriodicSmiRate32s,
> +  PmcPeriodicSmiRate64s
> +} PMC_PERIODIC_SMI_RATE;
> +
> +/**
> +  This function sets Periodic SMI Rate.
> +
> +  @param[in] PeriodicSmiRate        Refer to PMC_PERIODIC_SMI_RATE for
> possible values
> +**/
> +VOID
> +PmcSetPeriodicSmiRate (
> +  IN PMC_PERIODIC_SMI_RATE    PeriodicSmiRate
> +  );
> +
> +/**
> +  This function reads Power Button Level
> +
> +  @retval State of PWRBTN# signal (0: Low, 1: High)
> +**/
> +UINT8
> +PmcGetPwrBtnLevel (
> +  VOID
> +  );
> +
> +/**
> +  This function gets Group to GPE0 configuration
> +
> +  @param[out] GpeDw0Value       GPIO Group to GPE_DW0 assignment
> +  @param[out] GpeDw1Value       GPIO Group to GPE_DW1 assignment
> +  @param[out] GpeDw2Value       GPIO Group to GPE_DW2 assignment
> +**/
> +VOID
> +PmcGetGpioGpe (
> +  OUT UINT32    *GpeDw0Value,
> +  OUT UINT32    *GpeDw1Value,
> +  OUT UINT32    *GpeDw2Value
> +  );
> +
> +/**
> +  This function sets Group to GPE0 configuration
> +
> +  @param[out] GpeDw0Value       GPIO Group to GPE_DW0 assignment
> +  @param[out] GpeDw1Value       GPIO Group to GPE_DW1 assignment
> +  @param[out] GpeDw2Value       GPIO Group to GPE_DW2 assignment
> +**/
> +VOID
> +PmcSetGpioGpe (
> +  IN UINT32    GpeDw0Value,
> +  IN UINT32    GpeDw1Value,
> +  IN UINT32    GpeDw2Value
> +  );
> +
> +/**
> +  This function checks if SCI interrupt is enabled
> +
> +  @retval SCI Enable state
> +**/
> +BOOLEAN
> +PmcIsSciEnabled (
> +  VOID
> +  );
> +
> +/**
> +  This function triggers Software GPE
> +**/
> +VOID
> +PmcTriggerSwGpe (
> +  VOID
> +  );
> +
> +/**
> +  Disable SLP_S0# assertion when system is in debug mode
> +**/
> +VOID
> +PmcDisableSlpS0AssertionInDebugMode (
> +  VOID
> +  );
> +
> +/**
> +  Enable SLP_S0# assertion even when system is in debug mode
> +**/
> +VOID
> +PmcEnableSlpS0AssertionInDebugMode (
> +  VOID
> +  );
> +
> +#endif // _PMC_PRIVATE_LIB_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SiScheduleR
> esetLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SiSchedule
> ResetLib.h
> new file mode 100644
> index 0000000000..af5734b74b
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SiSchedule
> ResetLib.h
> @@ -0,0 +1,48 @@
> +/** @file
> +  Reset scheduling library services
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SI_SCHEDULE_RESET_LIB_H_
> +#define _SI_SCHEDULE_RESET_LIB_H_
> +
> +#include <Uefi/UefiMultiPhase.h>
> +#include <PchResetPlatformSpecific.h>
> +
> +/**
> +  This function updates the reset information in SiScheduleResetHob
> +  @param[in] ResetType        UEFI defined reset type.
> +  @param[in] ResetData        Optional element used to introduce a platform
> specific reset.
> +                               The exact type of the reset is defined by the EFI_GUID
> that follows
> +                               the Null-terminated Unicode string.
> +**/
> +VOID
> +SiScheduleResetSetType (
> +  IN EFI_RESET_TYPE     ResetType,
> +  IN PCH_RESET_DATA     *ResetData OPTIONAL
> +  );
> +
> +/**
> +  This function returns TRUE or FALSE depending on whether a reset is
> required based on SiScheduleResetHob
> +
> +  @retval     BOOLEAN       The function returns FALSE if no reset is required
> +**/
> +BOOLEAN
> +SiScheduleResetIsRequired (
> +  VOID
> +  );
> +
> +/**
> +  This function performs reset based on SiScheduleResetHob
> +
> +  @retval     BOOLEAN       The function returns FALSE if no reset is required
> +**/
> +BOOLEAN
> +SiScheduleResetPerformReset (
> +  VOID
> +  );
> +
> +#endif //_SI_SCHEDULE_RESET_LIB_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SmmPchPri
> vateLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SmmPchPri
> vateLib.h
> new file mode 100644
> index 0000000000..f074e0073a
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SmmPchPri
> vateLib.h
> @@ -0,0 +1,28 @@
> +/** @file
> +  Header file for private PCH SMM Lib.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SMM_PCH_PRIVATE_LIB_H_
> +#define _SMM_PCH_PRIVATE_LIB_H_
> +
> +/**
> +  Set InSmm.Sts bit
> +**/
> +VOID
> +PchSetInSmmSts (
> +  VOID
> +  );
> +
> +/**
> +  Clear InSmm.Sts bit
> +**/
> +VOID
> +PchClearInSmmSts (
> +  VOID
> +  );
> +
> +#endif // _SMM_PCH_PRIVATE_LIB_H_
> --
> 2.16.2.windows.1


  parent reply	other threads:[~2019-08-17  1:10 UTC|newest]

Thread overview: 121+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-17  0:15 [edk2-platforms][PATCH V1 00/37] Coffee Lake and Whiskey Lake support Kubacki, Michael A
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and Include headers Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:08   ` Chiu, Chasel
2019-08-17  1:18   ` Chaganty, Rangasai V
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add " Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:08   ` Chiu, Chasel
2019-08-17  6:58   ` Chaganty, Rangasai V
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: " Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:08   ` Chiu, Chasel
2019-08-17  7:04   ` Chaganty, Rangasai V
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add include headers Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:08   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add ConfigBlock headers Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:09   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add Library include headers Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:09   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI and Protocol " Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:09   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 08/37] CoffeelakeSiliconPkg/Pch: Add Register " Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:09   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add Private " Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:12   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add Private/Library " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:09   ` Chiu, Chasel [this message]
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol " Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:10   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode: Add Include headers Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:12   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 13/37] CoffeelakeSiliconPkg/SystemAgent: " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:12   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 14/37] CoffeelakeSiliconPkg: Add package common library instances Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:12   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:15   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 16/37] CoffeelakeSiliconPkg/Me: " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:12   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 17/37] CoffeelakeSiliconPkg/Pch: Add Base " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:13   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 18/37] CoffeelakeSiliconPkg/Pch: Add DXE " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:13   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 19/37] CoffeelakeSiliconPkg/Pch: Add PEI " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:13   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 20/37] CoffeelakeSiliconPkg/Pch: Add SMM " Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:16   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 21/37] CoffeelakeSiliconPkg/Pch: Add Base " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:13   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 22/37] CoffeelakeSiliconPkg/Pch: Add DXE private " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:13   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 23/37] CoffeelakeSiliconPkg/Pch: Add PEI " Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:14   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 24/37] CoffeelakeSiliconPkg/Pch: Add SMM " Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:14   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 25/37] CoffeelakeSiliconPkg/SystemAgent: Add " Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:14   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 26/37] CoffeelakeSiliconPkg/Pch: Add modules Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:14   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 27/37] CoffeelakeSiliconPkg/Pch: Add PchSmiDispatcher Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:15   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 28/37] CoffeelakeSiliconPkg/SystemAgent: Add modules Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:15   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package DSC files Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:14   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 30/37] Maintainers.txt: Add CoffeelakeSiliconPkg maintainers Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:15   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 31/37] WhiskeylakeOpenBoardPkg: Add package and headers Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:16   ` Chiu, Chasel
2019-08-19 18:09   ` Sinha, Ankit
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 32/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:16   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 33/37] WhiskeylakeOpenBoardPkg: Add library instances Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:16   ` Chiu, Chasel
2019-08-17  0:16 ` [edk2-platforms][PATCH V1 34/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: " Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:17   ` Chiu, Chasel
2019-08-17 20:08   ` Chaganty, Rangasai V
2019-08-17  0:16 ` [edk2-platforms][PATCH V1 35/37] WhiskeylakeOpenBoardPkg: Add modules Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:17   ` Chiu, Chasel
2019-08-17  7:50   ` Chaganty, Rangasai V
2019-08-17  0:16 ` [edk2-platforms][PATCH V1 36/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:16   ` Chiu, Chasel
2019-08-17 20:11   ` Chaganty, Rangasai V
2019-08-17  0:16 ` [edk2-platforms][PATCH V1 37/37] Add WhiskeylakeOpenBoardPkg to global build config and documentation Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:17   ` Chiu, Chasel
2019-08-17 20:00   ` Chaganty, Rangasai V
2019-08-19 18:14 ` [edk2-platforms][PATCH V1 00/37] Coffee Lake and Whiskey Lake support Sinha, Ankit

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