From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: chasel.chiu@intel.com) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by groups.io with SMTP; Fri, 16 Aug 2019 18:10:07 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 18:10:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="188973442" Received: from pgsmsx107.gar.corp.intel.com ([10.221.44.105]) by orsmga002.jf.intel.com with ESMTP; 16 Aug 2019 18:10:05 -0700 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.22]) by PGSMSX107.gar.corp.intel.com ([169.254.7.174]) with mapi id 14.03.0439.000; Sat, 17 Aug 2019 09:10:04 +0800 From: "Chiu, Chasel" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Desimone, Nathaniel L" , "Gao, Liming" , "Kinney, Michael D" , "Sinha, Ankit" Subject: Re: [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol include headers Thread-Topic: [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol include headers Thread-Index: AQHVVJEWB2YfX/fcYUWoQhFLOlggcab+h9UQ Date: Sat, 17 Aug 2019 01:10:04 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC504622B1@PGSMSX111.gar.corp.intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> <20190817001603.30632-12-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-12-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYTZiMGZkMmYtYmY0YS00YTYyLWE1YWQtYTQ5NjI4NTI1MDcwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiNHBwNE1cLythSmpDWVcxV1ZTbTJieHZKVjRiZloxUEYzZ015bTVYa3BCNFwvcFZ6OXBkZU5BM2U3VUJPQkZqNmlyIn0= x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.206] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: Kubacki, Michael A > Sent: Saturday, August 17, 2019 8:16 AM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Chiu, Chasel > ; Desimone, Nathaniel L > ; Gao, Liming ; > Kinney, Michael D ; Sinha, Ankit > > Subject: [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add > Private/Protocol include headers >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 >=20 > Adds the following header files: > * Pch/Include/Private/Protocol >=20 > Cc: Sai Chaganty > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Liming Gao > Cc: Michael D Kinney > Cc: Ankit Sinha > Signed-off-by: Michael Kubacki > --- >=20 > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsAre= a. > h | 31 ++++++++++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTra= p.h > | 37 ++++++++++++++++++++ > 2 files changed, 68 insertions(+) >=20 > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsA= r > ea.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsA= r > ea.h > new file mode 100644 > index 0000000000..75003c82ad > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/Pc > +++ hNvsArea.h > @@ -0,0 +1,31 @@ > +/** @file > + This file defines the PCH NVS Area Protocol. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _PCH_NVS_AREA_H_ > +#define _PCH_NVS_AREA_H_ > + > +// > +// PCH NVS Area definition > +// > +#include > + > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID gPchNvsAreaProtocolGuid; > + > +/** > + This protocol is used to sync PCH information from POST to runtime ASL= . > + This protocol exposes the pointer of PCH NVS Area only. Please refer > +to > + ASL definition for PCH NVS AREA. > +**/ > +typedef struct { > + PCH_NVS_AREA *Area; > +} PCH_NVS_AREA_PROTOCOL; > + > +#endif // _PCH_NVS_AREA_H_ > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoT= rap > .h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoT= rap > .h > new file mode 100644 > index 0000000000..2cd6b85d29 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/Pc > +++ ieIoTrap.h > @@ -0,0 +1,37 @@ > +/** @file > + This file defines the PCH PCIE IoTrap Protocol. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent **/ > + > +#ifndef _PCH_PCIE_IOTRAP_H_ > +#define _PCH_PCIE_IOTRAP_H_ > + > +// > +// Extern the GUID for protocol users. > +// > +extern EFI_GUID gPchPcieIoTrapProtocolGuid; > + > +// > +// Forward reference for ANSI C compatibility // typedef struct > +_PCH_PCIE_IOTRAP_PROTOCOL PCH_PCIE_IOTRAP_PROTOCOL; > + > +/// > +/// Pcie Trap valid types > +/// > +typedef enum { > + PciePmTrap, > + PcieTrapTypeMaximum > +} PCH_PCIE_TRAP_TYPE; > + > +/** > + This protocol is used to provide the IoTrap address to trigger PCH > +PCIE call back events **/ struct _PCH_PCIE_IOTRAP_PROTOCOL { > + UINT16 PcieTrapAddress; > +}; > + > +#endif > -- > 2.16.2.windows.1