From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: chasel.chiu@intel.com) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by groups.io with SMTP; Fri, 16 Aug 2019 18:12:16 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 18:12:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="352697539" Received: from pgsmsx112.gar.corp.intel.com ([10.108.55.201]) by orsmga005.jf.intel.com with ESMTP; 16 Aug 2019 18:12:13 -0700 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.22]) by PGSMSX112.gar.corp.intel.com ([169.254.3.188]) with mapi id 14.03.0439.000; Sat, 17 Aug 2019 09:12:13 +0800 From: "Chiu, Chasel" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Desimone, Nathaniel L" , "Gao, Liming" , "Kinney, Michael D" , "Sinha, Ankit" Subject: Re: [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add Private include headers Thread-Topic: [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add Private include headers Thread-Index: AQHVVJEVOHNH/T6TwUeU0kzTyhp6vKb+iG7Q Date: Sat, 17 Aug 2019 01:12:13 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC504622E7@PGSMSX111.gar.corp.intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> <20190817001603.30632-10-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-10-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZGMxNTE4MzctMjE5NC00YjEzLWI3MDEtN2NhZDk4ZmZjMWFiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiMEZcL21XbnpvOVNXVEswZjVFRzh4REhrcHZmdGsrS0J6alg1Y2VuU1lEeHhCd1pLMmNPYnU2THF6ZGdrV081cHcifQ== x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.206] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: Kubacki, Michael A > Sent: Saturday, August 17, 2019 8:16 AM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Chiu, Chasel > ; Desimone, Nathaniel L > ; Gao, Liming ; > Kinney, Michael D ; Sinha, Ankit > > Subject: [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add > Private include headers >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 >=20 > Adds the following header files: > * Pch/Include/Private >=20 > Cc: Sai Chaganty > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Liming Gao > Cc: Michael D Kinney > Cc: Ankit Sinha > Signed-off-by: Michael Kubacki > --- > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h > | 16 ++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h > | 273 ++++++++++++++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHdaEndpoints.h > | 115 +++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHsio.h = | > 92 +++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchNvsAreaDef.h > | 269 +++++++++++++++++++ > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchRstHob.h = | > 58 +++++ >=20 > Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/SiScheduleResetHob= . > h | 25 ++ > 7 files changed, 848 insertions(+) >=20 > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h > new file mode 100644 > index 0000000000..6c9d10e928 > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h > @@ -0,0 +1,16 @@ > +/** @file > + CnlPchLp Dx HSIO Header File > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _CNL_PCH_LP_HSIO_DX_H_ > +#define _CNL_PCH_LP_HSIO_DX_H_ > + > +#define CNL_PCH_LP_HSIO_VER_DX 0x7 > + > + > +extern UINT8 CnlPchLpChipsetInitTable_Dx[5072]; > +extern UINT8 CnlPchLpChipsetInitTable_eDBC_Dx[4612]= ; > +#endif //_CNL_PCH_LP_HSIO_DX_H_ > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h > new file mode 100644 > index 0000000000..5569da670d > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h > @@ -0,0 +1,273 @@ > +/** @file > + The GUID definition for PchConfigHob > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_CONFIG_HOB_H_ > +#define _PCH_CONFIG_HOB_H_ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +extern EFI_GUID gPchConfigHobGuid; > + > +#pragma pack (push,1) > + > +/// > +/// This structure contains the HOB which are related to PCH general con= fig. > +/// > +typedef struct { > + /** > + This member describes whether or not the Compatibility Revision ID (= CRID) > feature > + of PCH should be enabled. 0: Disable; 1: Enable > + **/ > + UINT32 Crid : 1; > + UINT32 RsvdBits0 : 31; ///< Reserved bits > + /// > + /// > +} GENERAL_HOB; > + > +/// > +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP > capable devices in the platform. > +/// > +typedef struct { > + UINT8 RsvdBytes[3]; > + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in > the RsvdSmbusAddressTable. > + /** > + Array of addresses reserved for non-ARP-capable SMBus devices. > + **/ > + UINT8 > RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS]; > +} SMBUS_HOB; > + > +/// > +/// The INTERRUPT describes interrupt settings for PCH HOB. > +/// > +typedef struct { > + UINT8 NumOfDevIntConfig; = ///< > Number of entries in DevIntConfig table > + UINT8 GpioIrqRoute; = ///< > Interrupt routing for GPIO. Default is 14. > + UINT8 Rsvd0[2]; = ///< > Reserved bytes, align to multiple 4. > + PCH_DEVICE_INTERRUPT_CONFIG > DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which > stores PCH devices interrupts settings > + UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG]; > ///< PCI interrupt routing for 8259 PIC controller > +} INTERRUPT_HOB; > + > +/// > +/// The CNVI_HOB block describes CNVi device. > +/// > +typedef struct { > + UINT32 Mode : 1; ///< 0: Disabled, 1:= Auto > + UINT32 RsvdBits0 : 31; > +} CNVI_HOB; > + > +/** > + The SERIAL_IO block provides the configurations to set the Serial IO > controllers > +**/ > +typedef struct { > + /** > + 0: Disabled; > + - Device is placed in D3 > + - Gpio configuration is skipped > + - Device will be disabled in PSF > + - !important! If given device is Function 0 and not all other = LPSS > functions on given device > + are disabled, then PSF disabling is skipped. > + PSF default will remain and device PCI CFG Space= will still be > visible. > + This is needed to allow PCI enumerator access fu= nctions > above 0 in a multifunction device. > + 1: Pci; > + - Gpio pin configuration in native mode for each assigned pin > + RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowC= trl > + - Device will be enabled in PSF > + - Only Bar 0 will be enabled > + 2: Acpi; > + - Gpio pin configuration in native mode for each assigned pin > + RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowC= trl > + - Device will be hidden in PSF and not available to PCI enumer= ator > + - Both BARs are enabled, BAR1 becomes devices Pci config Space > + @note Intel does not provide Windows SerialIo drivers for this mode > + 3: Hidden; > + Designated for Kernel Debug and Legacy UART configuartion, mig= ht > also be used for IO Expander on I2C > + - Device is placed in D0 > + - Gpio pin configuration in native mode for each assigned pin > + RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowC= trl > + - Device will be hidden in PSF and not available to PCI enumer= ator > + - Both BARs are enabled, BAR1 becomes devices Pci config Space > + - !important! In this mode UART will work in 16550 Legacy 8BIT= Mode, > it's resources will be assigned to mother board through ACPI (PNP0C02) > + @note Considering the PcdSerialIoUartDebugEnable and > PcdSerialIoUartNumber for all SerialIo UARTx, > + the PCD is more meaningful to represent the board design. It m= eans, > if PcdSerialIoUartDebugEnable is not 0, > + the board is designed to use the SerialIo UART for debug messa= ge and > the PcdSerialIoUartNumber is dedicated > + to be Debug UART usage. Therefore, it should grayout the optio= n from > setup menu since no other options > + available for this UART controller on this board, and also ove= rride the > policy default accordingly. > + While PcdSerialIoUartDebugEnable is 0, then it's allowed to co= nfigure > the UART controller by policy. > + **/ > + UINT8 DevMode[PCH_MAX_SERIALIO_CONTROLLERS]; > + UINT32 DebugUartNumber : 2; ///< UART nu= mber for > debug purpose. 0:UART0, 1: UART1, 2:UART2 > + UINT32 EnableDebugUartAfterPost : 1; ///< Enable = debug > UART controller after post. 0: disabled, 1: enabled > + UINT32 RsvdBits0 : 29; > +} SERIAL_IO_HOB; > + > + > +/// > +/// The PCH_PCIE_CONFIG block describes the expected configuration of th= e > PCH PCI Express controllers > +/// > +typedef struct { > + /// > + /// These members describe the configuration of each PCH PCIe root por= t. > + /// > + PCH_PCIE_ROOT_PORT_CONFIG > RootPort[PCH_MAX_PCIE_ROOT_PORTS]; > + /** > + This member allows BIOS to control ICC PLL Shutdown by determining P= CIe > devices are LTR capable > + or leaving untouched. > + - 0: Disable, ICC PLL Shutdown is determined by PCIe device LTR > capablility. > + - To allow ICC PLL shutdown if all present PCIe devices are LTR ca= pable or > if no PCIe devices are > + presented for maximum power savings where possible. > + - To disable ICC PLL shutdown when BIOS detects any non-LTR capabl= e > PCIe device for ensuring device > + functionality. > + - 1: Enable, To allow ICC PLL shutdown even if some devices do not s= upport > LTR capability. > + **/ > + UINT32 AllowNoLtrIccPllShutdown : 1; > + UINT32 RsvdBits0 : 31; > +} PCIERP_HOB; > + > +typedef struct { > + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable= ; 1: > Enable > + UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake > initiated by a codec in Sx, 0: Disable; 1: Enable > + UINT32 AudioLinkSndw1 : 1; ///< SoundWire1 link enablement= : > 0: Disable; 1: Enable. Muxed with HDA > + UINT32 AudioLinkSndw2 : 1; ///< SoundWire2 link enablement= : > 0: Disable; 1: Enable. Muxed with SSP1 > + UINT32 AudioLinkSndw3 : 1; ///< SoundWire3 link enablement= : > 0: Disable; 1: Enable. Muxed with DMIC1 > + UINT32 AudioLinkSndw4 : 1; ///< SoundWire4 link enablement= : > 0: Disable; 1: Enable. Muxed with DMIC0 > + UINT32 RsvdBits0 : 26; ///< Reserved bits > +} HDAUDIO_HOB; > + > +typedef struct { > + /// > + /// This member describes whether or not the SATA controllers should b= e > enabled. 0: Disable; 1: Enable. > + /// > + UINT32 Enable : 1; > + UINT32 TestMode : 1; ///< (Tes= t) 0: > Disable; 1: Allow entrance to the PCH SATA test modes > + UINT32 RsvdBits0 : 30; ///< Reserve= d bits > + /** > + This member configures the features, property, and capability for ea= ch > SATA port. > + **/ > + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS]; > + /** > + This member describes the details of implementation of Intel RST for= PCIe > Storage remapping (Intel RST Driver is required) > + **/ > + PCH_RST_PCIE_STORAGE_CONFIG > RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR]; > +} SATA_HOB; > + > +/// > +/// The SCS_HOB block describes Storage and Communication Subsystem > (SCS) settings for PCH. > +/// > +typedef struct { > + UINT32 ScsEmmcEnabled : 2; ///< Determine if e= MMC is > enabled - 0: Disabled, 1: Enabled. > + UINT32 ScsEmmcHs400Enabled : 1; ///< Determine eMMC > HS400 Mode if ScsEmmcEnabled - 0: Disabled, 1: Enabled > + /** > + Determine if HS400 Training is required, set to FALSE if Hs400 Data = is valid. > 0: Disabled, 1: Enabled. > + First Boot or CMOS clear, system boot with Default settings, set tun= ing > required. > + Subsequent Boots, Get Variable 'Hs400TuningData' > + - if failed to get variable, set tuning required > + - if passed, retrieve Hs400DataValid, Hs400RxStrobe1Dll and > Hs400TxDataDll from variable. Set tuning not required. > + **/ > + UINT32 ScsEmmcHs400TuningRequired : 1; > + UINT32 ScsEmmcHs400DllDataValid : 1; ///< Set if HS400 T= uning > Data Valid > + UINT32 ScsEmmcHs400DriverStrength : 3; ///< I/O driver str= ength: > 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm > + UINT32 ScsSdPowerEnableActiveHigh : 1; ///< Sd PWREN# acti= ve > high > + UINT32 ScsSdCardEnabled : 1; ///< Sd card enable= d > + UINT32 RsvdBits : 22; > +} SCS_HOB; > + > +/** > + The PCH_LOCK_DOWN_CONFIG block describes the expected configuration > of the PCH > + for security requirement. > +**/ > +typedef struct { > + UINT32 GlobalSmi : 1; > + /** > + (Test) Enable BIOS Interface Lock Down bit to prevent writes = to the > Backup Control Register > + Top Swap bit and the General Control and Status Registers Boot BIOS > Straps. 0: Disable; 1: Enable. > + **/ > + UINT32 BiosInterface : 1; > + /** > + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh = in the > upper > + and lower 128-byte bank of RTC RAM. 0: Disable; 1: Enable. > + **/ > + UINT32 RtcMemoryLock : 1; > + /** > + Enable the BIOS Lock Enable (BLE) feature and set EISS bit > (D31:F5:RegDCh[5]) > + for the BIOS region protection. When it is enabled, the BIOS Region = can > only be > + modified from SMM after EndOfDxe protocol is installed. > + Note: When BiosLock is enabled, platform code also needs to update t= o > take care > + of BIOS modification (including SetVariable) in DXE or runtime phase= after > + EndOfDxe protocol is installed. > + Enable InSMM.STS (EISS) in SPI > + If this EISS bit is set, then WPD must be a '1' and InSMM.STS must b= e '1' also > + in order to write to BIOS regions of SPI Flash. If this EISS bit is = clear, > + then the InSMM.STS is a don't care. > + The BIOS must set the EISS bit while BIOS Guard support is enabled. > + In recovery path, platform can temporary disable EISS for SPI progra= mming > in > + PEI phase or early DXE phase. > + 0: Disable; 1: Enable. > + **/ > + UINT32 BiosLock : 1; > + UINT32 RsvdBits : 28; > +} LOCK_DOWN_HOB; > + > +/** > + The PM_HOB block describes expected miscellaneous power management > settings. > + The PowerResetStatusClear field would clear the Power/Reset status bit= s, > please > + set the bits if you want PCH Init driver to clear it, if you want to c= heck the > + status later then clear the bits. > +**/ > +typedef struct { > + UINT32 SlpS0VmRuntimeControl : 1; /// < S= LP_S0 > Voltage Margining Runtime Control. 0: Disable; 1: Enable. > + UINT32 SlpS0Vm070VSupport : 1; /// < S= LP_S0 > 0.70V Voltage Margining Support. 0: Disable; 1: Enable. > + UINT32 SlpS0Vm075VSupport : 1; /// < S= LP_S0 > 0.75V Voltage Margining Support. 0: Disable; 1: Enable. > + UINT32 PsOnEnable : 1; /// < I= ndicates if > PS_ON support has been enabled, 0: Disable; 1: Enable. > + UINT32 RsvdBits1 : 28; > +} PM_HOB; > + > +/** > + PCH Trace Hub HOB settings. > +**/ > +typedef struct { > + UINT32 PchTraceHubMode : 2; // 0 =3D Disable; 1 =3D Tar= get > Debugger mode; 2 =3D Host Debugger mode > + UINT32 Rsvd1 : 30; // Reserved bytes > +} PCH_TRACEHUB_HOB; > + > +/** > + PCH eSPI HOB settings. > +**/ > +typedef struct { > + UINT32 BmeMasterSlaveEnabled : 1; // 0 =3D BME disable; 1 =3D= BME > enable > + UINT32 RsvdBits : 31; > +} PCH_ESPI_HOB; > + > + > +/// > +/// Pch Config Hob > +/// > +typedef struct { > + EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID HOB type structure > for gPchConfigHobGuid > + GENERAL_HOB General; ///< Pch general HOB definition > + INTERRUPT_HOB Interrupt; ///< Interrupt HOB definition > + SERIAL_IO_HOB SerialIo; ///< Serial io HOB definition > + PCIERP_HOB PcieRp; ///< PCIE root port HOB definit= ion > + SCS_HOB Scs; ///< Scs HOB definition > + CNVI_HOB Cnvi; ///< Cnvi Hob definition > + LOCK_DOWN_HOB LockDown; ///< Lock down HOB definition > + PM_HOB Pm; ///< PM HOB definition > + HDAUDIO_HOB HdAudio; ///< HD audio definition > + SATA_HOB Sata[PCH_MAX_SATA_CONTROLLERS]; ///< SATA > definition > + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; > + SMBUS_HOB Smbus; > + PCH_TRACEHUB_HOB PchTraceHub; ///< PCH Trace Hub definition > + PCH_ESPI_HOB Espi; ///< PCH eSPI definition > + > +} PCH_CONFIG_HOB; > +#pragma pack (pop) > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHdaEndpoints.= h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHdaEndpoints.= h > new file mode 100644 > index 0000000000..faaff9f497 > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHdaEndpoints.= h > @@ -0,0 +1,115 @@ > +/** @file > + Header file for PchHdaLib Endpoint descriptors. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_HDA_ENDPOINTS_H_ > +#define _PCH_HDA_ENDPOINTS_H_ > + > +#include > + > +typedef enum { > + HdaDmicX1 =3D 0, > + HdaDmicX2, > + HdaDmicX4, > + HdaBtRender, > + HdaBtCapture, > + HdaI2sRender1, > + HdaI2sRender2, > + HdaI2sCapture, > + HdaEndpointMax > +} NHLT_ENDPOINT; > + > +typedef struct { > + NHLT_ENDPOINT EndpointType; > + UINT32 EndpointFormatsBitmask; > + UINT32 EndpointDevicesBitmask; > + BOOLEAN Enable; > +} PCH_HDA_NHLT_ENDPOINTS; > + > +#define PCH_HDA_NHLT_TABLE_SIZE 0x2000 > + > +// Format bitmask > +#define B_HDA_DMIC_2CH_48KHZ_16BIT_FORMAT BIT0 > +#define B_HDA_DMIC_2CH_48KHZ_32BIT_FORMAT BIT1 > +#define B_HDA_DMIC_4CH_48KHZ_16BIT_FORMAT BIT2 > +#define B_HDA_DMIC_4CH_48KHZ_32BIT_FORMAT BIT3 > +#define B_HDA_DMIC_1CH_48KHZ_16BIT_FORMAT BIT4 > +#define B_HDA_BT_NARROWBAND_FORMAT BIT5 > +#define B_HDA_BT_WIDEBAND_FORMAT BIT6 > +#define B_HDA_BT_A2DP_FORMAT BIT7 > +#define B_HDA_I2S_RTK274_RENDER_4CH_48KHZ_24BIT_FORMAT BIT8 > +#define B_HDA_I2S_RTK274_CAPTURE_4CH_48KHZ_24BIT_FORMAT BIT9 > +#define V_HDA_FORMAT_MAX 10 > + > +// Formats > +extern CONST WAVEFORMATEXTENSIBLE Ch1_48kHz16bitFormat; > +extern CONST WAVEFORMATEXTENSIBLE Ch2_48kHz16bitFormat; > +extern CONST WAVEFORMATEXTENSIBLE Ch2_48kHz24bitFormat; > +extern CONST WAVEFORMATEXTENSIBLE Ch2_48kHz32bitFormat; > +extern CONST WAVEFORMATEXTENSIBLE Ch4_48kHz16bitFormat; > +extern CONST WAVEFORMATEXTENSIBLE Ch4_48kHz32bitFormat; > +extern CONST WAVEFORMATEXTENSIBLE NarrowbandFormat; > +extern CONST WAVEFORMATEXTENSIBLE WidebandFormat; > +extern CONST WAVEFORMATEXTENSIBLE A2dpFormat; > + > +// Format Config > +extern CONST UINT32 DmicStereo16BitFormatConfig[]; > +extern CONST UINT32 DmicStereo16BitFormatConfigSize; > +extern CONST UINT32 DmicStereo32BitFormatConfig[]; > +extern CONST UINT32 DmicStereo32BitFormatConfigSize; > +extern CONST UINT32 DmicQuad16BitFormatConfig[]; > +extern CONST UINT32 DmicQuad16BitFormatConfigSize; > +extern CONST UINT32 DmicQuad32BitFormatConfig[]; > +extern CONST UINT32 DmicQuad32BitFormatConfigSize; > +extern CONST UINT32 DmicMono16BitFormatConfig[]; > +extern CONST UINT32 DmicMono16BitFormatConfigSize; > + > +extern CONST UINT32 I2sRtk274Render4ch48kHz24bitFormatConfig[]; > +extern CONST UINT32 I2sRtk274Render4ch48kHz24bitFormatConfigSize; > +extern CONST UINT32 I2sRtk274Capture4ch48kHz24bitFormatConfig[]; > +extern CONST UINT32 I2sRtk274Capture4ch48kHz24bitFormatConfigSize; > +extern CONST UINT32 BtFormatConfig[]; > +extern CONST UINT32 BtFormatConfigSize; > + > +// Endpoints > +extern ENDPOINT_DESCRIPTOR HdaEndpointDmicX1; > +extern ENDPOINT_DESCRIPTOR HdaEndpointDmicX2; > +extern ENDPOINT_DESCRIPTOR HdaEndpointDmicX4; > +extern ENDPOINT_DESCRIPTOR HdaEndpointBtRender; > +extern ENDPOINT_DESCRIPTOR HdaEndpointBtCapture; > +extern ENDPOINT_DESCRIPTOR HdaEndpointI2sRender; > +extern ENDPOINT_DESCRIPTOR HdaEndpointI2sCapture; > + > +// Endpoint Config > +extern CONST UINT8 DmicX1Config[]; > +extern CONST UINT32 DmicX1ConfigSize; > +extern CONST UINT8 DmicX2Config[]; > +extern CONST UINT32 DmicX2ConfigSize; > +extern CONST UINT8 DmicX4Config[]; > +extern CONST UINT32 DmicX4ConfigSize; > +extern CONST UINT8 BtConfig[]; > +extern CONST UINT32 BtConfigSize; > +extern CONST UINT8 I2sRender1Config[]; > +extern CONST UINT32 I2sRender1ConfigSize; > +extern CONST UINT8 I2sRender2Config[]; > +extern CONST UINT32 I2sRender2ConfigSize; > +extern CONST UINT8 I2sCaptureConfig[]; > +extern CONST UINT32 I2sCaptureConfigSize; > + > +// Device Info bitmask > +#define B_HDA_I2S_RENDER_DEVICE_INFO BIT0 > +#define B_HDA_I2S_CAPTURE_DEVICE_INFO BIT1 > + > +// Device Info > +extern CONST DEVICE_INFO I2sRenderDeviceInfo; > +extern CONST DEVICE_INFO I2sCaptureDeviceInfo; > + > +// Oed Configuration > +extern CONST UINT32 NhltConfiguration[]; > +extern CONST UINT32 NhltConfigurationSize; > + > +#endif // _PCH_HDA_ENDPOINTS_H_ > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHs= io.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHsio.h > new file mode 100644 > index 0000000000..860ed89f0d > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHsio.h > @@ -0,0 +1,92 @@ > +/** @file > + Header file with all common HSIO information > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_HSIO_H_ > +#define _PCH_HSIO_H_ > + > +#define PCH_LANE_OWN_COMMON 0x10 > +#define PCH_LANE_BDCAST 0x11 > +#define PCH_HSIO_LANE_GROUP_NO 0x09 > +#define PCH_HSIO_LANE_GROUP_COMMON_LANE 0x00 > +#define PCH_HSIO_LANE_GROUP_PCIE 0x01 > +#define PCH_HSIO_LANE_GROUP_DMI 0x02 > +#define PCH_HSIO_LANE_GROUP_GBE 0x03 > +#define PCH_HSIO_LANE_GROUP_USB3 0x04 > +#define PCH_HSIO_LANE_GROUP_SATA 0x05 > +#define PCH_HSIO_LANE_GROUP_SSIC 0x06 > + > + > +/** > + PCH HSIO ChipsetInit Version Information > +**/ > +typedef struct { > + UINT16 BaseCrc; > + UINT16 SusCrc; > + UINT16 OemCrc; > + UINT8 Version; > + UINT8 Product; > + UINT8 MetalLayer : 4; > + UINT8 BaseLayer : 4; > + UINT8 OemVersion; > + UINT16 DebugMode : 1; > + UINT16 OemCrcValid : 1; > + UINT16 SusCrcValid : 1; > + UINT16 BaseCrcValid : 1; > + UINT16 Reserved : 12; > +} PCH_HSIO_VER_INFO; > + > +#define PMC_DATA_CMD_SIZE ((12/sizeof(UINT16))-1) > +#define PMC_DATA_DELAY_CMD_SIZE ((4/sizeof(UINT16))-1) > + > +#define RECORD_OFFSET(X, Y) ((X << 4) | Y) > +/** > + PCH HSIO ChipsetInit Command Field > +**/ > +typedef struct { > + UINT8 Command : 3; > + UINT8 Size : 5; > + UINT8 Pid; > + UINT8 OpCode; //PrivateControlWrite > + UINT8 Bar; //0 > + UINT8 Fbe; //First Byte Enable : 0x0F > + UINT8 Fid; //0 > + UINT16 Offset; > + UINT32 Value; > +} PCH_HSIO_CMD_FIELD; > + > +/** > +PCH HSIO Delay XRAM Data > +**/ > +typedef struct { > + UINT8 Command : 3; > + UINT8 Size : 5; > + UINT8 DelayPeriod; //(00h =3D 1us, 01h =3D 10us, 02h =3D 100us, ..., 0= 7h =3D 10s; > others reserved) > + UINT8 DelayCount; //(0 - 255); total delay =3D Delay period * Delay co= unt > + UINT8 Padding; > +} PCH_HSIO_DELAY_CMD_FIELD; > + > +typedef enum { > + Delay1us =3D 0x0, > + Delay10us, > + Delay100us, > + Delay1ms, > + Delay10ms, > + Delay100ms, > + Delay1s, > + Delay10s > +} PCH_HSIO_DELAY; > + > +/** > +PCH PCIE PLL SSC Data > +**/ > +#define MAX_PCIE_PLL_SSC_PERCENT 20 > + > +#include > + > +#endif //_PCH_HSIO_H_ > + > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchNvsAreaDef.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchNvsAreaDef.h > new file mode 100644 > index 0000000000..4617a01c0b > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchNvsAreaDef.h > @@ -0,0 +1,269 @@ > +/** @file > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + // > + // Define PCH NVS Area operatino region. > + // > + > +#ifndef _PCH_NVS_AREA_DEF_H_ > +#define _PCH_NVS_AREA_DEF_H_ > + > +#pragma pack (push,1) > +typedef struct { > + UINT16 PchSeries; ///< Offset 0 = PCH Series > + UINT16 PchGeneration; ///< Offset 2 = PCH > Generation > + UINT16 PchStepping; ///< Offset 4 = PCH Stepping > + UINT32 RpAddress[24]; ///< Offset 6 = Root Port > address 1 > + ///< Offset 10 = Root Port address 2 > + ///< Offset 14 = Root Port address 3 > + ///< Offset 18 = Root Port address 4 > + ///< Offset 22 = Root Port address 5 > + ///< Offset 26 = Root Port address 6 > + ///< Offset 30 = Root Port address 7 > + ///< Offset 34 = Root Port address 8 > + ///< Offset 38 = Root Port address 9 > + ///< Offset 42 = Root Port address 10 > + ///< Offset 46 = Root Port address 11 > + ///< Offset 50 = Root Port address 12 > + ///< Offset 54 = Root Port address 13 > + ///< Offset 58 = Root Port address 14 > + ///< Offset 62 = Root Port address 15 > + ///< Offset 66 = Root Port address 16 > + ///< Offset 70 = Root Port address 17 > + ///< Offset 74 = Root Port address 18 > + ///< Offset 78 = Root Port address 19 > + ///< Offset 82 = Root Port address 20 > + ///< Offset 86 = Root Port address 21 > + ///< Offset 90 = Root Port address 22 > + ///< Offset 94 = Root Port address 23 > + ///< Offset 98 = Root Port address 24 > + UINT64 NHLA; ///< Offset 102 = HD-Audio > NHLT ACPI address > + UINT32 NHLL; ///< Offset 110 = HD-Audio NHLT > ACPI length > + UINT32 ADFM; ///< Offset 114 = HD-Audio DSP > Feature Mask > + UINT8 SWQ0; ///< Offset 118 = HD-Audio > SoundWire Link #1 quirk mask > + UINT8 SWQ1; ///< Offset 119 = HD-Audio > SoundWire Link #2 quirk mask > + UINT8 SWQ2; ///< Offset 120 = HD-Audio > SoundWire Link #3 quirk mask > + UINT8 SWQ3; ///< Offset 121 = HD-Audio > SoundWire Link #4 quirk mask > + UINT32 DSPM; ///< Offset 122 = HD-Audio DSP > Stolen Memory Base Address > + UINT32 SBRG; ///< Offset 126 = SBREG_BAR > + UINT8 GEI0; ///< Offset 130 = GPIO > GroupIndex mapped to GPE_DW0 > + UINT8 GEI1; ///< Offset 131 = GPIO > GroupIndex mapped to GPE_DW1 > + UINT8 GEI2; ///< Offset 132 = GPIO > GroupIndex mapped to GPE_DW2 > + UINT8 GED0; ///< Offset 133 = GPIO DW part > of group mapped to GPE_DW0 > + UINT8 GED1; ///< Offset 134 = GPIO DW part > of group mapped to GPE_DW1 > + UINT8 GED2; ///< Offset 135 = GPIO DW part > of group mapped to GPE_DW2 > + UINT16 PcieLtrMaxSnoopLatency[24]; ///< Offset 136 = PCIE > LTR max snoop Latency 1 > + ///< Offset 138 = PCIE LTR max snoop > Latency 2 > + ///< Offset 140 = PCIE LTR max snoop > Latency 3 > + ///< Offset 142 = PCIE LTR max snoop > Latency 4 > + ///< Offset 144 = PCIE LTR max snoop > Latency 5 > + ///< Offset 146 = PCIE LTR max snoop > Latency 6 > + ///< Offset 148 = PCIE LTR max snoop > Latency 7 > + ///< Offset 150 = PCIE LTR max snoop > Latency 8 > + ///< Offset 152 = PCIE LTR max snoop > Latency 9 > + ///< Offset 154 = PCIE LTR max snoop > Latency 10 > + ///< Offset 156 = PCIE LTR max snoop > Latency 11 > + ///< Offset 158 = PCIE LTR max snoop > Latency 12 > + ///< Offset 160 = PCIE LTR max snoop > Latency 13 > + ///< Offset 162 = PCIE LTR max snoop > Latency 14 > + ///< Offset 164 = PCIE LTR max snoop > Latency 15 > + ///< Offset 166 = PCIE LTR max snoop > Latency 16 > + ///< Offset 168 = PCIE LTR max snoop > Latency 17 > + ///< Offset 170 = PCIE LTR max snoop > Latency 18 > + ///< Offset 172 = PCIE LTR max snoop > Latency 19 > + ///< Offset 174 = PCIE LTR max snoop > Latency 20 > + ///< Offset 176 = PCIE LTR max snoop > Latency 21 > + ///< Offset 178 = PCIE LTR max snoop > Latency 22 > + ///< Offset 180 = PCIE LTR max snoop > Latency 23 > + ///< Offset 182 = PCIE LTR max snoop > Latency 24 > + UINT16 PcieLtrMaxNoSnoopLatency[24]; ///< Offset 184 = PCIE > LTR max no snoop Latency 1 > + ///< Offset 186 = PCIE LTR max no > snoop Latency 2 > + ///< Offset 188 = PCIE LTR max no > snoop Latency 3 > + ///< Offset 190 = PCIE LTR max no > snoop Latency 4 > + ///< Offset 192 = PCIE LTR max no > snoop Latency 5 > + ///< Offset 194 = PCIE LTR max no > snoop Latency 6 > + ///< Offset 196 = PCIE LTR max no > snoop Latency 7 > + ///< Offset 198 = PCIE LTR max no > snoop Latency 8 > + ///< Offset 200 = PCIE LTR max no > snoop Latency 9 > + ///< Offset 202 = PCIE LTR max no > snoop Latency 10 > + ///< Offset 204 = PCIE LTR max no > snoop Latency 11 > + ///< Offset 206 = PCIE LTR max no > snoop Latency 12 > + ///< Offset 208 = PCIE LTR max no > snoop Latency 13 > + ///< Offset 210 = PCIE LTR max no > snoop Latency 14 > + ///< Offset 212 = PCIE LTR max no > snoop Latency 15 > + ///< Offset 214 = PCIE LTR max no > snoop Latency 16 > + ///< Offset 216 = PCIE LTR max no > snoop Latency 17 > + ///< Offset 218 = PCIE LTR max no > snoop Latency 18 > + ///< Offset 220 = PCIE LTR max no > snoop Latency 19 > + ///< Offset 222 = PCIE LTR max no > snoop Latency 20 > + ///< Offset 224 = PCIE LTR max no > snoop Latency 21 > + ///< Offset 226 = PCIE LTR max no > snoop Latency 22 > + ///< Offset 228 = PCIE LTR max no > snoop Latency 23 > + ///< Offset 230 = PCIE LTR max no > snoop Latency 24 > + UINT8 XHPC; ///< Offset 232 = Number of > HighSpeed ports implemented in XHCI controller > + UINT8 XRPC; ///< Offset 233 = Number of > USBR ports implemented in XHCI controller > + UINT8 XSPC; ///< Offset 234 = Number of > SuperSpeed ports implemented in XHCI controller > + UINT8 XSPA; ///< Offset 235 = Address of 1st > SuperSpeed port > + UINT32 HPTB; ///< Offset 236 = HPET base > address > + UINT8 HPTE; ///< Offset 240 = HPET enable > + //SerialIo block > + UINT8 SMD[12]; ///< Offset 241 = SerialIo > controller 0 mode > + ///< Offset 242 = SerialIo controller 1 > mode > + ///< Offset 243 = SerialIo controller 2 > mode > + ///< Offset 244 = SerialIo controller 3 > mode > + ///< Offset 245 = SerialIo controller 4 > mode > + ///< Offset 246 = SerialIo controller 5 > mode > + ///< Offset 247 = SerialIo controller 6 > mode > + ///< Offset 248 = SerialIo controller 7 > mode > + ///< Offset 249 = SerialIo controller 8 > mode > + ///< Offset 250 = SerialIo controller 9 > mode > + ///< Offset 251 = SerialIo controller A > mode > + ///< Offset 252 = SerialIo controller B > mode > + UINT8 SIR[12]; ///< Offset 253 = SerialIo > controller 0 irq number > + ///< Offset 254 = SerialIo controller 1 > irq number > + ///< Offset 255 = SerialIo controller 2 > irq number > + ///< Offset 256 = SerialIo controller 3 > irq number > + ///< Offset 257 = SerialIo controller 4 > irq number > + ///< Offset 258 = SerialIo controller 5 > irq number > + ///< Offset 259 = SerialIo controller 6 > irq number > + ///< Offset 260 = SerialIo controller 7 > irq number > + ///< Offset 261 = SerialIo controller 8 > irq number > + ///< Offset 262 = SerialIo controller 9 > irq number > + ///< Offset 263 = SerialIo controller A > irq number > + ///< Offset 264 = SerialIo controller B > irq number > + UINT64 SB0[12]; ///< Offset 265 = SerialIo > controller 0 BAR0 > + ///< Offset 273 = SerialIo controller 1 > BAR0 > + ///< Offset 281 = SerialIo controller 2 > BAR0 > + ///< Offset 289 = SerialIo controller 3 > BAR0 > + ///< Offset 297 = SerialIo controller 4 > BAR0 > + ///< Offset 305 = SerialIo controller 5 > BAR0 > + ///< Offset 313 = SerialIo controller 6 > BAR0 > + ///< Offset 321 = SerialIo controller 7 > BAR0 > + ///< Offset 329 = SerialIo controller 8 > BAR0 > + ///< Offset 337 = SerialIo controller 9 > BAR0 > + ///< Offset 345 = SerialIo controller A > BAR0 > + ///< Offset 353 = SerialIo controller B > BAR0 > + UINT64 SB1[12]; ///< Offset 361 = SerialIo > controller 0 BAR1 > + ///< Offset 369 = SerialIo controller 1 > BAR1 > + ///< Offset 377 = SerialIo controller 2 > BAR1 > + ///< Offset 385 = SerialIo controller 3 > BAR1 > + ///< Offset 393 = SerialIo controller 4 > BAR1 > + ///< Offset 401 = SerialIo controller 5 > BAR1 > + ///< Offset 409 = SerialIo controller 6 > BAR1 > + ///< Offset 417 = SerialIo controller 7 > BAR1 > + ///< Offset 425 = SerialIo controller 8 > BAR1 > + ///< Offset 433 = SerialIo controller 9 > BAR1 > + ///< Offset 441 = SerialIo controller A > BAR1 > + ///< Offset 449 = SerialIo controller B > BAR1 > + //end of SerialIo block > + UINT8 SGIR; ///< Offset 457 = GPIO IRQ > + UINT8 GPHD; ///< Offset 458 = Hide GPIO ACPI > device > + UINT8 RstPcieStorageInterfaceType[3]; ///< Offset 459 = RST PCIe > Storage Cycle Router#1 Interface Type > + ///< Offset 460 = RST PCIe Storage > Cycle Router#2 Interface Type > + ///< Offset 461 = RST PCIe Storage > Cycle Router#3 Interface Type > + UINT8 RstPcieStoragePmCapPtr[3]; ///< Offset 462 = RST PCIe > Storage Cycle Router#1 Power Management Capability Pointer > + ///< Offset 463 = RST PCIe Storage > Cycle Router#2 Power Management Capability Pointer > + ///< Offset 464 = RST PCIe Storage > Cycle Router#3 Power Management Capability Pointer > + UINT8 RstPcieStoragePcieCapPtr[3]; ///< Offset 465 = RST PCIe > Storage Cycle Router#1 PCIe Capabilities Pointer > + ///< Offset 466 = RST PCIe Storage > Cycle Router#2 PCIe Capabilities Pointer > + ///< Offset 467 = RST PCIe Storage > Cycle Router#3 PCIe Capabilities Pointer > + UINT16 RstPcieStorageL1ssCapPtr[3]; ///< Offset 468 = RST PCIe > Storage Cycle Router#1 L1SS Capability Pointer > + ///< Offset 470 = RST PCIe Storage > Cycle Router#2 L1SS Capability Pointer > + ///< Offset 472 = RST PCIe Storage > Cycle Router#3 L1SS Capability Pointer > + UINT8 RstPcieStorageEpL1ssControl2[3]; ///< Offset 474 = RST > PCIe Storage Cycle Router#1 Endpoint L1SS Control Data2 > + ///< Offset 475 = RST PCIe Storage > Cycle Router#2 Endpoint L1SS Control Data2 > + ///< Offset 476 = RST PCIe Storage > Cycle Router#3 Endpoint L1SS Control Data2 > + UINT32 RstPcieStorageEpL1ssControl1[3]; ///< Offset 477 = RST > PCIe Storage Cycle Router#1 Endpoint L1SS Control Data1 > + ///< Offset 481 = RST PCIe Storage > Cycle Router#2 Endpoint L1SS Control Data1 > + ///< Offset 485 = RST PCIe Storage > Cycle Router#3 Endpoint L1SS Control Data1 > + UINT16 RstPcieStorageLtrCapPtr[3]; ///< Offset 489 = RST PCIe > Storage Cycle Router#1 LTR Capability Pointer > + ///< Offset 491 = RST PCIe Storage > Cycle Router#2 LTR Capability Pointer > + ///< Offset 493 = RST PCIe Storage > Cycle Router#3 LTR Capability Pointer > + UINT32 RstPcieStorageEpLtrData[3]; ///< Offset 495 = RST PCIe > Storage Cycle Router#1 Endpoint LTR Data > + ///< Offset 499 = RST PCIe Storage > Cycle Router#2 Endpoint LTR Data > + ///< Offset 503 = RST PCIe Storage > Cycle Router#3 Endpoint LTR Data > + UINT16 RstPcieStorageEpLctlData16[3]; ///< Offset 507 = RST > PCIe Storage Cycle Router#1 Endpoint LCTL Data > + ///< Offset 509 = RST PCIe Storage > Cycle Router#2 Endpoint LCTL Data > + ///< Offset 511 = RST PCIe Storage > Cycle Router#3 Endpoint LCTL Data > + UINT16 RstPcieStorageEpDctlData16[3]; ///< Offset 513 = RST > PCIe Storage Cycle Router#1 Endpoint DCTL Data > + ///< Offset 515 = RST PCIe Storage > Cycle Router#2 Endpoint DCTL Data > + ///< Offset 517 = RST PCIe Storage > Cycle Router#3 Endpoint DCTL Data > + UINT16 RstPcieStorageEpDctl2Data16[3]; ///< Offset 519 = RST > PCIe Storage Cycle Router#1 Endpoint DCTL2 Data > + ///< Offset 521 = RST PCIe Storage > Cycle Router#2 Endpoint DCTL2 Data > + ///< Offset 523 = RST PCIe Storage > Cycle Router#3 Endpoint DCTL2 Data > + UINT16 RstPcieStorageRpDctl2Data16[3]; ///< Offset 525 = RST > PCIe Storage Cycle Router#1 RootPort DCTL2 Data > + ///< Offset 527 = RST PCIe Storage > Cycle Router#2 RootPort DCTL2 Data > + ///< Offset 529 = RST PCIe Storage > Cycle Router#3 RootPort DCTL2 Data > + UINT32 RstPcieStorageUniqueTableBar[3]; ///< Offset 531 = RST > PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR > + ///< Offset 535 = RST PCIe Storage > Cycle Router#2 Endpoint unique MSI-X Table BAR > + ///< Offset 539 = RST PCIe Storage > Cycle Router#3 Endpoint unique MSI-X Table BAR > + UINT32 RstPcieStorageUniqueTableBarValue[3]; ///< Offset 543 = RST > PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR value > + ///< Offset 547 = RST PCIe Storage > Cycle Router#2 Endpoint unique MSI-X Table BAR value > + ///< Offset 551 = RST PCIe Storage > Cycle Router#3 Endpoint unique MSI-X Table BAR value > + UINT32 RstPcieStorageUniquePbaBar[3]; ///< Offset 555 = RST > PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR > + ///< Offset 559 = RST PCIe Storage > Cycle Router#2 Endpoint unique MSI-X PBA BAR > + ///< Offset 563 = RST PCIe Storage > Cycle Router#3 Endpoint unique MSI-X PBA BAR > + UINT32 RstPcieStorageUniquePbaBarValue[3]; ///< Offset 567 = RST > PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR value > + ///< Offset 571 = RST PCIe Storage > Cycle Router#2 Endpoint unique MSI-X PBA BAR value > + ///< Offset 575 = RST PCIe Storage > Cycle Router#3 Endpoint unique MSI-X PBA BAR value > + UINT32 RstPcieStorageRootPortNum[3]; ///< Offset 579 = RST > PCIe Storage Cycle Router#1 Root Port number > + ///< Offset 583 = RST PCIe Storage > Cycle Router#2 Root Port number > + ///< Offset 587 = RST PCIe Storage > Cycle Router#3 Root Port number > + UINT8 EMH4; ///< Offset 591 = eMMC HS400 > mode enabled > + UINT8 EMDS; ///< Offset 592 = eMMC Driver > Strength > + UINT8 CpuSku; ///< Offset 593 = CPU SKU > + UINT16 IoTrapAddress[4]; ///< Offset 594 > + UINT8 IoTrapStatus[4]; ///< Offset 602 > + UINT16 PMBS; ///< Offset 606 = ACPI IO BASE > address > + UINT32 PWRM; ///< Offset 608 = PWRM MEM > BASE address > + // Cnvi specific > + UINT8 CnviMode; ///< Offset 612 = CNVi mode > + UINT32 RmrrCsmeBaseAddress; ///< Offset 613 = RMRR > CSME Base Address > + //Voltage Margining > + UINT8 SlpS0VmRuntimeControl; ///< Offset 617 = SLP_S0 > Voltage Margining Runtime Control > + UINT8 SlpS0Vm070VSupport; ///< Offset 618 = SLP_S0 > 0.70V Voltage Margining Support > + UINT8 SlpS0Vm075VSupport; ///< Offset 619 = SLP_S0 > 0.75V Voltage Margining Support > + // PCH Trace Hub > + UINT8 PchTraceHubMode; ///< Offset 620 = PCH Trace > Hub Mode > + // PCH PS_ON support > + UINT8 PsOnEnable; ///< Offset 621 = PCH PS_ON > enable > + UINT32 TempRsvdMemBase; ///< Offset 622 > Reserved memory base address for Temp MBAR > + // > + // These are for PchApciTablesSelfTest use > + // > + UINT8 LtrEnable[24]; ///< Offset 626 = Latency > Tolerance Reporting Enable > + ///< Offset 627 = Latency Tolerance > Reporting Enable > + ///< Offset 628 = Latency Tolerance > Reporting Enable > + ///< Offset 629 = Latency Tolerance > Reporting Enable > + ///< Offset 630 = Latency Tolerance > Reporting Enable > + ///< Offset 631 = Latency Tolerance > Reporting Enable > + ///< Offset 632 = Latency Tolerance > Reporting Enable > + ///< Offset 633 = Latency Tolerance > Reporting Enable > + ///< Offset 634 = Latency Tolerance > Reporting Enable > + ///< Offset 635 = Latency Tolerance > Reporting Enable > + ///< Offset 636 = Latency Tolerance > Reporting Enable > + ///< Offset 637 = Latency Tolerance > Reporting Enable > + ///< Offset 638 = Latency Tolerance > Reporting Enable > + ///< Offset 639 = Latency Tolerance > Reporting Enable > + ///< Offset 640 = Latency Tolerance > Reporting Enable > + ///< Offset 641 = Latency Tolerance > Reporting Enable > + ///< Offset 642 = Latency Tolerance > Reporting Enable > + ///< Offset 643 = Latency Tolerance > Reporting Enable > + ///< Offset 644 = Latency Tolerance > Reporting Enable > + ///< Offset 645 = Latency Tolerance > Reporting Enable > + ///< Offset 646 = Latency Tolerance > Reporting Enable > + ///< Offset 647 = Latency Tolerance > Reporting Enable > + ///< Offset 648 = Latency Tolerance > Reporting Enable > + ///< Offset 649 = Latency Tolerance > Reporting Enable > + UINT8 GBES; ///< Offset 650 = GbE Support > + UINT8 SataPortPresence; ///< Offset 651 = Holds > information from SATA PCS register about SATA ports which recieved COMINI= T > from connected devices. > + UINT8 SdPowerEnableActiveHigh; ///< Offset 652 = SD > PWREN# active high indication > + UINT8 EmmcEnabled; ///< Offset 653 = Set to > indicate that eMMC is enabled > + UINT8 SdCardEnabled; ///< Offset 654 = Set to > indicate that SD card is enabled > +} PCH_NVS_AREA; > + > +#pragma pack(pop) > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchRstHob.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchRstHob.h > new file mode 100644 > index 0000000000..94a5e0fad2 > --- /dev/null > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchRstHob.h > @@ -0,0 +1,58 @@ > +/** @file > + Definitions required to create RstHob > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_RST_HOB_ > +#define _PCH_RST_HOB_ > + > +extern EFI_GUID gPchRstHobGuid; > + > +// > +// This struct is used to record the fields that should be restored duri= ng device > wake up > +// > +typedef struct { > + UINT8 PmCapPtr; > + UINT8 PcieCapPtr; > + UINT16 L1ssCapPtr; > + UINT8 EndpointL1ssControl2; > + UINT32 EndpointL1ssControl1; > + UINT16 LtrCapPtr; > + UINT32 EndpointLtrData; > + UINT16 EndpointLctlData16; > + UINT16 EndpointDctlData16; > + UINT16 EndpointDctl2Data16; > + UINT16 RootPortDctl2Data16; > +} SAVED_DEVICE_CONFIG_SPACE; > + > +// > +// This structure is used to record the result of PCIe storageremapping = for > each cycle router > +// > +typedef struct { > + UINT8 RootPortNum; = // Indicates > the root port number with RST PCIe Storage Remapping remapping supported > and PCIe storage device plugged on, numbering is 0-based > + UINT8 DeviceInterface; = // Indicates the > interface of the PCIe storage device (AHCI or NVMe) > + UINT32 EndPointUniqueMsixTableBar; = // > Records the PCIe storage device's MSI-X Table BAR if it supports unique M= SI-X > Table BAR > + UINT32 EndPointUniqueMsixTableBarValue;= // > Records the PCIe storage device's MSI-X Table BAR value if it supports un= ique > MSI-X Table BAR > + UINT32 EndPointUniqueMsixPbaBar; = // > Records the PCIe storage device's MSI-X PBA BAR if it supports unique MSI= -X > PBA BAR > + UINT32 EndPointUniqueMsixPbaBarValue; = // > Records the PCIe storage device's MSI-X PBA BAR value if it supports uniq= ue > MSI-X PBA BAR > +} RST_CR_CONFIGURATION; > + > +// > +// Passes to DXE results of PCIe storage remapping > +// > +typedef struct { > + // > + // Stores configuration information about cycle router > + // > + RST_CR_CONFIGURATION > RstCrConfiguration[PCH_MAX_RST_PCIE_STORAGE_CR]; > + > + // > + // Saved fields from hidden device config space to be used later by RS= T driver > + // > + SAVED_DEVICE_CONFIG_SPACE > SavedRemapedDeviceConfigSpace[PCH_MAX_RST_PCIE_STORAGE_CR]; > +} PCH_RST_HOB; > + > +#endif > diff --git > a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/SiScheduleResetH= o > b.h > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/SiScheduleResetH= o > b.h > new file mode 100644 > index 0000000000..7a92a509b4 > --- /dev/null > +++ > b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/SiScheduleResetH= o > b.h > @@ -0,0 +1,25 @@ > +/** @file > + This file contains definitions of Si Schedule Reset HOB. > + > + Copyright (c) 2019 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _SI_SCHEDULE_RESET_HOB_H_ > +#define _SI_SCHEDULE_RESET_HOB_H_ > + > +#include > + > +/** > + This structure is used to provide information about PCH Resets > +**/ > +typedef struct { > + EFI_RESET_TYPE ResetType; > + PCH_RESET_DATA ResetData; > +} SI_SCHEDULE_RESET_HOB; > + > +extern EFI_GUID gSiScheduleResetHobGuid; > + > +#endif // _SI_SCHEDULE_RESET_HOB_H_ > + > -- > 2.16.2.windows.1