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From: "Chiu, Chasel" <chasel.chiu@intel.com>
To: "Kubacki, Michael A" <michael.a.kubacki@intel.com>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>,
	"Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>,
	"Gao, Liming" <liming.gao@intel.com>,
	"Kinney, Michael D" <michael.d.kinney@intel.com>,
	"Sinha, Ankit" <ankit.sinha@intel.com>
Subject: Re: [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode: Add Include headers
Date: Sat, 17 Aug 2019 01:12:22 +0000	[thread overview]
Message-ID: <3C3EFB470A303B4AB093197B6777CCEC504622F0@PGSMSX111.gar.corp.intel.com> (raw)
In-Reply-To: <20190817001603.30632-13-michael.a.kubacki@intel.com>


Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>


> -----Original Message-----
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>;
> Kinney, Michael D <michael.d.kinney@intel.com>; Sinha, Ankit
> <ankit.sinha@intel.com>
> Subject: [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode:
> Add Include headers
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
> 
> Adds header files common to silicon Sample Code.
> 
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>>
> Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatformL
> ib.h                     |   82 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/
> Guid/SmramMemoryReserve.h  |   51 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/
> Protocol/LegacyBios.h      | 1513 ++++++++++++++++++++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/
> Protocol/LegacyInterrupt.h |  118 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Gui
> d/AcpiS3Context.h            |   65 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Gui
> d/ConsoleOutDevice.h         |   17 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Gui
> d/MemoryTypeInformation.h    |   30 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Libr
> ary/ResetSystemLib.h        |   80 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Ppi/
> SmmAccess.h                 |  137 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Ppi/
> SmmControl.h                |   87 ++
> 
> Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Pro
> tocol/SmmVariable.h          |   33 +
>  11 files changed, 2213 insertions(+)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatfor
> mLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatfor
> mLib.h
> new file mode 100644
> index 0000000000..829d1190fc
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatfor
> mLib.h
> @@ -0,0 +1,82 @@
> +/** @file
> +  Prototype of SEC Platform hook library.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef  _SEC_PLATFORM_LIB_H_
> +#define  _SEC_PLATFORM_LIB_H_
> +
> +#include <Ppi/SecPlatformInformation.h>
> +#include <Ppi/SecPerformance.h>
> +
> +/**
> +  A developer supplied function to perform platform specific operations.
> +
> +  It's a developer supplied function to perform any operations appropriate to
> a
> +  given platform. It's invoked just before passing control to PEI core by SEC
> +  core. Platform developer may modify the SecCoreData passed to PEI Core.
> +  It returns a platform specific PPI list that platform wishes to pass to PEI core.
> +  The Generic SEC core module will merge this list to join the final list passed
> to
> +  PEI core.
> +
> +  @param  SecCoreData           The same parameter as passing to PEI core. It
> +                                could be overridden by this function.
> +
> +  @return The platform specific PPI list to be passed to PEI core or
> +          NULL if there is no need of such platform specific PPI list.
> +
> +**/
> +EFI_PEI_PPI_DESCRIPTOR *
> +EFIAPI
> +SecPlatformMain (
> +  IN OUT   EFI_SEC_PEI_HAND_OFF        *SecCoreData
> +  );
> +
> +
> +/**
> +  This interface conveys state information out of the Security (SEC) phase into
> PEI.
> +
> +  @param  PeiServices               Pointer to the PEI Services Table.
> +  @param  StructureSize             Pointer to the variable describing size of
> the input buffer.
> +  @param  PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.
> +
> +  @retval EFI_SUCCESS           The data was successfully returned.
> +  @retval EFI_BUFFER_TOO_SMALL  The buffer was too small.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecPlatformInformation (
> +  IN CONST EFI_PEI_SERVICES                     **PeiServices,
> +  IN OUT   UINT64                               *StructureSize,
> +     OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord
> +  );
> +
> +/**
> +  This interface conveys performance information out of the Security (SEC)
> phase into PEI.
> +
> +  This service is published by the SEC phase. The SEC phase handoff has an
> optional
> +  EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the
> +  PEI Foundation. As such, if the platform supports collecting performance
> data in SEC,
> +  this information is encapsulated into the data structure abstracted by this
> service.
> +  This information is collected for the boot-strap processor (BSP) on IA-32.
> +
> +  @param[in]  PeiServices  The pointer to the PEI Services Table.
> +  @param[in]  This         The pointer to this instance of the
> PEI_SEC_PERFORMANCE_PPI.
> +  @param[out] Performance  The pointer to performance data collected in
> SEC phase.
> +
> +  @retval     EFI_SUCCESS  The data was successfully returned.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecGetPerformance (
> +  IN CONST EFI_PEI_SERVICES          **PeiServices,
> +  IN       PEI_SEC_PERFORMANCE_PPI   *This,
> +  OUT      FIRMWARE_SEC_PERFORMANCE  *Performance
> +  );
> +
> +#endif
> +
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Includ
> e/Guid/SmramMemoryReserve.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Includ
> e/Guid/SmramMemoryReserve.h
> new file mode 100644
> index 0000000000..862a7c8aea
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Includ
> e/Guid/SmramMemoryReserve.h
> @@ -0,0 +1,51 @@
> +/** @file
> +  Definition of GUIDed HOB for reserving SMRAM regions.
> +
> +  This file defines:
> +  * the GUID used to identify the GUID HOB for reserving SMRAM regions.
> +  * the data structure of SMRAM descriptor to describe SMRAM candidate
> regions
> +  * values of state of SMRAM candidate regions
> +  * the GUID specific data structure of HOB for reserving SMRAM regions.
> +  This GUIDed HOB can be used to convey the existence of the T-SEG
> reservation and H-SEG usage
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _EFI_SMM_PEI_SMRAM_MEMORY_RESERVE_H_
> +#define _EFI_SMM_PEI_SMRAM_MEMORY_RESERVE_H_
> +
> +#define EFI_SMM_PEI_SMRAM_MEMORY_RESERVE \
> +  { \
> +    0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d }
> \
> +  }
> +
> +/**
> +* GUID specific data structure of HOB for reserving SMRAM regions.
> +*
> +* Inconsistent with specification here:
> +* EFI_HOB_SMRAM_DESCRIPTOR_BLOCK has been changed to
> EFI_SMRAM_HOB_DESCRIPTOR_BLOCK.
> +* This inconsistency is kept in code in order for backward compatibility.
> +**/
> +typedef struct {
> +  ///
> +  /// Designates the number of possible regions in the system
> +  /// that can be usable for SMRAM.
> +  ///
> +  /// Inconsistent with specification here:
> +  /// In Framework SMM CIS 0.91 specification, it defines the field type as
> UINTN.
> +  /// However, HOBs are supposed to be CPU neutral, so UINT32 should be
> used instead.
> +  ///
> +  UINT32                NumberOfSmmReservedRegions;
> +  ///
> +  /// Used throughout this protocol to describe the candidate
> +  /// regions for SMRAM that are supported by this platform.
> +  ///
> +  EFI_SMRAM_DESCRIPTOR  Descriptor[1];
> +} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK;
> +
> +extern EFI_GUID gEfiSmmPeiSmramMemoryReserveGuid;
> +
> +#endif
> +
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Includ
> e/Protocol/LegacyBios.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Includ
> e/Protocol/LegacyBios.h
> new file mode 100644
> index 0000000000..6ba23381b0
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Includ
> e/Protocol/LegacyBios.h
> @@ -0,0 +1,1513 @@
> +/** @file
> +  The EFI Legacy BIOS Protocol is used to abstract legacy Option ROM usage
> +  under EFI and Legacy OS boot.  This file also includes all the related
> +  COMPATIBILIY16 structures and defintions.
> +
> +  Note: The names for EFI_IA32_REGISTER_SET elements were picked to
> follow
> +  well known naming conventions.
> +
> +  Thunk is the code that switches from 32-bit protected environment into the
> 16-bit real-mode
> +  environment. Reverse thunk is the code that does the opposite.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _EFI_LEGACY_BIOS_H_
> +#define _EFI_LEGACY_BIOS_H_
> +
> +///
> +///
> +///
> +#pragma pack(1)
> +
> +typedef UINT8                       SERIAL_MODE;
> +typedef UINT8                       PARALLEL_MODE;
> +
> +#define EFI_COMPATIBILITY16_TABLE_SIGNATURE SIGNATURE_32 ('I', 'F', 'E',
> '$')
> +
> +///
> +/// There is a table located within the traditional BIOS in either the
> 0xF000:xxxx or 0xE000:xxxx
> +/// physical address range. It is located on a 16-byte boundary and provides
> the physical address of the
> +/// entry point for the Compatibility16 functions. These functions provide the
> platform-specific
> +/// information that is required by the generic EfiCompatibility code. The
> functions are invoked via
> +/// thunking by using EFI_LEGACY_BIOS_PROTOCOL.FarCall86() with the
> 32-bit physical
> +/// entry point.
> +///
> +typedef struct {
> +  ///
> +  /// The string "$EFI" denotes the start of the EfiCompatibility table. Byte 0
> is "I," byte
> +  /// 1 is "F," byte 2 is "E," and byte 3 is "$" and is normally accessed as a
> DWORD or UINT32.
> +  ///
> +  UINT32                            Signature;
> +
> +  ///
> +  /// The value required such that byte checksum of TableLength equals zero.
> +  ///
> +  UINT8                             TableChecksum;
> +
> +  ///
> +  /// The length of this table.
> +  ///
> +  UINT8                             TableLength;
> +
> +  ///
> +  /// The major EFI revision for which this table was generated.
> +  ///
> +  UINT8                             EfiMajorRevision;
> +
> +  ///
> +  /// The minor EFI revision for which this table was generated.
> +  ///
> +  UINT8                             EfiMinorRevision;
> +
> +  ///
> +  /// The major revision of this table.
> +  ///
> +  UINT8                             TableMajorRevision;
> +
> +  ///
> +  /// The minor revision of this table.
> +  ///
> +  UINT8                             TableMinorRevision;
> +
> +  ///
> +  /// Reserved for future usage.
> +  ///
> +  UINT16                            Reserved;
> +
> +  ///
> +  /// The segment of the entry point within the traditional BIOS for
> Compatibility16 functions.
> +  ///
> +  UINT16                            Compatibility16CallSegment;
> +
> +  ///
> +  /// The offset of the entry point within the traditional BIOS for
> Compatibility16 functions.
> +  ///
> +  UINT16                            Compatibility16CallOffset;
> +
> +  ///
> +  /// The segment of the entry point within the traditional BIOS for
> EfiCompatibility
> +  /// to invoke the PnP installation check.
> +  ///
> +  UINT16                            PnPInstallationCheckSegment;
> +
> +  ///
> +  /// The Offset of the entry point within the traditional BIOS for
> EfiCompatibility
> +  /// to invoke the PnP installation check.
> +  ///
> +  UINT16                            PnPInstallationCheckOffset;
> +
> +  ///
> +  /// EFI system resources table. Type EFI_SYSTEM_TABLE is defined in the
> IntelPlatform
> +  ///Innovation Framework for EFI Driver Execution Environment Core
> Interface Specification (DXE CIS).
> +  ///
> +  UINT32                            EfiSystemTable;
> +
> +  ///
> +  /// The address of an OEM-provided identifier string. The string is null
> terminated.
> +  ///
> +  UINT32                            OemIdStringPointer;
> +
> +  ///
> +  /// The 32-bit physical address where ACPI RSD PTR is stored within the
> traditional
> +  /// BIOS. The remained of the ACPI tables are located at their EFI addresses.
> The size
> +  /// reserved is the maximum for ACPI 2.0. The EfiCompatibility will fill in the
> ACPI
> +  /// RSD PTR with either the ACPI 1.0b or 2.0 values.
> +  ///
> +  UINT32                            AcpiRsdPtrPointer;
> +
> +  ///
> +  /// The OEM revision number. Usage is undefined but provided for OEM
> module usage.
> +  ///
> +  UINT16                            OemRevision;
> +
> +  ///
> +  /// The 32-bit physical address where INT15 E820 data is stored within the
> traditional
> +  /// BIOS. The EfiCompatibility code will fill in the E820Pointer value and copy
> the
> +  /// data to the indicated area.
> +  ///
> +  UINT32                            E820Pointer;
> +
> +  ///
> +  /// The length of the E820 data and is filled in by the EfiCompatibility code.
> +  ///
> +  UINT32                            E820Length;
> +
> +  ///
> +  /// The 32-bit physical address where the $PIR table is stored in the
> traditional BIOS.
> +  /// The EfiCompatibility code will fill in the IrqRoutingTablePointer value
> and
> +  /// copy the data to the indicated area.
> +  ///
> +  UINT32                            IrqRoutingTablePointer;
> +
> +  ///
> +  /// The length of the $PIR table and is filled in by the EfiCompatibility code.
> +  ///
> +  UINT32                            IrqRoutingTableLength;
> +
> +  ///
> +  /// The 32-bit physical address where the MP table is stored in the
> traditional BIOS.
> +  /// The EfiCompatibility code will fill in the MpTablePtr value and copy the
> data
> +  /// to the indicated area.
> +  ///
> +  UINT32                            MpTablePtr;
> +
> +  ///
> +  /// The length of the MP table and is filled in by the EfiCompatibility code.
> +  ///
> +  UINT32                            MpTableLength;
> +
> +  ///
> +  /// The segment of the OEM-specific INT table/code.
> +  ///
> +  UINT16                            OemIntSegment;
> +
> +  ///
> +  /// The offset of the OEM-specific INT table/code.
> +  ///
> +  UINT16                            OemIntOffset;
> +
> +  ///
> +  /// The segment of the OEM-specific 32-bit table/code.
> +  ///
> +  UINT16                            Oem32Segment;
> +
> +  ///
> +  /// The offset of the OEM-specific 32-bit table/code.
> +  ///
> +  UINT16                            Oem32Offset;
> +
> +  ///
> +  /// The segment of the OEM-specific 16-bit table/code.
> +  ///
> +  UINT16                            Oem16Segment;
> +
> +  ///
> +  /// The offset of the OEM-specific 16-bit table/code.
> +  ///
> +  UINT16                            Oem16Offset;
> +
> +  ///
> +  /// The segment of the TPM binary passed to 16-bit CSM.
> +  ///
> +  UINT16                            TpmSegment;
> +
> +  ///
> +  /// The offset of the TPM binary passed to 16-bit CSM.
> +  ///
> +  UINT16                            TpmOffset;
> +
> +  ///
> +  /// A pointer to a string identifying the independent BIOS vendor.
> +  ///
> +  UINT32                            IbvPointer;
> +
> +  ///
> +  /// This field is NULL for all systems not supporting PCI Express. This field is
> the base
> +  /// value of the start of the PCI Express memory-mapped configuration
> registers and
> +  /// must be filled in prior to EfiCompatibility code issuing the
> Compatibility16 function
> +  /// Compatibility16InitializeYourself().
> +  /// Compatibility16InitializeYourself() is defined in Compatability16
> +  /// Functions.
> +  ///
> +  UINT32                            PciExpressBase;
> +
> +  ///
> +  /// Maximum PCI bus number assigned.
> +  ///
> +  UINT8                             LastPciBus;
> +
> +  ///
> +  /// Start Address of Upper Memory Area (UMA) to be set as Read/Write. If
> +  /// UmaAddress is a valid address in the shadow RAM, it also indicates that
> the region
> +  /// from 0xC0000 to (UmaAddress - 1) can be used for Option ROM.
> +  ///
> +  UINT32                            UmaAddress;
> +
> +  ///
> +  /// Upper Memory Area size in bytes to be set as Read/Write. If zero, no
> UMA region
> +  /// will be set as Read/Write (i.e. all Shadow RAM is set as Read-Only).
> +  ///
> +  UINT32                            UmaSize;
> +
> +  ///
> +  /// Start Address of high memory that can be used for permanent allocation.
> If zero,
> +  /// high memory is not available for permanent allocation.
> +  ///
> +  UINT32                            HiPermanentMemoryAddress;
> +
> +  ///
> +  /// Size of high memory that can be used for permanent allocation in bytes.
> If zero,
> +  /// high memory is not available for permanent allocation.
> +  ///
> +  UINT32                            HiPermanentMemorySize;
> +} EFI_COMPATIBILITY16_TABLE;
> +
> +///
> +/// Functions provided by the CSM binary which communicate between the
> EfiCompatibility
> +/// and Compatability16 code.
> +///
> +/// Inconsistent with the specification here:
> +/// The member's name started with "Compatibility16" [defined in Intel
> Framework
> +/// Compatibility Support Module Specification / 0.97 version]
> +/// has been changed to "Legacy16" since keeping backward compatible.
> +///
> +typedef enum {
> +  ///
> +  /// Causes the Compatibility16 code to do any internal initialization
> required.
> +  /// Input:
> +  ///   AX = Compatibility16InitializeYourself
> +  ///   ES:BX = Pointer to EFI_TO_COMPATIBILITY16_INIT_TABLE
> +  /// Return:
> +  ///   AX = Return Status codes
> +  ///
> +  Legacy16InitializeYourself    = 0x0000,
> +
> +  ///
> +  /// Causes the Compatibility16 BIOS to perform any drive number
> translations to match the boot sequence.
> +  /// Input:
> +  ///   AX = Compatibility16UpdateBbs
> +  ///   ES:BX = Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE
> +  /// Return:
> +  ///   AX = Returned status codes
> +  ///
> +  Legacy16UpdateBbs             = 0x0001,
> +
> +  ///
> +  /// Allows the Compatibility16 code to perform any final actions before
> booting. The Compatibility16
> +  /// code is read/write.
> +  /// Input:
> +  ///   AX = Compatibility16PrepareToBoot
> +  ///   ES:BX = Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE structure
> +  /// Return:
> +  ///   AX = Returned status codes
> +  ///
> +  Legacy16PrepareToBoot         = 0x0002,
> +
> +  ///
> +  /// Causes the Compatibility16 BIOS to boot. The Compatibility16 code is
> Read/Only.
> +  /// Input:
> +  ///   AX = Compatibility16Boot
> +  /// Output:
> +  ///   AX = Returned status codes
> +  ///
> +  Legacy16Boot                  = 0x0003,
> +
> +  ///
> +  /// Allows the Compatibility16 code to get the last device from which a boot
> was attempted. This is
> +  /// stored in CMOS and is the priority number of the last attempted boot
> device.
> +  /// Input:
> +  ///   AX = Compatibility16RetrieveLastBootDevice
> +  /// Output:
> +  ///   AX = Returned status codes
> +  ///   BX = Priority number of the boot device.
> +  ///
> +  Legacy16RetrieveLastBootDevice = 0x0004,
> +
> +  ///
> +  /// Allows the Compatibility16 code rehook INT13, INT18, and/or INT19
> after dispatching a legacy OpROM.
> +  /// Input:
> +  ///   AX = Compatibility16DispatchOprom
> +  ///   ES:BX = Pointer to EFI_DISPATCH_OPROM_TABLE
> +  /// Output:
> +  ///   AX = Returned status codes
> +  ///   BX = Number of non-BBS-compliant devices found. Equals 0 if BBS
> compliant.
> +  ///
> +  Legacy16DispatchOprom         = 0x0005,
> +
> +  ///
> +  /// Finds a free area in the 0xFxxxx or 0xExxxx region of the specified length
> and returns the address
> +  /// of that region.
> +  /// Input:
> +  ///   AX = Compatibility16GetTableAddress
> +  ///   BX = Allocation region
> +  ///       00 = Allocate from either 0xE0000 or 0xF0000 64 KB blocks.
> +  ///       Bit 0 = 1 Allocate from 0xF0000 64 KB block
> +  ///       Bit 1 = 1 Allocate from 0xE0000 64 KB block
> +  ///   CX = Requested length in bytes.
> +  ///   DX = Required address alignment. Bit mapped. First non-zero bit from
> the right is the alignment.
> +  /// Output:
> +  ///   AX = Returned status codes
> +  ///   DS:BX = Address of the region
> +  ///
> +  Legacy16GetTableAddress       = 0x0006,
> +
> +  ///
> +  /// Enables the EfiCompatibility module to do any nonstandard processing
> of keyboard LEDs or state.
> +  /// Input:
> +  ///   AX = Compatibility16SetKeyboardLeds
> +  ///   CL = LED status.
> +  ///     Bit 0  Scroll Lock 0 = Off
> +  ///     Bit 1  NumLock
> +  ///     Bit 2  Caps Lock
> +  /// Output:
> +  ///     AX = Returned status codes
> +  ///
> +  Legacy16SetKeyboardLeds       = 0x0007,
> +
> +  ///
> +  /// Enables the EfiCompatibility module to install an interrupt handler for
> PCI mass media devices that
> +  /// do not have an OpROM associated with them. An example is SATA.
> +  /// Input:
> +  ///   AX = Compatibility16InstallPciHandler
> +  ///   ES:BX = Pointer to EFI_LEGACY_INSTALL_PCI_HANDLER structure
> +  /// Output:
> +  ///   AX = Returned status codes
> +  ///
> +  Legacy16InstallPciHandler     = 0x0008
> +} EFI_COMPATIBILITY_FUNCTIONS;
> +
> +
> +///
> +/// EFI_DISPATCH_OPROM_TABLE
> +///
> +typedef struct {
> +  UINT16  PnPInstallationCheckSegment;  ///< A pointer to the
> PnpInstallationCheck data structure.
> +  UINT16  PnPInstallationCheckOffset;   ///< A pointer to the
> PnpInstallationCheck data structure.
> +  UINT16  OpromSegment;                 ///< The segment where the OpROM
> was placed. Offset is assumed to be 3.
> +  UINT8   PciBus;                       ///< The PCI bus.
> +  UINT8   PciDeviceFunction;            ///< The PCI device * 0x08 | PCI
> function.
> +  UINT8   NumberBbsEntries;             ///< The number of valid BBS table
> entries upon entry and exit. The IBV code may
> +                                        ///< increase this number, if BBS-compliant
> devices also hook INTs in order to force the
> +                                        ///< OpROM BIOS Setup to be executed.
> +  UINT32  BbsTablePointer;              ///< A pointer to the BBS table.
> +  UINT16  RuntimeSegment;               ///< The segment where the OpROM
> can be relocated to. If this value is 0x0000, this
> +                                        ///< means that the relocation of this run time
> code is not supported.
> +                                        ///< Inconsistent with specification here:
> +                                        ///< The member's name
> "OpromDestinationSegment" [defined in Intel Framework Compatibility
> Support Module Specification / 0.97 version]
> +                                        ///< has been changed to "RuntimeSegment"
> since keeping backward compatible.
> +
> +} EFI_DISPATCH_OPROM_TABLE;
> +
> +///
> +/// EFI_TO_COMPATIBILITY16_INIT_TABLE
> +///
> +typedef struct {
> +  ///
> +  /// Starting address of memory under 1 MB. The ending address is assumed
> to be 640 KB or 0x9FFFF.
> +  ///
> +  UINT32                            BiosLessThan1MB;
> +
> +  ///
> +  /// The starting address of the high memory block.
> +  ///
> +  UINT32                            HiPmmMemory;
> +
> +  ///
> +  /// The length of high memory block.
> +  ///
> +  UINT32                            HiPmmMemorySizeInBytes;
> +
> +  ///
> +  /// The segment of the reverse thunk call code.
> +  ///
> +  UINT16                            ReverseThunkCallSegment;
> +
> +  ///
> +  /// The offset of the reverse thunk call code.
> +  ///
> +  UINT16                            ReverseThunkCallOffset;
> +
> +  ///
> +  /// The number of E820 entries copied to the Compatibility16 BIOS.
> +  ///
> +  UINT32                            NumberE820Entries;
> +
> +  ///
> +  /// The amount of usable memory above 1 MB, e.g., E820 type 1 memory.
> +  ///
> +  UINT32                            OsMemoryAbove1Mb;
> +
> +  ///
> +  /// The start of thunk code in main memory. Memory cannot be used by
> BIOS or PMM.
> +  ///
> +  UINT32                            ThunkStart;
> +
> +  ///
> +  /// The size of the thunk code.
> +  ///
> +  UINT32                            ThunkSizeInBytes;
> +
> +  ///
> +  /// Starting address of memory under 1 MB.
> +  ///
> +  UINT32                            LowPmmMemory;
> +
> +  ///
> +  /// The length of low Memory block.
> +  ///
> +  UINT32                            LowPmmMemorySizeInBytes;
> +} EFI_TO_COMPATIBILITY16_INIT_TABLE;
> +
> +///
> +/// DEVICE_PRODUCER_SERIAL.
> +///
> +typedef struct {
> +  UINT16                            Address;    ///< I/O address assigned to the
> serial port.
> +  UINT8                             Irq;        ///< IRQ assigned to the serial port.
> +  SERIAL_MODE                       Mode;       ///< Mode of serial port. Values
> are defined below.
> +} DEVICE_PRODUCER_SERIAL;
> +
> +///
> +/// DEVICE_PRODUCER_SERIAL's modes.
> +///@{
> +#define DEVICE_SERIAL_MODE_NORMAL               0x00
> +#define DEVICE_SERIAL_MODE_IRDA                 0x01
> +#define DEVICE_SERIAL_MODE_ASK_IR               0x02
> +#define DEVICE_SERIAL_MODE_DUPLEX_HALF          0x00
> +#define DEVICE_SERIAL_MODE_DUPLEX_FULL          0x10
> +///@)
> +
> +///
> +/// DEVICE_PRODUCER_PARALLEL.
> +///
> +typedef struct {
> +  UINT16                            Address;  ///< I/O address assigned to the
> parallel port.
> +  UINT8                             Irq;      ///< IRQ assigned to the parallel port.
> +  UINT8                             Dma;      ///< DMA assigned to the parallel port.
> +  PARALLEL_MODE                     Mode;     ///< Mode of the parallel port.
> Values are defined below.
> +} DEVICE_PRODUCER_PARALLEL;
> +
> +///
> +/// DEVICE_PRODUCER_PARALLEL's modes.
> +///@{
> +#define DEVICE_PARALLEL_MODE_MODE_OUTPUT_ONLY   0x00
> +#define DEVICE_PARALLEL_MODE_MODE_BIDIRECTIONAL 0x01
> +#define DEVICE_PARALLEL_MODE_MODE_EPP           0x02
> +#define DEVICE_PARALLEL_MODE_MODE_ECP           0x03
> +///@}
> +
> +///
> +/// DEVICE_PRODUCER_FLOPPY
> +///
> +typedef struct {
> +  UINT16                            Address;          ///< I/O address assigned to the
> floppy.
> +  UINT8                             Irq;              ///< IRQ assigned to the floppy.
> +  UINT8                             Dma;              ///< DMA assigned to the floppy.
> +  UINT8                             NumberOfFloppy;   ///< Number of floppies in
> the system.
> +} DEVICE_PRODUCER_FLOPPY;
> +
> +///
> +/// LEGACY_DEVICE_FLAGS
> +///
> +typedef struct {
> +  UINT32                            A20Kybd : 1;      ///< A20 controller by
> keyboard controller.
> +  UINT32                            A20Port90 : 1;    ///< A20 controlled by port
> 0x92.
> +  UINT32                            Reserved : 30;    ///< Reserved for future usage.
> +} LEGACY_DEVICE_FLAGS;
> +
> +///
> +/// DEVICE_PRODUCER_DATA_HEADER
> +///
> +typedef struct {
> +  DEVICE_PRODUCER_SERIAL            Serial[4];      ///< Data for serial port x.
> Type DEVICE_PRODUCER_SERIAL is defined below.
> +  DEVICE_PRODUCER_PARALLEL          Parallel[3];    ///< Data for parallel
> port x. Type DEVICE_PRODUCER_PARALLEL is defined below.
> +  DEVICE_PRODUCER_FLOPPY            Floppy;         ///< Data for floppy.
> Type DEVICE_PRODUCER_FLOPPY is defined below.
> +  UINT8                             MousePresent;   ///< Flag to indicate if mouse is
> present.
> +  LEGACY_DEVICE_FLAGS               Flags;          ///< Miscellaneous Boolean
> state information passed to CSM.
> +} DEVICE_PRODUCER_DATA_HEADER;
> +
> +///
> +/// ATAPI_IDENTIFY
> +///
> +typedef struct {
> +  UINT16                            Raw[256];     ///< Raw data from the IDE
> IdentifyDrive command.
> +} ATAPI_IDENTIFY;
> +
> +///
> +/// HDD_INFO
> +///
> +typedef struct {
> +  ///
> +  /// Status of IDE device. Values are defined below. There is one HDD_INFO
> structure
> +  /// per IDE controller. The IdentifyDrive is per drive. Index 0 is master and
> index
> +  /// 1 is slave.
> +  ///
> +  UINT16                            Status;
> +
> +  ///
> +  /// PCI bus of IDE controller.
> +  ///
> +  UINT32                            Bus;
> +
> +  ///
> +  /// PCI device of IDE controller.
> +  ///
> +  UINT32                            Device;
> +
> +  ///
> +  /// PCI function of IDE controller.
> +  ///
> +  UINT32                            Function;
> +
> +  ///
> +  /// Command ports base address.
> +  ///
> +  UINT16                            CommandBaseAddress;
> +
> +  ///
> +  /// Control ports base address.
> +  ///
> +  UINT16                            ControlBaseAddress;
> +
> +  ///
> +  /// Bus master address.
> +  ///
> +  UINT16                            BusMasterAddress;
> +
> +  UINT8                             HddIrq;
> +
> +  ///
> +  /// Data that identifies the drive data; one per possible attached drive.
> +  ///
> +  ATAPI_IDENTIFY                    IdentifyDrive[2];
> +} HDD_INFO;
> +
> +///
> +/// HDD_INFO status bits
> +///
> +#define HDD_PRIMARY               0x01
> +#define HDD_SECONDARY             0x02
> +#define HDD_MASTER_ATAPI_CDROM    0x04
> +#define HDD_SLAVE_ATAPI_CDROM     0x08
> +#define HDD_MASTER_IDE            0x20
> +#define HDD_SLAVE_IDE             0x40
> +#define HDD_MASTER_ATAPI_ZIPDISK  0x10
> +#define HDD_SLAVE_ATAPI_ZIPDISK   0x80
> +
> +///
> +/// BBS_STATUS_FLAGS;\.
> +///
> +typedef struct {
> +  UINT16                            OldPosition : 4;    ///< Prior priority.
> +  UINT16                            Reserved1 : 4;      ///< Reserved for future use.
> +  UINT16                            Enabled : 1;        ///< If 0, ignore this entry.
> +  UINT16                            Failed : 1;         ///< 0 = Not known if boot
> failure occurred.
> +                                                        ///< 1 = Boot attempted failed.
> +
> +  ///
> +  /// State of media present.
> +  ///   00 = No bootable media is present in the device.
> +  ///   01 = Unknown if a bootable media present.
> +  ///   10 = Media is present and appears bootable.
> +  ///   11 = Reserved.
> +  ///
> +  UINT16                            MediaPresent : 2;
> +  UINT16                            Reserved2 : 4;      ///< Reserved for future use.
> +} BBS_STATUS_FLAGS;
> +
> +///
> +/// BBS_TABLE, device type values & boot priority values.
> +///
> +typedef struct {
> +  ///
> +  /// The boot priority for this boot device. Values are defined below.
> +  ///
> +  UINT16                            BootPriority;
> +
> +  ///
> +  /// The PCI bus for this boot device.
> +  ///
> +  UINT32                            Bus;
> +
> +  ///
> +  /// The PCI device for this boot device.
> +  ///
> +  UINT32                            Device;
> +
> +  ///
> +  /// The PCI function for the boot device.
> +  ///
> +  UINT32                            Function;
> +
> +  ///
> +  /// The PCI class for this boot device.
> +  ///
> +  UINT8                             Class;
> +
> +  ///
> +  /// The PCI Subclass for this boot device.
> +  ///
> +  UINT8                             SubClass;
> +
> +  ///
> +  /// Segment:offset address of an ASCIIZ description string describing the
> manufacturer.
> +  ///
> +  UINT16                            MfgStringOffset;
> +
> +  ///
> +  /// Segment:offset address of an ASCIIZ description string describing the
> manufacturer.
> +  ///
> +  UINT16                            MfgStringSegment;
> +
> +  ///
> +  /// BBS device type. BBS device types are defined below.
> +  ///
> +  UINT16                            DeviceType;
> +
> +  ///
> +  /// Status of this boot device. Type BBS_STATUS_FLAGS is defined below.
> +  ///
> +  BBS_STATUS_FLAGS                  StatusFlags;
> +
> +  ///
> +  /// Segment:Offset address of boot loader for IPL devices or install INT13
> handler for
> +  /// BCV devices.
> +  ///
> +  UINT16                            BootHandlerOffset;
> +
> +  ///
> +  /// Segment:Offset address of boot loader for IPL devices or install INT13
> handler for
> +  /// BCV devices.
> +  ///
> +  UINT16                            BootHandlerSegment;
> +
> +  ///
> +  /// Segment:offset address of an ASCIIZ description string describing this
> device.
> +  ///
> +  UINT16                            DescStringOffset;
> +
> +  ///
> +  /// Segment:offset address of an ASCIIZ description string describing this
> device.
> +  ///
> +  UINT16                            DescStringSegment;
> +
> +  ///
> +  /// Reserved.
> +  ///
> +  UINT32                            InitPerReserved;
> +
> +  ///
> +  /// The use of these fields is IBV dependent. They can be used to flag that an
> OpROM
> +  /// has hooked the specified IRQ. The OpROM may be BBS compliant as
> some SCSI
> +  /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS
> Setup
> +  ///
> +  UINT32                            AdditionalIrq13Handler;
> +
> +  ///
> +  /// The use of these fields is IBV dependent. They can be used to flag that an
> OpROM
> +  /// has hooked the specified IRQ. The OpROM may be BBS compliant as
> some SCSI
> +  /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS
> Setup
> +  ///
> +  UINT32                            AdditionalIrq18Handler;
> +
> +  ///
> +  /// The use of these fields is IBV dependent. They can be used to flag that an
> OpROM
> +  /// has hooked the specified IRQ. The OpROM may be BBS compliant as
> some SCSI
> +  /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS
> Setup
> +  ///
> +  UINT32                            AdditionalIrq19Handler;
> +
> +  ///
> +  /// The use of these fields is IBV dependent. They can be used to flag that an
> OpROM
> +  /// has hooked the specified IRQ. The OpROM may be BBS compliant as
> some SCSI
> +  /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIOS
> Setup
> +  ///
> +  UINT32                            AdditionalIrq40Handler;
> +  UINT8                             AssignedDriveNumber;
> +  UINT32                            AdditionalIrq41Handler;
> +  UINT32                            AdditionalIrq46Handler;
> +  UINT32                            IBV1;
> +  UINT32                            IBV2;
> +} BBS_TABLE;
> +
> +///
> +/// BBS device type values
> +///@{
> +#define BBS_FLOPPY              0x01
> +#define BBS_HARDDISK            0x02
> +#define BBS_CDROM               0x03
> +#define BBS_PCMCIA              0x04
> +#define BBS_USB                 0x05
> +#define BBS_EMBED_NETWORK       0x06
> +#define BBS_BEV_DEVICE          0x80
> +#define BBS_UNKNOWN             0xff
> +///@}
> +
> +///
> +/// BBS boot priority values
> +///@{
> +#define BBS_DO_NOT_BOOT_FROM    0xFFFC
> +#define BBS_LOWEST_PRIORITY     0xFFFD
> +#define BBS_UNPRIORITIZED_ENTRY 0xFFFE
> +#define BBS_IGNORE_ENTRY        0xFFFF
> +///@}
> +
> +///
> +/// SMM_ATTRIBUTES
> +///
> +typedef struct {
> +  ///
> +  /// Access mechanism used to generate the soft SMI. Defined types are
> below. The other
> +  /// values are reserved for future usage.
> +  ///
> +  UINT16                            Type : 3;
> +
> +  ///
> +  /// The size of "port" in bits. Defined values are below.
> +  ///
> +  UINT16                            PortGranularity : 3;
> +
> +  ///
> +  /// The size of data in bits. Defined values are below.
> +  ///
> +  UINT16                            DataGranularity : 3;
> +
> +  ///
> +  /// Reserved for future use.
> +  ///
> +  UINT16                            Reserved : 7;
> +} SMM_ATTRIBUTES;
> +
> +///
> +/// SMM_ATTRIBUTES type values.
> +///@{
> +#define STANDARD_IO       0x00
> +#define STANDARD_MEMORY   0x01
> +///@}
> +
> +///
> +/// SMM_ATTRIBUTES port size constants.
> +///@{
> +#define PORT_SIZE_8       0x00
> +#define PORT_SIZE_16      0x01
> +#define PORT_SIZE_32      0x02
> +#define PORT_SIZE_64      0x03
> +///@}
> +
> +///
> +/// SMM_ATTRIBUTES data size constants.
> +///@{
> +#define DATA_SIZE_8       0x00
> +#define DATA_SIZE_16      0x01
> +#define DATA_SIZE_32      0x02
> +#define DATA_SIZE_64      0x03
> +///@}
> +
> +///
> +/// SMM_FUNCTION & relating constants.
> +///
> +typedef struct {
> +  UINT16                            Function : 15;
> +  UINT16                            Owner : 1;
> +} SMM_FUNCTION;
> +
> +///
> +/// SMM_FUNCTION Function constants.
> +///@{
> +#define INT15_D042        0x0000
> +#define GET_USB_BOOT_INFO 0x0001
> +#define DMI_PNP_50_57     0x0002
> +///@}
> +
> +///
> +/// SMM_FUNCTION Owner constants.
> +///@{
> +#define STANDARD_OWNER    0x0
> +#define OEM_OWNER         0x1
> +///@}
> +
> +///
> +/// This structure assumes both port and data sizes are 1. SmmAttribute must
> be
> +/// properly to reflect that assumption.
> +///
> +typedef struct {
> +  ///
> +  /// Describes the access mechanism, SmmPort, and SmmData sizes. Type
> +  /// SMM_ATTRIBUTES is defined below.
> +  ///
> +  SMM_ATTRIBUTES                    SmmAttributes;
> +
> +  ///
> +  /// Function Soft SMI is to perform. Type SMM_FUNCTION is defined below.
> +  ///
> +  SMM_FUNCTION                      SmmFunction;
> +
> +  ///
> +  /// SmmPort size depends upon SmmAttributes and ranges from2 bytes to
> 16 bytes.
> +  ///
> +  UINT8                             SmmPort;
> +
> +  ///
> +  /// SmmData size depends upon SmmAttributes and ranges from2 bytes to
> 16 bytes.
> +  ///
> +  UINT8                             SmmData;
> +} SMM_ENTRY;
> +
> +///
> +/// SMM_TABLE
> +///
> +typedef struct {
> +  UINT16                            NumSmmEntries;    ///< Number of entries
> represented by SmmEntry.
> +  SMM_ENTRY                         SmmEntry;         ///< One entry per
> function. Type SMM_ENTRY is defined below.
> +} SMM_TABLE;
> +
> +///
> +/// UDC_ATTRIBUTES
> +///
> +typedef struct {
> +  ///
> +  /// This bit set indicates that the ServiceAreaData is valid.
> +  ///
> +  UINT8                             DirectoryServiceValidity : 1;
> +
> +  ///
> +  /// This bit set indicates to use the Reserve Area Boot Code Address (RACBA)
> only if
> +  /// DirectoryServiceValidity is 0.
> +  ///
> +  UINT8                             RabcaUsedFlag : 1;
> +
> +  ///
> +  /// This bit set indicates to execute hard disk diagnostics.
> +  ///
> +  UINT8                             ExecuteHddDiagnosticsFlag : 1;
> +
> +  ///
> +  /// Reserved for future use. Set to 0.
> +  ///
> +  UINT8                             Reserved : 5;
> +} UDC_ATTRIBUTES;
> +
> +///
> +/// UD_TABLE
> +///
> +typedef struct {
> +  ///
> +  /// This field contains the bit-mapped attributes of the PARTIES information.
> Type
> +  /// UDC_ATTRIBUTES is defined below.
> +  ///
> +  UDC_ATTRIBUTES                    Attributes;
> +
> +  ///
> +  /// This field contains the zero-based device on which the selected
> +  /// ServiceDataArea is present. It is 0 for master and 1 for the slave device.
> +  ///
> +  UINT8                             DeviceNumber;
> +
> +  ///
> +  /// This field contains the zero-based index into the BbsTable for the parent
> device.
> +  /// This index allows the user to reference the parent device information
> such as PCI
> +  /// bus, device function.
> +  ///
> +  UINT8                             BbsTableEntryNumberForParentDevice;
> +
> +  ///
> +  /// This field contains the zero-based index into the BbsTable for the boot
> entry.
> +  ///
> +  UINT8                             BbsTableEntryNumberForBoot;
> +
> +  ///
> +  /// This field contains the zero-based index into the BbsTable for the HDD
> diagnostics entry.
> +  ///
> +  UINT8                             BbsTableEntryNumberForHddDiag;
> +
> +  ///
> +  /// The raw Beer data.
> +  ///
> +  UINT8                             BeerData[128];
> +
> +  ///
> +  /// The raw data of selected service area.
> +  ///
> +  UINT8                             ServiceAreaData[64];
> +} UD_TABLE;
> +
> +#define EFI_TO_LEGACY_MAJOR_VERSION 0x02
> +#define EFI_TO_LEGACY_MINOR_VERSION 0x00
> +#define MAX_IDE_CONTROLLER          8
> +
> +///
> +/// EFI_TO_COMPATIBILITY16_BOOT_TABLE
> +///
> +typedef struct {
> +  UINT16                            MajorVersion;                 ///< The
> EfiCompatibility major version number.
> +  UINT16                            MinorVersion;                 ///< The
> EfiCompatibility minor version number.
> +  UINT32                            AcpiTable;                    ///< The location of
> the RSDT ACPI table. < 4G range.
> +  UINT32                            SmbiosTable;                  ///< The location of
> the SMBIOS table in EFI memory. < 4G range.
> +  UINT32                            SmbiosTableLength;
> +  //
> +  // Legacy SIO state
> +  //
> +  DEVICE_PRODUCER_DATA_HEADER       SioData;                      ///<
> Standard traditional device information.
> +  UINT16                            DevicePathType;               ///< The default
> boot type.
> +  UINT16                            PciIrqMask;                   ///< Mask of which
> IRQs have been assigned to PCI.
> +  UINT32                            NumberE820Entries;            ///< Number of
> E820 entries. The number can change from the
> +                                                                  ///<
> Compatibility16InitializeYourself() function.
> +  //
> +  // Controller & Drive Identify[2] per controller information
> +  //
> +  HDD_INFO                          HddInfo[MAX_IDE_CONTROLLER];  ///< Hard
> disk drive information, including raw Identify Drive data.
> +  UINT32                            NumberBbsEntries;             ///< Number of
> entries in the BBS table
> +  UINT32                            BbsTable;                     ///< A pointer to the
> BBS table. Type BBS_TABLE is defined below.
> +  UINT32                            SmmTable;                     ///< A pointer to the
> SMM table. Type SMM_TABLE is defined below.
> +  UINT32                            OsMemoryAbove1Mb;             ///< The
> amount of usable memory above 1 MB, i.e. E820 type 1 memory. This value can
> +                                                                  ///< differ from the value in
> EFI_TO_COMPATIBILITY16_INIT_TABLE as more
> +                                                                  ///< memory may have been
> discovered.
> +  UINT32                            UnconventionalDeviceTable;    ///<
> Information to boot off an unconventional device like a PARTIES partition. Type
> +                                                                  ///< UD_TABLE is defined
> below.
> +} EFI_TO_COMPATIBILITY16_BOOT_TABLE;
> +
> +///
> +/// EFI_LEGACY_INSTALL_PCI_HANDLER
> +///
> +typedef struct {
> +  UINT8                             PciBus;             ///< The PCI bus of the device.
> +  UINT8                             PciDeviceFun;       ///< The PCI device in bits 7:3
> and function in bits 2:0.
> +  UINT8                             PciSegment;         ///< The PCI segment of the
> device.
> +  UINT8                             PciClass;           ///< The PCI class code of the
> device.
> +  UINT8                             PciSubclass;        ///< The PCI subclass code of
> the device.
> +  UINT8                             PciInterface;       ///< The PCI interface code of
> the device.
> +  //
> +  // Primary section
> +  //
> +  UINT8                             PrimaryIrq;         ///< The primary device IRQ.
> +  UINT8                             PrimaryReserved;    ///< Reserved.
> +  UINT16                            PrimaryControl;     ///< The primary device
> control I/O base.
> +  UINT16                            PrimaryBase;        ///< The primary device I/O
> base.
> +  UINT16                            PrimaryBusMaster;   ///< The primary device
> bus master I/O base.
> +  //
> +  // Secondary Section
> +  //
> +  UINT8                             SecondaryIrq;       ///< The secondary device
> IRQ.
> +  UINT8                             SecondaryReserved;  ///< Reserved.
> +  UINT16                            SecondaryControl;   ///< The secondary device
> control I/O base.
> +  UINT16                            SecondaryBase;      ///< The secondary device
> I/O base.
> +  UINT16                            SecondaryBusMaster; ///< The secondary
> device bus master I/O base.
> +} EFI_LEGACY_INSTALL_PCI_HANDLER;
> +
> +//
> +// Restore default pack value
> +//
> +#pragma pack()
> +
> +#define EFI_LEGACY_BIOS_PROTOCOL_GUID \
> +  { \
> +    0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e,
> 0x2d } \
> +  }
> +
> +typedef struct _EFI_LEGACY_BIOS_PROTOCOL EFI_LEGACY_BIOS_PROTOCOL;
> +
> +///
> +/// Flags returned by CheckPciRom().
> +///
> +#define NO_ROM            0x00
> +#define ROM_FOUND         0x01
> +#define VALID_LEGACY_ROM  0x02
> +#define ROM_WITH_CONFIG   0x04     ///< Not defined in the Framework
> CSM Specification.
> +
> +///
> +/// The following macros do not appear in the Framework CSM Specification
> and
> +/// are kept for backward compatibility only.  They convert 32-bit address
> (_Adr)
> +/// to Segment:Offset 16-bit form.
> +///
> +///@{
> +#define EFI_SEGMENT(_Adr)     (UINT16) ((UINT16) (((UINTN) (_Adr)) >> 4) &
> 0xf000)
> +#define EFI_OFFSET(_Adr)      (UINT16) (((UINT16) ((UINTN) (_Adr))) & 0xffff)
> +///@}
> +
> +#define CARRY_FLAG            0x01
> +
> +///
> +/// EFI_EFLAGS_REG
> +///
> +typedef struct {
> +  UINT32 CF:1;
> +  UINT32 Reserved1:1;
> +  UINT32 PF:1;
> +  UINT32 Reserved2:1;
> +  UINT32 AF:1;
> +  UINT32 Reserved3:1;
> +  UINT32 ZF:1;
> +  UINT32 SF:1;
> +  UINT32 TF:1;
> +  UINT32 IF:1;
> +  UINT32 DF:1;
> +  UINT32 OF:1;
> +  UINT32 IOPL:2;
> +  UINT32 NT:1;
> +  UINT32 Reserved4:2;
> +  UINT32 VM:1;
> +  UINT32 Reserved5:14;
> +} EFI_EFLAGS_REG;
> +
> +///
> +/// EFI_DWORD_REGS
> +///
> +typedef struct {
> +    UINT32           EAX;
> +    UINT32           EBX;
> +    UINT32           ECX;
> +    UINT32           EDX;
> +    UINT32           ESI;
> +    UINT32           EDI;
> +    EFI_EFLAGS_REG   EFlags;
> +    UINT16           ES;
> +    UINT16           CS;
> +    UINT16           SS;
> +    UINT16           DS;
> +    UINT16           FS;
> +    UINT16           GS;
> +    UINT32           EBP;
> +    UINT32           ESP;
> +} EFI_DWORD_REGS;
> +
> +///
> +/// EFI_FLAGS_REG
> +///
> +typedef struct {
> +  UINT16     CF:1;
> +  UINT16     Reserved1:1;
> +  UINT16     PF:1;
> +  UINT16     Reserved2:1;
> +  UINT16     AF:1;
> +  UINT16     Reserved3:1;
> +  UINT16     ZF:1;
> +  UINT16     SF:1;
> +  UINT16     TF:1;
> +  UINT16     IF:1;
> +  UINT16     DF:1;
> +  UINT16     OF:1;
> +  UINT16     IOPL:2;
> +  UINT16     NT:1;
> +  UINT16     Reserved4:1;
> +} EFI_FLAGS_REG;
> +
> +///
> +/// EFI_WORD_REGS
> +///
> +typedef struct {
> +    UINT16           AX;
> +    UINT16           ReservedAX;
> +    UINT16           BX;
> +    UINT16           ReservedBX;
> +    UINT16           CX;
> +    UINT16           ReservedCX;
> +    UINT16           DX;
> +    UINT16           ReservedDX;
> +    UINT16           SI;
> +    UINT16           ReservedSI;
> +    UINT16           DI;
> +    UINT16           ReservedDI;
> +    EFI_FLAGS_REG    Flags;
> +    UINT16           ReservedFlags;
> +    UINT16           ES;
> +    UINT16           CS;
> +    UINT16           SS;
> +    UINT16           DS;
> +    UINT16           FS;
> +    UINT16           GS;
> +    UINT16           BP;
> +    UINT16           ReservedBP;
> +    UINT16           SP;
> +    UINT16           ReservedSP;
> +} EFI_WORD_REGS;
> +
> +///
> +/// EFI_BYTE_REGS
> +///
> +typedef struct {
> +    UINT8   AL, AH;
> +    UINT16  ReservedAX;
> +    UINT8   BL, BH;
> +    UINT16  ReservedBX;
> +    UINT8   CL, CH;
> +    UINT16  ReservedCX;
> +    UINT8   DL, DH;
> +    UINT16  ReservedDX;
> +} EFI_BYTE_REGS;
> +
> +///
> +/// EFI_IA32_REGISTER_SET
> +///
> +typedef union {
> +  EFI_DWORD_REGS  E;
> +  EFI_WORD_REGS   X;
> +  EFI_BYTE_REGS   H;
> +} EFI_IA32_REGISTER_SET;
> +
> +/**
> +  Thunk to 16-bit real mode and execute a software interrupt with a vector
> +  of BiosInt. Regs will contain the 16-bit register context on entry and
> +  exit.
> +
> +  @param[in]     This      The protocol instance pointer.
> +  @param[in]     BiosInt   The processor interrupt vector to invoke.
> +  @param[in,out] Reg       Register contexted passed into (and returned)
> from thunk to
> +                           16-bit mode.
> +
> +  @retval TRUE                Thunk completed with no BIOS errors in the target
> code. See Regs for status.
> +  @retval FALSE                  There was a BIOS error in the target code.
> +**/
> +typedef
> +BOOLEAN
> +(EFIAPI *EFI_LEGACY_BIOS_INT86)(
> +  IN     EFI_LEGACY_BIOS_PROTOCOL  *This,
> +  IN     UINT8                     BiosInt,
> +  IN OUT EFI_IA32_REGISTER_SET     *Regs
> +  );
> +
> +/**
> +  Thunk to 16-bit real mode and call Segment:Offset. Regs will contain the
> +  16-bit register context on entry and exit. Arguments can be passed on
> +  the Stack argument
> +
> +  @param[in] This        The protocol instance pointer.
> +  @param[in] Segment     The segemnt of 16-bit mode call.
> +  @param[in] Offset      The offset of 16-bit mdoe call.
> +  @param[in] Reg         Register contexted passed into (and returned) from
> thunk to
> +                         16-bit mode.
> +  @param[in] Stack       The caller allocated stack used to pass arguments.
> +  @param[in] StackSize   The size of Stack in bytes.
> +
> +  @retval FALSE                 Thunk completed with no BIOS errors in the
> target code.                                See Regs for status.  @retval TRUE
> There was a BIOS error in the target code.
> +**/
> +typedef
> +BOOLEAN
> +(EFIAPI *EFI_LEGACY_BIOS_FARCALL86)(
> +  IN EFI_LEGACY_BIOS_PROTOCOL  *This,
> +  IN UINT16                    Segment,
> +  IN UINT16                    Offset,
> +  IN EFI_IA32_REGISTER_SET     *Regs,
> +  IN VOID                      *Stack,
> +  IN UINTN                     StackSize
> +  );
> +
> +/**
> +  Test to see if a legacy PCI ROM exists for this device. Optionally return
> +  the Legacy ROM instance for this PCI device.
> +
> +  @param[in]  This        The protocol instance pointer.
> +  @param[in]  PciHandle   The PCI PC-AT OPROM from this devices ROM BAR
> will be loaded
> +  @param[out] RomImage    Return the legacy PCI ROM for this device.
> +  @param[out] RomSize     The size of ROM Image.
> +  @param[out] Flags       Indicates if ROM found and if PC-AT. Multiple bits
> can be set as follows:
> +                            - 00 = No ROM.
> +                            - 01 = ROM Found.
> +                            - 02 = ROM is a valid legacy ROM.
> +
> +  @retval EFI_SUCCESS       The Legacy Option ROM available for this device
> +  @retval EFI_UNSUPPORTED   The Legacy Option ROM is not supported.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_BIOS_CHECK_ROM)(
> +  IN  EFI_LEGACY_BIOS_PROTOCOL  *This,
> +  IN  EFI_HANDLE                PciHandle,
> +  OUT VOID                      **RomImage, OPTIONAL
> +  OUT UINTN                     *RomSize, OPTIONAL
> +  OUT UINTN                     *Flags
> +  );
> +
> +/**
> +  Load a legacy PC-AT OPROM on the PciHandle device. Return information
> +  about how many disks were added by the OPROM and the shadow address
> and
> +  size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C:
> +
> +  @param[in]  This               The protocol instance pointer.
> +  @param[in]  PciHandle          The PCI PC-AT OPROM from this devices ROM
> BAR will be loaded.
> +                                 This value is NULL if RomImage is non-NULL. This is
> the normal
> +                                 case.
> +  @param[in]  RomImage           A PCI PC-AT ROM image. This argument is
> non-NULL if there is
> +                                 no hardware associated with the ROM and thus no
> PciHandle,
> +                                 otherwise is must be NULL.
> +                                 Example is PXE base code.
> +  @param[out] Flags              The type of ROM discovered. Multiple bits can
> be set, as follows:
> +                                   - 00 = No ROM.
> +                                   - 01 = ROM found.
> +                                   - 02 = ROM is a valid legacy ROM.
> +  @param[out] DiskStart          The disk number of first device hooked by the
> ROM. If DiskStart
> +                                 is the same as DiskEnd no disked were hooked.
> +  @param[out] DiskEnd            disk number of the last device hooked by the
> ROM.
> +  @param[out] RomShadowAddress   Shadow address of PC-AT ROM.
> +  @param[out] RomShadowSize      Size of RomShadowAddress in bytes.
> +
> +  @retval EFI_SUCCESS             Thunk completed, see Regs for status.
> +  @retval EFI_INVALID_PARAMETER   PciHandle not found
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_BIOS_INSTALL_ROM)(
> +  IN  EFI_LEGACY_BIOS_PROTOCOL  *This,
> +  IN  EFI_HANDLE                PciHandle,
> +  IN  VOID                      **RomImage,
> +  OUT UINTN                     *Flags,
> +  OUT UINT8                     *DiskStart, OPTIONAL
> +  OUT UINT8                     *DiskEnd, OPTIONAL
> +  OUT VOID                      **RomShadowAddress, OPTIONAL
> +  OUT UINT32                    *ShadowedRomSize OPTIONAL
> +  );
> +
> +/**
> +  This function attempts to traditionally boot the specified BootOption. If the
> EFI context has
> +  been compromised, this function will not return. This procedure is not used
> for loading an EFI-aware
> +  OS off a traditional device. The following actions occur:
> +  - Get EFI SMBIOS data structures, convert them to a traditional format, and
> copy to
> +    Compatibility16.
> +  - Get a pointer to ACPI data structures and copy the Compatibility16 RSD
> PTR to F0000 block.
> +  - Find the traditional SMI handler from a firmware volume and register the
> traditional SMI
> +    handler with the EFI SMI handler.
> +  - Build onboard IDE information and pass this information to the
> Compatibility16 code.
> +  - Make sure all PCI Interrupt Line registers are programmed to match 8259.
> +  - Reconfigure SIO devices from EFI mode (polled) into traditional mode
> (interrupt driven).
> +  - Shadow all PCI ROMs.
> +  - Set up BDA and EBDA standard areas before the legacy boot.
> +  - Construct the Compatibility16 boot memory map and pass it to the
> Compatibility16 code.
> +  - Invoke the Compatibility16 table function
> Compatibility16PrepareToBoot(). This
> +    invocation causes a thunk into the Compatibility16 code, which sets all
> appropriate internal
> +    data structures. The boot device list is a parameter.
> +  - Invoke the Compatibility16 Table function Compatibility16Boot(). This
> invocation
> +    causes a thunk into the Compatibility16 code, which does an INT19.
> +  - If the Compatibility16Boot() function returns, then the boot failed in a
> graceful
> +    manner--meaning that the EFI code is still valid. An ungraceful boot failure
> causes a reset because the state
> +    of EFI code is unknown.
> +
> +  @param[in] This             The protocol instance pointer.
> +  @param[in] BootOption       The EFI Device Path from BootXXXX variable.
> +  @param[in] LoadOptionSize   The size of LoadOption in size.
> +  @param[in] LoadOption       LThe oadOption from BootXXXX variable.
> +
> +  @retval EFI_DEVICE_ERROR      Failed to boot from any boot device and
> memory is uncorrupted.                                Note: This function normally
> does not returns. It will either boot the                                OS or reset the
> system if memory has been "corrupted" by loading                                a
> boot sector and passing control to it.
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_BIOS_BOOT)(
> +  IN EFI_LEGACY_BIOS_PROTOCOL  *This,
> +  IN BBS_BBS_DEVICE_PATH       *BootOption,
> +  IN UINT32                    LoadOptionsSize,
> +  IN VOID                      *LoadOptions
> +  );
> +
> +/**
> +  This function takes the Leds input parameter and sets/resets the BDA
> accordingly.
> +  Leds is also passed to Compatibility16 code, in case any special processing
> is required.
> +  This function is normally called from EFI Setup drivers that handle
> user-selectable
> +  keyboard options such as boot with NUM LOCK on/off. This function does
> not
> +  touch the keyboard or keyboard LEDs but only the BDA.
> +
> +  @param[in] This   The protocol instance pointer.
> +  @param[in] Leds   The status of current Scroll, Num & Cap lock LEDS:
> +                      - Bit 0 is Scroll Lock 0 = Not locked.
> +                      - Bit 1 is Num Lock.
> +                      - Bit 2 is Caps Lock.
> +
> +  @retval EFI_SUCCESS   The BDA was updated successfully.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_BIOS_UPDATE_KEYBOARD_LED_STATUS)(
> +  IN EFI_LEGACY_BIOS_PROTOCOL  *This,
> +  IN UINT8                     Leds
> +  );
> +
> +/**
> +  Retrieve legacy BBS info and assign boot priority.
> +
> +  @param[in]     This       The protocol instance pointer.
> +  @param[out]    HddCount   The number of HDD_INFO structures.
> +  @param[out]    HddInfo    Onboard IDE controller information.
> +  @param[out]    BbsCount   The number of BBS_TABLE structures.
> +  @param[in,out] BbsTable   Points to List of BBS_TABLE.
> +
> +  @retval EFI_SUCCESS   Tables were returned.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_BIOS_GET_BBS_INFO)(
> +  IN     EFI_LEGACY_BIOS_PROTOCOL  *This,
> +  OUT    UINT16                    *HddCount,
> +  OUT    HDD_INFO                  **HddInfo,
> +  OUT    UINT16                    *BbsCount,
> +  IN OUT BBS_TABLE                 **BbsTable
> +  );
> +
> +/**
> +  Assign drive number to legacy HDD drives prior to booting an EFI
> +  aware OS so the OS can access drives without an EFI driver.
> +
> +  @param[in]  This       The protocol instance pointer.
> +  @param[out] BbsCount   The number of BBS_TABLE structures
> +  @param[out] BbsTable   List of BBS entries
> +
> +  @retval EFI_SUCCESS   Drive numbers assigned.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_BIOS_PREPARE_TO_BOOT_EFI)(
> +  IN  EFI_LEGACY_BIOS_PROTOCOL  *This,
> +  OUT UINT16                    *BbsCount,
> +  OUT BBS_TABLE                 **BbsTable
> +  );
> +
> +/**
> +  To boot from an unconventional device like parties and/or execute
> +  HDD diagnostics.
> +
> +  @param[in]  This              The protocol instance pointer.
> +  @param[in]  Attributes        How to interpret the other input parameters.
> +  @param[in]  BbsEntry          The 0-based index into the BbsTable for the
> parent
> +                                device.
> +  @param[in]  BeerData          A pointer to the 128 bytes of ram BEER data.
> +  @param[in]  ServiceAreaData   A pointer to the 64 bytes of raw Service
> Area data. The
> +                                caller must provide a pointer to the specific Service
> +                                Area and not the start all Service Areas.
> +
> +  @retval EFI_INVALID_PARAMETER   If error. Does NOT return if no error.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_BIOS_BOOT_UNCONVENTIONAL_DEVICE)(
> +  IN EFI_LEGACY_BIOS_PROTOCOL  *This,
> +  IN UDC_ATTRIBUTES            Attributes,
> +  IN UINTN                     BbsEntry,
> +  IN VOID                      *BeerData,
> +  IN VOID                      *ServiceAreaData
> +  );
> +
> +/**
> +  Shadow all legacy16 OPROMs that haven't been shadowed.
> +  Warning: Use this with caution. This routine disconnects all EFI
> +  drivers. If used externally, then  the caller must re-connect EFI
> +  drivers.
> +
> +  @param[in]  This   The protocol instance pointer.
> +
> +  @retval EFI_SUCCESS   OPROMs were shadowed.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_BIOS_SHADOW_ALL_LEGACY_OPROMS)(
> +  IN EFI_LEGACY_BIOS_PROTOCOL  *This
> +  );
> +
> +/**
> +  Get a region from the LegacyBios for S3 usage.
> +
> +  @param[in]  This                  The protocol instance pointer.
> +  @param[in]  LegacyMemorySize      The size of required region.
> +  @param[in]  Region                The region to use.
> +                                    00 = Either 0xE0000 or 0xF0000 block.
> +                                      - Bit0 = 1 0xF0000 block.
> +                                      - Bit1 = 1 0xE0000 block.
> +  @param[in]  Alignment             Address alignment. Bit mapped. The first
> non-zero
> +                                    bit from right is alignment.
> +  @param[out] LegacyMemoryAddress   The Region Assigned
> +
> +  @retval EFI_SUCCESS           The Region was assigned.
> +  @retval EFI_ACCESS_DENIED     The function was previously invoked.
> +  @retval Other                 The Region was not assigned.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_BIOS_GET_LEGACY_REGION)(
> +  IN  EFI_LEGACY_BIOS_PROTOCOL  *This,
> +  IN  UINTN                     LegacyMemorySize,
> +  IN  UINTN                     Region,
> +  IN  UINTN                     Alignment,
> +  OUT VOID                      **LegacyMemoryAddress
> +  );
> +
> +/**
> +  Get a region from the LegacyBios for Tiano usage. Can only be invoked once.
> +
> +  @param[in]  This                        The protocol instance pointer.
> +  @param[in]  LegacyMemorySize            The size of data to copy.
> +  @param[in]  LegacyMemoryAddress         The Legacy Region destination
> address.
> +                                          Note: must be in region assigned by
> +                                          LegacyBiosGetLegacyRegion.
> +  @param[in]  LegacyMemorySourceAddress   The source of the data to
> copy.
> +
> +  @retval EFI_SUCCESS           The Region assigned.
> +  @retval EFI_ACCESS_DENIED     Destination was outside an assigned
> region.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_BIOS_COPY_LEGACY_REGION)(
> +  IN EFI_LEGACY_BIOS_PROTOCOL  *This,
> +  IN UINTN                     LegacyMemorySize,
> +  IN VOID                      *LegacyMemoryAddress,
> +  IN VOID                      *LegacyMemorySourceAddress
> +  );
> +
> +///
> +/// Abstracts the traditional BIOS from the rest of EFI. The LegacyBoot()
> +/// member function allows the BDS to support booting a traditional OS.
> +/// EFI thunks drivers that make EFI bindings for BIOS INT services use
> +/// all the other member functions.
> +///
> +struct _EFI_LEGACY_BIOS_PROTOCOL {
> +  ///
> +  /// Performs traditional software INT. See the Int86() function description.
> +  ///
> +  EFI_LEGACY_BIOS_INT86                       Int86;
> +
> +  ///
> +  /// Performs a far call into Compatibility16 or traditional OpROM code.
> +  ///
> +  EFI_LEGACY_BIOS_FARCALL86                   FarCall86;
> +
> +  ///
> +  /// Checks if a traditional OpROM exists for this device.
> +  ///
> +  EFI_LEGACY_BIOS_CHECK_ROM                   CheckPciRom;
> +
> +  ///
> +  /// Loads a traditional OpROM in traditional OpROM address space.
> +  ///
> +  EFI_LEGACY_BIOS_INSTALL_ROM                 InstallPciRom;
> +
> +  ///
> +  /// Boots a traditional OS.
> +  ///
> +  EFI_LEGACY_BIOS_BOOT                        LegacyBoot;
> +
> +  ///
> +  /// Updates BDA to reflect the current EFI keyboard LED status.
> +  ///
> +  EFI_LEGACY_BIOS_UPDATE_KEYBOARD_LED_STATUS
> UpdateKeyboardLedStatus;
> +
> +  ///
> +  /// Allows an external agent, such as BIOS Setup, to get the BBS data.
> +  ///
> +  EFI_LEGACY_BIOS_GET_BBS_INFO                GetBbsInfo;
> +
> +  ///
> +  /// Causes all legacy OpROMs to be shadowed.
> +  ///
> +  EFI_LEGACY_BIOS_SHADOW_ALL_LEGACY_OPROMS
> ShadowAllLegacyOproms;
> +
> +  ///
> +  /// Performs all actions prior to boot. Used when booting an EFI-aware OS
> +  /// rather than a legacy OS.
> +  ///
> +  EFI_LEGACY_BIOS_PREPARE_TO_BOOT_EFI         PrepareToBootEfi;
> +
> +  ///
> +  /// Allows EFI to reserve an area in the 0xE0000 or 0xF0000 block.
> +  ///
> +  EFI_LEGACY_BIOS_GET_LEGACY_REGION           GetLegacyRegion;
> +
> +  ///
> +  /// Allows EFI to copy data to the area specified by GetLegacyRegion.
> +  ///
> +  EFI_LEGACY_BIOS_COPY_LEGACY_REGION          CopyLegacyRegion;
> +
> +  ///
> +  /// Allows the user to boot off an unconventional device such as a PARTIES
> partition.
> +  ///
> +  EFI_LEGACY_BIOS_BOOT_UNCONVENTIONAL_DEVICE
> BootUnconventionalDevice;
> +};
> +
> +extern EFI_GUID gEfiLegacyBiosProtocolGuid;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Includ
> e/Protocol/LegacyInterrupt.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Includ
> e/Protocol/LegacyInterrupt.h
> new file mode 100644
> index 0000000000..1d776793d2
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Includ
> e/Protocol/LegacyInterrupt.h
> @@ -0,0 +1,118 @@
> +/** @file
> +  This protocol abstracts the PIRQ programming from the generic EFI
> Compatibility Support Modules (CSMs).
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _EFI_LEGACY_INTERRUPT_H_
> +#define _EFI_LEGACY_INTERRUPT_H_
> +
> +
> +#define EFI_LEGACY_INTERRUPT_PROTOCOL_GUID \
> +  { \
> +    0x31ce593d, 0x108a, 0x485d, {0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66,
> 0xbe } \
> +  }
> +
> +typedef struct _EFI_LEGACY_INTERRUPT_PROTOCOL
> EFI_LEGACY_INTERRUPT_PROTOCOL;
> +
> +/**
> +  Get the number of PIRQs this hardware supports.
> +
> +  @param  This                  The protocol instance pointer.
> +  @param  NumberPirsq           The number of PIRQs that are supported.
> +
> +  @retval EFI_SUCCESS           The number of PIRQs was returned
> successfully.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_INTERRUPT_GET_NUMBER_PIRQS)(
> +  IN EFI_LEGACY_INTERRUPT_PROTOCOL            *This,
> +  OUT UINT8                                   *NumberPirqs
> +  );
> +
> +/**
> +  Gets the PCI location associated with this protocol.
> +
> +  @param  This                  The Protocol instance pointer.
> +  @param  Bus                   The PCI Bus.
> +  @param  Device                The PCI Device.
> +  @param  Function              The PCI Function.
> +
> +  @retval EFI_SUCCESS           The Bus, Device, and Function were returned
> successfully.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_INTERRUPT_GET_LOCATION)(
> +  IN EFI_LEGACY_INTERRUPT_PROTOCOL            *This,
> +  OUT UINT8                                   *Bus,
> +  OUT UINT8                                   *Device,
> +  OUT UINT8                                   *Function
> +  );
> +
> +/**
> +  Read the PIRQ register and return the data
> +
> +  @param  This                  The protocol instance pointer.
> +  @param  PirqNumber            The PIRQ register to read.
> +  @param  PirqData              The data read.
> +
> +  @retval EFI_SUCCESS           The data was read.
> +  @retval EFI_INVALID_PARAMETER Invalid PIRQ number.
> +  @retval EFI_DEVICE_ERROR      Operation was unsuccessful
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_INTERRUPT_READ_PIRQ)(
> +  IN EFI_LEGACY_INTERRUPT_PROTOCOL           *This,
> +  IN  UINT8                                  PirqNumber,
> +  OUT UINT8                                  *PirqData
> +  );
> +
> +/**
> +  Write the specified PIRQ register with the given data.
> +
> +  @param  This                  The protocol instance pointer.
> +  @param  PirqNumber            A PIRQ register to read.
> +  @param  PirqData              The data to write.
> +
> +  @retval EFI_SUCCESS           The PIRQ was programmed.
> +  @retval EFI_INVALID_PARAMETER Invalid PIRQ number.
> +  @retval EFI_DEVICE_ERROR      Operation was unsuccessful
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *EFI_LEGACY_INTERRUPT_WRITE_PIRQ)(
> +  IN EFI_LEGACY_INTERRUPT_PROTOCOL           *This,
> +  IN  UINT8                                  PirqNumber,
> +  IN UINT8                                   PirqData
> +  );
> +
> +struct _EFI_LEGACY_INTERRUPT_PROTOCOL {
> +  ///
> +  ///   Gets the number of PIRQs supported.
> +  ///
> +  EFI_LEGACY_INTERRUPT_GET_NUMBER_PIRQS GetNumberPirqs;
> +
> +  ///
> +  /// Gets the PCI bus, device, and function that is associated with this
> protocol.
> +  ///
> +  EFI_LEGACY_INTERRUPT_GET_LOCATION     GetLocation;
> +
> +  ///
> +  /// Reads the indicated PIRQ register.
> +  ///
> +  EFI_LEGACY_INTERRUPT_READ_PIRQ        ReadPirq;
> +
> +  ///
> +  /// Writes to the indicated PIRQ register.
> +  ///
> +  EFI_LEGACY_INTERRUPT_WRITE_PIRQ       WritePirq;
> +};
> +
> +extern EFI_GUID gEfiLegacyInterruptProtocolGuid;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/G
> uid/AcpiS3Context.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/G
> uid/AcpiS3Context.h
> new file mode 100644
> index 0000000000..c1d1fc89ec
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/G
> uid/AcpiS3Context.h
> @@ -0,0 +1,65 @@
> +/** @file
> +  Definitions for data structures used in S3 resume.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _ACPI_S3_DATA_H_
> +#define _ACPI_S3_DATA_H_
> +
> +#include <Library/BaseLib.h>
> +
> +#define SMM_S3_RESUME_SMM_32 SIGNATURE_64
> ('S','M','M','S','3','_','3','2')
> +#define SMM_S3_RESUME_SMM_64 SIGNATURE_64
> ('S','M','M','S','3','_','6','4')
> +
> +#pragma pack(1)
> +
> +typedef struct {
> +  UINT64                Signature;
> +  EFI_PHYSICAL_ADDRESS  SmmS3ResumeEntryPoint;
> +  EFI_PHYSICAL_ADDRESS  SmmS3StackBase;
> +  UINT64                SmmS3StackSize;
> +  UINT64                SmmS3Cr0;
> +  UINT64                SmmS3Cr3;
> +  UINT64                SmmS3Cr4;
> +  UINT16                ReturnCs;
> +  EFI_PHYSICAL_ADDRESS  ReturnEntryPoint;
> +  EFI_PHYSICAL_ADDRESS  ReturnContext1;
> +  EFI_PHYSICAL_ADDRESS  ReturnContext2;
> +  EFI_PHYSICAL_ADDRESS  ReturnStackPointer;
> +  EFI_PHYSICAL_ADDRESS  Smst;
> +} SMM_S3_RESUME_STATE;
> +
> +
> +typedef struct {
> +  EFI_PHYSICAL_ADDRESS  AcpiFacsTable;
> +  EFI_PHYSICAL_ADDRESS  IdtrProfile;
> +  EFI_PHYSICAL_ADDRESS  S3NvsPageTableAddress;
> +  EFI_PHYSICAL_ADDRESS  BootScriptStackBase;
> +  UINT64                BootScriptStackSize;
> +  EFI_PHYSICAL_ADDRESS  S3DebugBufferAddress;
> +} ACPI_S3_CONTEXT;
> +
> +typedef struct {
> +  UINT16                ReturnCs;
> +  UINT64                ReturnStatus;
> +  EFI_PHYSICAL_ADDRESS  ReturnEntryPoint;
> +  EFI_PHYSICAL_ADDRESS  ReturnStackPointer;
> +  EFI_PHYSICAL_ADDRESS  AsmTransferControl;
> +  IA32_DESCRIPTOR       Idtr;
> +} PEI_S3_RESUME_STATE;
> +
> +#pragma pack()
> +
> +#define EFI_ACPI_S3_CONTEXT_GUID \
> +  { \
> +    0xef98d3a, 0x3e33, 0x497a, {0xa4, 0x1, 0x77, 0xbe, 0x3e, 0xb7, 0x4f, 0x38}
> \
> +  }
> +
> +extern EFI_GUID gEfiAcpiS3ContextGuid;
> +
> +extern EFI_GUID gEfiAcpiVariableGuid;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/G
> uid/ConsoleOutDevice.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/G
> uid/ConsoleOutDevice.h
> new file mode 100644
> index 0000000000..c770101b38
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/G
> uid/ConsoleOutDevice.h
> @@ -0,0 +1,17 @@
> +/** @file
> +  This GUID can be installed to the device handle to specify that the device is
> the console-out device.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef __CONSOLE_OUT_DEVICE_H__
> +#define __CONSOLE_OUT_DEVICE_H__
> +
> +#define EFI_CONSOLE_OUT_DEVICE_GUID    \
> +    { 0xd3b36f2c, 0xd551, 0x11d4, {0x9a, 0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1,
> 0x4d } }
> +
> +extern EFI_GUID gEfiConsoleOutDeviceGuid;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/G
> uid/MemoryTypeInformation.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/G
> uid/MemoryTypeInformation.h
> new file mode 100644
> index 0000000000..bf4b3cdeca
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/G
> uid/MemoryTypeInformation.h
> @@ -0,0 +1,30 @@
> +/** @file
> +  This file defines:
> +  * Memory Type Information GUID for HOB and Variable.
> +  * Memory Type Information Variable Name.
> +  * Memory Type Information GUID HOB data structure.
> +
> +  The memory type information HOB and variable can
> +  be used to store the information for each memory type in Variable or HOB.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef __MEMORY_TYPE_INFORMATION_GUID_H__
> +#define __MEMORY_TYPE_INFORMATION_GUID_H__
> +
> +#define EFI_MEMORY_TYPE_INFORMATION_GUID \
> +  { 0x4c19049f,0x4137,0x4dd3, { 0x9c,0x10,0x8b,0x97,0xa8,0x3f,0xfd,0xfa } }
> +
> +#define EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME
> L"MemoryTypeInformation"
> +
> +extern EFI_GUID gEfiMemoryTypeInformationGuid;
> +
> +typedef struct {
> +  UINT32  Type;             ///< EFI memory type defined in UEFI specification.
> +  UINT32  NumberOfPages;    ///< The pages of this type memory.
> +} EFI_MEMORY_TYPE_INFORMATION;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Li
> brary/ResetSystemLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Li
> brary/ResetSystemLib.h
> new file mode 100644
> index 0000000000..754865943e
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Li
> brary/ResetSystemLib.h
> @@ -0,0 +1,80 @@
> +/** @file
> +  System reset Library Services.  This library class defines a set of
> +  methods that reset the whole system.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef __RESET_SYSTEM_LIB_H__
> +#define __RESET_SYSTEM_LIB_H__
> +
> +/**
> +  This function causes a system-wide reset (cold reset), in which
> +  all circuitry within the system returns to its initial state. This type of reset
> +  is asynchronous to system operation and operates without regard to
> +  cycle boundaries.
> +
> +  If this function returns, it means that the system does not support cold
> reset.
> +**/
> +VOID
> +EFIAPI
> +ResetCold (
> +  VOID
> +  );
> +
> +/**
> +  This function causes a system-wide initialization (warm reset), in which all
> processors
> +  are set to their initial state. Pending cycles are not corrupted.
> +
> +  If this function returns, it means that the system does not support warm
> reset.
> +**/
> +VOID
> +EFIAPI
> +ResetWarm (
> +  VOID
> +  );
> +
> +/**
> +  This function causes the system to enter a power state equivalent
> +  to the ACPI G2/S5 or G3 states.
> +
> +  If this function returns, it means that the system does not support
> shutdown reset.
> +**/
> +VOID
> +EFIAPI
> +ResetShutdown (
> +  VOID
> +  );
> +
> +/**
> +  This function causes the system to enter S3 and then wake up immediately.
> +
> +  If this function returns, it means that the system does not support S3
> feature.
> +**/
> +VOID
> +EFIAPI
> +EnterS3WithImmediateWake (
> +  VOID
> +  );
> +
> +/**
> +  This function causes a systemwide reset. The exact type of the reset is
> +  defined by the EFI_GUID that follows the Null-terminated Unicode string
> passed
> +  into ResetData. If the platform does not recognize the EFI_GUID in
> ResetData
> +  the platform must pick a supported reset type to perform.The platform may
> +  optionally log the parameters from any non-normal reset that occurs.
> +
> +  @param[in]  DataSize   The size, in bytes, of ResetData.
> +  @param[in]  ResetData  The data buffer starts with a Null-terminated
> string,
> +                         followed by the EFI_GUID.
> +**/
> +VOID
> +EFIAPI
> +ResetPlatformSpecific (
> +  IN UINTN   DataSize,
> +  IN VOID    *ResetData
> +  );
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/P
> pi/SmmAccess.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/P
> pi/SmmAccess.h
> new file mode 100644
> index 0000000000..565d35b654
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/P
> pi/SmmAccess.h
> @@ -0,0 +1,137 @@
> +/** @file
> +  EFI SMM Access PPI definition.
> +
> +  This PPI is used to control the visibility of the SMRAM on the platform.
> +  It abstracts the location and characteristics of SMRAM.  The expectation is
> +  that the north bridge or memory controller would publish this PPI.
> +
> +  The principal functionality found in the memory controller includes the
> following:
> +  - Exposing the SMRAM to all non-SMM agents, or the "open" state
> +  - Shrouding the SMRAM to all but the SMM agents, or the "closed" state
> +  - Preserving the system integrity, or "locking" the SMRAM, such that the
> settings cannot be
> +    perturbed by either boot service or runtime agents
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SMM_ACCESS_PPI_H_
> +#define _SMM_ACCESS_PPI_H_
> +
> +#define PEI_SMM_ACCESS_PPI_GUID \
> +  { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e,
> 0xd6 }}
> +
> +typedef struct _PEI_SMM_ACCESS_PPI  PEI_SMM_ACCESS_PPI;
> +
> +/**
> +  Opens the SMRAM area to be accessible by a PEIM driver.
> +
> +  This function "opens" SMRAM so that it is visible while not inside of SMM.
> The function should
> +  return EFI_UNSUPPORTED if the hardware does not support hiding of
> SMRAM. The function
> +  should return EFI_DEVICE_ERROR if the SMRAM configuration is locked.
> +
> +  @param  PeiServices            General purpose services available to every
> PEIM.
> +  @param  This                   The pointer to the SMM Access Interface.
> +  @param  DescriptorIndex        The region of SMRAM to Open.
> +
> +  @retval EFI_SUCCESS            The region was successfully opened.
> +  @retval EFI_DEVICE_ERROR       The region could not be opened because
> locked by chipset.
> +  @retval EFI_INVALID_PARAMETER  The descriptor index was out of bounds.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *PEI_SMM_OPEN)(
> +  IN EFI_PEI_SERVICES                **PeiServices,
> +  IN PEI_SMM_ACCESS_PPI              *This,
> +  IN UINTN                           DescriptorIndex
> +  );
> +
> +/**
> +  Inhibits access to the SMRAM.
> +
> +  This function "closes" SMRAM so that it is not visible while outside of SMM.
> The function should
> +  return EFI_UNSUPPORTED if the hardware does not support hiding of
> SMRAM.
> +
> +  @param  PeiServices              General purpose services available to every
> PEIM.
> +  @param  This                     The pointer to the SMM Access Interface.
> +  @param  DescriptorIndex          The region of SMRAM to Close.
> +
> +  @retval EFI_SUCCESS              The region was successfully closed.
> +  @retval EFI_DEVICE_ERROR         The region could not be closed because
> locked by chipset.
> +  @retval EFI_INVALID_PARAMETER    The descriptor index was out of
> bounds.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *PEI_SMM_CLOSE)(
> +  IN EFI_PEI_SERVICES                **PeiServices,
> +  IN PEI_SMM_ACCESS_PPI              *This,
> +  IN UINTN                           DescriptorIndex
> +  );
> +
> +/**
> +  Inhibits access to the SMRAM.
> +
> +  This function prohibits access to the SMRAM region.  This function is
> usually implemented such
> +  that it is a write-once operation.
> +
> +  @param  PeiServices              General purpose services available to every
> PEIM.
> +  @param  This                     The pointer to the SMM Access Interface.
> +  @param  DescriptorIndex          The region of SMRAM to Close.
> +
> +  @retval EFI_SUCCESS            The region was successfully locked.
> +  @retval EFI_DEVICE_ERROR       The region could not be locked because at
> least
> +                                 one range is still open.
> +  @retval EFI_INVALID_PARAMETER  The descriptor index was out of bounds.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *PEI_SMM_LOCK)(
> +  IN EFI_PEI_SERVICES                **PeiServices,
> +  IN PEI_SMM_ACCESS_PPI              *This,
> +  IN UINTN                           DescriptorIndex
> +  );
> +
> +/**
> +  Queries the memory controller for the possible regions that will support
> SMRAM.
> +
> +  @param  PeiServices           General purpose services available to every
> PEIM.
> +  @param This                   The pointer to the SmmAccessPpi Interface.
> +  @param SmramMapSize           The pointer to the variable containing size
> of the
> +                                buffer to contain the description information.
> +  @param SmramMap               The buffer containing the data describing
> the Smram
> +                                region descriptors.
> +
> +  @retval EFI_BUFFER_TOO_SMALL  The user did not provide a sufficient
> buffer.
> +  @retval EFI_SUCCESS           The user provided a sufficiently-sized buffer.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *PEI_SMM_CAPABILITIES)(
> +  IN EFI_PEI_SERVICES                **PeiServices,
> +  IN PEI_SMM_ACCESS_PPI              *This,
> +  IN OUT UINTN                       *SmramMapSize,
> +  IN OUT EFI_SMRAM_DESCRIPTOR        *SmramMap
> +  );
> +
> +///
> +///  EFI SMM Access PPI is used to control the visibility of the SMRAM on the
> platform.
> +///  It abstracts the location and characteristics of SMRAM.  The expectation
> is
> +///  that the north bridge or memory controller would publish this PPI.
> +///
> +struct _PEI_SMM_ACCESS_PPI {
> +  PEI_SMM_OPEN          Open;
> +  PEI_SMM_CLOSE         Close;
> +  PEI_SMM_LOCK          Lock;
> +  PEI_SMM_CAPABILITIES  GetCapabilities;
> +  BOOLEAN               LockState;
> +  BOOLEAN               OpenState;
> +};
> +
> +extern EFI_GUID gPeiSmmAccessPpiGuid;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/P
> pi/SmmControl.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/P
> pi/SmmControl.h
> new file mode 100644
> index 0000000000..e982c00bf4
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/P
> pi/SmmControl.h
> @@ -0,0 +1,87 @@
> +/** @file
> +  EFI SMM Control PPI definition.
> +
> +  This PPI is used to initiate SMI/PMI activations. This protocol could be
> published by either:
> +  - A processor driver to abstract the SMI/PMI IPI
> +  - The driver that abstracts the ASIC that is supporting the APM port, such as
> the ICH in an
> +  Intel chipset
> +  Because of the possibility of performing SMI or PMI IPI transactions, the
> ability to generate this
> +  event from a platform chipset agent is an optional capability for both IA-32
> and Itanium-based
> +  systems.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SMM_CONTROL_PPI_H_
> +#define _SMM_CONTROL_PPI_H_
> +
> +#define PEI_SMM_CONTROL_PPI_GUID \
> +  { 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }
> +
> +typedef struct _PEI_SMM_CONTROL_PPI  PEI_SMM_CONTROL_PPI;
> +
> +/**
> +  Invokes SMI activation from either the preboot or runtime environment.
> +
> +  @param  PeiServices           General purpose services available to every
> PEIM.
> +  @param  This                  The PEI_SMM_CONTROL_PPI instance.
> +  @param  ArgumentBuffer        The optional sized data to pass into the
> protocol activation.
> +  @param  ArgumentBufferSize    The optional size of the data.
> +  @param  Periodic              An optional mechanism to periodically repeat
> activation.
> +  @param  ActivationInterval    An optional parameter to repeat at this
> period one
> +                                time or, if the Periodic Boolean is set, periodically.
> +
> +  @retval EFI_SUCCESS           The SMI/PMI has been engendered.
> +  @retval EFI_DEVICE_ERROR      The timing is unsupported.
> +  @retval EFI_INVALID_PARAMETER The activation period is unsupported.
> +  @retval EFI_NOT_STARTED       The SMM base service has not been
> initialized.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *PEI_SMM_ACTIVATE) (
> +  IN EFI_PEI_SERVICES                                **PeiServices,
> +  IN PEI_SMM_CONTROL_PPI                             * This,
> +  IN OUT INT8                                        *ArgumentBuffer OPTIONAL,
> +  IN OUT UINTN                                       *ArgumentBufferSize OPTIONAL,
> +  IN BOOLEAN                                         Periodic OPTIONAL,
> +  IN UINTN                                           ActivationInterval OPTIONAL
> +  );
> +
> +/**
> +  Clears any system state that was created in response to the Active call.
> +
> +  @param  PeiServices           General purpose services available to every
> PEIM.
> +  @param  This                  The PEI_SMM_CONTROL_PPI instance.
> +  @param  Periodic              Optional parameter to repeat at this period
> one
> +                                time or, if the Periodic Boolean is set, periodically.
> +
> +  @retval EFI_SUCCESS           The SMI/PMI has been engendered.
> +  @retval EFI_DEVICE_ERROR      The source could not be cleared.
> +  @retval EFI_INVALID_PARAMETER The service did not support the Periodic
> input argument.
> +
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *PEI_SMM_DEACTIVATE) (
> +  IN EFI_PEI_SERVICES                      **PeiServices,
> +  IN PEI_SMM_CONTROL_PPI                   * This,
> +  IN BOOLEAN                               Periodic OPTIONAL
> +  );
> +
> +///
> +///  PEI SMM Control PPI is used to initiate SMI/PMI activations. This protocol
> could be published by either:
> +///  - A processor driver to abstract the SMI/PMI IPI
> +///  - The driver that abstracts the ASIC that is supporting the APM port, such
> as the ICH in an
> +///  Intel chipset
> +///
> +struct _PEI_SMM_CONTROL_PPI {
> +  PEI_SMM_ACTIVATE    Trigger;
> +  PEI_SMM_DEACTIVATE  Clear;
> +};
> +
> +extern EFI_GUID gPeiSmmControlPpiGuid;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/P
> rotocol/SmmVariable.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/P
> rotocol/SmmVariable.h
> new file mode 100644
> index 0000000000..4aaa715d77
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/P
> rotocol/SmmVariable.h
> @@ -0,0 +1,33 @@
> +/** @file
> +  EFI SMM Variable Protocol is related to EDK II-specific implementation of
> variables
> +  and intended for use as a means to store data in the EFI SMM environment.
> +
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef __SMM_VARIABLE_H__
> +#define __SMM_VARIABLE_H__
> +
> +#define EFI_SMM_VARIABLE_PROTOCOL_GUID \
> +  { \
> +    0xed32d533, 0x99e6, 0x4209, { 0x9c, 0xc0, 0x2d, 0x72, 0xcd, 0xd9, 0x98,
> 0xa7 } \
> +  }
> +
> +typedef struct _EFI_SMM_VARIABLE_PROTOCOL
> EFI_SMM_VARIABLE_PROTOCOL;
> +
> +///
> +/// EFI SMM Variable Protocol is intended for use as a means
> +/// to store data in the EFI SMM environment.
> +///
> +struct _EFI_SMM_VARIABLE_PROTOCOL {
> +  EFI_GET_VARIABLE            SmmGetVariable;
> +  EFI_GET_NEXT_VARIABLE_NAME  SmmGetNextVariableName;
> +  EFI_SET_VARIABLE            SmmSetVariable;
> +  EFI_QUERY_VARIABLE_INFO     SmmQueryVariableInfo;
> +};
> +
> +extern EFI_GUID gEfiSmmVariableProtocolGuid;
> +
> +#endif
> --
> 2.16.2.windows.1


  parent reply	other threads:[~2019-08-17  1:16 UTC|newest]

Thread overview: 121+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-17  0:15 [edk2-platforms][PATCH V1 00/37] Coffee Lake and Whiskey Lake support Kubacki, Michael A
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and Include headers Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:08   ` Chiu, Chasel
2019-08-17  1:18   ` Chaganty, Rangasai V
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add " Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:08   ` Chiu, Chasel
2019-08-17  6:58   ` Chaganty, Rangasai V
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: " Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:08   ` Chiu, Chasel
2019-08-17  7:04   ` Chaganty, Rangasai V
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add include headers Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:08   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add ConfigBlock headers Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:09   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add Library include headers Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:09   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI and Protocol " Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:09   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 08/37] CoffeelakeSiliconPkg/Pch: Add Register " Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:09   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add Private " Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:12   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add Private/Library " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:09   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol " Kubacki, Michael A
2019-08-17  0:51   ` Nate DeSimone
2019-08-17  1:10   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode: Add Include headers Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:12   ` Chiu, Chasel [this message]
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 13/37] CoffeelakeSiliconPkg/SystemAgent: " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:12   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 14/37] CoffeelakeSiliconPkg: Add package common library instances Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:12   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:15   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 16/37] CoffeelakeSiliconPkg/Me: " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:12   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 17/37] CoffeelakeSiliconPkg/Pch: Add Base " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:13   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 18/37] CoffeelakeSiliconPkg/Pch: Add DXE " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:13   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 19/37] CoffeelakeSiliconPkg/Pch: Add PEI " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:13   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 20/37] CoffeelakeSiliconPkg/Pch: Add SMM " Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:16   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 21/37] CoffeelakeSiliconPkg/Pch: Add Base " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:13   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 22/37] CoffeelakeSiliconPkg/Pch: Add DXE private " Kubacki, Michael A
2019-08-17  0:52   ` Nate DeSimone
2019-08-17  1:13   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 23/37] CoffeelakeSiliconPkg/Pch: Add PEI " Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:14   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 24/37] CoffeelakeSiliconPkg/Pch: Add SMM " Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:14   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 25/37] CoffeelakeSiliconPkg/SystemAgent: Add " Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:14   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 26/37] CoffeelakeSiliconPkg/Pch: Add modules Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:14   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 27/37] CoffeelakeSiliconPkg/Pch: Add PchSmiDispatcher Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:15   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 28/37] CoffeelakeSiliconPkg/SystemAgent: Add modules Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:15   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package DSC files Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:14   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 30/37] Maintainers.txt: Add CoffeelakeSiliconPkg maintainers Kubacki, Michael A
2019-08-17  0:53   ` Nate DeSimone
2019-08-17  1:15   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 31/37] WhiskeylakeOpenBoardPkg: Add package and headers Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:16   ` Chiu, Chasel
2019-08-19 18:09   ` Sinha, Ankit
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 32/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:16   ` Chiu, Chasel
2019-08-17  0:15 ` [edk2-platforms][PATCH V1 33/37] WhiskeylakeOpenBoardPkg: Add library instances Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:16   ` Chiu, Chasel
2019-08-17  0:16 ` [edk2-platforms][PATCH V1 34/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: " Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:17   ` Chiu, Chasel
2019-08-17 20:08   ` Chaganty, Rangasai V
2019-08-17  0:16 ` [edk2-platforms][PATCH V1 35/37] WhiskeylakeOpenBoardPkg: Add modules Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:17   ` Chiu, Chasel
2019-08-17  7:50   ` Chaganty, Rangasai V
2019-08-17  0:16 ` [edk2-platforms][PATCH V1 36/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:16   ` Chiu, Chasel
2019-08-17 20:11   ` Chaganty, Rangasai V
2019-08-17  0:16 ` [edk2-platforms][PATCH V1 37/37] Add WhiskeylakeOpenBoardPkg to global build config and documentation Kubacki, Michael A
2019-08-17  0:54   ` Nate DeSimone
2019-08-17  1:17   ` Chiu, Chasel
2019-08-17 20:00   ` Chaganty, Rangasai V
2019-08-19 18:14 ` [edk2-platforms][PATCH V1 00/37] Coffee Lake and Whiskey Lake support Sinha, Ankit

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