From: "Chiu, Chasel" <chasel.chiu@intel.com>
To: "Kubacki, Michael A" <michael.a.kubacki@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>,
"Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>,
"Gao, Liming" <liming.gao@intel.com>,
"Kinney, Michael D" <michael.d.kinney@intel.com>,
"Sinha, Ankit" <ankit.sinha@intel.com>
Subject: Re: [edk2-platforms][PATCH V1 13/37] CoffeelakeSiliconPkg/SystemAgent: Add Include headers
Date: Sat, 17 Aug 2019 01:12:46 +0000 [thread overview]
Message-ID: <3C3EFB470A303B4AB093197B6777CCEC50462308@PGSMSX111.gar.corp.intel.com> (raw)
In-Reply-To: <20190817001603.30632-14-michael.a.kubacki@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>;
> Kinney, Michael D <michael.d.kinney@intel.com>; Sinha, Ankit
> <ankit.sinha@intel.com>
> Subject: [edk2-platforms][PATCH V1 13/37] CoffeelakeSiliconPkg/SystemAgent:
> Add Include headers
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2082
>
> Adds header files common to System Agent (SA) modules.
>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
> ---
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/GnaCo
> nfig.h | 33 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphic
> sDxeConfig.h | 53 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphic
> sPeiConfig.h | 96 ++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphic
> sPeiPreMemConfig.h | 70 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/IpuPre
> MemConfig.h | 46 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Memor
> yConfig.h | 534 ++++++++++++++++++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Memor
> yDxeConfig.h | 61 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/MiscDx
> eConfig.h | 33 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/OverCl
> ockingConfig.h | 51 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieDxe
> Config.h | 135 +++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PciePei
> Config.h | 60 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PciePei
> PreMemConfig.h | 354 +++++++++++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMisc
> PeiConfig.h | 61 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMisc
> PeiPreMemConfig.h | 103 ++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Switcha
> bleGraphicsConfig.h | 63 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/VbiosD
> xeConfig.h | 39 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/VtdCon
> fig.h | 42 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/DmaRemappingTabl
> e.h | 77 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/DxeSaPolicyL
> ib.h | 60 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolicyLi
> b.h | 87 ++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/SaPlatformLi
> b.h | 88 ++++
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/MemInfoHob.h
> | 259 ++++++++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Gra
> phicsInitLib.h | 15 +
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Lega
> cyRegion.h | 33 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/PeiC
> puTraceHubLib.h | 23 +
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/SaPc
> ieLib.h | 70 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protocol/SaI
> otrapSmi.h | 36 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protocol/Sa
> NvsArea.h | 31 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaConfigHo
> b.h | 89 ++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaNvsAreaD
> ef.h | 151 ++++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopComp
> onentName2.h | 63 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopPolicy.
> h | 73 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/IgdOpRegi
> on.h | 24 +
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/MemInfo.h
> | 132 +++++
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h
> | 66 +++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsGna
> .h | 32 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHos
> tBridge.h | 214 ++++++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsIgd.
> h | 50 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsIpu.
> h | 37 ++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsPeg.
> h | 64 +++
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaAccess.h
> | 106 ++++
>
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaCommonDefinitio
> ns.h | 23 +
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPciExpressLib.h
> | 25 +
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPolicyCommon.h
> | 51 ++
> Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaRegs.h
> | 32 ++
> 45 files changed, 3845 insertions(+)
>
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/GnaC
> onfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/GnaC
> onfig.h
> new file mode 100644
> index 0000000000..020a4aeab5
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/GnaC
> onfig.h
> @@ -0,0 +1,33 @@
> +/** @file
> + Policy definition for GNA Config Block
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _GNA_CONFIG_H_
> +#define _GNA_CONFIG_H_
> +#pragma pack(push, 1)
> +
> +#define GNA_CONFIG_REVISION 1
> +/**
> + GNA config block for configuring GNA.\n
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27
> Config Block Header
> + /**
> + Offset 28:0
> + This policy enables the GNA Device (SA Device 8) if supported.
> + If FALSE, all other policies in this config block will be ignored.
> + <b>1=TRUE</b>;
> + 0=FALSE.
> + **/
> + UINT32 GnaEnable : 1;
> + UINT32 RsvdBits0 : 31; ///< Offset 28:1 :Reserved for future
> use
> +} GNA_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _GNA_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Grap
> hicsDxeConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Grap
> hicsDxeConfig.h
> new file mode 100644
> index 0000000000..cc337a83f3
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Grap
> hicsDxeConfig.h
> @@ -0,0 +1,53 @@
> +/** @file
> + Graphics DXE Policy definitions
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _GRAPHICS_DXE_CONFIG_H_
> +#define _GRAPHICS_DXE_CONFIG_H_
> +
> +#pragma pack(push, 1)
> +
> +#define GRAPHICS_DXE_CONFIG_REVISION 2
> +
> +#define MAX_BCLM_ENTRIES 20
> +
> +/**
> + This configuration block is to configure IGD related variables used in DXE.
> + If Intel Gfx Device is not supported or disabled, all policies will be ignored.
> + The data elements should be initialized by a Platform Module.\n
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Adding BCLM[MAX_BCLM_ENTRIES]
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config
> Block Header
> + UINT32 Size; ///< Offset 28 - 31: This field gives the
> size of the GOP VBT Data buffer
> + EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: This
> field points to the GOP VBT data buffer
> + UINT8 PlatformConfig; ///< Offset 40: This field gives the
> Platform Configuration Information (0=Platform is S0ix Capable for ULT SKUs
> only, <b>1=Platform is not S0ix Capable</b>, 2=Force Platform is S0ix Capable
> for All SKUs)
> + UINT8 AlsEnable; ///< Offset 41: Ambient Light
> Sensor Enable: <b>0=Disable</b>, 2=Enable
> + UINT8 BacklightControlSupport; ///< Offset 42: Backlight
> Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
> + UINT8 IgdBootType; ///< Offset 43: IGD Boot Type
> CMOS option: <b>0=Default</b>, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3,
> 0x40=EFP2, 0x80=LFP2
> + UINT32 IuerStatusVal; ///< Offset 44 - 47: Offset 16 This
> field holds the current status of all the supported Ultrabook events (Intel(R)
> Ultrabook Event Status bits)
> + CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This field
> holds the GOP Driver Version. It is an Output Protocol and updated by the
> Silicon code
> + /**
> + Offset 80: IGD Panel Type CMOS option\n
> + <b>0=Default</b>, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS,
> 4=1280X1024LVDS, 5=1400X1050LVDS1\n
> + 6=1400X1050LVDS2, 7=1600X1200LVDS, 8=1280X768LVDS,
> 9=1680X1050LVDS, 10=1920X1200LVDS, 13=1600X900LVDS\n
> + 14=1280X800LVDS, 15=1280X600LVDS, 16=2048X1536LVDS,
> 17=1366X768LVDS
> + **/
> + UINT8 IgdPanelType;
> + UINT8 IgdPanelScaling; ///< Offset 81: IGD Panel Scaling:
> <b>0=AUTO</b>, 1=OFF, 6=Force scaling
> + UINT8 IgdBlcConfig; ///< Offset 82: Backlight Control
> Support: 0=PWM Inverted, <b>2=PWM Normal</b>
> + UINT8 IgdDvmtMemSize; ///< Offset 83: IGD DVMT
> Memory Size: 1=128MB, <b>2=256MB</b>, 3=MAX
> + UINT8 GfxTurboIMON; ///< Offset 84: IMON Current
> Value: 14=Minimal, <b>31=Maximum</b>
> + UINT8 Reserved[3]; ///< Offset 85: Reserved for
> DWORD alignment.
> + UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD
> Backlight Brightness Level Duty cycle Mapping Table.
> +} GRAPHICS_DXE_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _GRAPHICS_DXE_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Grap
> hicsPeiConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Grap
> hicsPeiConfig.h
> new file mode 100644
> index 0000000000..276289ae81
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Grap
> hicsPeiConfig.h
> @@ -0,0 +1,96 @@
> +/** @file
> + Policy definition for Internal Graphics Config Block (PostMem)
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _GRAPHICS_PEI_CONFIG_H_
> +#define _GRAPHICS_PEI_CONFIG_H_
> +#pragma pack(push, 1)
> +
> +#define GRAPHICS_PEI_CONFIG_REVISION 4
> +#define DDI_DEVICE_NUMBER 4
> +
> +//
> +// DDI defines
> +//
> +typedef enum {
> + DdiDisable = 0x00,
> + DdiDdcEnable = 0x01,
> + DdiTbtLsxEnable = 0x02,
> +} DDI_DDC_TBT_VAL;
> +
> +typedef enum {
> + DdiHpdDisable = 0x00,
> + DdiHpdEnable = 0x01,
> +} DDI_HPD_VAL;
> +
> +typedef enum {
> + DdiPortADisabled = 0x00,
> + DdiPortAEdp = 0x01,
> + DdiPortAMipiDsi = 0x02,
> +} DDI_PORTA_SETTINGS;
> +/**
> + This structure configures the Native GPIOs for DDI port per VBT settings.
> +**/
> +typedef struct {
> + UINT8 DdiPortEdp; /// The setting of eDP port, this settings must match
> VBT's settings. 0- Disable, <b>1- Enable</b>
> + UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings must
> match VBT's settings. 0- Disable, <b>1- Enable</b>
> + UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings must
> match VBT's settings. 0- Disable, <b>1- Enable</b>
> + UINT8 DdiPortDHpd; /// The HPD setting of DDI Port D, this settings must
> match VBT's settings. 0- Disable, <b>1- Enable</b>
> + UINT8 DdiPortFHpd; /// The HPD setting of DDI Port F, this settings must
> match VBT's settings. 0- Disable, <b>1- Enable</b>
> + UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings must
> match VBT's settings. 0- Disable, <b>1- Enable</b>
> + UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings must
> match VBT's settings. 0- Disable, <b>1- Enable</b>
> + UINT8 DdiPortDDdc; /// The DDC setting of DDI Port D, this settings must
> match VBT's settings. 0- Disable, <b>1- Enable</b>
> + UINT8 DdiPortFDdc; /// The DDC setting of DDI Port F, this settings must
> match VBT's settings. <b>0- Disable</b>, 1- Enable
> + UINT8 Rsvd[3]; ///< Reserved for 4 bytes alignment
> +} DDI_CONFIGURATION;
> +
> +/**
> + This configuration block is to configure IGD related variables used in
> PostMem PEI.
> + If Intel Gfx Device is not supported, all policies can be ignored.
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Added SkipS3CdClockInit.
> + <b>Revision 3</b>:
> + - Added DeltaT12PowerCycleDelay, BltBufferAddress, BltBufferSize.
> + <b>Revision 4</b>:
> + - Deprecated DeltaT12PowerCycleDelay.
> +
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config
> Block Header
> + UINT32 RenderStandby : 1; ///< Offset 28:0 :<b>(Test)</b>
> This field is used to enable or disable RC6 (Render Standby): 0=FALSE,
> <b>1=TRUE</b>
> + UINT32 PmSupport : 1; ///< Offset 28:1 :<b>(Test)</b>
> IGD PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
> + UINT32 PavpEnable : 1; ///< Offset 28:2 :IGD PAVP
> TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
> + /**
> + Offset 28:3
> + CdClock Frequency select\n
> + CFL\n
> + 0 = 337.5 Mhz, 1 = 450 Mhz,\n
> + 2 = 540 Mhz,<b> 3 = 675 Mhz</b>,\n
> +
> + **/
> + UINT32 CdClock : 3;
> + UINT32 PeiGraphicsPeimInit: 1; ///< Offset 28:6 : This policy is
> used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
> + UINT32 CdynmaxClampEnable : 1; ///< Offset 28:7 : This policy
> is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>,
> 0- Disable
> + UINT32 GtFreqMax : 8; ///< Offset 28:8 : <b>(Test)</b>
> Max GT frequency limited by user in multiples of 50MHz: Default value which
> indicates normal frequency is <b>0xFF</b>
> + UINT32 DisableTurboGt : 1; ///< Offset 28:9 : This policy is
> used to enable/disable DisableTurboGt <b>0- Disable</b>, 1- Enable
> + UINT32 RsvdBits0 : 15; ///< Offser 28:15 :Reserved for
> future use
> + VOID* LogoPtr; ///< Offset 32 Address of Intel Gfx
> PEIM Logo to be displayed
> + UINT32 LogoSize; ///< Offset 36 Intel Gfx PEIM Logo
> Size
> + VOID* GraphicsConfigPtr; ///< Offset 40 Address of the
> Graphics Configuration Table
> + DDI_CONFIGURATION DdiConfiguration; ///< Offset 44 DDI
> configuration, need to match with VBT settings.
> + UINT32 SkipS3CdClockInit : 1; ///< Offset 56 SKip full CD clock
> initialization being done during S3 resume.<b>0- Disable<\b>, 1- Enable
> + UINT32 ReservedBits : 31; ///< Offset 56: 1 : Reserved for
> future use.
> + UINT16 DeltaT12PowerCycleDelay; ///< Offset 60 @deprecated
> Power Cycle Delay required for eDP as per VESA standard.<b>0 - 0 ms<\b>,
> 0xFFFF - Auto calculate to max 500 ms
> + UINT8 Reserved[2]; ///< Offset 62 Reserved for future
> use.
> + VOID* BltBufferAddress; ///< Offset 64 Address of Blt
> buffer for PEIM Logo use
> + UINT32 BltBufferSize; ///< Offset 68 The size for Blt
> Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of
> EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
> +} GRAPHICS_PEI_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _GRAPHICS_PEI_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Grap
> hicsPeiPreMemConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Grap
> hicsPeiPreMemConfig.h
> new file mode 100644
> index 0000000000..4986fdab60
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Grap
> hicsPeiPreMemConfig.h
> @@ -0,0 +1,70 @@
> +/** @file
> + Policy definition for Internal Graphics Config Block (PreMem)
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _GRAPHICS_PEI_PREMEM_CONFIG_H_
> +#define _GRAPHICS_PEI_PREMEM_CONFIG_H_
> +#pragma pack(push, 1)
> +
> +#define GRAPHICS_PEI_PREMEM_CONFIG_REVISION 2
> +
> +
> +/**
> + This Configuration block is to configure GT related PreMem
> data/variables.\n
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Added DeltaT12PowerCycleDelayPreMem.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config
> Block Header
> + /**
> + Offset 28:0
> + Selection of the primary display device: 0=iGFX, 1=PEG, 2=PCIe Graphics on
> PCH, <b>3=AUTO</b>, 4=Switchable Graphics\n
> + When AUTO mode selected, the priority of display devices is: PCIe Graphics
> on PCH > PEG > iGFX
> + **/
> + UINT32 PrimaryDisplay : 3;
> + /**
> + Offset 28:3
> + Intel Gfx Support. It controls enabling/disabling iGfx device.
> + When AUTO mode selected, iGFX will be turned off when external graphics
> detected.
> + If FALSE, all other polices can be ignored.
> + <b>2 = AUTO</b>;
> + 0 = FALSE;
> + 1 = TRUE.
> + **/
> + UINT32 InternalGraphics : 2;
> + /**
> + Offset 28:5
> + Pre-allocated memory for iGFX\n
> + 0 = 0MB,1 or 247 = 32MB,\n
> + 2 = 64MB,\n
> + 240 = 4MB, 241 = 8MB,\n
> + 242 = 12MB, 243 = 16MB,\n
> + 244 = 20MB, 245 = 24MB,\n
> + 246 = 28MB, 248 = 36MB,\n
> + 249 = 40MB, 250 = 44MB,\n
> + 251 = 48MB, 252 = 52MB,\n
> + 253 = 56MB,<b> 254 = 60MB</b>,\n
> + <b>Note: enlarging pre-allocated memory for iGFX may need to reduce
> MmioSize because of 4GB boundary limitation</b>
> + **/
> + UINT32 IgdDvmt50PreAlloc : 8;
> + UINT32 PanelPowerEnable : 1; ///< Offset
> 28:13 :<b>(Test)</b> Control for enabling/disabling VDD force bit (Required
> only for early enabling of eDP panel): 0=FALSE, <b>1=TRUE</b>
> + UINT32 ApertureSize : 7; ///< Offser 28:14 :Graphics
> aperture size (256MB is the recommended size as per BWG) : 0=128MB,
> <b>1=256MB</b>, 3=512MB, 7=1024MB, 15=2048MB.
> + UINT32 GtPsmiSupport : 1; ///< Offser 28:21 :PSMI
> support On/Off: <b>0=FALSE</b>, 1=TRUE
> + UINT32 PsmiRegionSize : 3; ///< Offser 28:22 :Psmi
> region size: <b>0=32MB</b>, 1=288MB, 2=544MB, 3=800MB, 4=1056MB
> + UINT32 RsvdBits0 : 7; ///< Offser 28:25 :Reserved
> for future use
> + UINT32 GttMmAdr; ///< Offset 32 Temp Address
> of System Agent GTTMMADR : Default is <b>0xCF000000< / b>
> + UINT16 GttSize; ///< Offset 36 Selection of iGFX
> GTT Memory size: 1=2MB, 2=4MB, <b>3=8MB</b>
> + UINT8 Rsvd1[2]; ///< Offset 38 Reserved for
> DWORD alignment
> + UINT32 GmAdr; ///< Offset 40 Temp Address
> of System Agent GMADR : Default is <b>0xD0000000< / b>
> + UINT16 DeltaT12PowerCycleDelayPreMem; ///< Offset 44
> Power Cycle Delay required for eDP as per VESA standard.<b>0 - 0 ms<\b>,
> 0xFFFF - Auto calculate to max 500 ms
> + UINT8 Reserved[2]; ///< Offset 46 Reserved for
> future use.
> +} GRAPHICS_PEI_PREMEM_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _GRAPHICS_PEI_PREMEM_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/IpuPr
> eMemConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/IpuPr
> eMemConfig.h
> new file mode 100644
> index 0000000000..79025d16fe
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/IpuPr
> eMemConfig.h
> @@ -0,0 +1,46 @@
> +/** @file
> + IPU policy definitions (PreMem)
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _IPU_CONFIG_PREMEM_H_
> +#define _IPU_CONFIG_PREMEM_H_
> +
> +#pragma pack(push, 1)
> +
> +#define IPU_PREMEM_CONFIG_REVISION 1
> +
> +#define SA_IMR_IPU_CAMERA 0
> +#define SA_IMR_IPU_GEN 1
> +
> +/**
> + IPU PreMem configuration\n
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
> Header
> + /**
> + Offset 28:0 :
> + <b>(Test)</b> It enables the SA IPU Device if supported and not fused off.
> + If FALSE, all other policies in this config block will be ignored.
> + <b>1=TRUE</b>;
> + 0=FALSE.
> + **/
> + UINT32 SaIpuEnable:1;
> + /**
> + Offset 28:1 :
> + <b>(Test)</b> It configure the IPU IMR to IPU Camera or IPU Gen when IPU
> is enabled.
> + If FALSE, all other policies in this config block will be ignored.
> + <b>0=IPU Camera</b>;
> + 1=IPU Gen
> + **/
> + UINT32 SaIpuImrConfiguration:1;
> + UINT32 RsvdBits0:30; /// Offset 28:2 :Reserved for future
> use.
> +} IPU_PREMEM_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _IPU_PREMEM_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Mem
> oryConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Mem
> oryConfig.h
> new file mode 100644
> index 0000000000..8374ff5f68
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Mem
> oryConfig.h
> @@ -0,0 +1,534 @@
> +/** @file
> + Policy definition of Memory Config Block
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _MEMORY_CONFIG_H_
> +#define _MEMORY_CONFIG_H_
> +
> +#include <SaRegs.h>
> +
> +#pragma pack(push, 1)
> +
> +#define SA_MRC_ITERATION_MAX (6)
> +#define SA_MRC_MAX_RCOMP (3)
> +#define SA_MRC_MAX_RCOMP_TARGETS (5)
> +
> +#define MEMORY_CONFIG_REVISION 3
> +
> +///
> +/// SMRAM Memory Range
> +///
> +#define PEI_MR_SMRAM_ABSEG_MASK 0x01
> +#define PEI_MR_SMRAM_HSEG_MASK 0x02
> +
> +///
> +/// SA SPD profile selections.
> +///
> +typedef enum {
> + Default, ///< 0, Default SPD
> + UserDefined, ///< 1, User Defined profile
> + XMPProfile1, ///< 2, XMP Profile 1
> + XMPProfile2, ///< 3, XMP Profile 2
> + XMPProfileMax = 0xFF ///< Ensures SA_SPD is UINT8
> +} SA_SPD;
> +
> +///
> +/// Define the boot modes used by the SPD read function.
> +///
> +typedef enum {
> + SpdCold, ///< Cold boot
> + SpdWarm, ///< Warm boot
> + SpdS3, ///< S3 resume
> + SpdFast, ///< Fast boot
> + SpdBootModeMax ///< Delimiter
> +} SPD_BOOT_MODE;
> +
> +typedef struct {
> + UINT8
> SpdData[SA_MC_MAX_CHANNELS][SA_MC_MAX_SLOTS][SA_MC_MAX_SPD_S
> IZE];
> +//Next Field Offset 2048
> +} SPD_DATA_BUFFER;
> +
> +typedef struct {
> + UINT8
> DqByteMap[SA_MC_MAX_CHANNELS][SA_MRC_ITERATION_MAX][2];
> +//Next Field Offset 24
> +} SA_MEMORY_DQ_MAPPING;
> +
> +typedef struct {
> + UINT8
> DqsMapCpu2Dram[SA_MC_MAX_CHANNELS][SA_MC_MAX_BYTES_NO_ECC];
> +//Next Field Offset 16
> +} SA_MEMORY_DQS_MAPPING;
> +
> +typedef struct {
> + UINT16 RcompResistor[SA_MRC_MAX_RCOMP]; ///< Offset 0:
> Reference RCOMP resistors on motherboard
> + UINT16 RcompTarget[SA_MRC_MAX_RCOMP_TARGETS]; ///< Offset 6:
> RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv
> +//Next Field Offset 16
> +} SA_MEMORY_RCOMP;
> +
> +typedef struct {
> + UINT16 Start; ///< Offset 0
> + UINT16 End; ///< Offset 2
> + UINT8 BootMode; ///< Offset 4
> + UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use
> +} SPD_OFFSET_TABLE;
> +
> +///
> +/// SA memory address decode.
> +///
> +typedef struct
> +{
> + UINT8 Controller; ///< Offset 0 Zero based Controller number
> + UINT8 Channel; ///< Offset 1 Zero based Channel number
> + UINT8 Dimm; ///< Offset 2 Zero based DIMM number
> + UINT8 Rank; ///< Offset 3 Zero based Rank number
> + UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number
> + UINT8 Bank; ///< Offset 5 Zero based Bank number
> + UINT16 Cas; ///< Offset 6 Zero based CAS number
> + UINT32 Ras; ///< Offset 8 Zero based RAS number
> +} SA_ADDRESS_DECODE;
> +
> +typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress);
> +typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress);
> +typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress);
> +typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress,
> UINT8 Value);
> +typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress,
> UINT16 Value);
> +typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress,
> UINT32 Value);
> +typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address);
> +typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address);
> +typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address);
> +typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address);
> +typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address,
> UINT8 Value);
> +typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address,
> UINT16 Value);
> +typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address,
> UINT32 Value);
> +typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address,
> UINT64 Value);
> +typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address,
> RETURN_STATUS *Status);
> +typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address,
> RETURN_STATUS *Status);
> +typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address,
> UINT8 Value, RETURN_STATUS *Status);
> +typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address,
> UINT16 Value, RETURN_STATUS *Status);
> +typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus,
> UINT8 Device, UINT8 Function, UINT8 Offset);
> +typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus,
> UINT8 Device, UINT8 Function, UINT8 Offset);
> +typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second,
> UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year);
> +typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID
> *GlobalData);
> +typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destination,
> CONST VOID *Source, UINTN NumBytes);
> +typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer,
> UINTN NumBytes, UINT8 Value);
> +typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer,
> UINTN NumWords, UINT16 Value);
> +typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer,
> UINTN NumDwords, UINT32 Value);
> +typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UINTN
> NumBits);
> +typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data,
> UINTN NumBits);
> +typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64
> Multiplicand, UINT32 Multiplier);
> +typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend,
> UINT64 Divisor, UINT64 *Remainder);
> +typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA)
> (SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8
> *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize,
> UINT8 *LpddrTable, UINT32 LpddrTableSize);
> +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64
> Address, SA_ADDRESS_DECODE *DramAddress);
> +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE)
> (SA_ADDRESS_DECODE *DramAddress, UINT64 Address);
> +typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32
> *Rand);
> +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type,
> UINT32 Command, UINT32 *Value, UINT32 *Status);
> +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type,
> UINT32 Command, UINT32 Value, UINT32 *Status);
> +typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID
> *GlobalData, UINT32 DefaultVdd);
> +typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID
> *GlobalData, UINT32 DefaultVdd, UINT32 Value);
> +typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData,
> UINT32 CheckPoint, VOID *Scratch);
> +typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData,
> UINT16 DisplayDebugNumber);
> +typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs,
> UINT8 Channel);
> +typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UINT32
> Level, char *Format, ...);
> +typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String);
> +typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID
> *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast,
> UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData,
> UINT8 SkipWait, UINT32 RegFileParam);
> +typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UINT8
> OldMsb, UINT8 NewMsb);
> +typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID
> *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8
> GroupMask, INT32 NewValue, UINT8 UpdateHost);
> +typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData,
> UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32
> Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait);
> +typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location);
> +typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location);
> +typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location,
> UINT64 Data);
> +typedef UINT32 (EFIAPI * SA_THERMAL_OVERRIDES) (VOID
> *GlobalData);
> +typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID
> *GlobalData, UINT32 MrcStatus);
> +typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32
> PciEBaseAddress, UINT32 ResetValue);
> +typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT32
> PrmrrBaseAddress, UINT32 PrmrrSize);
> +
> +
> +///
> +/// Function calls into the SA.
> +///
> +typedef struct {
> + SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU I/O port
> 8-bit read.
> + SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU I/O port
> 16-bit read.
> + SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU I/O port
> 32-bit read.
> + SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU I/O port
> 8-bit write.
> + SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU I/O
> port 16-bit write.
> + SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU I/O
> port 32-bit write.
> + SA_MMIO_READ_8 MmioRead8; ///< Offset 24: -
> Memory Mapped I/O port 8-bit read.
> + SA_MMIO_READ_16 MmioRead16; ///< Offset 28: -
> Memory Mapped I/O port 16-bit read.
> + SA_MMIO_READ_32 MmioRead32; ///< Offset 32: -
> Memory Mapped I/O port 32-bit read.
> + SA_MMIO_READ_64 MmioRead64; ///< Offset 36: -
> Memory Mapped I/O port 64-bit read.
> + SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: -
> Memory Mapped I/O port 8-bit write.
> + SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: -
> Memory Mapped I/O port 16-bit write.
> + SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: -
> Memory Mapped I/O port 32-bit write.
> + SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: -
> Memory Mapped I/O port 64-bit write.
> + SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smbus
> 8-bit read.
> + SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: -
> Smbus 16-bit read.
> + SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smbus
> 8-bit write.
> + SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: -
> Smbus 16-bit write.
> + SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: -
> Get PCI device address.
> + SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: -
> Get PCI express device address.
> + SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get the
> current time value.
> + SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The
> current CPU time in milliseconds.
> + SA_MEMORY_COPY CopyMem; ///< Offset 88: -
> Perform byte copy operation.
> + SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: -
> Perform byte initialization operation.
> + SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: -
> Perform word initialization operation.
> + SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: -
> Perform dword initialization operation.
> + SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Left shift the
> 64-bit data value by specified number of bits.
> + SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Right shift
> the 64-bit data value by specified number of bits.
> + SA_MULT_U64_U32 MultU64x32; ///< Offset 112: -
> Multiply a 64-bit data value by a 32-bit data value.
> + SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Divide a
> 64-bit data value by a 64-bit data value.
> + SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Read the
> SPD data over the SMBus, at the given SmBus SPD address and copy the data
> to the data structure.
> + SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124:
> - Get the next random 32-bit number.
> + SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: -
> Perform a CPU mailbox read.
> + SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: -
> Perform a CPU mailbox write.
> + SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: -
> Get the current memory voltage (VDD).
> + SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set
> the memory voltage (VDD) to the given value.
> + SA_CHECKPOINT CheckPoint; ///< Offset 144: - Check
> point that is called at various points in the MRC.
> + SA_DEBUG_HOOK DebugHook; ///< Offset 148: -
> Typically used to display to the I/O port 80h.
> + SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Output a
> string to the debug stream/device.
> + SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get the
> current value of the specified RTC CMOS location.
> + SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get the
> current value of the specified MSR location.
> + SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set the
> current value of the specified MSR location.
> + SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168
> - Hook function after returning from MrcStartMemoryConfiguration()
> + SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 -
> Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
> +} SA_FUNCTION_CALLS;
> +
> +///
> +/// Function calls into the MRC.
> +///
> +typedef struct {
> + SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Returns
> whether Channel is or is not present.
> + SA_PRINTF MrcPrintf; ///< Offset 4: - Print to output
> stream/device.
> + SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: -
> Change the margin.
> + SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign
> extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
> + SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: -
> Move CMD/CTL/CLK/CKE PIs during training.
> + SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Update
> the Vref value and wait until it is stable.
> +} SA_MEMORY_FUNCTIONS;
> +
> +/**
> + Memory Configuration
> + The contents of this structure are CRC'd by the MRC for option change
> detection.
> + This structure is copied en mass to the MrcInput structure. If you add fields
> here, you must update the MrcInput structure.
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Removed GearType.
> + - Added Lp4DqsOscEn, RMTLoopCount, EnBER,
> DualDimmPerChannelBoardType.
> + <b>Revision 3</b>:
> + - Removed EvLoader, EvLoaderDelay.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
> + UINT16 Size; ///< Offset 28 The size of this structure, in bytes.
> Must be the first entry in this structure.
> + UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MRC
> +
> + UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection - for
> XMP supported DIMM: <b>0=Default DIMM profile</b>, 1=Customized profile,
> 2=XMP profile 1, 3=XMP profile 2.
> +
> + // The following parameters are used only when SpdProfileSelected is
> UserDefined (CUSTOM PROFILE)
> + UINT16 tCL; ///< Offset 32 User defined Memory Timing tCL
> value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>,
> 31=Maximum.
> + UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timing
> tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 63=Maximum
> + UINT16 tRAS; ///< Offset 36 User defined Memory Timing
> tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 64=Maximum.
> + UINT16 tWR; ///< Offset 38 User defined Memory Timing
> tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.
> + UINT16 tRFC; ///< Offset 40 User defined Memory Timing
> tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 1023=Maximum.
> + UINT16 tRRD; ///< Offset 42 User defined Memory Timing
> tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 15=Maximum.
> + UINT16 tWTR; ///< Offset 44 User defined Memory Timing
> tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 28=Maximum.
> + UINT16 tRTP; ///< Offset 46 User defined Memory Timing
> tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 15=Maximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12
> + UINT16 tFAW; ///< Offset 48 User defined Memory Timing
> tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 63=Maximum.
> + UINT16 tCWL; ///< Offset 50 User defined Memory Timing
> tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 20=Maximum.
> + UINT16 tREFI; ///< Offset 52 User defined Memory Timing
> tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 65535=Maximum.
> + UINT16 PciIndex; ///< Offset 54 Pci index register address:
> <b>0xCF8=Default</b>
> + UINT16 PciData; ///< Offset 56 Pci data register address:
> <b>0xCFC=Default</b>
> + UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in
> millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V
> etc.
> + UINT16 Idd3n; ///< Offset 60 EPG Active standby current
> (Idd3N) in milliamps from DIMM datasheet.
> + UINT16 Idd3p; ///< Offset 62 EPG Active power-down current
> (Idd3P) in milliamps from DIMM datasheet.
> +
> + UINT32 EccSupport:1; ///< Offset 64 DIMM Ecc Support
> option - for Desktop only: 0=Disable, <b>1=Enable</b>
> + UINT32 MrcSafeConfig:1; ///< - MRC Safe Mode:
> <b>0=Disable</b>, 1=Enable
> + UINT32 RemapEnable:1; ///< - This option is used to control
> whether to enable/disable memory remap above 4GB: 0=Disable,
> <b>1=Enable</b>.
> + UINT32 ScramblerSupport:1; ///< - Memory scrambler support:
> 0=Disable, <b>1=Enable</b>
> + UINT32 Vc1ReadMeter:1; ///< - VC1 Read Metering Enable:
> 0=Disable, <b>1=Enable</b>
> + UINT32 DdrThermalSensor:1; ///< - Ddr Thermal Sensor:
> 0=Disable, <b>1=Enable</b>
> + UINT32 LpddrMemWriteLatencySet:1; ///< - LPDDR3 Write Latency Set
> option: 0=Set A, <b>1=Set B</b>
> + UINT32 Off64Bits7to8Rsvd:2; ///< - Bit 7-8 Reserved
> + UINT32 SimicsFlag:1; ///< - Option to Enable SIMICS:
> 0=Disable, <b>1=Enable</b>
> + UINT32 Ddr4DdpSharedClock:1; ///< - Select if CLK0 is shared
> between Rank0 and Rank1 in DDR4 DDP package. <b>0=Not shared</b>,
> 1=Shared
> + UINT32 SharedZqPin:1; ///< - Select if ZQ pin is shared
> between Rank ranks. For CFL, this option only works for DDR4. the option
> works for LPDDR4 and DDR4. <b>0=Not shared</b>, 1=Shared
> + // Thermal Management
> + UINT32 ThermalManagement:1; ///< - <CFL> Memory Thermal
> Management Support: <b>0=Disable</b>, 1=Enable.
> + UINT32 PeciInjectedTemp:1; ///< - <CFL> Enable/Disable
> memory temperatures to be injected to the processor via PECI:
> <b>0=Disable</b>, 1=Enable.
> + UINT32 ExttsViaTsOnBoard:1; ///< - <CFL> Enable/Disable routing
> TS-on-Board's ALERT# and THERM# to EXTTS# pins on the PCH:
> <b>0=Disable</b>, 1=Enable.
> + UINT32 ExttsViaTsOnDimm:1; ///< - <CFL> Enable/Disable
> routing TS-on-DIMM's ALERT# to EXTTS# pin on the PCH: <b>0=Disable</b>,
> 1=Enable.
> + UINT32 VirtualTempSensor:1; ///< - <CFL> Enable/Disable Virtual
> Temperature Sensor (VTS): <b>0=Disable</b>, 1=Enable.
> + UINT32 Lp4DqsOscEn :1; ///< - <CNL> LpDdrDqDqsReTraining -
> DqDqsReTraining Enable: 0=Disable, <b>1=Enable</b>
> + UINT32 DualDimmPerChannelBoardType:1; ///< - <CFL>
> DualDimmPerChannelBoardType - Option to indicate if the Memory Design for
> the board includes two DIMMs per channel: <b>0=Single DIMM Design</b>,
> 1=Dual DIMM Design
> + UINT32 ReservedBits1:13;
> + /**
> + Disables a DIMM slot in the channel even if a DIMM is present\n
> + Array index represents the channel number (0 = channel 0, 1 = channel 1)\n
> + <b>0x0 = DIMM 0 and DIMM 1 enabled</b>\n
> + 0x1 = DIMM 0 disabled, DIMM 1 enabled\n
> + 0x2 = DIMM 0 enabled, DIMM 1 disabled\n
> + 0x3 = DIMM 0 and DIMM 1 disabled (will disable the whole channel)\n
> + **/
> + UINT8 DisableDimmChannel[SA_MC_MAX_CHANNELS]; ///< Offset 68
> + /**
> + Selects the ratio to multiply the reference clock by for the DDR frequency\n
> + When RefClk is 133MHz\n
> + <b>0x00 = Auto</b>, 0x03 through 0x0C are valid values, all others are
> invalid\n
> + When RefClk is 100MHz\n
> + <b>0x00 = Auto</b>, 0x06 through 0x10 are valid values, all others are
> invalid\n
> + **/
> + UINT8 Ratio; ///< Offset 70
> + UINT8 ProbelessTrace; ///< Offset 71 Probeless Trace:
> <b>0=Disabled</b>, <b>1=Enabled</b>
> + UINT32 BClkFrequency; ///< Offset 72 Base reference clock value, in
> Hertz: <b>100000000 = 100Hz</b>, 125000000=125Hz, 167000000=167Hz,
> 250000000=250Hz
> + /**
> + - Channel Hash Enable.\n
> + NOTE: BIT7 will interleave the channels at a 2 cache-line granularity, BIT8
> at 4 and BIT9 at 8\n
> + 0=BIT6, <B>1=BIT7</B>, 2=BIT8, 3=BIT9
> + **/
> + UINT8 ChHashInterleaveBit; ///< Offset 76 Option to select interleave
> Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW are 0-7 for
> BITS 6 - 13)
> + UINT8 EnergyScaleFact; ///< Offset 77 Energy Scale Factor. 0=Minimal,
> 7=Maximum, <b>4=Default</b>
> + BOOLEAN PerBankRefresh; ///< <CNL> Offset 78 Enables and Disables
> the per bank refresh. This only impacts memory technologies that support
> PBR: LPDDR3, LPDDR4. FALSE=Disabled, <b>TRUE=Enabled</b>
> + UINT8 McLock; ///< <CFL> Offset 79 Enable/Disable memory
> configuration register locking: 0=Disable, <b>1=Enable</b>.
> + // Training Algorithms 1
> + UINT32 ECT:1; ///< Offset 80 Enable/Disable Early Command
> Training. Note it is not recommended to change this setting from the default
> value: <b>0=Disable</b>, 1=Enable.
> + UINT32 SOT:1; ///< - Enable/Disable Sense Amp Offset
> Training. Note it is not recommended to change this setting from the default
> value: 0=Disable, <b>1=Enable</b>.
> + UINT32 ERDMPRTC2D:1; ///< - Enable/Disable Early ReadMPR
> Timing Centering 2D. Note it is not recommended to change this setting from
> the default value: 0=Disable, <b>1=Enable</b>.
> + UINT32 RDMPRT:1; ///< - Enable/Disable Read MPR Training.
> Note it is not recommended to change this setting from the default value:
> 0=Disable, <b>1=Enable</b>.
> + UINT32 RCVET:1; ///< - Enable/Disable Receive Enable Training.
> Note it is not recommended to change this setting from the default value:
> 0=Disable, <b>1=Enable</b>.
> + UINT32 JWRL:1; ///< - Enable/Disable JEDEC Write Leveling
> Training. Note it is not recommended to change this setting from the default
> value: 0=Disable, <b>1=Enable</b>.
> + UINT32 EWRTC2D:1; ///< - Enable/Disable Early Write Time
> Centering 2D Training. Note it is not recommended to change this setting from
> the default value: 0=Disable, <b>1=Enable</b>.
> + UINT32 ERDTC2D:1; ///< - Enable/Disable Early Read Time
> Centering 2D Training. Note it is not recommended to change this setting from
> the default value: 0=Disable, <b>1=Enable</b>.
> + UINT32 WRTC1D:1; ///< - Enable/Disable 1D Write Timing
> Centering Training. Note it is not recommended to change this setting from the
> default value: 0=Disable, <b>1=Enable</b>.
> + UINT32 WRVC1D:1; ///< - Enable/Disable 1D Write Voltage
> Centering Training. Note it is not recommended to change this setting from the
> default value: 0=Disable, <b>1=Enable</b>.
> + UINT32 RDTC1D:1; ///< - Enable/Disable 1D Read Timing
> Centering Training. Note it is not recommended to change this setting from the
> default value: 0=Disable, <b>1=Enable</b>.
> + UINT32 DIMMODTT:1; ///< - Enable/Disable DIMM ODT Training.
> Note it is not recommended to change this setting from the default value:
> <b>0=Disable</b>, 1=Enable.
> + UINT32 DIMMRONT:1; ///< - Enable/Disable DIMM RON training.
> Note it is not recommended to change this setting from the default value:
> 0=Disable, <b>1=Enable</b>.
> + UINT32 WRDSEQT:1; ///< - Enable/Disable Write Drive Strength /
> Equalization Training 2D. Note it is not recommended to change this setting
> from the default value: <b>0=Disable</b>, 1=Enable.
> + UINT32 WRSRT:1; ///< - Enable/Disable Write Slew Rate traning.
> Note it is not recommended to change this setting from the default value:
> 0=Disable, <b>1=Enable.</b>
> + UINT32 RDODTT:1; ///< - Enable/Disable Read ODT Training.
> Note it is not recommended to change this setting from the default value:
> <b>0=Disable</b>, 1=Enable.
> + UINT32 RDEQT:1; ///< - Enable/Disable Read Equalization
> Training. Note it is not recommended to change this setting from the default
> value: <b>0=Disable</b>, 1=Enable.
> + UINT32 RDAPT:1; ///< - Enable/Disable Read Amplifier Power
> Training. Note it is not recommended to change this setting from the default
> value: <b>0=Disable</b>, 1=Enable.
> + UINT32 WRTC2D:1; ///< - Enable/Disable 2D Write Timing
> Centering Training. Note it is not recommended to change this setting from the
> default value: 0=Disable, <b>1=Enable</b>.
> + UINT32 RDTC2D:1; ///< - Enable/Disable 2D Read Timing
> Centering Training. Note it is not recommended to change this setting from the
> default value: 0=Disable, <b>1=Enable</b>.
> + UINT32 WRVC2D:1; ///< - Enable/Disable 2D Write Voltage
> Centering Training. Note it is not recommended to change this setting from the
> default value: 0=Disable, <b>1=Enable</b>.
> + UINT32 RDVC2D:1; ///< - Enable/Disable 2D Read Voltage
> Centering Training. Note it is not recommended to change this setting from the
> default value: 0=Disable, <b>1=Enable</b>.
> + UINT32 CMDVC:1; ///< - Enable/Disable Command Vref
> Centering Training. Note it is not recommended to change this setting from the
> default value 0=Disable, <b>1=Enable</b>.
> + UINT32 LCT:1; ///< - Enable/Disable Late Command Training.
> Note it is not recommended to change this setting from the default value:
> 0=Disable, <b>1=Enable</b>.
> + UINT32 RTL:1; ///< - Enable/Disable Round Trip Latency
> function. Note it is not recommended to change this setting from the default
> value: 0=Disable, <b>1=Enable</b>.
> + UINT32 TAT:1; ///< - Enable/Disable Turn Around Time
> function. Note it is not recommended to change this setting from the default
> value: <b>0=Disable</b>, 1=Enable.
> + UINT32 RMT:1; ///< - Enable/Disable Rank Margin Tool
> function: <b>0=Disable</b>, 1=Enable.
> + UINT32 MEMTST:1; ///< - Enable/Disable Memory Test function:
> <b>0=Disable</b>, 1=Enable.
> + UINT32 ALIASCHK:1; ///< - Enable/Disable DIMM SPD Alias Check:
> 0=Disable, <b>1=Enable</b>
> + UINT32 RCVENC1D:1; ///< - Enable/Disable Receive Enable
> Centering Training (LPDDR Only). Note it is not recommended to change this
> setting from the default value: <b>0=Disable</b>, 1=Enable
> + UINT32 RMC:1; ///< - Enable/Disable Retrain Margin Check.
> Note it is not recommended to change this setting from the default value:
> <b>0=Disable</b>, 1=Enable
> + UINT32 WRDSUDT:1; ///< - Enable/Disable Write Drive Strength
> Up/Dn independently. Note it is not recommended to change this setting from
> the default value: <b>0=Disable</b>, 1=Enable
> + // Training Algorithms 2
> + UINT32 CMDSR : 1; ///< <CFL> Offset 84 - Enable/Disable CMD
> Slew Rate Training: 0=Disable, <b>1=Enable</b>.
> + UINT32 CMDDSEQ : 1; ///< <CFL> - Enable/Disable CMD Drive
> Strength and Tx Equalization: 0=Disable, <b>1=Enable</b>.
> + UINT32 CMDNORM : 1; ///< <CFL> - Enable/Disable CMD
> Normalization: 0=Disable, <b>1=Enable</b>.
> + UINT32 EWRDSEQ : 1; ///< <CFL> - Enable/Disable Early DQ Write
> Drive Strength and Equalization Training: 0=Disable, <b>1=Enable</b>.
> + UINT32 RDVC1D : 1; ///< <CNL> - Enable/Disable Read Voltage
> Centering 1D
> + UINT32 TXTCO : 1; ///< <CNL> - Enable/Disable Write TCO Comp
> Training
> + UINT32 CLKTCO : 1; ///< <CNL> - Enable/Disable Clock TCO Comp
> Training
> + UINT32 ReservedBits2 :25;
> +
> + UINT32 OddRatioMode:1; ///< Offset 88 If Odd Ratio Mode is
> enabled, QCLK frequency has an addition of 133/100 MHz: <b>0=Disable</b>,
> 1=Enable
> + UINT32 MrcTimeMeasure:1; ///< - Enables serial debug level to
> display the MRC execution times only: <b>0=Disable</b>, 1=Enable
> + UINT32 MrcFastBoot:1; ///< - Enables the MRC fast boot path
> for faster cold boot execution: 0=Disable, <b>1=Enable</b>
> + UINT32 DqPinsInterleaved:1; ///< - Interleaving mode of DQ/DQS
> pins for HSW_ULT which depends on board routing: <b>0=Disable</b>,
> 1=Enable
> + UINT32 RankInterleave:1; ///< - Rank Interleave Mode: 0=Disable,
> <b>1=Enable</b>
> + UINT32 EnhancedInterleave:1; ///< - Enhanced Interleave Mode:
> 0=Disable, <b>1=Enable</b>
> + UINT32 WeaklockEn:1; ///< - Weak Lock Enable: 0=Disable,
> <b>1=Enable</b>
> + UINT32 CmdTriStateDis:1; ///< - CMD Tri-State Support:
> <b>0=Enable</b>, 1=Disable. Note: This should be set to 1 (Disable) if
> Command RTT is not present on the platform.
> + UINT32 MemoryTrace:1; ///< - Memory Trace to second DDR
> channel using Stacked Mode: <b>0=Disable</b>, 1=Enable
> + UINT32 ChHashEnable:1; ///< - Channel Hash Enable: 0=Disable,
> <b>1=Enable</b>
> + UINT32 EnableExtts:1; ///< - Enable Extts: <b>0=Disable</b>,
> 1=Enable
> + UINT32 EnableCltm:1; ///< - Enable Closed Loop Thermal
> Management: <b>0=Disable</b>, 1=Enable
> + UINT32 EnableOltm:1; ///< - Enable Open Loop Thermal
> Management: <b>0=Disable</b>, 1=Enable
> + UINT32 EnablePwrDn:1; ///< - Enable Power Down control for
> DDR: 0=PCODE control, <b>1=BIOS control</b>
> + UINT32 EnablePwrDnLpddr:1; ///< - Enable Power Down for LPDDR:
> 0=PCODE control, <b>1=BIOS control</b>
> + UINT32 LockPTMregs:1; ///< - Lock PCU Thermal Management
> registers: 0=Disable, <b>1=Enable</b>
> + UINT32 UserPowerWeightsEn:1; ///< - Allows user to explicitly set
> power weight, scale factor, and channel power floor values: <b>0=Disable</b>,
> 1=Enable
> + UINT32 RaplLim2Lock:1; ///< - Lock DDR_RAPL_LIMIT register:
> <b>0=Disable</b>, 1=Enable
> + UINT32 RaplLim2Ena:1; ///< - Enable Power Limit 2:
> <b>0=Disable</b>, 1=Enable
> + UINT32 RaplLim1Ena:1; ///< - Enable Power Limit 1:
> <b>0=Disable</b>, 1=Enable
> + UINT32 SrefCfgEna:1; ///< - Enable Self Refresh: 0=Disable,
> <b>1=Enable</b>
> + UINT32 ThrtCkeMinDefeatLpddr:1; ///< - Throttler CKE min defeature
> for LPDDR: 0=Disable, <b>1=Enable</b>
> + UINT32 ThrtCkeMinDefeat:1; ///< - Throttler CKE min defeature:
> <b>0=Disable</b>, 1=Enable
> + UINT32 AutoSelfRefreshSupport:1; ///< - FALSE = No auto self refresh
> support, <b>TRUE = auto self refresh support</b>
> + UINT32 ExtTemperatureSupport:1; ///< - FALSE = No extended
> temperature support, <b>TRUE = extended temperature support</b>
> + UINT32 MobilePlatform:1; ///< - Memory controller device id
> indicates: <b>TRUE if mobile</b>, FALSE if not. Note: This will be
> auto-detected and updated.
> + UINT32 Force1Dpc:1; ///< - TRUE means force one DIMM per
> channel, <b>FALSE means no limit</b>
> + UINT32 ForceSingleRank:1; ///< - TRUE means use Rank0 only (in
> each DIMM): <b>0=Disable</b>, 1=Enable
> + UINT32 RhPrevention:1; ///< - RH Prevention Enable/Disable:
> 0=Disable, <b>1=Enable</b>
> + UINT32 VttTermination:1; ///< - Vtt Termination for Data ODT:
> <b>0=Disable</b>, 1=Enable
> + UINT32 VttCompForVsshi:1; ///< - Enable/Disable Vtt Comparator
> For Vsshi: <b>0=Disable</b>, 1=Enable
> + UINT32 ExitOnFailure:1; ///< - MRC option for exit on failure or
> continue on failure: 0=Disable, <b>1=Enable</b>
> +
> + UINT32 VddSettleWaitTime; ///< Offset 92 Amount of time in
> microseconds to wait for Vdd to settle on top of 200us required by JEDEC spec:
> <b>Default=0</b>
> + UINT16 FreqSaGvLow; ///< Offset 96 SA GV: 0 is Auto/default,
> otherwise holds the frequency value: <b>0=Default</b>, 1067, 1200, 1333,
> 1400, 1600, 1800, 1867.
> + UINT16 SrefCfgIdleTmr; ///< Offset 98 Self Refresh idle timer:
> <b>512=Minimal</b>, 65535=Maximum
> + UINT8 RhActProbability; ///< Offset 100 Activation probability for
> Hardware RHP
> + UINT8 SmramMask; ///< Offset 101 Reserved memory ranges for
> SMRAM
> + UINT16 Vc1ReadMeterThreshold; ///< <CFL> Offset 102 VC1 Read Meter
> Threshold (within Time Window): 0=Minimal, 0xFFFF=Maximum,
> <b>0x118=Default</b>
> + UINT32 Vc1ReadMeterTimeWindow; ///< <CFL> Offset 104 VC1 Read Meter
> Time Window: 0=Minimal, 0x1FFFF=Maximum, <b>0x320=Default</b>
> + UINT64 BerAddress[4]; ///< Offset 108 - 139 BER Address(es):
> <b>0=Minimal</b>, 0xFFFFFFFFFFFFFFFF=Maximum (step is 0x40)
> +
> + UINT16 ChHashMask; ///< Offset 140 Channel Hash Mask:
> 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE=
> BIT[19:18, 13:12 ,9:7] set</b>
> + UINT16 DdrFreqLimit; ///< Offset 142 Memory Frequency setting:
> 3=1067, 5=1333, 7=1600, 9=1867, 11=2133, 13=2400, <b>15=2667</b>
> + UINT8 RaplLim2WindX; ///< Offset 144 Power Limit 2 Time Window
> X value: 0=Minimal, 3=Maximum, <b>1=Default</b>
> + UINT8 RaplLim2WindY; ///< Offset 145 Power Limit 2 Time Window
> Y value: 0=Minimal, 3=Maximum, <b>1=Default</b>
> + UINT8 RaplLim1WindX; ///< Offset 146 Power Limit 1 Time Window
> X value: <b>0=Minimal</b>, 3=Maximum
> + UINT8 RaplLim1WindY; ///< Offset 147 Power Limit 1 Time Window
> Y value: <b>0=Minimal</b>, 31=Maximum
> + UINT16 RaplLim2Pwr; ///< Offset 148 Power Limit 2: 0=Minimal,
> 16383=Maximum, <b>222=Default</b>
> + UINT16 RaplLim1Pwr; ///< Offset 150 Power Limit 1:
> <b>0=Minimal</b>, 16383=Maximum
> + UINT8 WarmThresholdCh0Dimm0; ///< Offset 152 Warm Threshold
> (Channel 0, Dimm 0): 0=Minimal, <b>255=Maximum</b>
> + UINT8 WarmThresholdCh0Dimm1; ///< Offset 153 Warm Threshold
> (Channel 0, Dimm 1): 0=Minimal, <b>255=Maximum</b>
> + UINT8 WarmThresholdCh1Dimm0; ///< Offset 154 Warm Threshold
> (Channel 1, Dimm 0): 0=Minimal, <b>255=Maximum</b>
> + UINT8 WarmThresholdCh1Dimm1; ///< Offset 155 Warm Threshold
> (Channel 1, Dimm 1): 0=Minimal, <b>255=Maximum</b>
> + UINT8 HotThresholdCh0Dimm0; ///< Offset 156 Hot Threshold (Channel
> 0, Dimm 0): 0=Minimal, <b>255=Maximum</b>
> + UINT8 HotThresholdCh0Dimm1; ///< Offset 157 Hot Threshold (Channel
> 0, Dimm 1): 0=Minimal, <b>255=Maximum</b>
> + UINT8 HotThresholdCh1Dimm0; ///< Offset 158 Hot Threshold (Channel
> 1, Dimm 0): 0=Minimal, <b>255=Maximum</b>
> + UINT8 HotThresholdCh1Dimm1; ///< Offset 159 Hot Threshold (Channel
> 1, Dimm 1): 0=Minimal, <b>255=Maximum</b>
> + UINT8 WarmBudgetCh0Dimm0; ///< Offset 160 Warm Budget (Channel
> 0, Dimm 0): 0=Minimal, <b>255=Maximum</b>
> + UINT8 WarmBudgetCh0Dimm1; ///< Offset 161 Warm Budget (Channel
> 0, Dimm 1): 0=Minimal, <b>255=Maximum</b>
> + UINT8 WarmBudgetCh1Dimm0; ///< Offset 162 Warm Budget (Channel
> 1, Dimm 0): 0=Minimal, <b>255=Maximum</b>
> + UINT8 WarmBudgetCh1Dimm1; ///< Offset 163 Warm Budget (Channel
> 1, Dimm 1): 0=Minimal, <b>255=Maximum</b>
> + UINT8 HotBudgetCh0Dimm0; ///< Offset 164 Hot Budget (Channel 0,
> Dimm 0): 0=Minimal, <b>255=Maximum</b>
> + UINT8 HotBudgetCh0Dimm1; ///< Offset 165 Hot Budget (Channel 0,
> Dimm 1): 0=Minimal, <b>255=Maximum</b>
> + UINT8 HotBudgetCh1Dimm0; ///< Offset 166 Hot Budget (Channel 1,
> Dimm 0): 0=Minimal, <b>255=Maximum</b>
> + UINT8 HotBudgetCh1Dimm1; ///< Offset 167 Hot Budget (Channel 1,
> Dimm 1): 0=Minimal, <b>255=Maximum</b>
> + UINT8 IdleEnergyCh0Dimm0; ///< Offset 168 Idle Energy (Channel 0,
> Dimm 0): 0=Minimal, 63=Maximum, <b>10=Default</b>
> + UINT8 IdleEnergyCh0Dimm1; ///< Offset 169 Idle Energy (Channel 0,
> Dimm 1): 0=Minimal, 63=Maximum, <b>10=Default</b>
> + UINT8 IdleEnergyCh1Dimm0; ///< Offset 170 Idle Energy (Channel 1,
> Dimm 0): 0=Minimal, 63=Maximum, <b>10=Default</b>
> + UINT8 IdleEnergyCh1Dimm1; ///< Offset 171 Idle Energy (Channel 1,
> Dimm 1): 0=Minimal, 63=Maximum, <b>10=Default</b>
> + UINT8 PdEnergyCh0Dimm0; ///< Offset 172 Power Down Energy
> (Channel 0, Dimm 0): 0=Minimal, 63=Maximum, <b>6=Default</b>
> + UINT8 PdEnergyCh0Dimm1; ///< Offset 173 Power Down Energy
> (Channel 0, Dimm 1): 0=Minimal, 63=Maximum, <b>6=Default</b>
> + UINT8 PdEnergyCh1Dimm0; ///< Offset 174 Power Down Energy
> (Channel 1, Dimm 0): 0=Minimal, 63=Maximum, <b>6=Default</b>
> + UINT8 PdEnergyCh1Dimm1; ///< Offset 175 Power Down Energy
> (Channel 1, Dimm 1): 0=Minimal, 63=Maximum, <b>6=Default</b>
> + UINT8 ActEnergyCh0Dimm0; ///< Offset 176 Activation Energy
> (Channel 0, Dimm 0): 0=Minimal, 255=Maximum, <b>172=Default</b>
> + UINT8 ActEnergyCh0Dimm1; ///< Offset 177 Activation Energy
> (Channel 0, Dimm 1): 0=Minimal, 255=Maximum, <b>172=Default</b>
> + UINT8 ActEnergyCh1Dimm0; ///< Offset 178 Activation Energy
> (Channel 1, Dimm 0): 0=Minimal, 255=Maximum, <b>172=Default</b>
> + UINT8 ActEnergyCh1Dimm1; ///< Offset 179 Activation Energy
> (Channel 1, Dimm 1): 0=Minimal, 255=Maximum, <b>172=Default</b>
> + UINT8 RdEnergyCh0Dimm0; ///< Offset 180 Read Energy (Channel 0,
> Dimm 0): 0=Minimal, 255=Maximum, <b>212=Default</b>
> + UINT8 RdEnergyCh0Dimm1; ///< Offset 181 Read Energy (Channel 0,
> Dimm 1): 0=Minimal, 255=Maximum, <b>212=Default</b>
> + UINT8 RdEnergyCh1Dimm0; ///< Offset 182 Read Energy (Channel 1,
> Dimm 0): 0=Minimal, 255=Maximum, <b>212=Default</b>
> + UINT8 RdEnergyCh1Dimm1; ///< Offset 183 Read Energy (Channel 1,
> Dimm 1): 0=Minimal, 255=Maximum, <b>212=Default</b>
> + UINT8 WrEnergyCh0Dimm0; ///< Offset 184 Write Energy (Channel 0,
> Dimm 0): 0=Minimal, 255=Maximum, <b>221=Default</b>
> + UINT8 WrEnergyCh0Dimm1; ///< Offset 185 Write Energy (Channel 0,
> Dimm 1): 0=Minimal, 255=Maximum, <b>221=Default</b>
> + UINT8 WrEnergyCh1Dimm0; ///< Offset 186 Write Energy (Channel 1,
> Dimm 0): 0=Minimal, 255=Maximum, <b>221=Default</b>
> + UINT8 WrEnergyCh1Dimm1; ///< Offset 187 Write Energy (Channel 1,
> Dimm 1): 0=Minimal, 255=Maximum, <b>221=Default</b>
> +
> +
> + UINT8 MaxRttWr; ///< Offset 188 Maximum DIMM RTT_WR to
> use in power training: <b>0=ODT Off</b>, 1 = 120 ohms
> + UINT8 ThrtCkeMinTmr; ///< Offset 189 Throttler CKE min timer:
> 0=Minimal, 0xFF=Maximum, <b>0x30=Default</b>
> + UINT8 ThrtCkeMinTmrLpddr; ///< Offset 190 Throttler CKE min timer
> for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x40=Default</b>
> + UINT8 BerEnable; ///< Offset 191 BER Enable and # of Addresses
> passed in: <b>0=Minimal</b>, 8=Maximum
> + UINT8 CkeRankMapping; ///< Offset 192 Bits [7:4] - Channel 1, bits
> [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies which rank CKE[i] goes
> to.
> + UINT8 StrongWkLeaker; ///< Offset 193 Strong Weak Leaker:
> 1=Minimal, <b>7=Maximum</b>
> + UINT8 CaVrefConfig; ///< Offset 194 0=VREF_CA goes to both CH_A
> and CH_B, 1=VREF_CA to CH_A, VREF_DQ_A to CH_B, <b>2=VREF_CA to CH_A,
> VREF_DQ_B to CH_B</b>
> + UINT8 SaGv; ///< Offset 195 SA GV: 0=Disabled; 1=FixedLow;
> CFL: 2=FixedHigh, CNL: 2=FixedMid; <b>CFL: 3=Enabled</b> CNL: 3=FixedHigh;
> <b>CNL: 4=Enabled</b>
> + UINT8 RaplPwrFlCh1; ///< Offset 196 Power Channel 1 Floor value:
> <b>0=Minimal</b>, 255=Maximum
> + UINT8 RaplPwrFlCh0; ///< Offset 197 Power Channel 0 Floor value:
> <b>0=Minimal</b>, 255=Maximum
> + UINT8 NModeSupport; ///< Offset 198 Memory N Mode Support -
> Enable user to select Auto, 1N or 2N: <b>0=AUTO</b>, 1=1N, 2=2N.
> + UINT8 RefClk; ///< Offset 199 Selects the DDR base reference
> clock. 0x01 = 100MHz, <b>0x00 = 133MHz</b>
> + UINT8 EnCmdRate; ///< Offset 200 CMD Rate Enable: 0=Disable,
> 1=1 CMD, 2=2 CMDs, <b>3=3 CMDs</b>, 4=4 CMDs, 5=5 CMDs, 6=6 CMDs, 7=7
> CMDs
> + UINT8 Refresh2X; ///< Offset 201 Refresh 2x: <b>0=Disable</b>,
> 1=Enable for WARM or HOT, 2=Enable for HOT only
> + UINT8 EpgEnable; ///< Offset 202 Enable Energy Performance
> Gain.
> + UINT8 RhSolution; ///< Offset 203 Type of solution to be used for
> RHP - 0/1 = HardwareRhp/Refresh2x
> + UINT8 UserThresholdEnable; ///< Offset 204 Flag to manually select the
> DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable, <b>0=Default</b>
> + UINT8 UserBudgetEnable; ///< Offset 205 Flag to manually select the
> Budget Registers for CLTM Memory Dimms , 0=Disable, 1=Enable,
> <b>0=Default</b>
> + UINT8 TsodTcritMax; ///< Offset 206 TSOD Tcrit Maximum Value
> to be Configure , 0=Minimal, 128=Maximum, , <b>105=Default</b>
> +
> + UINT8 TsodEventMode; ///< Offset 207 Flag to Enable Event Mode
> Interruption in TSOD Configuration Register, 0=Disable, 1=Enable,
> <b>1=Default</b>
> + UINT8 TsodEventPolarity; ///< Offset 208 Event Signal Polarity in TSOD
> Configuration Register, 0=Low, 1=High, <b>0=Default</b>
> + UINT8 TsodCriticalEventOnly; ///< Offset 209 Critical Trigger Only in TSOD
> Configuration Register,0=Disable, 1=Enable, <b>1=Default</b>
> + UINT8 TsodEventOutputControl; ///< Offset 210 Event Output Control in
> TSOD Configuration Register,0=Disable, 1=Enable, <b>1=Default</b>
> + UINT8 TsodAlarmwindowLockBit; ///< Offset 211 Alarm Windows Lock Bit
> in TSOD Configuration Register,0=Unlock, 1=Lock, <b>0=Default</b>
> + UINT8 TsodCriticaltripLockBit;///< Offset 212 Critical Trip Lock Bit in TSOD
> Configuration Register,0=Unlock, 1=Lock, <b>0=Default</b>
> + UINT8 TsodShutdownMode; ///< Offset 213 Shutdown Mode TSOD
> Configuration Register,0=Enable, 1=Disable, <b>0=Default</b>
> + UINT8 TsodThigMax; ///< Offset 214 Thigh Max Value In the for
> CLTM Memory Dimms , 0=Disable, 1=Enable, <b>0=Default</b>
> + UINT8 TsodManualEnable; ///< Offset 215 Flag to manually select the
> TSOD Register Values , 0=Disable, 1=Enable, <b>0=Default</b>
> + UINT8 DllBwEn0; ///< Offset 216 DllBwEn value for 1067
> + UINT8 DllBwEn1; ///< Offset 217 DllBwEn value for 1333
> + UINT8 DllBwEn2; ///< Offset 218 DllBwEn value for 1600
> + UINT8 DllBwEn3; ///< Offset 219 DllBwEn value for 1867 and up
> + UINT8 RetrainOnFastFail; ///< Offset 220 Restart MRC in Cold mode if
> SW MemTest fails during Fast flow. 0 = Disabled, <b>1 = Enabled</b>
> + UINT8 ForceOltmOrRefresh2x; ///< Offset 221 Force OLTM or 2X Refresh
> when needed. <b>0 = Force OLTM</b>, 1 = Force 2x Refresh
> + UINT8 PowerDownMode; ///< Offset 222 CKE Power Down Mode:
> <b>0xFF=AUTO</b>, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode
> + UINT8 PwdwnIdleCounter; ///< Offset 223 CKE Power Down Mode
> Idle Counter: 0=Minimal, 255=Maximum, <b>0x80=0x80 DCLK</b>
> + UINT8 IsvtIoPort; ///< Offset 224 ISVT IO Port Address: 0=Minimal,
> 0xFF=Maximum, <b>0x99=Default</b>
> + UINT8 CmdRanksTerminated; ///< <CNL> Offset 225 LPDDR4: Bitmask
> of ranks that have CA bus terminated. <b>0x01=Default, Rank0 is terminating
> and Rank1 is non-terminating</b>
> + UINT8 GdxcEnable; ///< <CFL> Offset 226 GDXC MOT enable
> + UINT8 GdxcIotSize; ///< <CFL> Offset 227 IOT size in multiples of
> 8MEG
> + UINT8 GdxcMotSize; ///< <CFL> Offset 228 MOT size in multiples
> of 8MEG
> + UINT8 RMTLoopCount; ///< Offset 229 Indicates the Loop Count to
> be used for Rank Margin Tool Testing: 1=Minimal, 32=Maximum, 0=AUTO,
> <b>0=Default</b>
> + UINT16 FreqSaGvMid; ///< Offset 230 SA GV: 0 is Auto/default,
> otherwise holds the frequency value expressed as an integer:
> <b>0=Default</b>, 1600, 1800, 1867, 2000, 2133, etc.
> +
> + UINT32 RmtPerTask:1; ///< Offset 232 Bit 0: Rank Margin Tool
> Per Task. <b>0 = Disabled</b>, 1 = Enabled
> + UINT32 TrainTrace:1; ///< Offset 232 Bit 1: Trained state tracing
> debug. <b>0 = Disabled</b>, 1 = Enabled
> + UINT32 SafeMode:1; ///< Offset 232 Bit 2: Define if safe mode
> is enabled for MC/IO
> + UINT32 EnBER:1; ///< Offset 232 Bit 3: Define if EnBER is
> enabled for Rank Margin Tool
> + UINT32 Ddr4MixedUDimm2DpcLimit:1; ///< Offset 232 Bit 4:
> Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm
> 2DPC population. 0 = Disabled, <b>1 = Enabled</b>
> + UINT32 FastBootRmt:1; ///< Offset 232 Bit 5: Enable/Disable
> RMT on FastBoot. <b>0 = Disabled</b>, 1 = Enabled
> + UINT32 MrcTrainOnWarm:1; ///< Offset 232 Bit 6: Force MRC
> training on warm boot : <b>0 = Disabled</b>, 1 = Enabled
> + UINT32 LongFlyByModeEnabled:1; ///< Offset 232 Bit 7: Long FlyBy
> Mode Enabled : <b>0 = Disabled</b>, 1 = Enabled
> + UINT32 Off232RsvdBits:24; ///< Offset 232 Bit 8-31: Reserved
> +
> + // TurnAround Timing
> + UINT8 tRd2RdSG; ///< Offset 236 - Read-to-Read Same Group
> Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum.
> + UINT8 tRd2RdDG; ///< Offset 237 - Read-to-Read Different
> Group Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum. Same
> Group and Different Group Timings must be the same for Non-DDR4 memory.
> + UINT8 tRd2RdDR; ///< Offset 238 - Read-to-Read Different
> Rank Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum.
> + UINT8 tRd2RdDD; ///< Offset 239 - Read-to-Read Different
> DIMM Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum.
> + UINT8 tRd2WrSG; ///< Offset 240 - Read-to-Write Same Group
> Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum.
> + UINT8 tRd2WrDG; ///< Offset 241 - Read-to-Write Different
> Group Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum. Same
> Group and Different Group Timings must be the same for Non-DDR4 memory.
> + UINT8 tRd2WrDR; ///< Offset 242 - Read-to-Write Different
> Rank Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum.
> + UINT8 tRd2WrDD; ///< Offset 243 - Read-to-Write Different
> DIMM Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum.
> + UINT8 tWr2RdSG; ///< Offset 244 - Write-to-Read Same Group
> Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 86=Maximum.
> + UINT8 tWr2RdDG; ///< Offset 245 - Write-to-Read Different
> Group Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum. Same
> Group and Different Group Timings must be the same for Non-DDR4 memory.
> + UINT8 tWr2RdDR; ///< Offset 246 - Write-to-Read Different
> Rank Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum.
> + UINT8 tWr2RdDD; ///< Offset 247 - Write-to-Read Different
> DIMM Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum.
> + UINT8 tWr2WrSG; ///< Offset 248 - Write-to-Write Same Group
> Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum.
> + UINT8 tWr2WrDG; ///< Offset 249 - Write-to-Write Different
> Group Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum. Same
> Group and Different Group Timings must be the same for Non-DDR4 memory.
> + UINT8 tWr2WrDR; ///< Offset 250 - Write-to-Write Different
> Rank Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum.
> + UINT8 tWr2WrDD; ///< Offset 251 - Write-to-Write Different
> DIMM Turn Around Timing: <b>0=AUTO</b>, 4=Minimal, 64=Maximum.
> + UINT16 tRRD_L; ///< <CFL> Offset 252 - User defined DDR4
> Memory Timing tRRD_L value, valid when MemoryProfile is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 15=Maximum.
> + UINT16 tRRD_S; ///< <CFL> Offset 254 - User defined DDR4
> Memory Timing tRRD_S value, valid when MemoryProfile is CUSTOM_PROFILE:
> <b>0=AUTO</b>, 15=Maximum.
> + UINT16 tWTR_L; ///< <CFL> Offset 266 - User defined DDR4
> Memory Timing tWTR_L value, valid when MemoryProfile is
> CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
> + UINT16 tWTR_S; ///< <CFL> Offset 268 - User defined DDR4
> Memory Timing tWTR_S value, valid when MemoryProfile is
> CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
> +
> +} MEMORY_CONFIGURATION;
> +
> +/// Memory Configuration
> +/// The contents of this structure are not CRC'd by the MRC for option change
> detection.
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config
> Block Header
> + SA_FUNCTION_CALLS SaCall; ///< Offset 24 Function calls
> into the SA.
> + SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 200 Function
> calls into the MRC.
> + SPD_DATA_BUFFER *SpdData; ///< Offset 236 Memory SPD
> data, will be used by the MRC when SPD SmBus address is zero.
> + SA_MEMORY_DQ_MAPPING *DqByteMap; ///< Offset 240
> LPDDR3 DQ byte mapping to CMD/CTL/CLK, from the CPU side.
> + SA_MEMORY_DQS_MAPPING *DqsMap; ///< Offset 244
> LPDDR3 DQS byte swizzling between CPU and DRAM.
> + SA_MEMORY_RCOMP *RcompData; ///< Offset 248 DDR
> RCOMP resistors and target values.
> + UINT64 PlatformMemorySize; ///< Offset 252 The minimum
> platform memory size required to pass control into DXE
> + UINT32 CleanMemory:1; ///< Offset 260 Ask MRC to
> clear memory content: <b>FALSE=Do not Clear Memory</b>; TRUE=Clear
> Memory
> + UINT32 MemTestOnWarmBoot:1; ///< Offset 260 Run Base
> Memory Test On WarmBoot: 0=Disabled, <b>1=Enabled</b>
> + UINT32 ReservedBits5:30;
> + /**
> + Sets the serial debug message level\n
> + 0x00 = Disabled\n
> + 0x01 = Errors only\n
> + 0x02 = Errors and Warnings\n
> + <b>0x03 = Errors, Warnings, and Info</b>\n
> + 0x04 = Errors, Warnings, Info, and Events\n
> + 0x05 = Displays Memory Init Execution Time Summary only\n
> + **/
> + UINT8 SerialDebugLevel; ///< Offset 264
> + UINT8 Reserved11[3]; ///< Offset 265 Reserved
> +} MEMORY_CONFIG_NO_CRC;
> +#pragma pack(pop)
> +
> +#endif // _MEMORY_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Mem
> oryDxeConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Mem
> oryDxeConfig.h
> new file mode 100644
> index 0000000000..9f01c172f2
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Mem
> oryDxeConfig.h
> @@ -0,0 +1,61 @@
> +/** @file
> + Memory DXE Policy definitions
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _MEMORY_DXE_CONFIG_H_
> +#define _MEMORY_DXE_CONFIG_H_
> +
> +#pragma pack(push, 1)
> +
> +#define MEMORY_DXE_CONFIG_REVISION 1
> +
> +/**
> + The Memory Configuration includes DIMM SPD address Map and DIMM Slot
> Mechanical present bit map.
> + The data elements should be initialized by a Platform Module.\n
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config
> Block Header
> +/**
> + Offset 28:
> + Dimm SPD address
> + Only Server support 2 channels * 3 slots per channel = 6 sockets totally
> + The Desktop and mobile only support 2 channels * 2 slots per channel = 4
> sockets totally
> + So there is mapping rule here for Desktop and mobile that there are no more
> 4 DIMMS totally in a system:
> + Channel A/ Slot 0 --> Dimm 0 --> SpdAddressTable[0]
> + Channel A/ Slot 1 --> Dimm 1 --> SpdAddressTable[1]
> + Channel B/ Slot 0 --> Dimm 2 --> SpdAddressTable[2]
> + Channel B/ Slot 1 --> Dimm 3 --> SpdAddressTable[3]
> + Refer to SmbiosMemory.c for use
> + If change the mapping rule, please update the Revision number.
> +**/
> + UINT8 *SpdAddressTable;
> +/**
> + Offset 36:
> + Channel A DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 ->
> DIMM1, ...
> + if the bit is 1, the related DIMM slot is present.
> + E.g. if channel A has 2 DIMMs, ChannelASlotMap = 0x03;
> + E.g. if channel A has only 1 DIMMs, ChannelASlotMap = 0x01;
> + Refer to SmbiosMemory.c
> +**/
> + UINT8 ChannelASlotMap;
> +/**
> + Offset 37:
> + Channel B DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 ->
> DIMM1, ...
> + if the bit is 1, the related DIMM slot is present.
> + E.g. if channel B has 2 DIMMs, ChannelBSlotMap = 0x03;
> + E.g. if channel B has only 1 DIMMs, ChannelBSlotMap = 0x01;
> + Refer to SmbiosMemory.c
> +**/
> + UINT8 ChannelBSlotMap;
> + UINT8 MrcTimeMeasure; ///< Offset 38: MRC execution time
> measurement: <b>0=Disable</b>, 1=Enable
> + UINT8 MrcFastBoot; ///< Offset 39: Fast boot: 0=Disable,
> <b>1=Enable</b>
> +} MEMORY_DXE_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _MEMORY_DXE_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Misc
> DxeConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Misc
> DxeConfig.h
> new file mode 100644
> index 0000000000..7a8894a5c0
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Misc
> DxeConfig.h
> @@ -0,0 +1,33 @@
> +/** @file
> + MISC DXE policy definitions
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _MISC_DXE_CONFIG_H_
> +#define _MISC_DXE_CONFIG_H_
> +
> +#pragma pack(push, 1)
> +
> +#define MISC_DXE_CONFIG_REVISION 2
> +
> +/**
> + This data structure includes miscellaneous configuration variables such SA
> thermal device
> + control. The data elements should be initialized by a Platform Module.\n
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2:</b>
> + - Added RmrrCsmeBaseAddress fields.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config
> Block Header
> + EFI_PHYSICAL_ADDRESS *RmrrUsbBaseAddress; ///< Offset 28 The
> field is used to describe the platform USB Reserved memory for Intel VT-d
> support. Platform code should provide this information for Intel VT-d DXE
> driver use
> + UINT32 EnableAbove4GBMmio : 1; ///< Offset 29:0
> Enable/disable above 4GB MMIO resource support: <b>0=Disable</b>,
> 1=Enable
> + UINT32 RsvdBits0 : 31; ///< Offset 29:1 Reserved bits.
> + EFI_PHYSICAL_ADDRESS *RmrrCsmeBaseAddress; ///< The field is used
> to describe the CSME Reserved memory.
> +} MISC_DXE_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _MISC_DXE_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Over
> ClockingConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Over
> ClockingConfig.h
> new file mode 100644
> index 0000000000..b623f14c15
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Over
> ClockingConfig.h
> @@ -0,0 +1,51 @@
> +/** @file
> + Policy definition for System Agent overclocking Config Block
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _OVERCLOCKING_PREMEM_CONFIG__H_
> +#define _OVERCLOCKING_PREMEM_CONFIG__H_
> +#pragma pack(push, 1)
> +
> +#define SA_OVERCLOCKING_CONFIG_REVISION 2
> +
> +/**
> + Defines the overclocking configuration parameters for System Agent.\n
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Add GT unslice support.
> +
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
> + /**
> + Offset 28:0 :
> + Enable disable of SA overclocking mailbox commands.
> + If disabled, or if PcdSaOcEnable is disabled, all other policies in this config
> block are ignored.
> + <b>0=Disable</b>,
> + 1=Enable
> + **/
> + UINT32 OcSupport : 1;
> + UINT32 GtVoltageMode : 1; ///< Offset 28:1 :Specifies whether GT
> voltage is operating in Adaptive or Override mode: <b>0=Adaptive</b>,
> 1=Override
> + UINT32 RealtimeMemoryTiming : 1; ///< Offset 28:2 :Enable/Disable
> the message sent to the CPU to allow realtime memory timing changes after
> MRC_DONE. <b>0=Disable</b>, 1=Enable
> + UINT32 GtusVoltageMode : 1; ///< Offset 28:3 :Specifies whether GT
> unslice voltage is operating in Adaptive or Override mode: <b>0=Adaptive</b>,
> 1=Override
> + UINT32 RsvdBits0 : 28; ///< Offset 28:4 - 31 :Reserved for future
> use
> + UINT8 GtMaxOcRatio; ///< Offset 32 Maximum GT turbo ratio
> override: 0=Minimal, 255=Maximum, <b>0=AUTO</b>
> + UINT8 Rsvd0; ///< Offset 33 Reserved for DWORD
> alignment
> + INT16 GtVoltageOffset; ///< Offset 34 The voltage offset applied
> to GT slice. Valid range from -1000mv to 1000mv: <b>0=Minimal</b>,
> 1000=Maximum
> + UINT16 GtVoltageOverride; ///< Offset 36 The GT voltage override
> which is applied to the entire range of GT frequencies <b>0=Default</b>
> + UINT16 GtExtraTurboVoltage; ///< Offset 38 The adaptive voltage
> applied during turbo frequencies. Valid range from 0 to 2000mV:
> <b>0=Minimal</b>, 2000=Maximum
> + INT16 SaVoltageOffset; ///< Offset 40 The voltage offset applied
> to the SA. Valid range from -1000mv to 1000mv: <b>0=Default</b>
> + INT16 GtusVoltageOffset; ///< Offset 42 The voltage offset applied
> to GT unslice. Valid range from -1000mv to 1000mv: <b>0=Minimal</b>,
> 1000=Maximum
> + UINT16 GtusVoltageOverride; ///< Offset 44 The GT unslice voltage
> override which is applied to the entire range of GT frequencies:
> <b>0=Default</b>
> + UINT16 GtusExtraTurboVoltage; ///< Offset 46 The adaptive voltage
> applied during turbo frequencies. Valid range from 0 to 2000mV:
> <b>0=Default</b>
> + UINT8 GtusMaxOcRatio; ///< Offset 48 Maximum GTus turbo
> ratio override: 0=Minimal, 6=Maximum, <b>0=AUTO</b>
> + UINT8 Rsvd1[3]; ///< Offset 49-51 Reserved for DWORD
> alignment
> +} OVERCLOCKING_PREMEM_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _OVERCLOCKING_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieD
> xeConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieD
> xeConfig.h
> new file mode 100644
> index 0000000000..f0b9670f64
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieD
> xeConfig.h
> @@ -0,0 +1,135 @@
> +/** @file
> + PCIE DXE policy definitions
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCIE_DXE_CONFIG_H_
> +#define _PCIE_DXE_CONFIG_H_
> +
> +#pragma pack(push, 1)
> +
> +#define PCIE_DXE_CONFIG_REVISION 1
> +
> +///
> +/// Device List for special ASPM override
> +///
> +typedef struct {
> + UINT16 VendorId; ///< Offset 0 PCI Configuration space offset 0
> + UINT16 DeviceId; ///< Offset 2 PCI Configuration space offset 2
> + UINT8 RevId; ///< Offset 4 PCI Configuration space offset 8; 0xFF
> means all steppings
> + UINT8 RootApmcMask; ///< Offset 5 Root ASPM override bit mask
> <b>0=No override</b>
> + UINT8 EndpointApmcMask; ///< Offset 6 Endpoint ASPM override bit
> mask <b>0=No override</b>
> + UINT8 Rsvd; ///< Offset 7 Reserved
> +} PCIE_ASPM_OVERRIDE_LIST;
> +
> +typedef struct {
> + UINT16 VendorId; ///< Offset 0 PCI Config space offset 0
> + UINT16 DeviceId; ///< Offset 2 PCI Config space offset 2
> +/**
> + Offset 4:
> + SnoopLatency bit definition
> + Note: All Reserved bits must be set to 0
> +
> + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
> + When clear values in bits 9:0 will be ignored
> + BIT[14] - Should be set to 0b
> + BIT[13] - Reserved
> + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
> + 000b - 1 ns
> + 001b - 32 ns
> + 010b - 1024 ns
> + 011b - 32,768 ns
> + 100b - 1,048,576 ns
> + 101b - 33,554,432 ns
> + 110b - Reserved
> + 111b - Reserved
> + BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied
> with
> + the scale in bits 12:10
> +**/
> + UINT16 SnoopLatency;
> +/**
> + Offset 6:
> + NonSnoopLatency bit definition
> + Note: All Reserved bits must be set to 0
> +
> + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
> + When clear values in bits 9:0 will be ignored
> + BIT[14] - Should be set to 0b
> + BIT[13] - Reserved
> + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
> + 000b - 1 ns
> + 001b - 32 ns
> + 010b - 1024 ns
> + 011b - 32,768 ns
> + 100b - 1,048,576 ns
> + 101b - 33,554,432 ns
> + 110b - Reserved
> + 111b - Reserved
> + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be
> multiplied with
> + the scale in bits 12:10
> +**/
> + UINT16 NonSnoopLatency;
> + UINT8 RevId; ///< Offset 8 PCI Config space offset 8; 0xFF means all
> steppings
> + UINT8 Rsvd0[3]; ///< Offset 9
> +} PCIE_LTR_DEV_INFO;
> +
> +///
> +/// PCIE Power Optimizer config
> +///
> +typedef struct {
> + UINT16 LtrMaxSnoopLatency; ///< Offset 0 LTR Maximum Snoop Latency:
> <b>0x0846=70us</b>
> + UINT16 LtrMaxNoSnoopLatency; ///< Offset 2 LTR Maximum Non-Snoop
> Latency: <b>0x0846=70us</b>
> + UINT8 ObffEnable; ///< Offset 4 LTR enable/disable: 0=Disable,
> <b>1=Enable</b>
> + UINT8 LtrEnable; ///< Offset 5 LTR enable/disable: 0=Disable,
> <b>1=Enable</b>
> + UINT8 Rsvd0[2]; ///< Offset 6 Reserved
> +} SA_PCIE_PWR_OPT;
> +
> +
> +/**
> + The PCI Express Configuration info includes PCI Resources Range Base and
> Limits and the control
> + for PEG ASPM.
> + The data elements should be initialized by a Platform Module.\n
> + @note <b>Optional.</b> These policies will be ignored if there is no PEG
> port present on board.
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27
> Config Block Header
> +/**
> + Offset 28: This field is used to describe the ASPM control for PEG Ports\n
> + 0=ASPM Disabled, 1=ASPM L0s Enabled, 2=ASPM L1 Enabled, 3=ASPM L0sL1
> Enabled, <b>4=ASPM AUTO</b>
> +**/
> + UINT8 PegAspm[SA_PEG_MAX_FUN];
> +/**
> + Offset 32: This field is used to describe the PEG L0s advanced control
> + 0=ASPM L0s disabled, 1=ASPM L0s enabled on RP, 2=ASPM L0s enabled on EP,
> <b>3=ASPM L0s enabled on both RP and EP</b>
> +**/
> + UINT8 PegAspmL0s[SA_PEG_MAX_FUN];
> +/**
> + Offset 36: PCIe Hot Plug Enable/Disable. It has 2 policies.
> + - <b>Disabled (0x0)</b> : No hotplug.
> + - Enabled (0x1) : Bios assist hotplug.
> +**/
> + UINT8 PegRootPortHPE[SA_PEG_MAX_FUN];
> +/**
> + Offset 40: This field is used as a pointer to the ASPM device override table,
> default points to an\n
> + existing table mPcieAspmDevsOverride\n
> + Refer to DxeSaPolicyLib.c for the usage.
> + Note: This exclusion list helps avoid potential system hangs.
> +**/
> + PCIE_ASPM_OVERRIDE_LIST *PcieAspmDevsOverride;
> +/**
> + Offset 48: This field is used as a pointer to the LTR device override table,
> default points to an existing
> + table mPcieLtrDevsOverride.\n
> + Refer to DxeSaPolicyLib.c for the usage.
> +**/
> + PCIE_LTR_DEV_INFO *PcieLtrDevsOverride;
> + SA_PCIE_PWR_OPT PegPwrOpt[SA_PEG_MAX_FUN]; ///< Offset
> 60: This field is used to describe the PCIe LTR/OBFF relevant settings
> + UINT8 Rsvd1[3]; /// Reserved for future use
> +} PCIE_DXE_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _PCIE_DXE_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieP
> eiConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieP
> eiConfig.h
> new file mode 100644
> index 0000000000..7899504865
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieP
> eiConfig.h
> @@ -0,0 +1,60 @@
> +/** @file
> + Policy definition for PCIe Config Block
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCIE_PEI_CONFIG_H_
> +#define _PCIE_PEI_CONFIG_H_
> +
> +#include <Library/GpioLib.h>
> +#include <SaAccess.h>
> +
> +#pragma pack(push, 1)
> +
> +#define SA_PCIE_PEI_CONFIG_REVISION 1
> +
> +/**
> + PCI Express and DMI controller configuration - PostMem\n
> + @note <b>Optional.</b> These policies will be ignored if there is no PEG port
> present on board.
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config
> Block Header
> + /**
> + Offset 28:0
> + <b>(Test)</b>DMI Extended Sync Control
> + - <b>Disabled</b> (0x0) : Disable DMI Extended Sync (Default)
> + - Enabled (0x1) : Enable DMI Extended Sync
> + **/
> + UINT32 DmiExtSync : 1;
> + /**
> + Offset 28:1
> + <b>(Test)</b>DMI IOT Control
> + - <b>Disabled</b> (0x0) : Disable DMI IOT (Default)
> + - Enabled (0x1) : Enable DMI IOT
> + **/
> + UINT32 DmiIot : 1;
> + UINT32 RsvdBits1 : 30; ///< Offset
> 28:2-31 :Reserved for future use.
> + UINT8 DmiAspm; ///< Offset 32 This
> field is used to describe the ASPM control for DMI: <b>3=PcieAspmL0sL1</b>,
> 2=PcieAspmL1, 1=PcieAspmL0s, 0=PcieAspmDisabled.
> + UINT8 Rsvd1[3]; ///< Offset 33 to 35
> + UINT8 PegDeEmphasis[SA_PEG_MAX_FUN]; ///<
> Offset 36 This field is used to describe the DeEmphasis control for PEG (-6 dB
> and -3.5 dB are the options)SA_PEG_MAX_FUN = 3 for CFL and
> SA_PEG_MAX_FUN = 4 for CNL, offsets are adjusted accordingly
> + UINT8 PegMaxPayload[SA_PEG_MAX_FUN]; ///<
> <b>(Test)</b> Offset 39/40 This field is used to describe the PEG Max Pay Load
> Size (0xFF: Auto, 0:128B, 1:256B)
> + /**
> + PCIe Slot Power Capabilities. SlotPowerLimitValue in combination with
> SlotPowerLimitScale specifies the upper limit on power supplied by slot.
> + **/
> + UINT8 PegSlotPowerLimitValue[SA_PEG_MAX_FUN]; ///<
> Offset 42/44 8 bit value
> + UINT8 PegSlotPowerLimitScale[SA_PEG_MAX_FUN]; ///<
> Offset 45/48 2 bit value: <b>00 = 1.0x</b>, 01 = 0.1x, 10 = 0.01x and 11 = 0.001x
> + /**
> + Offset 48/52
> + PCIe Physical Slot Number (13 bit value). Indicates the physical slot number
> attached to the port.
> + **/
> + UINT16 PegPhysicalSlotNumber[SA_PEG_MAX_FUN];
> + UINT8 Rsvd2[2];
> +} PCIE_PEI_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _PCIE_PEI_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieP
> eiPreMemConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieP
> eiPreMemConfig.h
> new file mode 100644
> index 0000000000..a53bf3c7bd
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieP
> eiPreMemConfig.h
> @@ -0,0 +1,354 @@
> +/** @file
> + Policy definition for PCIe Config Block
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCIE_PEI_PREMEM_CONFIG_H_
> +#define _PCIE_PEI_PREMEM_CONFIG_H_
> +
> +#include <Library/GpioLib.h>
> +#include <SaAccess.h>
> +
> +#pragma pack(push, 1)
> +
> +#define SA_PCIE_PEI_PREMEM_CONFIG_REVISION 3
> +
> +///
> +/// SA GPIO Data Structure
> +///
> +typedef struct {
> + GPIO_PAD GpioPad; ///< Offset 0: GPIO Pad
> + UINT8 Value; ///< Offset 4: GPIO Value
> + UINT8 Rsvd0[3]; ///< Offset 5: Reserved for 4 bytes alignment
> + UINT32 Active :1; ///< Offset 8: 0=Active Low; 1=Active High
> + UINT32 RsvdBits0:31;
> +} SA_GPIO_INFO_PCIE;
> +
> +///
> +/// SA Board PEG GPIO Info
> +///
> +typedef struct {
> + SA_GPIO_INFO_PCIE SaPeg0ResetGpio; ///< Offset 0: PEG0 PERST#
> GPIO assigned, must be a PCH GPIO pin
> + SA_GPIO_INFO_PCIE SaPeg3ResetGpio; ///< Offset 12: PEG3 PERST#
> GPIO assigned, must be a PCH GPIO pin
> + BOOLEAN GpioSupport; ///< Offset 24: 1=Supported; 0=Not
> Supported
> + UINT8 Rsvd0[3]; ///< Offset 25: Reserved for 4 bytes
> alignment
> +} PEG_GPIO_DATA;
> +
> +
> +/**
> + PCI Express and DMI controller configuration\n
> + @note <b>Optional.</b> These policies will be ignored if there is no PEG port
> present on board.
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Change PegGen3RxCtleOverride of PCIE_PEI_PREMEM_CONFIG from one
> bit to UINT8
> + - Change DmiGen3RxCtlePeaking default to 0
> + <b>Revision 3</b>:
> + - Added PEG IMR support
> + - Added UINT8 PegImrEnable
> + - Added UINT16 PegImrSize
> + - Added UINT8 ImrRpSelection
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset
> 0-27 Config Block Header
> + /**
> + Offset 28:0 :
> + <b>(Test)</b> DMI Link Speed Control
> + - <b>Auto</b> (0x0) : Maximum possible link speed (Default)
> + - Gen1 (0x1) : Limit Link to Gen1 Speed
> + - Gen2 (0x2) : Limit Link to Gen2 Speed
> + - Gen3 (0x3) : Limit Link to Gen3 Speed
> + **/
> + UINT32 DmiMaxLinkSpeed : 2;
> + /**
> + Offset 28:2 :
> + <b>(Test)</b> DMI Equalization Phase 2 Enable Control
> + - Disabled (0x0) : Disable phase 2
> + - Enabled (0x1) : Enable phase 2
> + - <b>Auto</b> (0x2) : Use the current default method (Default)
> + **/
> + UINT32 DmiGen3EqPh2Enable : 2;
> + /**
> + Offset 28:4 :
> + <b>(Test)</b> Selects the method for performing Phase3 of Gen3
> Equalization on DMI
> + - <b>Auto</b> (0x0) : Use the current default method (Default)
> + - HwEq (0x1) : Use Adaptive Hardware Equalization
> + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented in
> BIOS Reference Code)
> + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset
> array for Phase1 AND Phase3 (Instead of just Phase1)
> + - Disabled (0x4) : Bypass Equalization Phase 3
> + **/
> + UINT32 DmiGen3EqPh3Method : 3;
> + /**
> + Offset 28:7 :
> + <b>(Test)</b> Program DMI Gen3 EQ Phase1 Static Presets
> + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
> + - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming
> (Default)
> + **/
> + UINT32 DmiGen3ProgramStaticEq : 1;
> +
> + /**
> + Offset 28:8 to 28:15 :
> + <b>(Test)</b> PEG Enable Control
> + - Disabled (0x0) : Disable PEG Port
> + - Enabled (0x1) : Enable PEG Port (If Silicon SKU permits it)
> + - <b>Auto</b> (0x2) : If an endpoint is present, enable the PEG Port,
> Disable otherwise (Default)
> + **/
> + UINT32 Peg0Enable : 2; ///<
> Enable/Disable PEG 0:1:0 Root Port
> + UINT32 Peg1Enable : 2; ///<
> <b>(Test)</b> Enable/Disable PEG 0:1:1 Root Port
> + UINT32 Peg2Enable : 2; ///<
> <b>(Test)</b> Enable/Disable PEG 0:1:2 Root Port
> + UINT32 Peg3Enable : 2; ///<
> <b>(Test)</b> Enable/Disable PEG 0:6:0 Root Port.
> +
> + /**
> + Offset 28:16 :
> + <b>(Test)</b> PCIe Link Speed Control
> + - <b>Auto</b> (0x0) : Maximum possible Link speed (Default)
> + - Gen1 (0x1) : Limit Link to Gen1 Speed
> + - Gen2 (0x2) : Limit Link to Gen2 Speed
> + - Gen3 (0x3) : Limit Link to Gen3 Speed
> + **/
> + UINT32 Peg0MaxLinkSpeed : 2; ///< PCIe Link
> Speed Control for PEG 0:1:0 Root Port.
> + UINT32 Peg1MaxLinkSpeed : 2; ///<
> <b>(Test)</b> PCIe Link Speed Control for PEG 0:1:1 Root Port.
> + UINT32 Peg2MaxLinkSpeed : 2; ///<
> <b>(Test)</b> PCIe Link Speed Control for PEG 0:1:2 Root Port.
> + UINT32 Peg3MaxLinkSpeed : 2; ///<
> <b>(Test)</b> PCIe Link Speed Control for PEG 0:6:0 Root Port.
> + UINT32 RsvdBits0 : 8; ///< Offset
> 28:24 :Reserved for future use
> +
> + /**
> + Offset 32:0 :
> + <b>(Test)</b> PCIe Link Width Control
> + - <b>Auto</b> (0x0) : Maximum possible Link width (Default)
> + - X1 (0x1) : Limit Link to X1 Width
> + - X2 (0x2) : Limit Link to X2 Width
> + - X4 (0x3) : Limit Link to X4 Width
> + - X8 (0x4) : Limit Link to X8 Width
> + **/
> + UINT32 Peg0MaxLinkWidth : 3; ///< PCIe Link
> Width Control for PEG 0:1:0 Root Port.
> + UINT32 Peg1MaxLinkWidth : 3; ///<
> <b>(Test)</b> PCIe Link Width Control for PEG 0:1:1 Root Port.
> + UINT32 Peg2MaxLinkWidth : 3; ///<
> <b>(Test)</b> PCIe Link Width Control for PEG 0:1:2 Root Port.
> + UINT32 Peg3MaxLinkWidth : 3; ///<
> <b>(Test)</b> PCIe Link Width Control for PEG 0:6:0 Root Port.
> + /**
> + Offset 32:12 to 32:15 :
> + Power down unused lanes on the PEG Root Port.
> + - Disabled (0x0) : No power saving.
> + - <b>Auto</b> (0x1) : Bios will power down unused lanes based on the max
> possible link width
> + **/
> + UINT32 Peg0PowerDownUnusedLanes : 1; ///<
> Power down unused lanes on the PEG 0:1:0 Root Port.
> + UINT32 Peg1PowerDownUnusedLanes : 1; ///<
> Power down unused lanes on the PEG 0:1:1 Root Port.
> + UINT32 Peg2PowerDownUnusedLanes : 1; ///<
> Power down unused lanes on the PEG 0:1:2 Root Port.
> + UINT32 Peg3PowerDownUnusedLanes : 1; ///<
> Power down unused lanes on the PEG 0:6:0 Root Port.
> +
> + /**
> + Offset 32:16 to 32:23 :
> + <b>(Test)</b> PCIe Equalization Phase 2 Enable Control
> + - Disabled (0x0) : Disable phase 2
> + - Enabled (0x1) : Enable phase 2
> + - <b>Auto</b> (0x2) : Use the current default method (Default)
> + **/
> + UINT32 Peg0Gen3EqPh2Enable : 2; ///< Phase2
> EQ enable on the PEG 0:1:0 Root Port.
> + UINT32 Peg1Gen3EqPh2Enable : 2; ///<
> <b>(Test)</b> Phase2 EQ enable on the PEG 0:1:1 Root Port.
> + UINT32 Peg2Gen3EqPh2Enable : 2; ///<
> <b>(Test)</b> Phase2 EQ enable on the PEG 0:1:2 Root Port.
> + UINT32 Peg3Gen3EqPh2Enable : 2; ///<
> <b>(Test)</b> Phase2 EQ enable on the PEG 0:6:0 Root Port.
> + UINT32 RsvdBits1 : 8; ///< Offset
> 32:24 :Reserved for future use
> + /**
> + Offset 36:0 to 36:11 :
> + <b>(Test)</b> Select the method for performing Phase3 of Gen3
> Equalization.
> + - <b>Auto</b> (0x0) : Use the current default method (Default)
> + - HwEq (0x1) : Use Adaptive Hardware Equalization
> + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented in
> BIOS Reference Code)
> + - Static (0x3) : Use the Static EQs provided in PegGen3EndPointPreset
> array for Phase1 AND Phase3 (Instead of just Phase1)
> + - Disabled (0x4) : Bypass Equalization Phase 3
> + **/
> + UINT32 Peg0Gen3EqPh3Method : 3; ///< Phase3
> EQ method on the PEG 0:1:0 Root Port.
> + UINT32 Peg1Gen3EqPh3Method : 3; ///<
> <b>(Test)</b> Phase3 EQ method on the PEG 0:1:1 Root Port.
> + UINT32 Peg2Gen3EqPh3Method : 3; ///<
> <b>(Test)</b> Phase3 EQ method on the PEG 0:1:2 Root Port.
> + UINT32 Peg3Gen3EqPh3Method : 3; ///<
> <b>(Test)</b> Phase3 EQ method on the PEG 0:6:0 Root Port.
> + /**
> + Offset 36:12 :
> + <b>(Test)</b> Program PEG Gen3 EQ Phase1 Static Presets
> + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
> + - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming
> (Default)
> + **/
> + UINT32 PegGen3ProgramStaticEq : 1;
> + /**
> + Offset 36:13 :
> + <b>(Test)</b> Always Attempt Gen3 Software Equalization
> +
> + When enabled, Gen3 Software Equalization will be executed every boot.
> When disabled, it will be only executed if the CPU
> + or EP is changed, otherwise it is skipped and the previous EQ value will be
> re-used.
> +
> + This setting will only have an effect if Software Equalization is enabled and
> OEM Platform Code implements
> + save/restore of the PegDataPtr data (see below). If PegDataPtr is not
> saved/restored RC forces this to be enabled.
> +
> + - <b>Disabled</b> (0x0) : Reuse EQ settings saved/restored from NVRAM
> whenever possible (Default)
> + - Enabled (0x1) : Re-test and generate new EQ values every boot, not
> recommended
> + **/
> + UINT32 Gen3SwEqAlwaysAttempt : 1;
> + /**
> + Offset 36:14 to 36:16 :
> + <b>(Test)</b> Select number of TxEq presets to test in the PCIe/DMI
> Software Equalization Algorithm
> + - P7,P3,P5,P8 (0x0) : Test Presets 7, 3, 5, and 8
> + - P0-P9 (0x1) : Test Presets 0-9
> + - <b>Auto</b> (0x2) : Use the current default method (Default)
> + Auto will test Presets 7, 3, 5, and 8. It is possible for this default to change
> over time;
> + using "Auto" will ensure Reference Code always uses the latest default
> settings.
> + @warning Do not change from the default. Hard to detect issues are likely.
> + **/
> + UINT32 Gen3SwEqNumberOfPresets : 3;
> + /**
> + Offset 36:17 to 36:18:
> + <b>(Test)</b> Offset 36 Enable use of the Voltage Offset and Centering Test
> in the PCIe Software Equalization Algorithm
> + - Disabled (0x0) : Disable VOC Test
> + - Enabled (0x1) : Enable VOC Test
> + - <b>Auto</b> (0x2) : Use the current default (Default)
> + **/
> + UINT32 Gen3SwEqEnableVocTest : 2;
> + /**
> + Offset 36:19 :
> + Select when PCIe ASPM programming will happen in relation to the Oprom
> + - <b>Before</b> (0x0) : Do PCIe ASPM programming before Oprom. (Default)
> + - After (0x1) : Do PCIe ASPM programming after Oprom. This will
> require an SMI handler to save/restore ASPM settings.
> + **/
> + UINT32 InitPcieAspmAfterOprom : 1;
> + /**
> + Offset 36:20 :
> + <b>(Test)</b> PCIe Rx Compliance Testing Mode
> + - <b>Disabled</b> (0x0) : Normal Operation - Disable PCIe Rx
> Compliance testing (Default)
> + - Enabled (0x1) : PCIe Rx Compliance Test Mode - PEG controller is in
> Rx Compliance Testing Mode; it should only be set when doing PCIe compliance
> testing
> + **/
> + UINT32 PegRxCemTestingMode : 1;
> +
> + /**
> + Offset 36:21 to 36:24 :
> + <b>(Test)</b> PCIe Rx Compliance Loopback Lane
> +
> + When PegRxCemTestingMode is Enabled, the specificied Lane (0 - 15) will
> be
> + used for RxCEMLoopback.
> +
> + Default is Lane 0.
> + **/
> + UINT32 PegRxCemLoopbackLane : 4;
> + /**
> + Offset 36:25 to 36:28 :
> + <b>(Test)</b> Generate PCIe BDAT Margin Table. Set this policy to enable
> the generation and addition of PCIe margin data to the BDAT table.
> + - <b>Disabled</b> (0x0) : Normal Operation - Disable PCIe BDAT
> margin data generation (Default)
> + - PortData (0x1) : Port Data - Generate PCIe BDAT margin
> data
> + **/
> + UINT32 PegGenerateBdatMarginTable : 4;
> + /**
> + Offset 36:29 :
> + <b>(Test)</b> PCIe Non-Protocol Awareness for Rx Compliance Testing
> + - <b>Disabled</b> (0x0) : Normal Operation - Disable
> non-protocol awareness (Default)
> + - Enabled (0x1) : Non-Protocol Awareness Enabled - Enable
> non-protocol awareness for compliance testing
> + **/
> + UINT32 PegRxCemNonProtocolAwareness : 1;
> + /**
> + Offset 36:30 :
> + <b>(Test)</b> PCIe Disable Spread Spectrum Clocking. This feature should
> be TRUE only for compliance testing
> + - <b>False</b> (0x0) : Normal Operation - SSC enabled
> (Default)
> + - True (0x1) : Disable SSC - Disable SSC for
> compliance testing
> + **/
> + UINT32 PegDisableSpreadSpectrumClocking : 1;
> +
> + UINT32 RsvdBits2 : 1;
> +
> + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///<
> Offset 40 Used for programming DMI Gen3 preset values per lane. Range: 0-9,
> 8 is default for each lane
> + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///<
> Offset 44 Used for programming DMI Gen3 preset values per lane. Range: 0-9,
> 7 is default for each lane
> + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///<
> Offset 48 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is
> default for each lane
> + /**
> + Offset 52 :
> + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15).
> This setting
> + has to be specified based upon platform design and must follow the
> guideline. Default is 0.
> + **/
> +
> + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE];
> +
> + UINT8 PegGen3RootPortPreset[SA_PEG_MAX_LANE]; ///<
> Offset 54 <b>(Test)</b> Used for programming PEG Gen3 preset values per
> lane. Range: 0-9, 8 is default for each lane
> + UINT8 PegGen3EndPointPreset[SA_PEG_MAX_LANE]; ///<
> Offset 70 <b>(Test)</b> Used for programming PEG Gen3 preset values per
> lane. Range: 0-9, 7 is default for each lane
> + UINT8 PegGen3EndPointHint[SA_PEG_MAX_LANE]; ///<
> Offset 86 <b>(Test)</b> Hint value per lane for the PEG Gen3 End Point. Range:
> 0-6, 2 is default for each lane
> + /**
> + Offset 102:
> + PCIe Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15).
> This setting
> + has to be specified based upon platform design and must follow the
> guideline. Default is 12.
> + **/
> + UINT8 PegGen3RxCtlePeaking[SA_PEG_MAX_BUNDLE];
> + /**
> + Offset 110:
> + <b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535,
> default is 1000.
> + @warning Do not change from the default. Hard to detect issues are likely.
> + @note An attack on this policy could result in an apparent hang,
> + but the system will eventually boot. This variable should be protected.
> + **/
> + UINT16 Gen3SwEqJitterDwellTime;
> + /**
> + Offset 112:
> + This is a memory data pointer for saved preset search results. The reference
> code will store
> + the Gen3 Preset Search results in the SaPegHob. In order to skip the Gen3
> + preset search on boots where the PEG card configuration has not changed
> since the previous boot,
> + platform code can save the contents of the SaPegHob in DXE (When it
> present and for size reported by Header.HobLength)
> + and provide a pointer to a restored copy of that data. Default value is NULL,
> which results in a full
> + preset search every boot.
> +
> + @note An attack on this policy could prevent the PCIe display from working
> until a boot when
> + PegDataPtr is NULL or Gen3SwEqAlwaysAttempt is enabled. The variable
> used to save the
> + preset search results should be protected in a way that it can only be
> modified by the
> + platform manufacturer.
> + **/
> + VOID *PegDataPtr;
> + /**
> + Offset 116:
> + <b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535,
> default is 1.
> + @warning Do not change from the default. Hard to detect issues are likely.
> + **/
> + UINT16 Gen3SwEqJitterErrorTarget;
> +
> + /**
> + Offset 118:
> + <b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535,
> default is 10000.
> + @warning Do not change from the default. Hard to detect issues are likely.
> + @note An attack on this policy could result in an apparent hang,
> + but the system will eventually boot. This variable should be protected.
> + **/
> + UINT16 Gen3SwEqVocDwellTime;
> +
> + /**
> + Offset 120:
> + <b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535,
> default is 2.
> + @warning Do not change from the default. Hard to detect issues are likely.
> + **/
> + UINT16 Gen3SwEqVocErrorTarget;
> + /**
> + Offset 122:
> + PCIe Hot Plug Enable/Disable. It has 2 policies.
> + - Disabled (0x0) : No hotplug.
> + - Enabled (0x1) : Bios assist hotplug.
> + **/
> + UINT8 PegRootPortHPE[SA_PEG_MAX_FUN];
> + UINT8 DmiDeEmphasis; ///< Offset 125
> This field is used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB
> are the options)
> + UINT8 Rsvd0[2]; ///< Offset 126
> + /**
> + Offset 128:
> + This contains the PCIe PERST# GPIO information. This structure is required
> + for PCIe Gen3 operation. The reference code will use the information in this
> structure in
> + order to reset PCIe Gen3 devices during equalization, if necessary. Refer to
> the Platform
> + Developer's Guide (PDG) for additional details.
> + **/
> + PEG_GPIO_DATA PegGpioData;
> +
> + /**
> + Offset 156
> + <b>(Test)</b> PCIe Override RxCTLE. This feature should only be true to
> disable RxCTLE adaptive behavior for compliance testing
> + - <b>False</b> (0x0) : Normal Operation - RxCTLE
> adaptive behavior enabled (Default)
> + - True (0x1) : Override RxCTLE - Disable RxCTLE
> adaptive behavior to keep the configured RxCTLE peak values unmodified
> + From CFL onwards, modularity is introduced to this setup option so that the
> RxCTLE adaptive behavior could be controlled at the controller level.
> + Making this variable a UINT8 to accomodate the values of all controllers as
> bit definition
> + **/
> + UINT8 PegGen3RxCtleOverride;
> + UINT8 Reserved1;
> + UINT16 Reserved2;
> +
> +} PCIE_PEI_PREMEM_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _PCIE_PEI_PREMEM_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMi
> scPeiConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMi
> scPeiConfig.h
> new file mode 100644
> index 0000000000..12648b836b
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMi
> scPeiConfig.h
> @@ -0,0 +1,61 @@
> +/** @file
> + Policy details for miscellaneous configuration in System Agent
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_MISC_PEI_CONFIG_H_
> +#define _SA_MISC_PEI_CONFIG_H_
> +
> +#pragma pack(push, 1)
> +
> +#ifndef SA_MC_MAX_SOCKETS
> +#define SA_MC_MAX_SOCKETS 4
> +#endif
> +
> +#define SA_MISC_PEI_CONFIG_REVISION 1
> +
> +///
> +/// Subsystem Vendor ID / Subsystem ID
> +///
> +typedef struct _SA_DEFAULT_SVID_SID{
> + UINT16 SubSystemVendorId;
> + UINT16 SubSystemId;
> +} SA_DEFAULT_SVID_SID;
> +
> +/**
> + This configuration block is to configure SA Miscellaneous variables during
> PEI Post-Mem.\n
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
> Header
> + /**
> + Offset 28:0
> + This policy is used to control enable or disable System Agent Thermal device
> (0,4,0).
> + The default value is <b>1: TRUE</b> for WHL, and <b>0: FALSE</b> for all
> other CPU's
> + **/
> + UINT32 Device4Enable:1;
> + /**
> + Offset 28:1
> + <b>(Test)</b>This policy is used to control enable or disable System Agent
> Chap device (0,7,0).
> + <b>0=FALSE</b>,
> + 1=TRUE.
> + **/
> + UINT32 ChapDeviceEnable:1;
> + /**
> + Offset 28:2
> + For Platforms supporting Intel(R) SIPP, this policy is use control
> enable/disable Compatibility Revision ID (CRID) feature.
> + <b>0=FALSE</b>,
> + 1=TRUE
> + **/
> + UINT32 CridEnable:1;
> + UINT32 SkipPamLock:1; ///< Offset 28:3 :To skip PAM
> register locking. @note It is still recommended to set PCI Config space B0: D0:
> F0: Offset 80h[0]=1 in platform code even Silicon code skipped this.\n <b>0=All
> PAM registers will be locked in Silicon code</b>, 1=Skip lock PAM registers in
> Silicon code.
> + UINT32 EdramTestMode:2; ///< Offset 28:4 :EDRAM Test
> Mode. For EDRAM stepping - 0- EDRAM SW Disable, 1- EDRAM SW Enable, <b>
> 2- EDRAM HW Mode</b>
> + UINT32 RsvdBits0 :26; ///< Offset 28:7 :Reserved for future
> use
> +} SA_MISC_PEI_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _SA_MISC_PEI_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMi
> scPeiPreMemConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMi
> scPeiPreMemConfig.h
> new file mode 100644
> index 0000000000..2c831404ef
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMi
> scPeiPreMemConfig.h
> @@ -0,0 +1,103 @@
> +/** @file
> + Policy details for miscellaneous configuration in System Agent
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_MISC_PEI_PREMEM_CONFIG_H_
> +#define _SA_MISC_PEI_PREMEM_CONFIG_H_
> +
> +#pragma pack(push, 1)
> +
> +#ifndef SA_MC_MAX_SOCKETS
> +#define SA_MC_MAX_SOCKETS 4
> +#endif
> +
> +#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 3
> +
> +/**
> + This configuration block is to configure SA Miscellaneous variables during
> PEI Pre-Mem phase like programming
> + different System Agent BARs, TsegSize, IedSize, MmioSize required etc.
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - add BdatTestType, default is RMT
> + <b>Revision 3</b>:
> + - Remove SgSubSystemId.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
> Header
> + UINT8 SpdAddressTable[SA_MC_MAX_SOCKETS];///< Offset 28 Memory
> DIMMs' SPD address for reading SPD data. <b>example:
> SpdAddressTable[0]=0xA2(C0D0), SpdAddressTable[1]=0xA0(C0D1),
> SpdAddressTable[2]=0xA2(C1D0), SpdAddressTable[3]=0xA0(C1D1)</b>
> + VOID *S3DataPtr; ///< Offset 32 Memory data save
> pointer for S3 resume. The memory space should be allocated and filled with
> proper S3 resume data on a resume path
> + UINT32 MchBar; ///< Offset 36 Address of System
> Agent MCHBAR: <b>0xFED10000</b>
> + UINT32 DmiBar; ///< Offset 40 Address of System
> Agent DMIBAR: <b>0xFED18000</b>
> + UINT32 EpBar; ///< Offset 44 Address of System Agent
> EPBAR: <b>0xFED19000</b>
> + UINT32 SmbusBar; ///< Offset 48 Address of System
> Agent SMBUS BAR: <b>0xEFA0</b>
> + UINT32 GdxcBar; ///< Offset 52 Address of System
> Agent GDXCBAR: <b>0xFED84000</b>
> + /**
> + Offset 56 Size of TSEG in bytes. (Must be power of 2)
> + <b>0x400000</b>: 4MB for Release build (When IED enabled, it will be
> 8MB)
> + 0x1000000 : 16MB for Debug build (Regardless IED enabled or
> disabled)
> + **/
> + UINT32 TsegSize;
> + UINT32 EdramBar; ///< Offset 60 Address of System
> Agent EDRAMBAR: <b>0xFED80000</b>
> + /**
> + Offset 64
> + <b>(Test)</b> Size of IED region in bytes.
> + <b>0</b> : IED Disabled (no memory occupied)
> + 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG)
> + <b>Note: Enabling IED may also enlarge TsegSize together.</b>
> + **/
> + UINT32 IedSize;
> + UINT8 UserBd; ///< Offset 68 <b>0=Mobile/Mobile
> Halo</b>, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile Halo, 7=UP Server
> + UINT8 SgMode; ///< Offset 69 SgMode:
> <b>0=Disabled</b>, 1=SG Muxed, 2=SG Muxless, 3=PEG
> + UINT16 SgDelayAfterPwrEn; ///< Offset 70 Dgpu Delay after
> Power enable using Setup option: 0=Minimal, 1000=Maximum, <b>300=300
> microseconds</b>
> + UINT16 SgDelayAfterHoldReset; ///< Offset 72 Dgpu Delay after
> Hold Reset using Setup option: 0=Minimal, 1000=Maximum, <b>100=100
> microseconds</b>
> + UINT32 SkipExtGfxScan:1; ///< <b>(Test)</b> OFfset
> 74:0 :1=Skip External Gfx Device Scan; <b>0=Scan for external graphics
> devices</b>. Set this policy to skip External Graphics card scanning if the
> platform uses Internal Graphics only.
> + UINT32 BdatEnable:1; ///< Offset 74:1 :This field enables
> the generation of the BIOS DATA ACPI Tables: <b>0=FALSE</b>, 1=TRUE.
> + UINT32 TxtImplemented:1; ///< OFfset 74:2 :This field
> currently is used to tell MRC if it should run after TXT initializatoin completed:
> <b>0=Run without waiting for TXT</b>, 1=Run after TXT initialization by
> callback
> + /**
> + Offset 74:3 :
> + <b>(Test)</b> Scan External Discrete Graphics Devices for Legacy Only VGA
> OpROMs
> +
> + When enabled, if the primary graphics device is an external discrete
> graphics device, Si will scan the
> + graphics device for legacy only VGA OpROMs. If the primary graphics
> device only implements legacy VBIOS, then the
> + LegacyOnlyVgaOpRomDetected field in the SA_DATA_HOB will be set to 1.
> +
> + This is intended to ease the implementation of a BIOS feature to
> automatically enable CSM if the Primary Gfx device
> + only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling
> CSM won't result in no video being displayed.
> + This is useful for platforms that implement PCIe slots that allow the end
> user to install an arbitrary Gfx device.
> +
> + This setting will only take effect if SkipExtGfxScan == 0. It is ignored
> otherwise.
> +
> + - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Default)
> + - <b>Enabled</b> (0x1) : Scan External Gfx for Legacy Only VGA OpROM
> + **/
> + UINT32 ScanExtGfxForLegacyOpRom:1;
> + UINT32 RsvdBits0 :28; ///< OFfset 74:4 :Reserved for future
> use
> + UINT8 LockPTMregs; ///< <b>(Test)</b> Offset 78 Lock
> PCU Thermal Management registers: 0=FALSE, <b>1=TRUE</b>
> + UINT8 BdatTestType; ///< Offset 79 When BdatEnable is
> set to TRUE, this option selects the type of data which will be populated in the
> BIOS Data ACPI Tables: <b>0=RMT</b>, 1=RMT Per Bit, 2=Margin 2D.
> + UINT8 Rsvd1[4]; ///< Offset 80 Reserved for future use
> + /**
> + Offset 84 :
> + Size of reserved MMIO space for PCI devices\n
> + <b>0=AUTO</b>, 512=512MB, 768=768MB, 1024=1024MB, 1280=1280MB,
> 1536=1536MB, 1792=1792MB,
> + 2048=2048MB, 2304=2304MB, 2560=2560MB, 2816=2816MB,
> 3072=3072MB\n
> + When AUTO mode selected, the MMIO size will be calculated by required
> MMIO size from PCIe devices detected.
> + **/
> + UINT16 MmioSize;
> + INT16 MmioSizeAdjustment; ///< Offset 86 Increase (given
> positive value) or Decrease (given negative value) the Reserved MMIO size
> when Dynamic Tolud/AUTO mode enabled (in MBs): <b>0=no adjustment</b>
> + UINT64 AcpiReservedMemoryBase; ///< Offset 88 The Base
> address of a Reserved memory buffer allocated in previous boot for S3 resume
> used. Originally it is retrieved from AcpiVariableCompatibility variable.
> + UINT64 SystemMemoryLength; ///< Offset 96 Total system
> memory length from previous boot, this is required for S3 resume. Originally it
> is retrieved from AcpiVariableCompatibility variable.
> + UINT32 AcpiReservedMemorySize; ///< Offset 104 The Size of a
> Reserved memory buffer allocated in previous boot for S3 resume used.
> Originally it is retrieved from AcpiVariableCompatibility variable.
> + UINT32 OpRomScanTempMmioBar; ///< <b>(Test)</b> Offset
> 108 Temporary address to MMIO map OpROMs during VGA scanning. Used for
> ScanExtGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED!
> + UINT32 OpRomScanTempMmioLimit; ///< <b>(Test)</b> Offset
> 112 Limit address for OpROM MMIO range. Used for
> ScanExtGfxForLegacyOpRom feature. (OpROMScanTempMmioLimit -
> OpRomScanTempMmioBar) MUST BE >= 16MB!
> +
> + // Since the biggest element is UINT64, this structure should be aligned with
> 64 bits.
> + UINT8 Rsvd[4]; ///< Reserved for config block
> alignment.
> +} SA_MISC_PEI_PREMEM_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _SA_MISC_PEI_PREMEM_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Switc
> hableGraphicsConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Switc
> hableGraphicsConfig.h
> new file mode 100644
> index 0000000000..cc6179a61c
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Switc
> hableGraphicsConfig.h
> @@ -0,0 +1,63 @@
> +/** @file
> + Switchable Graphics policy definitions
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SWITCHABLE_GRAPHICS_CONFIG_H_
> +#define _SWITCHABLE_GRAPHICS_CONFIG_H_
> +
> +#define SWITCHABLE_GRAPHICS_CONFIG_REVISION 1
> +
> +#define GP_ENABLE 1
> +#define GP_DISABLE 0
> +
> +#pragma pack(push, 1)
> +///
> +/// GPIO Support
> +///
> +typedef enum {
> + NotSupported = 0,
> + PchGpio,
> + I2CGpio,
> +} GPIO_SUPPORT;
> +
> +///
> +/// SA GPIO Data Structure
> +///
> +typedef struct {
> + UINT8 ExpanderNo; ///< Offset 0 Expander No For I2C based GPIO
> + BOOLEAN Active; ///< Offset 1 0=Active Low; 1=Active High
> + UINT8 Rsvd0[2]; ///< Offset 2 Reserved
> + UINT32 GpioNo; ///< Offset 4 GPIO pad
> +} SA_GPIO_INFO;
> +
> +/**
> + SA PCIE RTD3 GPIO Data Structure
> +**/
> +typedef struct {
> + SA_GPIO_INFO HoldRst; ///< Offset 0 This field contain PCIe HLD RESET
> GPIO value and level information
> + SA_GPIO_INFO PwrEnable; ///< Offset 8 This field contain PCIe PWR
> Enable GPIO value and level information
> + UINT32 WakeGpioNo; ///< Offset 16 This field contain PCIe RTD3
> Device Wake GPIO Number
> + UINT8 GpioSupport; ///< Offset 20 Depends on board design the
> GPIO configuration may be different: <b>0=Not Supported</b>, 1=PCH Based,
> 2=I2C based
> + UINT8 Rsvd0[3]; ///< Offset 21
> +} SA_PCIE_RTD3_GPIO;
> +
> +/**
> + This Configuration block configures SA PCI Express 0/1/2 RTD3 GPIOs & Root
> Port.
> + Swithable Gfx/Hybrid Gfx uses the same GPIOs & Root port as PCI Express
> 0/1/2 RTD3.
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
> Header
> + SA_PCIE_RTD3_GPIO SaRtd3Pcie0Gpio; ///< Offset 28 RTD3 GPIOs used
> for PCIe0
> + SA_PCIE_RTD3_GPIO SaRtd3Pcie1Gpio; ///< Offset 52 RTD3 GPIOs used
> for PCIe1
> + SA_PCIE_RTD3_GPIO SaRtd3Pcie2Gpio; ///< Offset 76 RTD3 GPIOs used
> for PCIe2
> + UINT8 RootPortIndex; ///< Offset 124 Root Port Index
> number used for SG
> + UINT8 Rsvd0[3]; ///< Offset 125 Reserved for DWORD
> Alignment
> +} SWITCHABLE_GRAPHICS_CONFIG;
> +#pragma pack(pop)
> +#endif // _SWITCHABLE_GRAPHICS_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Vbios
> DxeConfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Vbios
> DxeConfig.h
> new file mode 100644
> index 0000000000..690ad8630a
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Vbios
> DxeConfig.h
> @@ -0,0 +1,39 @@
> +/** @file
> + VBIOS DXE policy definitions
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _VBIOS_DXE_CONFIG_H_
> +#define _VBIOS_DXE_CONFIG_H_
> +
> +#pragma pack(push, 1)
> +
> +#define VBIOS_DXE_CONFIG_REVISION 1
> +
> +/**
> + This data structure includes Switchable Graphics VBIOS configuration.
> + If Switchable Graphics/Hybrid Gfaphics feature is not supported, all the
> policies in this configuration block can be ignored.
> + The data elements should be initialized by a Platform Module.\n
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block
> Header
> + UINT8 LoadVbios : 1; ///< Offset 28:0 :This field is used to
> describe if the dGPU VBIOS needs to be loaded: <b>0=Not load</b>, 1=Load
> + UINT8 ExecuteVbios : 1; ///< Offset 28:1 :This field is used to
> describe if the dGPU VBIOS need to be executed: <b>0=Not execute</b>,
> 1=Execute
> +/**
> + Offset 28:2 :
> + This field is used to identify the source location of dGPU VBIOS\n
> + <b>1 = secondary display device VBIOS Source is PCI Card</b>\n
> + 0 = secondary display device VBIOS Source is FW Volume\n
> +**/
> + UINT8 VbiosSource : 1;
> + UINT8 RsvdBits0 : 5; ///< Offset 28:3 Reserved for future
> use
> + UINT8 Rsvd[3]; ///< Offset 29 : Reserved for DWORD
> alignment
> +} VBIOS_DXE_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _VBIOS_DXE_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/VtdC
> onfig.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/VtdC
> onfig.h
> new file mode 100644
> index 0000000000..adde1f836b
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/VtdC
> onfig.h
> @@ -0,0 +1,42 @@
> +/** @file
> + VT-d policy definitions.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _VTD_CONFIG_H_
> +#define _VTD_CONFIG_H_
> +
> +#pragma pack(push, 1)
> +
> +#define VTD_CONFIG_REVISION 2
> +
> +/**
> + The data elements should be initialized by a Platform Module.
> + The data structure is for VT-d driver initialization\n
> + <b>Revision 1</b>:
> + - Initial version.
> + <b>Revision 2</b>:
> + - Add DMA_CONTROL_GUARANTEE bit in the DMAR table
> +**/
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config
> Block Header
> + /**
> + Offset 28:0 :
> + VT-D Support can be verified by reading CAP ID register as expalined in
> BIOS Spec.
> + This policy is for debug purpose only.
> + If VT-D is not supported, all other policies in this config block will be
> ignored.
> + <b>0 = To use Vt-d</b>;
> + 1 = Avoids programming Vtd bars, Vtd overrides and DMAR table.
> + **/
> + UINT32 VtdDisable : 1;
> + UINT32 X2ApicOptOut : 1; ///< Offset 28:1 :This field is
> used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=Enable/Set and
> <b>0=Disable/Clear</b>
> + UINT32 DmaControlGuarantee : 1; ///< Offset 28:2 :This field
> is used to enable the DMA_CONTROL_GUARANTEE bit in the DMAR table.
> 1=Enable/Set and <b>0=Disable/Clear</b>
> + UINT32 RsvdBits0 : 29; ///< Offset 28:3 :Reserved bits
> for future use
> + UINT32 BaseAddress[SA_VTD_ENGINE_NUMBER]; ///< Offset 32: This
> field is used to describe the base addresses for VT-d function:
> <b>BaseAddress[0]=0xFED90000, BaseAddress[1]=0xFED92000,
> BaseAddress[2]=0xFED91000 </b>
> +} VTD_CONFIG;
> +#pragma pack(pop)
> +
> +#endif // _VTD_CONFIG_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/DmaRemappingTa
> ble.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/DmaRemappingTa
> ble.h
> new file mode 100644
> index 0000000000..a1d88cb5a2
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/DmaRemappingTa
> ble.h
> @@ -0,0 +1,77 @@
> +/** @file
> + This code defines ACPI DMA Remapping table related definitions.
> + See the System Agent BIOS specification for definition of the table.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _DMA_REMAPPING_TABLE_H_
> +#define _DMA_REMAPPING_TABLE_H_
> +
> +#include <Uefi.h>
> +#include <Base.h>
> +#include <IndustryStandard/DmaRemappingReportingTable.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +#pragma pack(1)
> +///
> +/// DMAR table signature
> +///
> +#define EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE 0x52414D44 ///<
> "DMAR"
> +#define EFI_ACPI_DMAR_TABLE_REVISION 1
> +#define EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH 0x10
> +#define EFI_ACPI_RMRR_HEADER_LENGTH 0x18
> +#define MAX_PCI_DEPTH 5
> +
> +typedef struct {
> + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER
> DeviceScopeStructureHeader;
> + EFI_ACPI_DMAR_PCI_PATH PciPath; // device, function
> +} EFI_ACPI_DEV_SCOPE_STRUCTURE;
> +
> +typedef struct {
> + EFI_ACPI_DMAR_DRHD_HEADER DrhdHeader;
> + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1];
> +} EFI_ACPI_DRHD_ENGINE1_STRUCT;
> +
> +typedef struct {
> + EFI_ACPI_DMAR_DRHD_HEADER DrhdHeader;
> + //
> + // @todo use PCD
> + //
> + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2];
> +} EFI_ACPI_DRHD_ENGINE3_STRUCT;
> +
> +typedef struct {
> + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader;
> + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2];
> +} EFI_ACPI_RMRR_USB_STRUC;
> +
> +typedef struct {
> + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader;
> + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // IGD
> +} EFI_ACPI_RMRR_IGD_STRUC;
> +
> +typedef struct {
> + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader;
> + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // CSME
> +} EFI_ACPI_RMRR_CSME_STRUC;
> +
> +typedef struct {
> + EFI_ACPI_DMAR_ANDD_HEADER AnddHeader;
> + UINT8 AcpiObjectName[20];
> +} EFI_ACPI_ANDD_STRUC;
> +
> +typedef struct {
> + EFI_ACPI_DMAR_HEADER DmarHeader;
> + EFI_ACPI_DRHD_ENGINE1_STRUCT DrhdEngine1;
> + EFI_ACPI_DRHD_ENGINE3_STRUCT DrhdEngine3;
> + EFI_ACPI_RMRR_USB_STRUC RmrrUsb;
> + EFI_ACPI_RMRR_IGD_STRUC RmrrIgd;
> + EFI_ACPI_RMRR_CSME_STRUC RmrrCsme;
> +} EFI_ACPI_DMAR_TABLE;
> +
> +#pragma pack()
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/DxeSaPoli
> cyLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/DxeSaPoli
> cyLib.h
> new file mode 100644
> index 0000000000..663b0f2202
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/DxeSaPoli
> cyLib.h
> @@ -0,0 +1,60 @@
> +/** @file
> + Prototype of the DxeSaPolicyLib library.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _DXE_SA_POLICY_LIB_H_
> +#define _DXE_SA_POLICY_LIB_H_
> +
> +#include <Protocol/SaPolicy.h>
> +
> +/**
> + This function prints the DXE phase policy.
> +
> + @param[in] SaPolicy - SA DXE Policy protocol
> +**/
> +VOID
> +SaPrintPolicyProtocol (
> + IN SA_POLICY_PROTOCOL *SaPolicy
> + )
> +;
> +
> +/**
> + CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy.
> + It allocates and zero out buffer, and fills in the Intel default settings.
> +
> + @param[out] SaPolicy The pointer to get SA Policy Protocol
> instance
> +
> + @retval EFI_SUCCESS The policy default is initialized.
> + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create
> buffer
> +**/
> +EFI_STATUS
> +EFIAPI
> +CreateSaDxeConfigBlocks(
> + IN OUT SA_POLICY_PROTOCOL **SaPolicy
> +);
> +
> +/**
> + SaInstallPolicyProtocol installs SA Policy.
> + While installed, RC assumes the Policy is ready and finalized. So please
> update and override
> + any setting before calling this function.
> +
> + @param[in] ImageHandle Image handle of this driver.
> + @param[in] SaPolicy The pointer to SA Policy Protocol
> instance
> +
> + @retval EFI_SUCCESS The policy is installed.
> + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create
> buffer
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SaInstallPolicyProtocol (
> + IN EFI_HANDLE ImageHandle,
> + IN SA_POLICY_PROTOCOL *SaPolicy
> + )
> +;
> +
> +#endif // _DXE_SA_POLICY_LIB_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolic
> yLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolic
> yLib.h
> new file mode 100644
> index 0000000000..c29d67a305
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolic
> yLib.h
> @@ -0,0 +1,87 @@
> +/** @file
> + Prototype of the PeiSaPolicy library.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PEI_SA_POLICY_LIB_H_
> +#define _PEI_SA_POLICY_LIB_H_
> +
> +#include <Ppi/SiPolicy.h>
> +#include <Library/ConfigBlockLib.h>
> +
> +/**
> + This function prints the PEI phase PreMem policy.
> +
> + @param[in] SiPolicyPreMemPpi The RC PreMem Policy PPI
> instance
> +**/
> +VOID
> +EFIAPI
> +SaPrintPolicyPpiPreMem (
> + IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi
> + );
> +
> +/**
> + This function prints the PEI phase policy.
> +
> + @param[in] SiPolicyPpi The RC Policy PPI instance
> +**/
> +VOID
> +EFIAPI
> +SaPrintPolicyPpi (
> + IN SI_POLICY_PPI *SiPolicyPpi
> + );
> +
> +/**
> + Get SA config block table total size.
> +
> + @retval Size of SA config block table
> +**/
> +UINT16
> +EFIAPI
> +SaGetConfigBlockTotalSize (
> + VOID
> + );
> +
> +/**
> + Get SA config block table total size.
> +
> + @retval Size of SA config block table
> +**/
> +UINT16
> +EFIAPI
> +SaGetConfigBlockTotalSizePreMem (
> + VOID
> + );
> +
> +/**
> + SaAddConfigBlocksPreMem add all SA config blocks.
> +
> + @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
> +
> + @retval EFI_SUCCESS The policy default is initialized.
> + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create
> buffer
> +**/
> +EFI_STATUS
> +EFIAPI
> +SaAddConfigBlocksPreMem (
> + IN VOID *ConfigBlockTableAddress
> + );
> +
> +/**
> + SaAddConfigBlocks add all SA config blocks.
> +
> + @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
> +
> + @retval EFI_SUCCESS The policy default is initialized.
> + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create
> buffer
> +**/
> +EFI_STATUS
> +EFIAPI
> +SaAddConfigBlocks (
> + IN VOID *ConfigBlockTableAddress
> + );
> +
> +#endif // _PEI_SA_POLICY_LIBRARY_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/SaPlatfor
> mLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/SaPlatfor
> mLib.h
> new file mode 100644
> index 0000000000..a1289abe81
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/SaPlatfor
> mLib.h
> @@ -0,0 +1,88 @@
> +/** @file
> + Header file for SaPlatformLib.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_PLATFORM_LIB_H_
> +#define _SA_PLATFORM_LIB_H_
> +
> +#include <SaAccess.h>
> +#include <CpuAccess.h>
> +
> +/**
> + Determine if PCH Link is DMI/OPI
> +
> + @param[in] CpuModel CPU model
> +
> + @retval TRUE DMI
> + @retval FALSE OPI
> +**/
> +BOOLEAN
> +IsPchLinkDmi (
> + IN CPU_FAMILY CpuModel
> + );
> +
> +/**
> + Returns the number of DMI lanes for current CPU
> +
> + @retval UINT8
> +**/
> +UINT8
> +GetMaxDmiLanes (
> + );
> +
> +
> +/**
> + Returns the number of DMI bundles for current CPU
> +
> + @retval UINT8
> +**/
> +UINT8
> +GetMaxDmiBundles (
> + );
> +
> +
> +/**
> + Returns the function numbers for current CPU
> +
> + @retval UINT8
> +**/
> +UINT8
> +GetMaxPegFuncs (
> + );
> +
> +
> +/**
> + Returns the number of DMI lanes for current CPU
> +
> + @retval UINT8
> +**/
> +UINT8
> +GetMaxPegLanes (
> + );
> +
> +
> +/**
> + Returns the number of DMI bundles for current CPU
> +
> + @retval UINT8
> +**/
> +UINT8
> +GetMaxPegBundles (
> + );
> +
> +/**
> + Checks if PEG port is present
> +
> + @retval TRUE PEG is presented
> + @retval FALSE PEG is not presented
> +**/
> +BOOLEAN
> +IsPegPresent (
> + VOID
> + );
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/MemInfoHob.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/MemInfoHob.h
> new file mode 100644
> index 0000000000..da285bbcba
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/MemInfoHob.h
> @@ -0,0 +1,259 @@
> +/** @file
> + This file contains definitions required for creation of
> + Memory S3 Save data, Memory Info data and Memory Platform
> + data hobs.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _MEM_INFO_HOB_H_
> +#define _MEM_INFO_HOB_H_
> +
> +#include <Uefi/UefiMultiPhase.h>
> +#include <Pi/PiBootMode.h>
> +#include <Pi/PiHob.h>
> +
> +#pragma pack (push, 1)
> +
> +extern EFI_GUID gSiMemoryS3DataGuid;
> +extern EFI_GUID gSiMemoryInfoDataGuid;
> +extern EFI_GUID gSiMemoryPlatformDataGuid;
> +
> +#define MAX_NODE 1
> +#define MAX_CH 2
> +#define MAX_DIMM 2
> +
> +///
> +/// Host reset states from MRC.
> +///
> +#define WARM_BOOT 2
> +
> +#define R_MC_CHNL_RANK_PRESENT 0x7C
> +#define B_RANK0_PRS BIT0
> +#define B_RANK1_PRS BIT1
> +#define B_RANK2_PRS BIT4
> +#define B_RANK3_PRS BIT5
> +
> +///
> +/// Defines taken from MRC so avoid having to include MrcInterface.h
> +///
> +
> +//
> +// Matches MAX_SPD_SAVE define in MRC
> +//
> +#ifndef MAX_SPD_SAVE
> +#define MAX_SPD_SAVE 29
> +#endif
> +
> +//
> +// MRC version description.
> +//
> +typedef struct {
> + UINT8 Major; ///< Major version number
> + UINT8 Minor; ///< Minor version number
> + UINT8 Rev; ///< Revision number
> + UINT8 Build; ///< Build number
> +} SiMrcVersion;
> +
> +//
> +// Matches MrcChannelSts enum in MRC
> +//
> +#ifndef CHANNEL_NOT_PRESENT
> +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the
> controller.
> +#endif
> +#ifndef CHANNEL_DISABLED
> +#define CHANNEL_DISABLED 1 // There is a channel present but it is
> disabled.
> +#endif
> +#ifndef CHANNEL_PRESENT
> +#define CHANNEL_PRESENT 2 // There is a channel present and it is
> enabled.
> +#endif
> +
> +//
> +// Matches MrcDimmSts enum in MRC
> +//
> +#ifndef DIMM_ENABLED
> +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be
> detected.
> +#endif
> +#ifndef DIMM_DISABLED
> +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of
> presence.
> +#endif
> +#ifndef DIMM_PRESENT
> +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank
> pair and it will be used.
> +#endif
> +#ifndef DIMM_NOT_PRESENT
> +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank
> pair.
> +#endif
> +
> +//
> +// Matches MrcBootMode enum in MRC
> +//
> +#ifndef bmCold
> +#define bmCold 0 // Cold boot
> +#endif
> +#ifndef bmWarm
> +#define bmWarm 1 // Warm boot
> +#endif
> +#ifndef bmS3
> +#define bmS3 2 // S3 resume
> +#endif
> +#ifndef bmFast
> +#define bmFast 3 // Fast boot
> +#endif
> +
> +//
> +// Matches MrcDdrType enum in MRC
> +//
> +#ifndef MRC_DDR_TYPE_DDR4
> +#define MRC_DDR_TYPE_DDR4 0
> +#endif
> +#ifndef MRC_DDR_TYPE_DDR3
> +#define MRC_DDR_TYPE_DDR3 1
> +#endif
> +#ifndef MRC_DDR_TYPE_LPDDR3
> +#define MRC_DDR_TYPE_LPDDR3 2
> +#endif
> +#ifndef MRC_DDR_TYPE_UNKNOWN
> +#define MRC_DDR_TYPE_UNKNOWN 3
> +#endif
> +
> +#define MAX_PROFILE_NUM 4 // number of memory profiles supported
> +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
> +
> +//
> +// DIMM timings
> +//
> +typedef struct {
> + UINT32 tCK; ///< Memory cycle time, in femtoseconds.
> + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's
> command rate mode.
> + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS
> latency.
> + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's
> minimum CAS write latency time.
> + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's
> minimum four activate window delay time.
> + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's
> minimum active to precharge delay time.
> + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's
> minimum RAS# to CAS# delay time and Row Precharge delay time.
> + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's
> minimum Average Periodic Refresh Interval.
> + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's
> minimum refresh recovery delay time.
> + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's
> minimum per bank refresh recovery delay time.
> + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's
> minimum refresh recovery delay time.
> + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's
> minimum refresh recovery delay time.
> + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's
> minimum row precharge delay time for all banks.
> + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's
> minimum row active to row active delay time.
> + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's
> minimum row active to row active delay time for same bank groups.
> + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's
> minimum row active to row active delay time for different bank groups.
> + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's
> minimum internal read to precharge command delay time.
> + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's
> minimum write recovery time.
> + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's
> minimum internal write to read command delay time.
> + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's
> minimum internal write to read command delay time for same bank groups.
> + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's
> minimum internal write to read command delay time for different bank
> groups.
> + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's
> minimum CAS-to-CAS delay for same bank group.
> +} MRC_CH_TIMING;
> +
> +typedef struct {
> + UINT8 SG; ///< Number of tCK cycles between transactions in the
> same bank group.
> + UINT8 DG; ///< Number of tCK cycles between transactions when
> switching bank groups.
> + UINT8 DR; ///< Number of tCK cycles between transactions when
> switching between Ranks (in the same DIMM).
> + UINT8 DD; ///< Number of tCK cycles between transactions when
> switching between DIMMs.
> +} MRC_TA_TIMING;
> +
> +///
> +/// Memory SMBIOS & OC Memory Data Hob
> +///
> +typedef struct {
> + UINT8 Status; ///< See MrcDimmStatus for the
> definition of this field.
> + UINT8 DimmId;
> + UINT32 DimmCapacity; ///< DIMM size in MBytes.
> + UINT16 MfgId;
> + UINT8 ModulePartNum[20]; ///< Module part number for
> DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20
> bytes
> + UINT8 RankInDimm; ///< The number of ranks in this
> DIMM.
> + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType
> information needed for SMBIOS structure creation.
> + UINT8 SpdModuleType; ///< Save SPD ModuleType
> information needed for SMBIOS structure creation.
> + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD
> ModuleMemoryBusWidth information needed for SMBIOS structure creation.
> + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing
> information needed for SMBIOS structure creation.
> + UINT16 Speed; ///< The maximum capable speed of
> the device, in MHz.
> +} DIMM_INFO;
> +
> +typedef struct {
> + UINT8 Status; ///< Indicates whether this channel
> should be used.
> + UINT8 ChannelId;
> + UINT8 DimmCount; ///< Number of valid DIMMs that
> exist in the channel.
> + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing
> values.
> + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output
> characteristics.
> + MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around
> Timings
> + MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around
> Timings
> + MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around
> Timings
> + MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around
> Timings
> +} CHANNEL_INFO;
> +
> +typedef struct {
> + UINT8 Status; ///< Indicates whether this controller
> should be used.
> + UINT16 DeviceId; ///< The PCI device id of this memory
> controller.
> + UINT8 RevisionId; ///< The PCI revision id of this memory
> controller.
> + UINT8 ChannelCount; ///< Number of valid channels that
> exist on the controller.
> + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are
> channel level definitions.
> + MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to
> CHANNEL_INFO. Read-to-Read Turn Around Timings
> + MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to
> CHANNEL_INFO. Read-to-Write Turn Around Timings
> + MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to
> CHANNEL_INFO. Write-to-Read Turn Around Timings
> + MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to
> CHANNEL_INFO. Write-to-Write Turn Around Timings
> +} CONTROLLER_INFO;
> +
> +typedef struct {
> + UINT8 Revision;
> + UINT16 DataWidth; ///< Data width, in bits, of this
> memory device
> + /** As defined in SMBIOS 3.0 spec
> + Section 7.18.2 and Table 75
> + **/
> + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or
> LPDDR3
> + UINT16 MaximumMemoryClockSpeed;///< The maximum capable
> speed of the device, in megahertz (MHz)
> + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock
> speed to the memory device, in megahertz (MHz)
> + /** As defined in SMBIOS 3.0 spec
> + Section 7.17.3 and Table 72
> + **/
> + UINT8 ErrorCorrectionType;
> +
> + SiMrcVersion Version;
> + BOOLEAN EccSupport;
> + UINT8 MemoryProfile;
> + UINT32 TotalPhysicalMemorySize;
> + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the
> tCK value read from SPD XMP profiles if they exist.
> + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs
> are detected, this will indicate which XMP Profiles are common among all
> DIMMs.
> + UINT8 Ratio;
> + UINT8 RefClk;
> + UINT32 VddVoltage[MAX_PROFILE_NUM];
> + CONTROLLER_INFO Controller[MAX_NODE];
> +} MEMORY_INFO_DATA_HOB;
> +
> +/**
> + Memory Platform Data Hob
> +
> + <b>Revision 1:</b>
> + - Initial version.
> + <b>Revision 2:</b>
> + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize,
> PciEBaseAddress fields
> +**/
> +typedef struct {
> + UINT8 Revision;
> + UINT8 Reserved[3];
> + UINT32 BootMode;
> + UINT32 TsegSize;
> + UINT32 TsegBase;
> + UINT32 PrmrrSize;
> + UINT32 PrmrrBase;
> + UINT32 GttBase;
> + UINT32 MmioSize;
> + UINT32 PciEBaseAddress;
> + UINT32 GdxcIotBase;
> + UINT32 GdxcIotSize;
> + UINT32 GdxcMotBase;
> + UINT32 GdxcMotSize;
> +} MEMORY_PLATFORM_DATA;
> +
> +typedef struct {
> + EFI_HOB_GUID_TYPE EfiHobGuidType;
> + MEMORY_PLATFORM_DATA Data;
> + UINT8 *Buffer;
> +} MEMORY_PLATFORM_DATA_HOB;
> +
> +#pragma pack (pop)
> +
> +#endif // _MEM_INFO_HOB_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Gr
> aphicsInitLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Gr
> aphicsInitLib.h
> new file mode 100644
> index 0000000000..ff7cfa838f
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Gr
> aphicsInitLib.h
> @@ -0,0 +1,15 @@
> +/** @file
> + Graphics header file
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _GRAPHICS_INIT_H_
> +#define _GRAPHICS_INIT_H_
> +
> +#include <SaPolicyCommon.h>
> +#include <Ppi/SiPolicy.h>
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Le
> gacyRegion.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Le
> gacyRegion.h
> new file mode 100644
> index 0000000000..497c860824
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Le
> gacyRegion.h
> @@ -0,0 +1,33 @@
> +/** @file
> + This code supports a private implementation of the Legacy Region protocol.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _LEGACY_REGION_H_
> +#define _LEGACY_REGION_H_
> +
> +#include <Uefi.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/DebugLib.h>
> +#include <Protocol/LegacyRegion2.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +#include <Protocol/Cpu.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <SaAccess.h>
> +
> +/**
> + Install Driver to produce Legacy Region protocol.
> +
> + @param[in] ImageHandle Handle for the image of this driver
> +
> + @retval EFI_SUCCESS - Legacy Region protocol installed
> + @retval Other - No protocol installed, unload driver.
> +**/
> +EFI_STATUS
> +LegacyRegionInstall (
> + IN EFI_HANDLE ImageHandle
> + );
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Pe
> iCpuTraceHubLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Pe
> iCpuTraceHubLib.h
> new file mode 100644
> index 0000000000..8bf46528ab
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Pe
> iCpuTraceHubLib.h
> @@ -0,0 +1,23 @@
> +/** @file
> + Header file for North TraceHub Lib.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _NORTH_TRACEHUB_LIB_H_
> +#define _NORTH_TRACEHUB_LIB_H_
> +
> +#include <SaPolicyCommon.h>
> +#include <SaAccess.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/PciSegmentLib.h>
> +#include <IndustryStandard/Pci.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/CpuPlatformLib.h>
> +#include <Library/MtrrLib.h>
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Sa
> PcieLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Sa
> PcieLib.h
> new file mode 100644
> index 0000000000..19dd634a35
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Sa
> PcieLib.h
> @@ -0,0 +1,70 @@
> +/** @file
> + Defines and prototypes for the System Agent PCIe library module
> + This library is expected to share between DXE and SMM drivers.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_PCIE_LIB_H_
> +#define _SA_PCIE_LIB_H_
> +
> +#include <Library/S3BootScriptLib.h>
> +#include <Protocol/SaPolicy.h>
> +
> +#define MAX_SUPPORTED_ROOT_BRIDGE_NUMBER 3
> +#define MAX_SUPPORTED_DEVICE_NUMBER 192
> +
> +/**
> + Enumerate all end point devices connected to root bridge ports and record
> their MMIO base address
> +
> + @exception EFI_UNSUPPORTED PCIe capability structure not found
> + @retval EFI_SUCCESS All done successfully
> +**/
> +EFI_STATUS
> +EnumerateAllPcieDevices (
> + VOID
> + );
> +
> +/**
> + Sets Common Clock, TCx-VC0 mapping, and Max Payload for PCIe
> +**/
> +VOID
> +SaPcieConfigBeforeOpRom (
> + VOID
> + );
> +
> +/**
> + This function does all SA ASPM initialization
> +**/
> +VOID
> +SaAspm (
> + VOID
> + );
> +
> +/**
> + This function checks PEG end point device for extended tag capability and
> enables them if they are.
> +**/
> +VOID
> +EnableExtendedTag (
> + VOID
> + );
> +
> +/**
> + This function handles SA S3 resume
> +**/
> +VOID
> +SaS3Resume (
> + VOID
> + );
> +
> +/**
> + Wrapper function for all SA S3 resume tasks which can be a callback
> function.
> +**/
> +VOID
> +SaS3ResumeCallback (
> + VOID
> + );
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protocol/
> SaIotrapSmi.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protocol/
> SaIotrapSmi.h
> new file mode 100644
> index 0000000000..2c765b09b8
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protocol/
> SaIotrapSmi.h
> @@ -0,0 +1,36 @@
> +/** @file
> + This file defines the SA Iotrap SMI Protocol to provide the
> + I/O address for registered Iotrap SMI.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_IOTRAP_SMI_PROTOCOL_H_
> +#define _SA_IOTRAP_SMI_PROTOCOL_H_
> +
> +//
> +// Extern the GUID for protocol users.
> +//
> +extern EFI_GUID gSaIotrapSmiProtocolGuid;
> +
> +#define SA_IOTRAP_SMI_PROTOCOL_REVISION_1 1
> +
> +//
> +// SA IO Trap SMI Protocol definition (Private protocol for RC internal use
> only)
> +//
> +typedef struct {
> +/*
> + Protocol revision number
> + Any backwards compatible changes to this protocol will result in an update
> in the revision number
> + Major changes will require publication of a new protocol
> +
> + <b>Revision 1</b>:
> + - First version
> +*/
> + UINT8 Revision;
> + UINT16 SaIotrapSmiAddress;
> +} SA_IOTRAP_SMI_PROTOCOL;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protocol/
> SaNvsArea.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protocol/
> SaNvsArea.h
> new file mode 100644
> index 0000000000..1bae2d95e5
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protocol/
> SaNvsArea.h
> @@ -0,0 +1,31 @@
> +/** @file
> + Definition of the System Agent global NVS area protocol.
> + This protocol publishes the address and format of a global ACPI NVS buffer
> + used as a communications buffer between SMM/DXE/PEI code and ASL
> code.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SYSTEM_AGENT_NVS_AREA_H_
> +#define _SYSTEM_AGENT_NVS_AREA_H_
> +
> +//
> +// SA NVS Area definition
> +//
> +#include <Private/SaNvsAreaDef.h>
> +
> +//
> +// Extern the GUID for protocol users.
> +//
> +extern EFI_GUID gSaNvsAreaProtocolGuid;
> +
> +///
> +/// System Agent Global NVS Area Protocol
> +///
> +typedef struct {
> + SYSTEM_AGENT_NVS_AREA *Area; ///< System Agent Global NVS
> Area Structure
> +} SYSTEM_AGENT_NVS_AREA_PROTOCOL;
> +
> +#endif // _SYSTEM_AGENT_NVS_AREA_H_
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaConfigH
> ob.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaConfigH
> ob.h
> new file mode 100644
> index 0000000000..f1b72488ca
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaConfigH
> ob.h
> @@ -0,0 +1,89 @@
> +/** @file
> + The GUID definition for SaConfigHob
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_CONFIG_HOB_H_
> +#define _SA_CONFIG_HOB_H_
> +
> +#include <SaAccess.h>
> +#include <Base.h>
> +
> +extern EFI_GUID gSaConfigHobGuid;
> +
> +#pragma pack (push,1)
> +///
> +#define DPR_DIRECTORY_MAX 2 ///< DPR Maximum Size
> +/// DPR directory entry definition
> +///
> +typedef struct {
> + UINT8 Type; ///< DPR Directory Type
> + UINT8 Size; ///< DPR Size in MB
> + UINT32 PhysBase; ///< Must be 4K aligned (bits 11..0 must be clear)
> + UINT16 Reserved; ///< Must be 0
> +} DPR_DIRECTORY_ENTRY;
> +
> +///
> +/// The data elements should be initialized by a Platform Module.
> +/// The data structure is for VT-d driver initialization
> +///
> +typedef struct {
> + BOOLEAN VtdDisable; ///< 1 = Avoids
> programming Vtd bars, Vtd overrides and DMAR table
> + UINT32 BaseAddress[SA_VTD_ENGINE_NUMBER]; ///< This field
> is used to describe the base addresses for VT-d function
> + BOOLEAN X2ApicOptOut; ///< This field is used to
> enable the X2APIC_OPT_OUT bit in the DMAR table. <b>1=Enable/Set</b> and
> 0=Disable/Clear
> + BOOLEAN InterruptRemappingSupport; ///< This field is
> used to indicate Interrupt Remapping supported or not
> +} SA_VTD_CONFIGURATION_HOB;
> +
> +///
> +/// SA GPIO Data Structure
> +///
> +typedef struct {
> + UINT8 ExpanderNo; ///< =Expander No For I2C based GPIO
> + UINT32 GpioNo; ///< GPIO pad
> + BOOLEAN Active; ///< 0=Active Low; 1=Active High
> +} SA_GPIO;
> +
> +///
> +/// SA PCIE RTD3 GPIO Data Structure
> +///
> +typedef struct {
> + UINT8 GpioSupport; ///< 0=Not Supported; 1=PCH based;
> 2=I2C Based
> + SA_GPIO HoldRst; ///< Offset 8 This field contain PCIe HLD
> RESET GPIO value and level information
> + SA_GPIO PwrEnable; ///< This field contain PCIe PWR Enable
> GPIO value and level information
> + UINT32 WakeGpioNo; ///< This field contain PCIe RTD3 Device
> Wake GPIO number
> +} PCIE_RTD3_GPIO;
> +
> +///
> +/// SG Info HOB
> +///
> +typedef struct {
> + SG_MODE SgMode;
> + UINT8 RootPortIndex;
> + PCIE_RTD3_GPIO Rtd3Pcie0Gpio;
> + PCIE_RTD3_GPIO Rtd3Pcie1Gpio;
> + PCIE_RTD3_GPIO Rtd3Pcie2Gpio;
> + UINT16 DelayAfterPwrEn;
> + UINT16 DelayAfterHoldReset;
> +} SA_RTD3;
> +
> +///
> +/// System Agent Config Hob
> +///
> +typedef struct {
> + EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID
> Hob type structure for gSaConfigHobGuid
> + DPR_DIRECTORY_ENTRY DprDirectory[DPR_DIRECTORY_MAX];
> ///< DPR directory entry definition
> + BOOLEAN InitPcieAspmAfterOprom; ///<
> 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
> + SA_RTD3 SaRtd3; ///< SG Info HOB
> + UINT8 ApertureSize; ///< Aperture size
> value
> + UINT8 IpuAcpiMode; ///< IPU ACPI
> mode: 0=Disabled, 1=IGFX Child device, 2=ACPI device
> + SA_VTD_CONFIGURATION_HOB VtdData; ///< VT-d
> Data HOB
> + BOOLEAN CridEnable; ///< This field
> inidicates if CRID is enabled or disabled (to support Intel(R) SIPP)
> + BOOLEAN SkipPamLock; ///< 0=All PAM
> registers will be locked in System Agent code, 1=Do not lock PAM registers in
> System Agent code.
> + UINT8 PowerDownUnusedBundles[SA_PEG_MAX_FUN];
> ///< PCIe power down unused bundles support
> + UINT8 PegMaxPayload[SA_PEG_MAX_FUN]; ///< PEG
> Max Pay Load Size (0xFF: Auto, 0:128B, 1:256B)
> +} SA_CONFIG_HOB;
> +#pragma pack (pop)
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaNvsAre
> aDef.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaNvsAre
> aDef.h
> new file mode 100644
> index 0000000000..095942d483
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaNvsAre
> aDef.h
> @@ -0,0 +1,151 @@
> +/** @file
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> + //
> + // Define SA NVS Area operatino region.
> + //
> +
> +#ifndef _SA_NVS_AREA_DEF_H_
> +#define _SA_NVS_AREA_DEF_H_
> +
> +#pragma pack (push,1)
> +typedef struct {
> + UINT32 IgdOpRegionAddress; ///< Offset 0 IGD
> OpRegion base address
> + UINT8 GfxTurboIMON; ///< Offset 4 IMON
> Current Value
> + UINT8 IgdState; ///< Offset 5 IGD State
> (Primary Display = 1)
> + UINT8 IgdBootType; ///< Offset 6 IGD Boot
> Display Device
> + UINT8 IgdPanelType; ///< Offset 7 IGD Panel
> Type CMOS option
> + UINT8 IgdPanelScaling; ///< Offset 8 IGD Panel
> Scaling
> + UINT8 IgdBiaConfig; ///< Offset 9 IGD BIA
> Configuration
> + UINT8 IgdSscConfig; ///< Offset 10 IGD SSC
> Configuration
> + UINT8 IgdDvmtMemSize; ///< Offset 11 IGD DVMT
> Memory Size
> + UINT8 IgdFunc1Enable; ///< Offset 12 IGD Function
> 1 Enable
> + UINT8 IgdHpllVco; ///< Offset 13 HPLL VCO
> + UINT8 IgdSciSmiMode; ///< Offset 14 GMCH
> SMI/SCI mode (0=SCI)
> + UINT8 IgdPAVP; ///< Offset 15 IGD PAVP data
> + UINT8 CurrentDeviceList; ///< Offset 16 Current
> Attached Device List
> + UINT16 CurrentDisplayState; ///< Offset 17 Current
> Display State
> + UINT16 NextDisplayState; ///< Offset 19 Next Display
> State
> + UINT8 NumberOfValidDeviceId; ///< Offset 21 Number
> of Valid Device IDs
> + UINT32 DeviceId1; ///< Offset 22 Device ID 1
> + UINT32 DeviceId2; ///< Offset 26 Device ID 2
> + UINT32 DeviceId3; ///< Offset 30 Device ID 3
> + UINT32 DeviceId4; ///< Offset 34 Device ID 4
> + UINT32 DeviceId5; ///< Offset 38 Device ID 5
> + UINT32 DeviceId6; ///< Offset 42 Device ID 6
> + UINT32 DeviceId7; ///< Offset 46 Device ID 7
> + UINT32 DeviceId8; ///< Offset 50 Device ID 8
> + UINT32 DeviceId9; ///< Offset 54 Device ID 9
> + UINT32 DeviceId10; ///< Offset 58 Device ID 10
> + UINT32 DeviceId11; ///< Offset 62 Device ID 11
> + UINT32 DeviceId12; ///< Offset 66 Device ID 12
> + UINT32 DeviceId13; ///< Offset 70 Device ID 13
> + UINT32 DeviceId14; ///< Offset 74 Device ID 14
> + UINT32 DeviceId15; ///< Offset 78 Device ID 15
> + UINT32 DeviceIdX; ///< Offset 82 Device ID for
> eDP device
> + UINT32 NextStateDid1; ///< Offset 86 Next state
> DID1 for _DGS
> + UINT32 NextStateDid2; ///< Offset 90 Next state
> DID2 for _DGS
> + UINT32 NextStateDid3; ///< Offset 94 Next state
> DID3 for _DGS
> + UINT32 NextStateDid4; ///< Offset 98 Next state
> DID4 for _DGS
> + UINT32 NextStateDid5; ///< Offset 102 Next state
> DID5 for _DGS
> + UINT32 NextStateDid6; ///< Offset 106 Next state
> DID6 for _DGS
> + UINT32 NextStateDid7; ///< Offset 110 Next state
> DID7 for _DGS
> + UINT32 NextStateDid8; ///< Offset 114 Next state
> DID8 for _DGS
> + UINT32 NextStateDidEdp; ///< Offset 118 Next state
> DID for eDP
> + UINT8 LidState; ///< Offset 122 Lid State (Lid
> Open = 1)
> + UINT32 AKsv0; ///< Offset 123 First four bytes
> of AKSV (manufacturing mode)
> + UINT8 AKsv1; ///< Offset 127 Fifth byte of
> AKSV (manufacturing mode)
> + UINT8 BrightnessPercentage; ///< Offset 128 Brightness
> Level Percentage
> + UINT8 AlsEnable; ///< Offset 129 Ambient Light
> Sensor Enable
> + UINT8 AlsAdjustmentFactor; ///< Offset 130 Ambient
> Light Adjusment Factor
> + UINT8 LuxLowValue; ///< Offset 131 LUX Low
> Value
> + UINT8 LuxHighValue; ///< Offset 132 LUX High
> Value
> + UINT8 ActiveLFP; ///< Offset 133 Active LFP
> + UINT8 IpuAcpiMode; ///< Offset 134 IPU ACPI
> device type (0=Disabled, 1=AVStream virtual device as child of GFX)
> + UINT8 EdpValid; ///< Offset 135 Check for eDP
> display device
> + UINT8 SgMode; ///< Offset 136 SG Mode
> (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=DGPU Only)
> + UINT8 SgFeatureList; ///< Offset 137 SG Feature
> List
> + UINT8 Pcie0GpioSupport; ///< Offset 138 PCIe0 GPIO
> Support (0=Disabled, 1=PCH Based, 2=I2C Based)
> + UINT8 Pcie0HoldRstExpanderNo; ///< Offset 139 PCIe0
> HLD RST IO Expander Number
> + UINT32 Pcie0HoldRstGpioNo; ///< Offset 140 PCIe0
> HLD RST GPIO Number
> + UINT8 Pcie0HoldRstActiveInfo; ///< Offset 144 PCIe0 HLD
> RST GPIO Active Information
> + UINT8 Pcie0PwrEnExpanderNo; ///< Offset 145 PCIe0
> PWR Enable IO Expander Number
> + UINT32 Pcie0PwrEnGpioNo; ///< Offset 146 PCIe0
> PWR Enable GPIO Number
> + UINT8 Pcie0PwrEnActiveInfo; ///< Offset 150 PCIe0 PWR
> Enable GPIO Active Information
> + UINT8 Pcie1GpioSupport; ///< Offset 151 PCIe1 GPIO
> Support (0=Disabled, 1=PCH Based, 2=I2C Based)
> + UINT8 Pcie1HoldRstExpanderNo; ///< Offset 152 PCIe1
> HLD RST IO Expander Number
> + UINT32 Pcie1HoldRstGpioNo; ///< Offset 153 PCIe1
> HLD RST GPIO Number
> + UINT8 Pcie1HoldRstActiveInfo; ///< Offset 157 PCIe1 HLD
> RST GPIO Active Information
> + UINT8 Pcie1PwrEnExpanderNo; ///< Offset 158 PCIe1
> PWR Enable IO Expander Number
> + UINT32 Pcie1PwrEnGpioNo; ///< Offset 159 PCIe1
> PWR Enable GPIO Number
> + UINT8 Pcie1PwrEnActiveInfo; ///< Offset 163 PCIe1 PWR
> Enable GPIO Active Information
> + UINT8 Pcie2GpioSupport; ///< Offset 164 PCIe2 GPIO
> Support (0=Disabled, 1=PCH Based, 2=I2C Based)
> + UINT8 Pcie2HoldRstExpanderNo; ///< Offset 165 PCIe2
> HLD RST IO Expander Number
> + UINT32 Pcie2HoldRstGpioNo; ///< Offset 166 PCIe2
> HLD RST GPIO Number
> + UINT8 Pcie2HoldRstActiveInfo; ///< Offset 170 PCIe2 HLD
> RST GPIO Active Information
> + UINT8 Pcie2PwrEnExpanderNo; ///< Offset 171 PCIe2
> PWR Enable IO Expander Number
> + UINT32 Pcie2PwrEnGpioNo; ///< Offset 172 PCIe2
> PWR Enable GPIO Number
> + UINT8 Pcie2PwrEnActiveInfo; ///< Offset 176 PCIe2 PWR
> Enable GPIO Active Information
> + UINT16 DelayAfterPwrEn; ///< Offset 177 Delay after
> power enable for PCIe
> + UINT16 DelayAfterHoldReset; ///< Offset 179 Delay
> after Hold Reset for PCIe
> + UINT8 Pcie0EpCapOffset; ///< Offset 181 PCIe0
> Endpoint Capability Structure Offset
> + UINT32 XPcieCfgBaseAddress; ///< Offset 182 Any
> Device's PCIe Config Space Base Address
> + UINT16 GpioBaseAddress; ///< Offset 186 GPIO Base
> Address
> + UINT32 NvIgOpRegionAddress; ///< Offset 188 NVIG
> opregion address
> + UINT32 NvHmOpRegionAddress; ///< Offset 192 NVHM
> opregion address
> + UINT32 ApXmOpRegionAddress; ///< Offset 196 AMDA
> opregion address
> + UINT8 Peg0LtrEnable; ///< Offset 200 Latency
> Tolerance Reporting Enable
> + UINT8 Peg0ObffEnable; ///< Offset 201 Optimized
> Buffer Flush and Fill
> + UINT8 Peg1LtrEnable; ///< Offset 202 Latency
> Tolerance Reporting Enable
> + UINT8 Peg1ObffEnable; ///< Offset 203 Optimized
> Buffer Flush and Fill
> + UINT8 Peg2LtrEnable; ///< Offset 204 Latency
> Tolerance Reporting Enable
> + UINT8 Peg2ObffEnable; ///< Offset 205 Optimized
> Buffer Flush and Fill
> + UINT8 Peg3LtrEnable; ///< Offset 206 Latency
> Tolerance Reporting Enable
> + UINT8 Peg3ObffEnable; ///< Offset 207 Optimized
> Buffer Flush and Fill
> + UINT16 PegLtrMaxSnoopLatency; ///< Offset 208 SA Peg
> Latency Tolerance Reporting Max Snoop Latency
> + UINT16 PegLtrMaxNoSnoopLatency; ///< Offset 210 SA Peg
> Latency Tolerance Reporting Max No Snoop Latency
> + UINT8 Peg0PowerDownUnusedBundles; ///< Offset 212
> Peg0 Unused Bundle Control
> + UINT8 Peg1PowerDownUnusedBundles; ///< Offset 213
> Peg1 Unused Bundle Control
> + UINT8 Peg2PowerDownUnusedBundles; ///< Offset 214
> Peg2 Unused Bundle Control
> + UINT8 Peg3PowerDownUnusedBundles; ///< Offset 215
> Peg3 Unused Bundle Control
> + UINT8 PackageCstateLimit; ///< Offset 216 The lowest
> C-state for the package
> + UINT8 PwrDnBundlesGlobalEnable; ///< Offset 217 Pegx
> Unused Bundle Control Global Enable (0=Disabled, 1=Enabled)
> + UINT64 Mmio64Base; ///< Offset 218 Base of
> above 4GB MMIO resource
> + UINT64 Mmio64Length; ///< Offset 226 Length of
> above 4GB MMIO resource
> + UINT32 CpuIdInfo; ///< Offset 234 CPU ID info to
> get Family Id or Stepping
> + UINT8 Pcie1EpCapOffset; ///< Offset 238 PCIe1
> Endpoint Capability Structure Offset
> + UINT8 Pcie2EpCapOffset; ///< Offset 239 PCIe2
> Endpoint Capability Structure Offset
> + UINT8 Pcie0SecBusNum; ///< Offset 240 PCIe0
> Secondary Bus Number (PCIe0 Endpoint Bus Number)
> + UINT8 Pcie1SecBusNum; ///< Offset 241 PCIe1
> Secondary Bus Number (PCIe0 Endpoint Bus Number)
> + UINT8 Pcie2SecBusNum; ///< Offset 242 PCIe2
> Secondary Bus Number (PCIe0 Endpoint Bus Number)
> + UINT32 Mmio32Base; ///< Offset 243 Base of
> below 4GB MMIO resource
> + UINT32 Mmio32Length; ///< Offset 247 Length of
> below 4GB MMIO resource
> + UINT32 Pcie0WakeGpioNo; ///< Offset 251 PCIe0
> RTD3 Device Wake GPIO Number
> + UINT32 Pcie1WakeGpioNo; ///< Offset 255 PCIe1
> RTD3 Device Wake GPIO Number
> + UINT32 Pcie2WakeGpioNo; ///< Offset 259 PCIe2
> RTD3 Device Wake GPIO Number
> + UINT8 VtdDisable; ///< Offset 263 VT-d
> Enable/Disable
> + UINT32 VtdBaseAddress1; ///< Offset 264 VT-d Base
> Address 1
> + UINT32 VtdBaseAddress2; ///< Offset 268 VT-d Base
> Address 2
> + UINT32 VtdBaseAddress3; ///< Offset 272 VT-d Base
> Address 3
> + UINT16 VtdEngine1Vid; ///< Offset 276 VT-d
> Engine#1 Vendor ID
> + UINT16 VtdEngine2Vid; ///< Offset 278 VT-d
> Engine#2 Vendor ID
> + UINT8 Pcie3SecBusNum; ///< Offset 280 PCIe3
> Secondary Bus Number (PCIe3 Endpoint Bus Number)
> + UINT8 Pcie3GpioSupport; ///< Offset 281 PCIe3 GPIO
> Support (0=Disabled, 1=PCH Based, 2=I2C Based)
> + UINT8 Pcie3HoldRstExpanderNo; ///< Offset 282 PCIe3
> HLD RST IO Expander Number
> + UINT32 Pcie3HoldRstGpioNo; ///< Offset 283 PCIe3
> HLD RST GPIO Number
> + UINT8 Pcie3HoldRstActiveInfo; ///< Offset 287 PCIe3 HLD
> RST GPIO Active Information
> + UINT8 Pcie3PwrEnExpanderNo; ///< Offset 288 PCIe3
> PWR Enable IO Expander Number
> + UINT32 Pcie3PwrEnGpioNo; ///< Offset 289 PCIe3
> PWR Enable GPIO Number
> + UINT8 Pcie3PwrEnActiveInfo; ///< Offset 293 PCIe3 PWR
> Enable GPIO Active Information
> + UINT32 Pcie3WakeGpioNo; ///< Offset 294 PCIe3
> RTD3 Device Wake GPIO Number
> + UINT8 Pcie3EpCapOffset; ///< Offset 298 PCIe3
> Endpoint Capability Structure Offset
> + UINT8 RootPortIndex; ///< Offset 299 RootPort
> Number
> + UINT32 RootPortAddress; ///< Offset 300
> RootPortAddress
> + UINT8 Reserved0[196]; ///< Offset 304:499
> +} SYSTEM_AGENT_NVS_AREA;
> +
> +#pragma pack(pop)
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopCom
> ponentName2.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopCom
> ponentName2.h
> new file mode 100644
> index 0000000000..a9db25404f
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopCom
> ponentName2.h
> @@ -0,0 +1,63 @@
> +/** @file
> + Protocol to retrieve the GOP driver version
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _GOP_COMPONENT_NAME2_H_
> +#define _GOP_COMPONENT_NAME2_H_
> +
> +
> +typedef struct _GOP_COMPONENT_NAME2_PROTOCOL
> GOP_COMPONENT_NAME2_PROTOCOL;
> +
> +///
> +/// GOP Component protocol for retrieving driver name
> +///
> +typedef
> +EFI_STATUS
> +(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_NAME) (
> + IN GOP_COMPONENT_NAME2_PROTOCOL * This,
> + IN CHAR8 *Language,
> + OUT CHAR16 **DriverName
> + );
> +
> +///
> +/// GOP Component protocol for retrieving controller name
> +///
> +typedef
> +EFI_STATUS
> +(EFIAPI *GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME) (
> + IN GOP_COMPONENT_NAME2_PROTOCOL * This,
> + IN EFI_HANDLE ControllerHandle,
> + IN EFI_HANDLE ChildHandle OPTIONAL,
> + IN CHAR8 *Language,
> + OUT CHAR16 **ControllerName
> + );
> +
> +///
> +/// GOP Component protocol for retrieving driver version
> +///
> +typedef
> +EFI_STATUS
> +(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_VERSION) (
> + IN GOP_COMPONENT_NAME2_PROTOCOL * This,
> + IN CHAR8 *Language,
> + OUT CHAR16 **DriverVersion
> + );
> +
> +/**
> + GOP Component protocol\n
> + This protocol will be installed by GOP driver and can be used to retrieve GOP
> information.
> +**/
> +struct _GOP_COMPONENT_NAME2_PROTOCOL {
> + GOP_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName;
> ///< Protocol function to get driver name
> + GOP_COMPONENT_NAME2_GET_DRIVER_VERSION GetDriverVersion;
> ///< Protocol function to get driver version
> + GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME
> GetControllerName; ///< Protocol function to get controller name
> + CHAR8 *SupportedLanguages; ///< Number of
> Supported languages.
> +};
> +
> +extern EFI_GUID gGopComponentName2ProtocolGuid;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopPolic
> y.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopPoli
> cy.h
> new file mode 100644
> index 0000000000..866f60b9c2
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopPoli
> cy.h
> @@ -0,0 +1,73 @@
> +/** @file
> + Interface definition for GopPolicy Protocol.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _GOP_POLICY_PROTOCOL_H_
> +#define _GOP_POLICY_PROTOCOL_H_
> +
> +
> +#define GOP_POLICY_PROTOCOL_REVISION_01 0x01
> +#define GOP_POLICY_PROTOCOL_REVISION_03 0x03
> +
> +typedef enum {
> + LidClosed,
> + LidOpen,
> + LidStatusMax
> +} LID_STATUS;
> +
> +typedef enum {
> + Docked,
> + UnDocked,
> + DockStatusMax
> +} DOCK_STATUS;
> +
> +///
> +/// Function to retrieve LID status
> +///
> +typedef
> +EFI_STATUS
> +(EFIAPI *GET_PLATFORM_LID_STATUS) (
> + OUT LID_STATUS * CurrentLidStatus
> + );
> +
> +///
> +/// Function to retrieve Dock status
> +///
> +typedef
> +EFI_STATUS
> +(EFIAPI *GET_PLATFORM_DOCK_STATUS) (
> + OUT DOCK_STATUS CurrentDockStatus
> +);
> +
> +///
> +/// Function to retrieve VBT table address and size
> +///
> +typedef
> +EFI_STATUS
> +(EFIAPI *GET_VBT_DATA) (
> + OUT EFI_PHYSICAL_ADDRESS * VbtAddress,
> + OUT UINT32 *VbtSize
> + );
> +
> +/**
> + System Agent Graphics Output Protocol (GOP) - Policy Protocol\n
> + Graphics Output Protocol (GOP) is a UEFI API replacing legacy Video ROMs
> for EFI boot\n
> + When GOP Driver is used this protocol can be consumed by GOP driver or
> platform code for GOP relevant initialization\n
> + All functions in this protocol should be initialized by platform code basing
> on platform implementation\n
> +**/
> +typedef struct {
> + UINT32 Revision; ///< Protocol revision
> + GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Protocol
> function to get Lid Status. Platform code should provide this function basing on
> design.
> + GET_VBT_DATA GetVbtData; ///< Protocol function to get
> Vbt Data address and size. Platform code should provide this function basing
> on design.
> + GET_PLATFORM_DOCK_STATUS GetPlatformDockStatus; ///< Function
> pointer for get platform dock status.
> + EFI_GUID GopOverrideGuid; ///< A GUID provided by
> BIOS in case GOP is to be overridden.
> +} GOP_POLICY_PROTOCOL;
> +
> +extern EFI_GUID gGopPolicyProtocolGuid;
> +extern EFI_GUID gIntelGraphicsVbtGuid;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/IgdOpRe
> gion.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/IgdOpRe
> gion.h
> new file mode 100644
> index 0000000000..ef2edfe122
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/IgdOpRe
> gion.h
> @@ -0,0 +1,24 @@
> +/** @file
> + This file is part of the IGD OpRegion Implementation. The IGD OpRegion is
> + an interface between system BIOS, ASL code, and Graphics drivers.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _IGD_OPREGION_PROTOCOL_H_
> +#define _IGD_OPREGION_PROTOCOL_H_
> +
> +#include <IndustryStandard/IgdOpRegion.h>
> +
> +extern EFI_GUID gIgdOpRegionProtocolGuid;
> +
> +///
> +/// IGD OpRegion Protocol
> +///
> +typedef struct {
> + IGD_OPREGION_STRUCTURE *OpRegion; ///< IGD Operation Region
> Structure
> +} IGD_OPREGION_PROTOCOL;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/MemInf
> o.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/MemInf
> o.h
> new file mode 100644
> index 0000000000..031e55b9b4
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/MemInf
> o.h
> @@ -0,0 +1,132 @@
> +/** @file
> + This protocol provides the memory information data, such as
> + total physical memory size, memory frequency, memory size
> + of each dimm and rank.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _MEM_INFO_PROTOCOL_H_
> +#define _MEM_INFO_PROTOCOL_H_
> +
> +
> +//
> +// Extern the GUID for protocol users.
> +//
> +extern EFI_GUID gMemInfoProtocolGuid;
> +
> +//
> +// Protocol definitions
> +//
> +#define NODE_NUM 1
> +#define CH_NUM 2
> +#define DIMM_NUM 2
> +#define RANK_NUM 2
> +#define SLOT_NUM (CH_NUM * DIMM_NUM)
> +#define PROFILE_NUM 4 // number of memory profiles supported
> +#define XMP_PROFILE_NUM 2 // number of XMP profiles supported
> +
> +//
> +// Matches MrcDdrType enum in MRC
> +//
> +#ifndef MRC_DDR_TYPE_DDR4
> +#define MRC_DDR_TYPE_DDR4 0
> +#endif
> +#ifndef MRC_DDR_TYPE_DDR3
> +#define MRC_DDR_TYPE_DDR3 1
> +#endif
> +#ifndef MRC_DDR_TYPE_LPDDR3
> +#define MRC_DDR_TYPE_LPDDR3 2
> +#endif
> +#ifndef MRC_DDR_TYPE_UNKNOWN
> +#define MRC_DDR_TYPE_UNKNOWN 3
> +#endif
> +
> +//
> +// Matches MrcDimmSts enum in MRC
> +//
> +#ifndef DIMM_ENABLED
> +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be
> detected.
> +#endif
> +#ifndef DIMM_DISABLED
> +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of
> presence.
> +#endif
> +#ifndef DIMM_PRESENT
> +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank
> pair and it will be used.
> +#endif
> +#ifndef DIMM_NOT_PRESENT
> +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank
> pair.
> +#endif
> +
> +#pragma pack(1)
> +///
> +/// Memory timing Structure
> +///
> +typedef struct {
> + UINT32 tCK; ///< Offset 0 Memory cycle time, in femtoseconds.
> + UINT16 NMode; ///< Offset 4 Number of tCK cycles for the channel DIMM's
> command rate mode.
> + UINT16 tCL; ///< Offset 6 Number of tCK cycles for the channel DIMM's
> CAS latency.
> + UINT16 tCWL; ///< Offset 8 Number of tCK cycles for the channel DIMM's
> minimum CAS write latency time.
> + UINT16 tFAW; ///< Offset 10 Number of tCK cycles for the channel DIMM's
> minimum four activate window delay time.
> + UINT16 tRAS; ///< Offset 12 Number of tCK cycles for the channel DIMM's
> minimum active to precharge delay time.
> + UINT16 tRCDtRP; ///< Offset 14 Number of tCK cycles for the channel DIMM's
> minimum RAS# to CAS# delay time and Row Precharge delay time
> + UINT16 tREFI; ///< Offset 16 Number of tCK cycles for the channel DIMM's
> minimum Average Periodic Refresh Interval.
> + UINT16 tRFC; ///< Offset 18 Number of tCK cycles for the channel DIMM's
> minimum refresh recovery delay time.
> + UINT16 tRPab; ///< Offset 20 Number of tCK cycles for the channel DIMM's
> minimum row precharge delay time for all banks.
> + UINT16 tRRD; ///< Offset 22 Number of tCK cycles for the channel DIMM's
> minimum row active to row active delay time.
> + UINT16 tRTP; ///< Offset 24 Number of tCK cycles for the channel DIMM's
> minimum internal read to precharge command delay time.
> + UINT16 tWR; ///< Offset 26 Number of tCK cycles for the channel DIMM's
> minimum write recovery time.
> + UINT16 tWTR; ///< Offset 28 Number of tCK cycles for the channel DIMM's
> minimum internal write to read command delay time.
> + UINT16 tRRD_L; ///< Offset 30 Number of tCK cycles for the channel DIMM's
> minimum row active to row active delay time for same bank groups.
> + UINT16 tRRD_S; ///< Offset 32 Number of tCK cycles for the channel DIMM's
> minimum row active to row active delay time for different bank groups.
> + UINT16 tWTR_L; ///< Offset 34 Number of tCK cycles for the channel
> DIMM's minimum internal write to read command delay time for same bank
> groups.
> + UINT16 tWTR_S; ///< Offset 36 Number of tCK cycles for the channel
> DIMM's minimum internal write to read command delay time for different
> bank groups.
> + UINT8 Rsvd[2]; ///< Offset 38
> +} MEMORY_TIMING;
> +
> +typedef struct {
> + UINT8 SG; ///< Number of tCK cycles between transactions in the same
> bank group.
> + UINT8 DG; ///< Number of tCK cycles between transactions when
> switching bank groups.
> + UINT8 DR; ///< Number of tCK cycles between transactions when
> switching between Ranks (in the same DIMM).
> + UINT8 DD; ///< Number of tCK cycles between transactions when
> switching between DIMMs
> +} TURNAROUND_TIMING;
> +
> +// @todo use the MemInfoHob data instead of duplicate structure.
> +///
> +/// Memory information Data Structure
> +///
> +typedef struct {
> + MEMORY_TIMING Timing[PROFILE_NUM]; ///< Offset 0
> Timming information for the DIMM
> + UINT32 memSize; ///< Offset 128 Total physical
> memory size
> + UINT16 ddrFreq; ///< Offset 132 DDR Current
> Frequency
> + UINT16 ddrFreqMax; ///< Offset 134 DDR
> Maximum Frequency
> + UINT16 dimmSize[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset
> 136 Size of each DIMM
> + UINT16 VddVoltage[PROFILE_NUM]; ///< Offset 144 The
> voltage setting for the DIMM
> + UINT8 DimmStatus[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset
> 152 The enumeration value from MrcDimmSts
> + UINT8 RankInDimm[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset
> 156 No. of ranks in a dimm
> + UINT8 *DimmsSpdData[NODE_NUM * CH_NUM * DIMM_NUM]; ///<
> Offset 160 SPD data of each DIMM
> + UINT8 RefClk; ///< Offset 192 Reference Clock
> + UINT8 Ratio; ///< Offset 193 Clock Multiplier
> + BOOLEAN EccSupport; ///< Offset 194 ECC
> supported or not
> + UINT8 Profile; ///< Offset 195 Currently running
> memory profile
> + UINT8 XmpProfileEnable; ///< Offset 196: 0 = no XMP
> DIMMs in system
> + UINT8 DdrType; ///< Offset 197: Current DDR
> type, see DDR_TYPE_xxx defines above
> + UINT8 Reserved[2]; ///< Offset 198 Reserved bytes
> for future use
> + UINT32 DefaultXmptCK[XMP_PROFILE_NUM]; ///< Offset 200
> The Default XMP tCK values read from SPD.
> + TURNAROUND_TIMING tRd2Rd[CH_NUM]; ///<
> Read-to-Read Turn Around Timings
> + TURNAROUND_TIMING tRd2Wr[CH_NUM]; ///<
> Read-to-Write Turn Around Timings
> + TURNAROUND_TIMING tWr2Rd[CH_NUM]; ///<
> Write-to-Read Turn Around Timings
> + TURNAROUND_TIMING tWr2Wr[CH_NUM]; ///<
> Write-to-Write Turn Around Timings
> +} MEMORY_INFO_DATA;
> +#pragma pack()
> +
> +///
> +/// Memory information Protocol definition
> +///
> +typedef struct {
> + MEMORY_INFO_DATA MemInfoData; ///< Memory Information Data
> Structure
> +} MEM_INFO_PROTOCOL;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.
> h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.
> h
> new file mode 100644
> index 0000000000..7b68f3072b
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.
> h
> @@ -0,0 +1,66 @@
> +/** @file
> + Interface definition details between System Agent and platform drivers
> during DXE phase.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_POLICY_H_
> +#define _SA_POLICY_H_
> +
> +#include <SaAccess.h>
> +#include <ConfigBlock.h>
> +#include <Library/ConfigBlockLib.h>
> +#include <ConfigBlock/GraphicsDxeConfig.h>
> +#include <ConfigBlock/MemoryDxeConfig.h>
> +#include <ConfigBlock/MiscDxeConfig.h>
> +#include <ConfigBlock/PcieDxeConfig.h>
> +#include <ConfigBlock/VbiosDxeConfig.h>
> +
> +///
> +/// Extern the GUID for protocol users.
> +///
> +extern EFI_GUID gSaPolicyProtocolGuid;
> +extern EFI_GUID gGraphicsDxeConfigGuid;
> +extern EFI_GUID gMiscDxeConfigGuid;
> +extern EFI_GUID gPcieDxeConfigGuid;
> +extern EFI_GUID gMemoryDxeConfigGuid;
> +extern EFI_GUID gVbiosDxeConfigGuid;
> +
> +/**
> + Don't change the original SA_POLICY_PROTOCOL_REVISION macro, external
> + modules maybe have consumed this macro in their source code. Directly
> + update the SA_POLICY_PROTOCOL_REVISION version number may cause
> those
> + external modules to auto mark themselves wrong version info.
> + Always create new version macro for new Policy protocol interface.
> +**/
> +#define SA_POLICY_PROTOCOL_REVISION 1
> +
> +#define SA_PCIE_DEV_END_OF_TABLE 0xFFFF
> +
> +#define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel
> recommended maximum value for Snoop Latency
> +#define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel
> recommended maximum value for Non-Snoop Latency
> +
> +
> +/**
> + SA DXE Policy
> +
> + The SA_POLICY_PROTOCOL producer drvier is recommended to
> + set all the SA_POLICY_PROTOCOL size buffer zero before init any member
> parameter,
> + this clear step can make sure no random value for those unknow new version
> parameters.
> +
> + Make sure to update the Revision if any change to the protocol, including the
> existing
> + internal structure definations.\n
> + Note: Here revision will be bumped up when adding/removing any config
> block under this structure.\n
> + <b>Revision 1</b>:
> + - Initial version.
> +**/
> +typedef struct {
> + CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Offset 0-31
> +/*
> + Individual Config Block Structures are added here in memory as part of
> AddConfigBlock()
> +*/
> +} SA_POLICY_PROTOCOL;
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsG
> na.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsG
> na.h
> new file mode 100644
> index 0000000000..6f3541e3e9
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsG
> na.h
> @@ -0,0 +1,32 @@
> +/** @file
> + Register names for GNA block
> + <b>Conventions</b>:
> + - Prefixes:
> + - Definitions beginning with "R_" are registers
> + - Definitions beginning with "B_" are bits within registers
> + - Definitions beginning with "V_" are meaningful values of bits within the
> registers
> + - Definitions beginning with "S_" are register sizes
> + - Definitions beginning with "N_" are the bit position
> + - In general, SA registers are denoted by "_SA_" in register names
> + - Registers / bits that are different between SA generations are denoted by
> + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
> + - Registers / bits that are different between SKUs are denoted by
> "_[SKU_name]"
> + at the end of the register/bit names
> + - Registers / bits of new devices introduced in a SA generation will be just
> named
> + as "_SA_" without [generation_name] inserted.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_REGS_GNA_H_
> +#define _SA_REGS_GNA_H_
> +
> +//
> +// Device 8 Equates
> +//
> +#define SA_GNA_BUS_NUM 0x00
> +#define SA_GNA_DEV_NUM 0x08
> +#define SA_GNA_FUN_NUM 0x00
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsH
> ostBridge.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsH
> ostBridge.h
> new file mode 100644
> index 0000000000..2cc0e5be68
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsH
> ostBridge.h
> @@ -0,0 +1,214 @@
> +/** @file
> + Register names for Host Bridge block
> + <b>Conventions</b>:
> + - Prefixes:
> + - Definitions beginning with "R_" are registers
> + - Definitions beginning with "B_" are bits within registers
> + - Definitions beginning with "V_" are meaningful values of bits within the
> registers
> + - Definitions beginning with "S_" are register sizes
> + - Definitions beginning with "N_" are the bit position
> + - In general, SA registers are denoted by "_SA_" in register names
> + - Registers / bits that are different between SA generations are denoted by
> + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
> + - Registers / bits that are different between SKUs are denoted by
> "_[SKU_name]"
> + at the end of the register/bit names
> + - Registers / bits of new devices introduced in a SA generation will be just
> named
> + as "_SA_" without [generation_name] inserted.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_REGS_HOST_BRIDGE_H_
> +#define _SA_REGS_HOST_BRIDGE_H_
> +
> +//
> +// DEVICE 0 (Memory Controller Hub)
> +//
> +#define SA_MC_BUS 0x00
> +#define SA_MC_DEV 0x00
> +#define SA_MC_FUN 0x00
> +#define V_SA_MC_VID 0x8086
> +#define R_SA_MC_DEVICE_ID 0x02
> +#define R_SA_MC_CAPID0_B 0xE8
> +
> +///
> +/// Maximum number of SDRAM channels supported by the memory
> controller
> +///
> +#define SA_MC_MAX_CHANNELS 2
> +
> +///
> +/// Maximum number of DIMM sockets supported by each channel
> +///
> +#define SA_MC_MAX_SLOTS 2
> +
> +///
> +/// Maximum number of sides supported per DIMM
> +///
> +#define SA_MC_MAX_SIDES 2
> +
> +///
> +/// Maximum number of DIMM sockets supported by the memory controller
> +///
> +#define SA_MC_MAX_SOCKETS (SA_MC_MAX_CHANNELS *
> SA_MC_MAX_SLOTS)
> +
> +///
> +/// Maximum number of rows supported by the memory controller
> +///
> +#define SA_MC_MAX_RANKS (SA_MC_MAX_SOCKETS * SA_MC_MAX_SIDES)
> +
> +///
> +/// Maximum number of rows supported by the memory controller
> +///
> +#define SA_MC_MAX_ROWS (SA_MC_MAX_SIDES * SA_MC_MAX_SOCKETS)
> +
> +///
> +/// Maximum memory supported by the memory controller
> +/// 4 GB in terms of KB
> +///
> +#define SA_MC_MAX_MEM_CAPACITY (4 * 1024 * 1024)
> +
> +///
> +/// Define the maximum number of data bytes on a system with no ECC
> memory support.
> +///
> +#define SA_MC_MAX_BYTES_NO_ECC (8)
> +
> +///
> +/// Define the maximum number of SPD data bytes on a DIMM.
> +///
> +#define SA_MC_MAX_SPD_SIZE (512)
> +//
> +// Maximum DMI lanes and bundles supported (x8 and 4 lanes)
> +//
> +#define SA_DMI_MAX_LANE 0x04
> +#define SA_DMI_MAX_BUNDLE 0x02
> +
> +#define SA_DMI_CFL_MAX_LANE 0x04
> +#define SA_DMI_CFL_MAX_BUNDLE 0x02
> +//
> +// KabyLake CPU Mobile SA Device IDs B0:D0:F0
> +//
> +#define V_SA_DEVICE_ID_KBL_MB_ULT_1 0x5904 ///< Kabylake Ult (OPI)
> (2+1F/1.5F/2F/3/3E) Mobile SA DID
> +//
> +// KabyLake CPU Halo SA Device IDs B0:D0:F0
> +//
> +#define V_SA_DEVICE_ID_KBL_HALO_2 0x5910 ///< Kabylake Halo
> (4+2/4E/3FE) SA DID
> +//
> +// KabyLake CPU Desktop SA Device IDs B0:D0:F0
> +//
> +#define V_SA_DEVICE_ID_KBL_DT_2 0x591F ///< Kabylake Desktop
> (4+1.5F/2/4) SA DID
> +//
> +// KabyLake CPU Server SA Device IDs B0:D0:F0
> +//
> +#define V_SA_DEVICE_ID_KBL_SVR_2 0x5918 ///< Kabylake Server
> (4+1/2/4E) SA DID
> +
> +//
> +// CoffeeLake CPU Mobile SA Device IDs B0:D0:F0
> +//
> +#define V_SA_DEVICE_ID_CFL_ULT_1 0x3ED0 ///< CoffeeLake Mobile
> (CFL-U 4+3e) SA DID
> +#define V_SA_DEVICE_ID_CFL_ULT_2 0x3ECC ///< CoffeeLake Mobile
> (CFL-U 2+3e) SA DID
> +#define V_SA_DEVICE_ID_CFL_ULT_3 0x3E34 ///< CoffeeLake Mobile
> (CFL-U 4+(1 or 2)) SA DID
> +#define V_SA_DEVICE_ID_CFL_ULT_4 0x3E35 ///< CoffeeLake Mobile
> (CFL-U 2+(1 or 2)) SA DID
> +#define V_SA_DEVICE_ID_CFL_ULT_6 0x3ECC ///< CoffeeLake Mobile
> (CFL-U 2+3e) SA DID
> +
> +//
> +// CoffeeLake CPU Desktop SA Device IDs B0:D0:F0
> +//
> +#define V_SA_DEVICE_ID_CFL_DT_1 0x3EC2 ///< CoffeeLake Desktop
> (6+2) SA DID
> +#define V_SA_DEVICE_ID_CFL_DT_2 0x3E1F ///< CoffeeLake Desktop
> (4+2) SA DID
> +#define V_SA_DEVICE_ID_CFL_DT_3 0x3E0F ///< CoffeeLake Desktop
> (2+2) SA DID
> +#define V_SA_DEVICE_ID_CFL_DT_4 0x3E30 ///< CoffeeLake Desktop
> (8+2) SA DID
> +
> +//
> +// CoffeeLake CPU Halo SA Device IDs B0:D0:F0
> +//
> +#define V_SA_DEVICE_ID_CFL_HALO_1 0x3EC4 ///< CoffeeLake Halo
> (6+2) SA DID
> +#define V_SA_DEVICE_ID_CFL_HALO_2 0x3E10 ///< CoffeeLake Halo
> (4+2) SA DID
> +#define V_SA_DEVICE_ID_CFL_HALO_3 0x3E20 ///< CoffeeLake Halo
> (8+2) SA DID
> +
> +//
> +// CoffeeLake CPU WS SA Device IDs B0:D0:F0
> +//
> +#define V_SA_DEVICE_ID_CFL_WS_1 0x3EC6 ///< CoffeeLake
> WorkStation (6+2) SA DID
> +#define V_SA_DEVICE_ID_CFL_WS_2 0x3E18 ///< CoffeeLake
> WrokStation (4+2) SA DID
> +#define V_SA_DEVICE_ID_CFL_WS_3 0x3E31 ///< CoffeeLake
> WrokStation (8+2) SA DID
> +
> +//
> +// CPU Server SA Device IDs B0:D0:F0
> +//
> +#define V_SA_DEVICE_ID_CFL_SVR_1 0x3ECA ///< CoffeeLake Server
> (6+0) SA DID
> +#define V_SA_DEVICE_ID_CFL_SVR_2 0x3E32 ///< CoffeeLake Server
> (8+0) SA DID
> +#define V_SA_DEVICE_ID_CFL_SVR_3 0x3E33 ///< CoffeeLake Server
> (4+0) SA DID
> +/**
> + <b>Description</b>:
> + - This is the base address for the Host Memory Mapped Configuration space.
> There is no physical memory within this 32KB window that can be addressed.
> The 32KB reserved by this register does not alias to any PCI 2.3 compliant
> memory mapped space. On reset, the Host MMIO Memory Mapped
> Configuation space is disabled and must be enabled by writing a 1 to
> MCHBAREN [Dev 0, offset48h, bit 0].
> + - All the bits in this register are locked in LT mode.
> + - The register space contains memory control, initialization, timing, and
> buffer strength registers; clocking registers; and power and thermal
> management registers.
> +**/
> +#define R_SA_MCHBAR (0x48)
> +/**
> + <b>Description</b>:
> + - All the bits in this register are LT lockable.
> +**/
> +#define R_SA_GGC (0x50)
> +#define N_SA_GGC_GMS_OFFSET (0x8)
> +#define B_SA_GGC_GMS_MASK (0xff00)
> +#define N_SA_GGC_GGMS_OFFSET (0x6)
> +#define B_SA_GGC_GGMS_MASK (0xc0)
> +#define V_SA_GGC_GGMS_8MB 3
> +/**
> + Description:
> + - Allows for enabling/disabling of PCI devices and functions that are within
> the CPU package. The table below the bit definitions describes the behavior of
> all combinations of transactions to devices controlled by this register.
> + All the bits in this register are LT Lockable.
> +**/
> +#define R_SA_DEVEN (0x54)
> +#define B_SA_DEVEN_D2EN_MASK (0x10)
> +/**
> + Description:
> + This is the base address for the PCI Express configuration space. This
> window of addresses contains the 4KB of configuration space for each PCI
> Express device that can potentially be part of the PCI Express Hierarchy
> associated with the Uncore. There is no actual physical memory within this
> window of up to 256MB that can be addressed. The actual size of this range
> is determined by a field in this register.
> + Each PCI Express Hierarchy requires a PCI Express BASE register. The Uncore
> supports one PCI Express Hierarchy. The region reserved by this register does
> not alias to any PCI2.3 compliant memory mapped space. For example, the
> range reserved for MCHBAR is outside of PCIEXBAR space.
> + On reset, this register is disabled and must be enabled by writing a 1 to the
> enable field in this register. This base address shall be assigned on a boundary
> consistent with the number of buses (defined by the length field in this
> register), above TOLUD and still within 39-bit addressable memory space.
> + The PCI Express Base Address cannot be less than the maximum address
> written to the Top of physical memory register (TOLUD). Software must
> guarantee that these ranges do not overlap with known ranges located above
> TOLUD.
> + Software must ensure that the sum of the length of the enhanced
> configuration region + TOLUD + any other known ranges reserved above TOLUD
> is not greater than the 39-bit addessable limit of 512GB. In general, system
> implementation and the number of PCI/PCI Express/PCI-X buses supported in
> the hierarchy will dictate the length of the region.
> + All the bits in this register are locked in LT mode.
> +**/
> +#define R_SA_PCIEXBAR (0x60)
> +
> +/**
> + Description:
> + - This register controls the read, write and shadowing attributes of the BIOS
> range from F_0000h to F_FFFFh. The Uncore allows programmable memory
> attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB
> address range. Seven Programmable Attribute Map (PAM) registers are used
> to support these features. Cacheability of these areas is controlled via the
> MTRR register in the core.
> + - Two bits are used to specify memory attributes for each memory segment.
> These bits apply to host accesses to the PAM areas. These attributes are:
> + - RE - Read Enable. When RE=1, the host read accesses to the corresponding
> memory segment are claimed by the Uncore and directed to main memory.
> Conversely, when RE=0, the host read accesses are directed to DMI.
> + - WE - Write Enable. When WE=1, the host write accesses to the
> corresponding memory segment are claimed by the Uncore and directed to
> main memory. Conversely, when WE=0, the host read accesses are directed to
> DMI.
> + - The RE and WE attributes permit a memory segment to be Read Only, Write
> Only, Read/Write or Disabled. For example, if a memory segment has RE=1
> and WE=0, the segment is Read Only.
> +**/
> +#define R_SA_PAM0 (0x80)
> +
> +///
> +/// Description:
> +/// The SMRAMC register controls how accesses to Compatible SMRAM
> spaces are treated. The Open, Close and Lock bits function only when
> G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lock bit
> is set.
> +///
> +#define R_SA_SMRAMC (0x88)
> +#define B_SA_SMRAMC_D_LCK_MASK (0x10)
> +#define B_SA_SMRAMC_D_CLS_MASK (0x20)
> +#define B_SA_SMRAMC_D_OPEN_MASK (0x40)
> +///
> +/// Description:
> +/// This register contains the Top of low memory address.
> +///
> +#define R_SA_TOLUD (0xbc)
> +#define R_SA_MC_CAPID0_A_OFFSET 0xE4
> +//
> +// MCHBAR IO Register Offset Equates
> +//
> +#define R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET 0x5DA8
> +
> +#define V_SA_LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel
> recommended maximum value for Snoop Latency (70us)
> +#define V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///<
> Intel recommended maximum value for Non-Snoop Latency (70us)
> +///
> +/// Vt-d Engine base address.
> +///
> +#define R_SA_MCHBAR_VTD1_OFFSET 0x5400 ///< HW UNIT1
> for IGD
> +#define R_SA_MCHBAR_VTD3_OFFSET 0x5410 ///< HW UNIT3 for all
> other - PEG, USB, SATA etc
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsIg
> d.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsIg
> d.h
> new file mode 100644
> index 0000000000..f8b794a9fb
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsIg
> d.h
> @@ -0,0 +1,50 @@
> +/** @file
> + Register names for IGD block
> + <b>Conventions</b>:
> + - Prefixes:
> + - Definitions beginning with "R_" are registers
> + - Definitions beginning with "B_" are bits within registers
> + - Definitions beginning with "V_" are meaningful values of bits within the
> registers
> + - Definitions beginning with "S_" are register sizes
> + - Definitions beginning with "N_" are the bit position
> + - In general, SA registers are denoted by "_SA_" in register names
> + - Registers / bits that are different between SA generations are denoted by
> + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
> + - Registers / bits that are different between SKUs are denoted by
> "_[SKU_name]"
> + at the end of the register/bit names
> + - Registers / bits of new devices introduced in a SA generation will be just
> named
> + as "_SA_" without [generation_name] inserted.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_REGS_IGD_H_
> +#define _SA_REGS_IGD_H_
> +
> +///
> +/// Device 2 Register Equates
> +///
> +//
> +// The following equates must be reviewed and revised when the
> specification is ready.
> +//
> +#define SA_IGD_BUS 0x00
> +#define SA_IGD_DEV 0x02
> +#define SA_IGD_FUN_0 0x00
> +#define SA_IGD_DEV_FUN (SA_IGD_DEV << 3)
> +#define SA_IGD_BUS_DEV_FUN (SA_MC_BUS << 8) + SA_IGD_DEV_FUN
> +
> +#define V_SA_IGD_VID 0x8086
> +#define SA_GT_APERTURE_SIZE_256MB 1 ///< 256MB is the
> recommanded GT Aperture Size as per BWG.
> +
> +#define V_SA_PCI_DEV_2_GT2_CFL_ULT_1_ID 0x3EA0 ///< Dev2 CFL-U GT2
> +#define V_SA_PCI_DEV_2_GT1_CFL_ULT_1_ID 0x3EA1 ///< Dev2 CFL-U GT1
> +#define R_SA_IGD_VID 0x00
> +#define R_SA_IGD_DID 0x02
> +#define R_SA_IGD_CMD 0x04
> +
> +#define R_SA_IGD_SWSCI_OFFSET 0x00E8
> +#define R_SA_IGD_ASLS_OFFSET 0x00FC ///< ASL Storage
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsIp
> u.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsIp
> u.h
> new file mode 100644
> index 0000000000..b26c79ec95
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsIp
> u.h
> @@ -0,0 +1,37 @@
> +/** @file
> + Register names for IPU block
> + <b>Conventions</b>:
> + - Prefixes:
> + - Definitions beginning with "R_" are registers
> + - Definitions beginning with "B_" are bits within registers
> + - Definitions beginning with "V_" are meaningful values of bits within the
> registers
> + - Definitions beginning with "S_" are register sizes
> + - Definitions beginning with "N_" are the bit position
> + - In general, SA registers are denoted by "_SA_" in register names
> + - Registers / bits that are different between SA generations are denoted by
> + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
> + - Registers / bits that are different between SKUs are denoted by
> "_[SKU_name]"
> + at the end of the register/bit names
> + - Registers / bits of new devices introduced in a SA generation will be just
> named
> + as "_SA_" without [generation_name] inserted.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_REGS_IPU_H_
> +#define _SA_REGS_IPU_H_
> +
> +//
> +// Device 5 Equates
> +//
> +#define SA_IPU_BUS_NUM 0x00
> +#define SA_IPU_DEV_NUM 0x05
> +#define SA_IPU_FUN_NUM 0x00
> +
> +//
> +// GPIO native features pins data
> +//
> +#define SA_GPIO_IMGUCLK_NUMBER_OF_PINS 2
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsPe
> g.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsP
> eg.h
> new file mode 100644
> index 0000000000..b7e9416fc6
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsP
> eg.h
> @@ -0,0 +1,64 @@
> +/** @file
> + Register names for PEG block
> + <b>Conventions</b>:
> + - Prefixes:
> + - Definitions beginning with "R_" are registers
> + - Definitions beginning with "B_" are bits within registers
> + - Definitions beginning with "V_" are meaningful values of bits within the
> registers
> + - Definitions beginning with "S_" are register sizes
> + - Definitions beginning with "N_" are the bit position
> + - In general, SA registers are denoted by "_SA_" in register names
> + - Registers / bits that are different between SA generations are denoted by
> + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
> + - Registers / bits that are different between SKUs are denoted by
> "_[SKU_name]"
> + at the end of the register/bit names
> + - Registers / bits of new devices introduced in a SA generation will be just
> named
> + as "_SA_" without [generation_name] inserted.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_REGS_PEG_H_
> +#define _SA_REGS_PEG_H_
> +//
> +// Device 1 Memory Mapped IO Register Offset Equates
> +//
> +#define SA_PEG_BUS_NUM 0x00
> +#define SA_PEG_DEV_NUM 0x01
> +#define SA_PEG0_DEV_NUM SA_PEG_DEV_NUM
> +#define SA_PEG0_FUN_NUM 0x00
> +#define SA_PEG1_DEV_NUM SA_PEG_DEV_NUM
> +#define SA_PEG1_FUN_NUM 0x01
> +#define SA_PEG2_DEV_NUM SA_PEG_DEV_NUM
> +#define SA_PEG2_FUN_NUM 0x02
> +//
> +// Temporary Device & Function Number used for Switchable Graphics DGPU
> +//
> +#define SA_TEMP_DGPU_DEV 0x00
> +#define SA_TEMP_DGPU_FUN 0x00
> +
> +//
> +// SA PCI Express* Port configuration
> +//
> +#define SA_PEG_MAX_FUN 0x03
> +#define SA_PEG_MAX_LANE 0x10
> +#define SA_PEG_MAX_BUNDLE 0x08
> +
> +//
> +// Silicon and SKU- specific MAX defines
> +//
> +#define SA_PEG_CNL_H_MAX_FUN SA_PEG_MAX_FUN // CNL-H-
> SKU supports 4 controllers with 20 PEG lanes and 10 bundles
> +#define SA_PEG_CNL_H_MAX_LANE SA_PEG_MAX_LANE
> +#define SA_PEG_CNL_H_MAX_BUNDLE SA_PEG_MAX_BUNDLE
> +#define SA_PEG_NON_CNL_H_MAX_FUN 0x03 // All
> non-CNL-H- SKU supports 3 controllers with 16 PEG lanes and 8 bundles
> +#define SA_PEG_NON_CNL_H_MAX_LANE 0x10
> +#define SA_PEG_NON_CNL_H_MAX_BUNDLE 0x08
> +
> +
> +
> +#define R_SA_PEG_VID_OFFSET 0x00 ///< Vendor ID
> +#define R_SA_PEG_DID_OFFSET 0x02 ///< Device ID
> +#define R_SA_PEG_SS_OFFSET 0x8C ///< Subsystem ID
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaAccess.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaAccess.h
> new file mode 100644
> index 0000000000..b98f1732ba
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaAccess.h
> @@ -0,0 +1,106 @@
> +/** @file
> + Macros to simplify and abstract the interface to PCI configuration.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SAACCESS_H_
> +#define _SAACCESS_H_
> +
> +#include "SaRegs.h"
> +#include "SaCommonDefinitions.h"
> +
> +///
> +/// SystemAgent Base Address definition
> +///
> +#ifndef STALL_ONE_MICRO_SECOND
> +#define STALL_ONE_MICRO_SECOND 1
> +#endif
> +#ifndef STALL_ONE_MILLI_SECOND
> +#define STALL_ONE_MILLI_SECOND 1000
> +#endif
> +
> +//
> +// SA Segement Number
> +//
> +#define SA_SEG_NUM 0x00
> +
> +#define V_SA_DEVICE_ID_INVALID 0xFFFF
> +
> +
> +///
> +/// The value before AutoConfig match the setting of PCI Express Base
> Specification 1.1, please be careful for adding new feature
> +///
> +typedef enum {
> + PcieAspmDisabled,
> + PcieAspmL0s,
> + PcieAspmL1,
> + PcieAspmL0sL1,
> + PcieAspmAutoConfig,
> + PcieAspmMax
> +} SA_PCIE_ASPM_CONFIG;
> +
> +///
> +/// SgMode settings
> +///
> +typedef enum {
> + SgModeDisabled = 0,
> + SgModeReserved,
> + SgModeMuxless,
> + SgModeDgpu,
> + SgModeMax
> +} SG_MODE;
> +
> +//
> +// Macros that judge which type a device ID belongs to
> +//
> +#define IS_SA_DEVICE_ID_MOBILE(DeviceId) \
> + ( \
> + (DeviceId == V_SA_DEVICE_ID_KBL_MB_ULT_1) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_ULT_1) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_ULT_2) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_ULT_3) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_ULT_4) \
> + )
> +
> +///
> +/// Device IDs that are Desktop specific B0:D0:F0
> +///
> +#define IS_SA_DEVICE_ID_DESKTOP(DeviceId) \
> + ( \
> + (DeviceId == V_SA_DEVICE_ID_KBL_DT_2) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_DT_1) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_DT_2) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_DT_3) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_DT_4) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_WS_1) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_WS_2) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_WS_3) \
> + )
> +
> +///
> +/// Device IDS that are Server specific B0:D0:F0
> +///
> +#define IS_SA_DEVICE_ID_SERVER(DeviceId) \
> + ( \
> + (DeviceId == V_SA_DEVICE_ID_KBL_SVR_2) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_SVR_1) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_SVR_2) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_SVR_3) \
> + )
> +
> +///
> +/// Device IDs that are Halo specific B0:D0:F0
> +///
> +#define IS_SA_DEVICE_ID_HALO(DeviceId) \
> + ( \
> + (DeviceId == V_SA_DEVICE_ID_KBL_HALO_2) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_HALO_1) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_HALO_2) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_HALO_3) || \
> + (DeviceId == V_SA_DEVICE_ID_CFL_HALO_IOT_1) \
> + )
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaCommonDefinit
> ions.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaCommonDefinit
> ions.h
> new file mode 100644
> index 0000000000..ab9224e573
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaCommonDefinit
> ions.h
> @@ -0,0 +1,23 @@
> +/** @file
> + This header file provides common definitions just for System Agent using to
> avoid including extra module's file.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_COMMON_DEFINITIONS_H_
> +#define _SA_COMMON_DEFINITIONS_H_
> +
> +#define ERROR_BY_16 (0xEE15)
> +#define ERROR_NOT_BY_16 (0xED15)
> +
> +#define MAX_PCIE_ASPM_OVERRIDE 500
> +#define MAX_PCIE_LTR_OVERRIDE 500
> +
> +#define DISABLED 0
> +#define ENABLED 1
> +
> +#define SA_VTD_ENGINE_NUMBER 3
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPciExpressLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPciExpressLib.h
> new file mode 100644
> index 0000000000..87aa105df2
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPciExpressLib.h
> @@ -0,0 +1,25 @@
> +/** @file
> + Header file for the PCI Express library.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_PCI_EXPRESS_LIB_H_
> +#define _SA_PCI_EXPRESS_LIB_H_
> +
> +
> +/**
> + Gets the base address of PCI Express.
> +
> + This internal functions retrieves PCI Express Base Address.
> +
> + @return The base address of PCI Express.
> +**/
> +VOID*
> +GetPciExpressBaseAddress (
> + VOID
> +);
> +
> +#endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPolicyCommon.
> h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPolicyCommon.
> h
> new file mode 100644
> index 0000000000..086c60bfed
> --- /dev/null
> +++
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPolicyCommon.
> h
> @@ -0,0 +1,51 @@
> +/** @file
> + Main System Agent Policy structure definition which will contain several
> config blocks during runtime.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_POLICY_COMMON_H_
> +#define _SA_POLICY_COMMON_H_
> +
> +#include <Uefi.h>
> +#include <Library/SmbusLib.h>
> +#include <SaAccess.h>
> +#include <ConfigBlock.h>
> +#include <Library/ConfigBlockLib.h>
> +#include <ConfigBlock/SwitchableGraphicsConfig.h>
> +#include <ConfigBlock/MemoryConfig.h>
> +#include <ConfigBlock/GraphicsPeiPreMemConfig.h>
> +#include <ConfigBlock/PciePeiPreMemConfig.h>
> +#include <ConfigBlock/IpuPreMemConfig.h>
> +#include <ConfigBlock/SaMiscPeiPreMemConfig.h>
> +#include <ConfigBlock/GnaConfig.h>
> +#include <ConfigBlock/GraphicsPeiConfig.h>
> +#include <ConfigBlock/SaMiscPeiConfig.h>
> +#include <ConfigBlock/OverClockingConfig.h>
> +#include <ConfigBlock/VtdConfig.h>
> +#include <ConfigBlock/PciePeiConfig.h>
> +
> +
> +//
> +// Extern the GUID for PPI users.
> +//
> +extern EFI_GUID gSiPolicyPpiGuid;
> +extern EFI_GUID gSaMiscPeiConfigGuid;
> +extern EFI_GUID gGraphicsPeiConfigGuid;
> +extern EFI_GUID gSaPciePeiConfigGuid;
> +extern EFI_GUID gGnaConfigGuid;
> +extern EFI_GUID gVtdConfigGuid;
> +extern EFI_GUID gSaOverclockingPreMemConfigGuid;
> +extern EFI_GUID gSiPreMemPolicyPpiGuid;
> +extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
> +extern EFI_GUID gSaPciePeiPreMemConfigGuid;
> +extern EFI_GUID gGraphicsPeiPreMemConfigGuid;
> +extern EFI_GUID gIpuPreMemConfigGuid;
> +extern EFI_GUID gSwitchableGraphicsConfigGuid;
> +extern EFI_GUID gCpuTraceHubConfigGuid;
> +extern EFI_GUID gMemoryConfigGuid;
> +extern EFI_GUID gMemoryConfigNoCrcGuid;
> +
> +#endif // _SA_POLICY_COMMON_H_
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaRegs.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaRegs.h
> new file mode 100644
> index 0000000000..593b907d2a
> --- /dev/null
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaRegs.h
> @@ -0,0 +1,32 @@
> +/** @file
> + Register names for System Agent (SA) registers
> + <b>Conventions</b>:
> + - Prefixes:
> + - Definitions beginning with "R_" are registers
> + - Definitions beginning with "B_" are bits within registers
> + - Definitions beginning with "V_" are meaningful values of bits within the
> registers
> + - Definitions beginning with "S_" are register sizes
> + - Definitions beginning with "N_" are the bit position
> + - In general, SA registers are denoted by "_SA_" in register names
> + - Registers / bits that are different between SA generations are denoted by
> + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
> + - Registers / bits that are different between SKUs are denoted by
> "_[SKU_name]"
> + at the end of the register/bit names
> + - Registers / bits of new devices introduced in a SA generation will be just
> named
> + as "_SA_" without [generation_name] inserted.
> +
> + Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _SA_REGS_H_
> +#define _SA_REGS_H_
> +
> +#include <Register/SaRegsHostBridge.h>
> +#include <Register/SaRegsIgd.h>
> +#include <Register/SaRegsPeg.h>
> +#include <Register/SaRegsIpu.h>
> +#include <Register/SaRegsGna.h>
> +
> +#endif
> --
> 2.16.2.windows.1
next prev parent reply other threads:[~2019-08-17 1:12 UTC|newest]
Thread overview: 121+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-17 0:15 [edk2-platforms][PATCH V1 00/37] Coffee Lake and Whiskey Lake support Kubacki, Michael A
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and Include headers Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:08 ` Chiu, Chasel
2019-08-17 1:18 ` Chaganty, Rangasai V
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:08 ` Chiu, Chasel
2019-08-17 6:58 ` Chaganty, Rangasai V
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:08 ` Chiu, Chasel
2019-08-17 7:04 ` Chaganty, Rangasai V
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add include headers Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:08 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add ConfigBlock headers Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add Library include headers Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI and Protocol " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 08/37] CoffeelakeSiliconPkg/Pch: Add Register " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add Private " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add Private/Library " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:09 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol " Kubacki, Michael A
2019-08-17 0:51 ` Nate DeSimone
2019-08-17 1:10 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode: Add Include headers Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 13/37] CoffeelakeSiliconPkg/SystemAgent: " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel [this message]
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 14/37] CoffeelakeSiliconPkg: Add package common library instances Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:15 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 16/37] CoffeelakeSiliconPkg/Me: " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:12 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 17/37] CoffeelakeSiliconPkg/Pch: Add Base " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 18/37] CoffeelakeSiliconPkg/Pch: Add DXE " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 19/37] CoffeelakeSiliconPkg/Pch: Add PEI " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 20/37] CoffeelakeSiliconPkg/Pch: Add SMM " Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 21/37] CoffeelakeSiliconPkg/Pch: Add Base " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 22/37] CoffeelakeSiliconPkg/Pch: Add DXE private " Kubacki, Michael A
2019-08-17 0:52 ` Nate DeSimone
2019-08-17 1:13 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 23/37] CoffeelakeSiliconPkg/Pch: Add PEI " Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 24/37] CoffeelakeSiliconPkg/Pch: Add SMM " Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 25/37] CoffeelakeSiliconPkg/SystemAgent: Add " Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 26/37] CoffeelakeSiliconPkg/Pch: Add modules Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 27/37] CoffeelakeSiliconPkg/Pch: Add PchSmiDispatcher Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:15 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 28/37] CoffeelakeSiliconPkg/SystemAgent: Add modules Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:15 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package DSC files Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:14 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 30/37] Maintainers.txt: Add CoffeelakeSiliconPkg maintainers Kubacki, Michael A
2019-08-17 0:53 ` Nate DeSimone
2019-08-17 1:15 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 31/37] WhiskeylakeOpenBoardPkg: Add package and headers Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-19 18:09 ` Sinha, Ankit
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 32/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-17 0:15 ` [edk2-platforms][PATCH V1 33/37] WhiskeylakeOpenBoardPkg: Add library instances Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-17 0:16 ` [edk2-platforms][PATCH V1 34/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: " Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:17 ` Chiu, Chasel
2019-08-17 20:08 ` Chaganty, Rangasai V
2019-08-17 0:16 ` [edk2-platforms][PATCH V1 35/37] WhiskeylakeOpenBoardPkg: Add modules Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:17 ` Chiu, Chasel
2019-08-17 7:50 ` Chaganty, Rangasai V
2019-08-17 0:16 ` [edk2-platforms][PATCH V1 36/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:16 ` Chiu, Chasel
2019-08-17 20:11 ` Chaganty, Rangasai V
2019-08-17 0:16 ` [edk2-platforms][PATCH V1 37/37] Add WhiskeylakeOpenBoardPkg to global build config and documentation Kubacki, Michael A
2019-08-17 0:54 ` Nate DeSimone
2019-08-17 1:17 ` Chiu, Chasel
2019-08-17 20:00 ` Chaganty, Rangasai V
2019-08-19 18:14 ` [edk2-platforms][PATCH V1 00/37] Coffee Lake and Whiskey Lake support Sinha, Ankit
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