From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: chasel.chiu@intel.com) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by groups.io with SMTP; Fri, 16 Aug 2019 18:16:38 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 18:16:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="195107961" Received: from pgsmsx102.gar.corp.intel.com ([10.221.44.80]) by fmsmga001.fm.intel.com with ESMTP; 16 Aug 2019 18:16:32 -0700 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.22]) by PGSMSX102.gar.corp.intel.com ([169.254.6.48]) with mapi id 14.03.0439.000; Sat, 17 Aug 2019 09:16:31 +0800 From: "Chiu, Chasel" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Gao, Liming" , "Desimone, Nathaniel L" , "Kinney, Michael D" , "Sinha, Ankit" Subject: Re: [edk2-platforms][PATCH V1 33/37] WhiskeylakeOpenBoardPkg: Add library instances Thread-Topic: [edk2-platforms][PATCH V1 33/37] WhiskeylakeOpenBoardPkg: Add library instances Thread-Index: AQHVVJEeF1w7nuW5NU6Yw7jUeYuOOab+iZXA Date: Sat, 17 Aug 2019 01:16:30 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC5046242D@PGSMSX111.gar.corp.intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> <20190817001603.30632-34-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-34-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOWI2ZDVjZmItYjM2Ny00MmZlLWIyZTktYmY2YmI5NjBlYTUzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoib3JLbE82TzBaREVjS0g4QmVPNjhya0xEZE5hZlRcLzdQcUFGU3lRaXBCXC9NRzR0eVwvVmF5NFBISm1IVWFXdmVMMCJ9 x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.206] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: Kubacki, Michael A > Sent: Saturday, August 17, 2019 8:16 AM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Chiu, Chasel > ; Gao, Liming ; Desimone, > Nathaniel L ; Kinney, Michael D > ; Sinha, Ankit > Subject: [edk2-platforms][PATCH V1 33/37] WhiskeylakeOpenBoardPkg: Add > library instances >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2083 >=20 > Common package library instances. >=20 > * BaseAcpiTimerLib - Support for ACPI timer services. > * BaseGpioExpanderLib - Support for the TCA6424 IO expander. > * DxePolicyUpdateLib - Policy update in DXE. > * DxeTbtPolicyLib - DXE Thunderbolt policy initialization. > * PeiDTbtInitLib - PEI discrete Thunderbolt initialization services. > * PeiFspPolicyInitLib - PEI Intel FSP policy initialization. > * PeiI2cAccessLib - Provides I2C read and write services. > * PeiPolicyInitLib - Policy initialization in PEI. > * PeiPolicyUpdateLib - Policy update in PEI. > * PeiSiliconPolicyUpdateLibFsp - PEI FSP silicon policy initialization. > * PeiTbtPolicyLib - PEI Thunderbolt policy initialization. > * SecFspWrapperPlatformSecLib - FSP wrapper PlatformSecLib instance. > * TbtCommonLib - Common Thunderbolt services. >=20 > Cc: Sai Chaganty > Cc: Chasel Chiu > Cc: Liming Gao > Cc: Nate DeSimone > Cc: Michael D Kinney > Cc: Ankit Sinha > Signed-off-by: Michael Kubacki > --- >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolic > yLib/DxeTbtPolicyLib.inf | 43 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmm > TbtCommonLib/TbtCommonLib.inf | 60 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolic > yLib/PeiTbtPolicyLib.inf | 51 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/Pei > DTbtInitLib/PeiDTbtInitLib.inf | 45 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspPolicyInitLib.inf | 161 ++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol > icyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 139 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap > perPlatformSecLib/SecFspWrapperPlatformSecLib.inf | 97 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTi > merLib.inf | 54 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/Ba > seGpioExpanderLib.inf | 36 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiH > daVerbTableLib.inf | 67 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAcc > essLib.inf | 39 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi > b/DxePolicyUpdateLib.inf | 58 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pe= i > PolicyInitLib.inf | 61 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiPolicyUpdateLib.inf | 272 ++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolic > yLib/DxeTbtPolicyLibrary.h | 25 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolic > yLib/PeiTbtPolicyLibrary.h | 19 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspPolicyInitLib.h | 234 ++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol > icyUpdateLibFsp/PeiMiscPolicyUpdate.h | 25 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol > icyUpdateLibFsp/PeiPchPolicyUpdate.h | 28 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol > icyUpdateLibFsp/PeiSaPolicyUpdate.h | 30 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap > perPlatformSecLib/FsptCoreUpd.h | 40 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap > perPlatformSecLib/Ia32/Fsp.h | 43 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchH > daVerbTables.h | 3014 ++++++++++++++++= ++++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi > b/DxeMePolicyUpdate.h | 91 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi > b/DxeSaPolicyUpdate.h | 25 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pe= i > CpuPolicyInit.h | 37 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pe= i > MePolicyInit.h | 23 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pe= i > PolicyInit.h | 23 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pe= i > SaPolicyInit.h | 58 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pe= i > SiPolicyInit.h | 22 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiCpuPolicyUpdate.h | 32 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiMePolicyUpdate.h | 14 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiPchPolicyUpdate.h | 25 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiSaPolicyUpdate.h | 53 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiSiPolicyUpdate.h | 19 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolic > yLib/DxeTbtPolicyLib.c | 148 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmm > TbtCommonLib/TbtCommonLib.c | 316 ++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolic > yLib/PeiTbtPolicyLib.c | 206 ++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/Pei > DTbtInitLib/PeiDTbtInitLib.c | 567 ++++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspCpuPolicyInitLib.c | 461 +++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspMePolicyInitLib.c | 121 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspMiscUpdInitLib.c | 77 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspPchPolicyInitLib.c | 736 +++++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspPolicyInitLib.c | 223 ++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspSaPolicyInitLib.c | 848 ++++++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspSecurityPolicyInitLib.c | 70 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI > nitLib/PeiFspSiPolicyInitLib.c | 95 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol > icyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 100 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol > icyUpdateLibFsp/PeiFspPolicyUpdateLib.c | 124 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol > icyUpdateLibFsp/PeiPchPolicyUpdate.c | 60 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol > icyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c | 39 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol > icyUpdateLibFsp/PeiSaPolicyUpdate.c | 85 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPol > icyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c | 87 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap > perPlatformSecLib/FspWrapperPlatformSecLib.c | 163 ++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap > perPlatformSecLib/PlatformInit.c | 54 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap > perPlatformSecLib/SecGetPerformance.c | 90 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap > perPlatformSecLib/SecPlatformInformation.c | 79 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap > perPlatformSecLib/SecRamInitData.c | 37 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap > perPlatformSecLib/SecTempRamDone.c | 48 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTi > merLib.c | 48 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/Ba > seGpioExpanderLib.c | 310 ++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiH > daVerbTableLib.c | 132 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAcc > essLib.c | 115 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi > b/DxeCpuPolicyUpdate.c | 88 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi > b/DxeMePolicyUpdate.c | 105 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi > b/DxePchPolicyUpdate.c | 39 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLi > b/DxeSaPolicyUpdate.c | 57 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pe= i > PolicyInit.c | 65 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pe= i > PolicyInitPreMem.c | 60 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pe= i > SaPolicyInit.c | 114 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiCpuPolicyUpdate.c | 80 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiCpuPolicyUpdatePreMem.c | 108 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiMePolicyUpdate.c | 49 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiMePolicyUpdatePreMem.c | 32 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiPchPolicyUpdate.c | 523 ++++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiPchPolicyUpdatePreMem.c | 113 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiSaPolicyUpdate.c | 242 ++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiSaPolicyUpdatePreMem.c | 221 ++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib > /PeiSiPolicyUpdate.c | 168 ++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap > perPlatformSecLib/Ia32/PeiCoreEntry.nasm | 130 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap > perPlatformSecLib/Ia32/SecEntry.nasm | 361 +++ >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrap > perPlatformSecLib/Ia32/Stack.nasm | 72 + >=20 > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTi > merLib.uni | 15 + > 83 files changed, 13144 insertions(+) >=20 > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPo > licyLib/DxeTbtPolicyLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPo > licyLib/DxeTbtPolicyLib.inf > new file mode 100644 > index 0000000000..0d2a6cceeb > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPo > licyLib/DxeTbtPolicyLib.inf > @@ -0,0 +1,43 @@ > +## @file > +# Component description file for Tbt functionality > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > +INF_VERSION =3D 0x00010017 > +BASE_NAME =3D DxeTbtPolicyLib > +FILE_GUID =3D 28ABF346-4E52-4BD3-b1FF-63BA7563C9D4 > +VERSION_STRING =3D 1.0 > +MODULE_TYPE =3D BASE > +LIBRARY_CLASS =3D DxeTbtPolicyLib > + > + > +[LibraryClasses] > +BaseMemoryLib > +UefiRuntimeServicesTableLib > +UefiBootServicesTableLib > +DebugLib > +PostCodeLib > +HobLib > + > +[Packages] > +MdePkg/MdePkg.dec > +CoffeelakeSiliconPkg/SiPkg.dec > +WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec > +[Sources] > +DxeTbtPolicyLib.c > + > + > +[Guids] > +gEfiEndOfDxeEventGroupGuid > +gTbtInfoHobGuid > + > +[Protocols] > +gDxeTbtPolicyProtocolGuid > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSm > mTbtCommonLib/TbtCommonLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSm > mTbtCommonLib/TbtCommonLib.inf > new file mode 100644 > index 0000000000..f2330b5b71 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSm > mTbtCommonLib/TbtCommonLib.inf > @@ -0,0 +1,60 @@ > +## @file > +# Component information file for Tbt common library > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010017 > + BASE_NAME =3D TbtCommonLib > + FILE_GUID =3D 5F03614E-CB56-40B1-9989-A09E25BBA29= 4 > + VERSION_STRING =3D 1.0 > + MODULE_TYPE =3D BASE > + LIBRARY_CLASS =3D TbtCommonLib > +# > +# The following information is for reference only and not required by th= e > build tools. > +# > +# VALID_ARCHITECTURES =3D IA32 X64 EBC > +# > + > +[LibraryClasses] > + DebugLib > + PchPcieRpLib > + PciSegmentLib > + TimerLib > + BaseLib > + GpioLib > + GpioExpanderLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec > + CoffeelakeSiliconPkg/SiPkg.dec > + > + > +[Pcd] > +gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode ## > CONSUMES > +gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSUMES > +gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI ## CONSUMES > +gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES > +gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES > +gBoardModuleTokenSpaceGuid.PcdDTbtAspm ## CONSUMES > +gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES > +gBoardModuleTokenSpaceGuid.PcdRtd3Tbt ## CONSUMES > +gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES > +gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## > CONSUMES > +gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSUMES > +gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## > CONSUMES > +gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber > + > +[Sources] > + TbtCommonLib.c > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol > icyLib/PeiTbtPolicyLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol > icyLib/PeiTbtPolicyLib.inf > new file mode 100644 > index 0000000000..b74e641e16 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol > icyLib/PeiTbtPolicyLib.inf > @@ -0,0 +1,51 @@ > +## @file > +# Component description file for Tbt policy > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > +INF_VERSION =3D 0x00010017 > +BASE_NAME =3D PeiTbtPolicyLib > +FILE_GUID =3D 4A95FDBB-2535-49eb-9A79-D56D24257106 > +VERSION_STRING =3D 1.0 > +MODULE_TYPE =3D PEIM > +LIBRARY_CLASS =3D PeiTbtPolicyLib > + > + > +[LibraryClasses] > +BaseMemoryLib > +PeiServicesLib > +PeiServicesTablePointerLib > +MemoryAllocationLib > +DebugLib > +PostCodeLib > +HobLib > +GpioLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec > + CoffeelakeSiliconPkg/SiPkg.dec > + IntelSiliconPkg/IntelSiliconPkg.dec > + > +[Pcd] > +gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad ## > CONSUMES > + > +[Sources] > +PeiTbtPolicyLib.c > + > +[Guids] > +gTbtInfoHobGuid > + > +[Ppis] > +gEfiPeiReadOnlyVariable2PpiGuid > +gPeiTbtPolicyPpiGuid > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/P > eiDTbtInitLib/PeiDTbtInitLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/P > eiDTbtInitLib/PeiDTbtInitLib.inf > new file mode 100644 > index 0000000000..8e0dbe73ce > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/P > eiDTbtInitLib/PeiDTbtInitLib.inf > @@ -0,0 +1,45 @@ > +## @file > +# Component description file for PEI DTBT Init library. > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010017 > + BASE_NAME =3D PeiDTbtInitLib > + FILE_GUID =3D 06768A8D-8152-403f-83C1-59584FD2B43= 8 > + VERSION_STRING =3D 1.0 > + MODULE_TYPE =3D PEIM > + LIBRARY_CLASS =3D PeiDTbtInitLib > + > +[LibraryClasses] > + PeiServicesLib > + DebugLib > + PcdLib > + TbtCommonLib > + PciSegmentLib > + PeiTbtPolicyLib > + PchPmcLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec > + CoffeelakeSiliconPkg/SiPkg.dec > + > +[Ppis] > + gPeiTbtPolicyPpiGuid ## CONSUMES > + > +[Pcd] > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES > + #gClientCommonModuleTokenSpaceGuid.PcdTbtSupport ## PRODUCES > + > +[Sources] > + PeiDTbtInitLib.c > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspPolicyInitLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspPolicyInitLib.inf > new file mode 100644 > index 0000000000..bd39cd60b7 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspPolicyInitLib.inf > @@ -0,0 +1,161 @@ > +## @file > +# Library functions for Fsp Policy Initialization Library. > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +############################################################### > ################# > +# > +# Defines Section - statements that will be processed to create a Makefi= le. > +# > +############################################################### > ################# > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D PeiFspPolicyInitLib > + FILE_GUID =3D 2CB87D67-D1A4-4CD3-8CD7-91A1FA1DF6E= 0 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D SiliconPolicyInitLib > + > +# > +# The following information is for reference only and not required by th= e > build tools. > +# > +# VALID_ARCHITECTURES =3D IA32 > +# > + > +############################################################### > ################# > +# > +# Sources Section - list of files that are required for the build to suc= ceed. > +# > +############################################################### > ################# > + > +[Sources] > + PeiFspPolicyInitLib.c > + PeiFspSiPolicyInitLib.c > + PeiFspPchPolicyInitLib.c > + PeiFspCpuPolicyInitLib.c > + PeiFspMePolicyInitLib.c > + PeiFspSaPolicyInitLib.c > + PeiFspSecurityPolicyInitLib.c > + PeiFspMiscUpdInitLib.c > + > +############################################################### > ################# > +# > +# Package Dependency Section - list of Package files that are required f= or > +# this module. > +# > +############################################################### > ################# > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + IntelFsp2Pkg/IntelFsp2Pkg.dec > + CoffeelakeSiliconPkg/SiPkg.dec > + CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec > + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + > +[LibraryClasses] > + BaseMemoryLib > + DebugLib > + IoLib > + PeiServicesLib > + SmbusLib > + ConfigBlockLib > + PcdLib > + MemoryAllocationLib > + PchInfoLib > + SpiLib > + > +[Pcd] > + gSiPkgTokenSpaceGuid.PcdTsegSize > + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress > + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## > CONSUMES > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## > CONSUMES > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## > CONSUMES > + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## > CONSUMES > + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## > CONSUMES > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## > CONSUMES > + > +[Ppis] > + gSiPolicyPpiGuid ## CONSUMES > + gSiPreMemPolicyPpiGuid ## CONSUMES > + gEfiSecPlatformInformation2PpiGuid ## CONSUMES > + gEfiSecPlatformInformationPpiGuid ## CONSUMES > + > +[Guids] > + gPchTraceHubPreMemConfigGuid ## CONSUMES > + gSmbusPreMemConfigGuid ## CONSUMES > + gDciPreMemConfigGuid ## CONSUMES > + gPcieRpPreMemConfigGuid ## CONSUMES > + gHdAudioPreMemConfigGuid ## CONSUMES > + gIshPreMemConfigGuid ## CONSUMES > + gHsioPciePreMemConfigGuid ## CONSUMES > + gHsioSataPreMemConfigGuid ## CONSUMES > + gLpcPreMemConfigGuid ## CONSUMES > + gPchGeneralPreMemConfigGuid ## CONSUMES > + gWatchDogPreMemConfigGuid ## CONSUMES > + gLanConfigGuid ## CONSUMES > + gPcieRpConfigGuid ## CONSUMES > + gSataConfigGuid ## CONSUMES > + gHdAudioConfigGuid ## CONSUMES > + gScsConfigGuid ## CONSUMES > + gIshConfigGuid ## CONSUMES > + gSataConfigGuid ## CONSUMES > + gUsbConfigGuid ## CONSUMES > + gSerialIoConfigGuid ## CONSUMES > + gInterruptConfigGuid ## CONSUMES > + gLockDownConfigGuid ## CONSUMES > + gSaMiscPeiPreMemConfigGuid ## PRODUCES > + gSaMiscPeiConfigGuid ## PRODUCES > + gMemoryConfigGuid ## CONSUMES > + gMemoryConfigNoCrcGuid ## CONSUMES > + gSwitchableGraphicsConfigGuid ## CONSUMES > + gGraphicsPeiPreMemConfigGuid ## CONSUMES > + gSaPciePeiPreMemConfigGuid ## CONSUMES > + gSaMiscPeiConfigGuid ## CONSUMES > + gSaPciePeiConfigGuid ## CONSUMES > + gGraphicsPeiConfigGuid ## CONSUMES > + gCpuTraceHubConfigGuid ## CONSUMES > + gIpuPreMemConfigGuid ## CONSUMES > + gCnviConfigGuid ## CONSUMES > + gHsioConfigGuid ## CONSUMES > + gEspiConfigGuid ## CONSUMES > + gGnaConfigGuid ## CONSUMES > + gVtdConfigGuid ## CONSUMES > + gSaOverclockingPreMemConfigGuid ## CONSUMES > + gMePeiPreMemConfigGuid ## CONSUMES > + gMePeiConfigGuid ## CONSUMES > + gDmiConfigGuid ## CONSUMES > + gFlashProtectionConfigGuid ## CONSUMES > + gIoApicConfigGuid ## CONSUMES > + gPmConfigGuid ## CONSUMES > + gP2sbConfigGuid ## CONSUMES > + gPchGeneralConfigGuid ## CONSUMES > + gSerialIrqConfigGuid ## CONSUMES > + gThermalConfigGuid ## CONSUMES > + gCpuSecurityPreMemConfigGuid ## CONSUMES > + gCpuConfigGuid ## CONSUMES > + gCpuOverclockingPreMemConfigGuid ## CONSUMES > + gCpuConfigLibPreMemConfigGuid ## CONSUMES > + gCpuPowerMgmtBasicConfigGuid ## CONSUMES > + gCpuPowerMgmtCustomConfigGuid ## CONSUMES > + gCpuTestConfigGuid ## CONSUMES > + gCpuPidTestConfigGuid ## CONSUMES > + gCpuPowerMgmtTestConfigGuid ## CONSUMES > + gFspNonVolatileStorageHobGuid ## CONSUMES > + gSmramCpuDataHeaderGuid ## CONSUMES > + gFspReservedMemoryResourceHobTsegGuid ## CONSUMES > + gSiConfigGuid ## CONSUMES > + gDebugConfigHobGuid ## CONSUMES > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP > olicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf > new file mode 100644 > index 0000000000..994cf93e33 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf > @@ -0,0 +1,139 @@ > +## @file > +# Provide FSP wrapper platform related function. > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +############################################################### > ################# > +# > +# Defines Section - statements that will be processed to create a Makefi= le. > +# > +############################################################### > ################# > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D SiliconPolicyUpdateLibFsp > + FILE_GUID =3D 4E83003B-49A9-459E-AAA6-1CA3C6D04FB= 2 > + MODULE_TYPE =3D PEIM > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D SiliconPolicyUpdateLib > + > + > +# > +# The following information is for reference only and not required by th= e > build tools. > +# > +# VALID_ARCHITECTURES =3D IA32 X64 > +# > + > +############################################################### > ################# > +# > +# Sources Section - list of files that are required for the build to suc= ceed. > +# > +############################################################### > ################# > + > +[Sources] > + PeiFspPolicyUpdateLib.c > + PeiPchPolicyUpdatePreMem.c > + PeiPchPolicyUpdate.c > + PeiSaPolicyUpdatePreMem.c > + PeiSaPolicyUpdate.c > + PeiFspMiscUpdUpdateLib.c > + > +############################################################### > ################# > +# > +# Package Dependency Section - list of Package files that are required f= or > +# this module. > +# > +############################################################### > ################# > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + IntelFsp2Pkg/IntelFsp2Pkg.dec > + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > + IntelSiliconPkg/IntelSiliconPkg.dec > + CoffeelakeSiliconPkg/SiPkg.dec > + CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec > + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + > +[LibraryClasses.IA32] > + FspWrapperApiLib > + OcWdtLib > + PchResetLib > + FspWrapperPlatformLib > + BaseMemoryLib > + CpuPlatformLib > + DebugLib > + HdaVerbTableLib > + HobLib > + IoLib > + PcdLib > + PostCodeLib > + SmbusLib > + ConfigBlockLib > + PeiSaPolicyLib > + PchGbeLib > + PchInfoLib > + PchHsioLib > + PchPcieRpLib > + MemoryAllocationLib > + DebugPrintErrorLevelLib > + SiPolicyLib > + PchGbeLib > + TimerLib > + GpioLib > + PeiLib > + > +[Pcd] > + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcSpdData > + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize > + > + > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES > + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES > + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES > + gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES > + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES > + > + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 > + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 > + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size > + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size > + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 > + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 > + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size > + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size > + > + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 > + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 > + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size > + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size > + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 > + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 > + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size > + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size > + > + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid > + > + # SPD Address Table > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 > + > +[Guids] > + gFspNonVolatileStorageHobGuid ## CONSUMES > + gTianoLogoGuid ## CONSUMES > + gEfiMemoryOverwriteControlDataGuid > + > +[Depex] > + gEdkiiVTdInfoPpiGuid > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra > pperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > new file mode 100644 > index 0000000000..06489a6336 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/SecFspWrapperPlatformSecLib.inf > @@ -0,0 +1,97 @@ > +## @file > +# Provide FSP wrapper platform sec related function. > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +############################################################### > ################# > +# > +# Defines Section - statements that will be processed to create a Makefi= le. > +# > +############################################################### > ################# > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D SecFspWrapperPlatformSecLib > + FILE_GUID =3D 4E1C4F95-90EA-47de-9ACC-B8920189A1F= 5 > + MODULE_TYPE =3D SEC > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D PlatformSecLib > + > + > +# > +# The following information is for reference only and not required by th= e > build tools. > +# > +# VALID_ARCHITECTURES =3D IA32 X64 > +# > + > +############################################################### > ################# > +# > +# Sources Section - list of files that are required for the build to suc= ceed. > +# > +############################################################### > ################# > + > +[Sources] > + FspWrapperPlatformSecLib.c > + SecRamInitData.c > + SecPlatformInformation.c > + SecGetPerformance.c > + SecTempRamDone.c > + PlatformInit.c > + > +[Sources.IA32] > + Ia32/SecEntry.nasm > + Ia32/PeiCoreEntry.nasm > + Ia32/Stack.nasm > + Ia32/Fsp.h > + > +############################################################### > ################# > +# > +# Package Dependency Section - list of Package files that are required f= or > +# this module. > +# > +############################################################### > ################# > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + IntelFsp2Pkg/IntelFsp2Pkg.dec > + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + CoffeelakeSiliconPkg/SiPkg.dec > + > +[LibraryClasses] > + LocalApicLib > + SerialPortLib > + FspWrapperPlatformLib > + FspWrapperApiLib > + BoardInitLib > + SecBoardInitLib > + TestPointCheckLib > + IoLib > + > +[Ppis] > + gEfiSecPlatformInformationPpiGuid ## CONSUMES > + gPeiSecPerformancePpiGuid ## CONSUMES > + gTopOfTemporaryRamPpiGuid ## PRODUCES > + gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES > + > +[Pcd] > + gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## > CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## > CONSUMES > + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## > CONSUMES > + gSiPkgTokenSpaceGuid.PcdTcoBaseAddress > + > +[FixedPcd] > + gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress > ## CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize > ## CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## > CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress > ## CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## > CONSUMES > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpi > TimerLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpi > TimerLib.inf > new file mode 100644 > index 0000000000..e7eef24906 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpi > TimerLib.inf > @@ -0,0 +1,54 @@ > +## @file > +# Base ACPI Timer Library > +# > +# Provides basic timer support using the ACPI timer hardware. The > performance > +# counter features are provided by the processors time stamp counter. > +# > +# Note: The implementation uses the lower 24-bits of the ACPI timer and > +# is compatible with both 24-bit and 32-bit ACPI timers. > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D BaseAcpiTimerLib > + FILE_GUID =3D 564DE85F-049E-4481-BF7A-CA04D2788CF= 9 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D TimerLib|SEC PEI_CORE PEIM > + CONSTRUCTOR =3D AcpiTimerLibConstructor > + MODULE_UNI_FILE =3D BaseAcpiTimerLib.uni > + > +[Sources] > + AcpiTimerLib.c > + BaseAcpiTimerLib.c > + > +[Packages] > + MdePkg/MdePkg.dec > + PcAtChipsetPkg/PcAtChipsetPkg.dec > + UefiCpuPkg/UefiCpuPkg.dec ## OVERRIDE > + > +[LibraryClasses] > + BaseLib > + PcdLib > + PciLib > + IoLib > + DebugLib > + > +[Pcd] > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber ## > CONSUMES > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber ## > CONSUMES > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber ## > CONSUMES > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset ## > CONSUMES > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask ## > CONSUMES > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset ## > CONSUMES > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress ## > CONSUMES > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset ## > CONSUMES > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask ## > CONSUMES > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/ > BaseGpioExpanderLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/ > BaseGpioExpanderLib.inf > new file mode 100644 > index 0000000000..ef5ede18cc > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/ > BaseGpioExpanderLib.inf > @@ -0,0 +1,36 @@ > +## @file > +# Library producing Gpio Expander functionality. > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010017 > + BASE_NAME =3D BaseGpioExpanderLib > + FILE_GUID =3D D10AE2A4-782E-427E-92FB-BB74505ED32= 9 > + VERSION_STRING =3D 1.0 > + MODULE_TYPE =3D BASE > + LIBRARY_CLASS =3D GpioExpanderLib > + > +[LibraryClasses] > + BaseLib > + IoLib > + DebugLib > + TimerLib > + PchSerialIoLib > + I2cAccessLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec > + CoffeelakeSiliconPkg/SiPkg.dec > + > +[Sources] > + BaseGpioExpanderLib.c > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei > HdaVerbTableLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pe > iHdaVerbTableLib.inf > new file mode 100644 > index 0000000000..3c017577b6 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pe > iHdaVerbTableLib.inf > @@ -0,0 +1,67 @@ > +## @file > +# PEI Intel HD Audio Verb Table library. > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +############################################################### > ################# > +# > +# Defines Section - statements that will be processed to create a Makefi= le. > +# > +############################################################### > ################# > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D PeiHdaVerbTableLib > + FILE_GUID =3D 821486A2-CF3B-4D24-BC45-AFE40D9737E= B > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D HdaVerbTableLib > + > +# > +# The following information is for reference only and not required by th= e > build tools. > +# > +# VALID_ARCHITECTURES =3D IA32 X64 > +# > + > +############################################################### > ################# > +# > +# Sources Section - list of files that are required for the build to suc= ceed. > +# > +############################################################### > ################# > + > +[Sources] > + PeiHdaVerbTableLib.c > + > +############################################################### > ################# > +# > +# Package Dependency Section - list of Package files that are required f= or > +# this module. > +# > +############################################################### > ################# > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + CoffeelakeSiliconPkg/SiPkg.dec > + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec > + > +[LibraryClasses] > + BaseLib > + BaseMemoryLib > + DebugLib > + MemoryAllocationLib > + PcdLib > + > +[Pcd] > + gBoardModuleTokenSpaceGuid.PcdHdaVerbTable ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable ## > CONSUMES > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cA > ccessLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cA > ccessLib.inf > new file mode 100644 > index 0000000000..887cbf84f8 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cA > ccessLib.inf > @@ -0,0 +1,39 @@ > +## @file > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010017 > + BASE_NAME =3D PeiI2cAccessLib > + FILE_GUID =3D 72CD3A7B-FEA5-4F5E-9165-4DD12187BB1= 3 > + VERSION_STRING =3D 1.0 > + MODULE_TYPE =3D BASE > + LIBRARY_CLASS =3D PeiI2cAccessLib > +# > +# The following information is for reference only and not required by th= e > build tools. > +# > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC > +# > + > +[LibraryClasses] > + BaseLib > + BaseMemoryLib > + DebugLib > + TimerLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec > + SecurityPkg/SecurityPkg.dec > + CoffeelakeSiliconPkg/SiPkg.dec > + > +[Sources] > + PeiI2cAccessLib.c > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxePolicyUpdateLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxePolicyUpdateLib.inf > new file mode 100644 > index 0000000000..16653f38bd > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxePolicyUpdateLib.inf > @@ -0,0 +1,58 @@ > +## @file > +# Component description file for DXE DxePolicyUpdateLib Library > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D DxePolicyUpdateLib > + FILE_GUID =3D 690B3786-D215-4ABB-9EF2-7A80128560E= 0 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D DxePolicyUpdateLib|DXE_DRIVER > + > +# > +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC > +# > + > +[Sources] > + DxeMePolicyUpdate.c > + DxeSaPolicyUpdate.c > + DxePchPolicyUpdate.c > + DxeCpuPolicyUpdate.c > + > +[Packages] > + MdePkg/MdePkg.dec > + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec > + CoffeelakeSiliconPkg/SiPkg.dec > + > +[LibraryClasses] > + UefiBootServicesTableLib > + UefiRuntimeServicesTableLib > + BaseLib > + BaseMemoryLib > + PcdLib > + DebugLib > + IoLib > + CpuPlatformLib > + HobLib > + ConfigBlockLib > + PciSegmentLib > + > +[Pcd] > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES > + > +[Guids] > + gEfiGlobalVariableGuid ## CONSUMES > + gEfiEndOfDxeEventGroupGuid ## CONSUMES > + gMeInfoSetupGuid ## PRODUCES > + gMePolicyHobGuid ## CONSUMES > + gCpuSetupVariableGuid ## CONSUMES > + gPchSetupVariableGuid ## CONSUMES > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiPolicyInitLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiPolicyInitLib.inf > new file mode 100644 > index 0000000000..293abf1904 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiPolicyInitLib.inf > @@ -0,0 +1,61 @@ > +## @file > +# Component description file for PeiPolicyInit library. > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010017 > + BASE_NAME =3D PeiPolicyInitLib > + FILE_GUID =3D B494DF39-A5F8-48A1-B2D0-EF523AD91C5= 5 > + VERSION_STRING =3D 1.0 > + MODULE_TYPE =3D PEIM > + LIBRARY_CLASS =3D PeiPolicyInitLib > + > +[LibraryClasses] > + BaseMemoryLib > + BaseLib > + CpuPlatformLib > + DebugLib > + DebugPrintErrorLevelLib > + HobLib > + IoLib > + MemoryAllocationLib > + PeiServicesLib > + PeiPolicyBoardConfigLib > + PeiPolicyUpdateLib > + PostCodeLib > + SmbusLib > + ConfigBlockLib > + SiPolicyLib > + TimerLib > + > +[Packages] > + MdePkg/MdePkg.dec > + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec > + CoffeelakeSiliconPkg/SiPkg.dec > + > +[Pcd] > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES > + gPlatformModuleTokenSpaceGuid.PcdDumpDefaultSiliconPolicy ## > CONSUMES > + > + > +[Sources] > + PeiPolicyInitPreMem.c > + PeiPolicyInit.c > + PeiPolicyInit.h > + PeiCpuPolicyInit.h > + PeiMePolicyInit.h > + PeiSaPolicyInit.c > + PeiSaPolicyInit.h > + > +[Ppis] > + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES > + gSiPolicyPpiGuid ## CONSUMES > + gSiPreMemPolicyPpiGuid ## CONSUMES > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiPolicyUpdateLib.inf > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiPolicyUpdateLib.inf > new file mode 100644 > index 0000000000..3095a7333e > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiPolicyUpdateLib.inf > @@ -0,0 +1,272 @@ > +## @file > +# Module Information file for PEI PolicyUpdateLib Library > +# > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010017 > + BASE_NAME =3D PeiPolicyUpdateLib > + FILE_GUID =3D 6EA9585C-3C15-47DA-9FFC-25E9E4EA4D0= C > + VERSION_STRING =3D 1.0 > + MODULE_TYPE =3D PEIM > + LIBRARY_CLASS =3D PeiPolicyUpdateLib|PEIM PEI_CORE SE= C > + > +[LibraryClasses] > + HobLib > + BaseCryptLib > + CpuPlatformLib > + IoLib > + PeiSaPolicyLib > + ConfigBlockLib > + PchGbeLib > + PchInfoLib > + PchPcieRpLib > + HdaVerbTableLib > + MemoryAllocationLib > + PeiServicesTablePointerLib > + PcdLib > + Tpm2CommandLib > + Tpm12CommandLib > + Tpm2DeviceLib > + Tpm12DeviceLib > + PmcLib > + SataLib > + PchInfoLib > + PciSegmentLib > + SiPolicyLib > + PeiServicesLib > + SpiLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec > + CoffeelakeSiliconPkg/SiPkg.dec > + SecurityPkg/SecurityPkg.dec > + IntelSiliconPkg/IntelSiliconPkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + > +[FixedPcd] > + gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUM= ES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize ## > CONSUMES > + > +[Pcd] > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## > CONSUMES > + gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES > + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES > + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES > + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES > + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES > + gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES > + gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES > + gPlatformModuleTokenSpaceGuid.PcdGttMmAddress ## CONSUMES > + gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress ## CONSUMES > + gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES > + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES > + gBoardModuleTokenSpaceGuid.PcdBoardBomId ## CONSUMES > + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent > + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES > + > + # SA Misc Config > + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcSpdData ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize ## > CONSUMES > + > + # Display DDI > + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## > CONSUMES > + > + # PEG Reset By GPIO > + gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive ## > CONSUMES > + > + # PCIE RTD3 GPIO > + gBoardModuleTokenSpaceGuid.PcdRootPortDev ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdRootPortFunc ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdRootPortIndex ## > CONSUMES > + > + gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive ## > CONSUMES > + > + gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive ## > CONSUMES > + > + gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive ## > CONSUMES > + > + gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive ## > CONSUMES > + > + # SPD Address Table > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## > CONSUMES > + > + # CA Vref Configuration > + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdMobileDramPresent ## > CONSUMES > + > + # PCIe Clock Info > + gBoardModuleTokenSpaceGuid.PcdPcieClock0 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock1 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock2 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock3 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock4 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock5 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock6 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock7 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock8 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock9 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock10 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock11 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock12 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock13 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock14 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPcieClock15 ## > CONSUMES > + > + # USB 2.0 Port AFE > + gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe ## > CONSUMES > + > + # USB 2.0 Port Over Current Pin > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 ## > CONSUMES > + > + # USB 3.0 Port Over Current Pin > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 ## > CONSUMES > + > + # Pch SerialIo I2c Pads Termination > + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## > CONSUMES > + > + gBoardModuleTokenSpaceGuid.PcdEcPresent > + > + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdSataLedEnable ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdVrAlertEnable ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport ## > CONSUMES > + gBoardModuleTokenSpaceGuid.PcdPchThermalHotEnable ## > CONSUMES > + > gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEna > ble ## CONSUMES > + > gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEna > ble ## CONSUMES > + > gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid > ## CONSUMES > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber > ## CONSUMES > + > +[FixedPcd] > + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize > ## CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize > ## CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize > ## CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize > ## CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize > ## CONSUMES > + > +[Sources] > + PeiPchPolicyUpdatePreMem.c > + PeiPchPolicyUpdate.c > + PeiCpuPolicyUpdatePreMem.c > + PeiCpuPolicyUpdate.c > + PeiMePolicyUpdatePreMem.c > + PeiMePolicyUpdate.c > + PeiSaPolicyUpdate.c > + PeiSaPolicyUpdatePreMem.c > + PeiSiPolicyUpdate.c > + > +[Ppis] > + gWdtPpiGuid ## CONSUMES > + gPchSpiPpiGuid ## CONSUMES > + gSiPolicyPpiGuid ## CONSUMES > + gSiPreMemPolicyPpiGuid ## CONSUMES > + gPeiTbtPolicyPpiGuid ## CONSUMES > + > +[Guids] > + gTianoLogoGuid ## CONSUMES > + gSiConfigGuid ## CONSUMES > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPo > licyLib/DxeTbtPolicyLibrary.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPo > licyLib/DxeTbtPolicyLibrary.h > new file mode 100644 > index 0000000000..a88385f36f > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPo > licyLib/DxeTbtPolicyLibrary.h > @@ -0,0 +1,25 @@ > +/** @file > + Header file for the DxeTBTPolicy library. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _DXE_TBT_POLICY_LIBRARY_H_ > +#define _DXE_TBT_POLICY_LIBRARY_H_ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +//#include > +#include > + > +#endif // _DXE_TBT_POLICY_LIBRARY_H_ > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol > icyLib/PeiTbtPolicyLibrary.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol > icyLib/PeiTbtPolicyLibrary.h > new file mode 100644 > index 0000000000..462bf780e3 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol > icyLib/PeiTbtPolicyLibrary.h > @@ -0,0 +1,19 @@ > +/** @file > + Header file for the PeiTBTPolicy library. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_TBT_POLICY_LIBRARY_H_ > +#define _PEI_TBT_POLICY_LIBRARY_H_ > + > +#include > +#include > +#include > +#include > +#include > + > +#endif // _PEI_TBT_POLICY_LIBRARY_H_ > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspPolicyInitLib.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspPolicyInitLib.h > new file mode 100644 > index 0000000000..52f9fbed8b > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspPolicyInitLib.h > @@ -0,0 +1,234 @@ > +/** @file > + Internal header file for Fsp Policy Initialization Library. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_FSP_POLICY_INIT_LIB_H_ > +#define _PEI_FSP_POLICY_INIT_LIB_H_ > + > +#include > + > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > + > +/** > + Performs FSP SI PEI Policy pre mem initialization. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSiPolicyInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ); > + > +/** > + Performs FSP SI PEI Policy initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSiPolicyInit ( > + IN OUT FSPS_UPD *FspsUpd > + ); > + > +/** > + Performs FSP PCH PEI Policy pre mem initialization. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspPchPolicyInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ); > + > +/** > + Performs FSP PCH PEI Policy initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspPchPolicyInit ( > + IN OUT FSPS_UPD *FspsUpd > + ); > + > +/** > + Performs FSP CPU PEI Policy initialization. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspCpuPolicyInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ); > + > +/** > +Performs FSP Security PEI Policy initialization. > + > +@param[in][out] FspmUpd Pointer to FSP UPD Data. > + > +@retval EFI_SUCCESS FSP UPD Data is updated. > +@retval EFI_NOT_FOUND Fail to locate required PPI. > +@retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSecurityPolicyInitPreMem( > +IN OUT FSPM_UPD *FspmUpd > +); > + > +/** > + Performs FSP ME PEI Policy pre mem initialization. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspMePolicyInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ); > + > +/** > + Performs FSP ME PEI Policy initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspMePolicyInit ( > + IN OUT FSPS_UPD *FspsUpd > + ); > + > +/** > + Performs FSP SA PEI Policy initialization in pre-memory. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSaPolicyInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ); > + > +/** > + Performs FSP SA PEI Policy initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSaPolicyInit ( > + IN OUT FSPS_UPD *FspsUpd > + ); > + > +/** > + Performs FSP CPU PEI Policy post memory initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspCpuPolicyInit ( > + IN OUT FSPS_UPD *FspsUpd > + ); > + > +/** > +Performs FSP Security PEI Policy post memory initialization. > + > +@param[in][out] FspsUpd Pointer to FSP UPD Data. > + > +@retval EFI_SUCCESS FSP UPD Data is updated. > +@retval EFI_NOT_FOUND Fail to locate required PPI. > +@retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSecurityPolicyInit( > +IN OUT FSPS_UPD *FspsUpd > +); > + > +/** > + PeiGetSectionFromFv finds the file in FV and gets file Address and Siz= e > + > + @param[in] NameGuid - File GUID > + @param[out] Address - Pointer to the File Address > + @param[out] Size - Pointer to File Size > + > + @retval EFI_SUCCESS Successfull in reading the section = from FV > +**/ > +EFI_STATUS > +EFIAPI > +PeiGetSectionFromFv ( > + IN CONST EFI_GUID NameGuid, > + OUT VOID **Address, > + OUT UINT32 *Size > + ); > + > +/** > + Performs FSP Misc UPD initialization. > + > + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspMiscUpdInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ); > + > +#endif // _PEI_FSP_POLICY_INIT_LIB_H_ > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP > olicyUpdateLibFsp/PeiMiscPolicyUpdate.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiMiscPolicyUpdate.h > new file mode 100644 > index 0000000000..a0c8f2dae7 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiMiscPolicyUpdate.h > @@ -0,0 +1,25 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_MISC_POLICY_UPDATE_H_ > +#define _PEI_MISC_POLICY_UPDATE_H_ > + > +#include > + > +/** > + Performs FSP Misc UPD initialization. > + > + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspMiscUpdUpdatePreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ); > + > +#endif > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP > olicyUpdateLibFsp/PeiPchPolicyUpdate.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiPchPolicyUpdate.h > new file mode 100644 > index 0000000000..1ff16e2f32 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiPchPolicyUpdate.h > @@ -0,0 +1,28 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_PCH_POLICY_UPDATE_H_ > +#define _PEI_PCH_POLICY_UPDATE_H_ > + > +// > +// External include files do NOT need to be explicitly specified in real= EDKII > +// environment > +// > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#endif > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP > olicyUpdateLibFsp/PeiSaPolicyUpdate.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiSaPolicyUpdate.h > new file mode 100644 > index 0000000000..9b8c28c469 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiSaPolicyUpdate.h > @@ -0,0 +1,30 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_SA_POLICY_UPDATE_H_ > +#define _PEI_SA_POLICY_UPDATE_H_ > + > +// > +// External include files do NOT need to be explicitly specified in real= EDKII > +// environment > +// > +#include > +#include > +#include > +#include > +#include "PeiPchPolicyUpdate.h" > +#include > +#include > + > +#include > +#include > +#include > + > +extern EFI_GUID gTianoLogoGuid; > + > +#endif > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra > pperPlatformSecLib/FsptCoreUpd.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/FsptCoreUpd.h > new file mode 100644 > index 0000000000..e7b5ed952b > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/FsptCoreUpd.h > @@ -0,0 +1,40 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef __FSPT_CORE_UPD_H__ > +#define __FSPT_CORE_UPD_H__ > + > +#pragma pack(1) > + > +/** Fsp T Core UPD > +**/ > +typedef struct { > + > +/** Offset 0x0020 > +**/ > + UINT32 MicrocodeRegionBase; > + > +/** Offset 0x0024 > +**/ > + UINT32 MicrocodeRegionSize; > + > +/** Offset 0x0028 > +**/ > + UINT32 CodeRegionBase; > + > +/** Offset 0x002C > +**/ > + UINT32 CodeRegionSize; > + > +/** Offset 0x0030 > +**/ > + UINT8 Reserved[16]; > +} FSPT_CORE_UPD; > + > +#pragma pack() > + > +#endif > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra > pperPlatformSecLib/Ia32/Fsp.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/Ia32/Fsp.h > new file mode 100644 > index 0000000000..1c88285a1d > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/Ia32/Fsp.h > @@ -0,0 +1,43 @@ > +/** @file > + Fsp related definitions > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef __FSP_H__ > +#define __FSP_H__ > + > +// > +// Fv Header > +// > +#define FVH_SIGINATURE_OFFSET 0x28 > +#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid > signature:_FVH > +#define FVH_HEADER_LENGTH_OFFSET 0x30 > +#define FVH_EXTHEADER_OFFSET_OFFSET 0x34 > +#define FVH_EXTHEADER_SIZE_OFFSET 0x10 > + > +// > +// Ffs Header > +// > +#define FSP_HEADER_GUID_DWORD1 0x912740BE > +#define FSP_HEADER_GUID_DWORD2 0x47342284 > +#define FSP_HEADER_GUID_DWORD3 0xB08471B9 > +#define FSP_HEADER_GUID_DWORD4 0x0C3F3527 > +#define FFS_HEADER_SIZE_VALUE 0x18 > + > +// > +// Section Header > +// > +#define SECTION_HEADER_TYPE_OFFSET 0x03 > +#define RAW_SECTION_HEADER_SIZE_VALUE 0x04 > + > +// > +// Fsp Header > +// > +#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C > +#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 > + > +#endif > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pc > hHdaVerbTables.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pc > hHdaVerbTables.h > new file mode 100644 > index 0000000000..0d26e8ad7a > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pc > hHdaVerbTables.h > @@ -0,0 +1,3014 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PCH_HDA_VERB_TABLES_H_ > +#define _PCH_HDA_VERB_TABLES_H_ > + > +#include > + > +HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio =3D > HDAUDIO_VERB_TABLE_INIT ( > + // > + // VerbTable: CFL Display Audio Codec > + // Revision ID =3D 0xFF > + // Codec Vendor: 0x8086280B > + // > + 0x8086, 0x280B, > + 0xFF, 0xFF, > + // > + // Display Audio Verb Table > + // > + // For GEN9, the Vendor Node ID is 08h > + // Port to be exposed to the inbox driver in the vanilla mode: PORT C = - > BIT[7:6] =3D 01b > + 0x00878140, > + // Pin Widget 5 - PORT B - Configuration Default: 0x18560010 > + 0x00571C10, > + 0x00571D00, > + 0x00571E56, > + 0x00571F18, > + // Pin Widget 6 - PORT C - Configuration Default: 0x18560020 > + 0x00671C20, > + 0x00671D00, > + 0x00671E56, > + 0x00671F18, > + // Pin Widget 7 - PORT D - Configuration Default: 0x18560030 > + 0x00771C30, > + 0x00771D00, > + 0x00771E56, > + 0x00771F18, > + // Disable the third converter and third Pin (NID 08h) > + 0x00878140 > +); > + > +// > +//codecs verb tables > +// > +HDAUDIO_VERB_TABLE HdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT ( > + // > + // VerbTable: (Realtek ALC700) > + // Revision ID =3D 0xff > + // Codec Verb Table > + // Codec Address: CAd value (0/1/2) > + // Codec Vendor: 0x10EC0700 > + // > + 0x10EC, 0x0700, > + 0xFF, 0xFF, > + > //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + // > + // Realtek Semiconductor Corp. > + // > + > //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 > + //Realtek HD Audio Codec : ALC700 > + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 > + //HDA Codec PnP ID : > HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2 > + //The number of verb command block : 17 > + > + // NID 0x12 : 0x411111F0 > + // NID 0x13 : 0x40000000 > + // NID 0x14 : 0x411111F0 > + // NID 0x15 : 0x411111F0 > + // NID 0x16 : 0x411111F0 > + // NID 0x17 : 0x90170110 > + // NID 0x18 : 0x411111F0 > + // NID 0x19 : 0x04A11030 > + // NID 0x1A : 0x411111F0 > + // NID 0x1B : 0x411111F0 > + // NID 0x1D : 0x40622005 > + // NID 0x1E : 0x411111F0 > + // NID 0x1F : 0x411111F0 > + // NID 0x21 : 0x04211020 > + // NID 0x29 : 0x411111F0 > + > + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D > + //HDA Codec Subsystem ID : 0x10EC10F2 > + 0x001720F2, > + 0x00172110, > + 0x001722EC, > + 0x00172310, > + > + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D > + //Widget node 0x01 : > + 0x0017FF00, > + 0x0017FF00, > + 0x0017FF00, > + 0x0017FF00, > + //Pin widget 0x12 - DMIC > + 0x01271C00, > + 0x01271D00, > + 0x01271E00, > + 0x01271F40, > + //Pin widget 0x13 - DMIC > + 0x01371C00, > + 0x01371D00, > + 0x01371E00, > + 0x01371F40, > + //Pin widget 0x14 - FRONT (Port-D) > + 0x01471CF0, > + 0x01471D11, > + 0x01471E11, > + 0x01471F41, > + //Pin widget 0x15 - I2S-OUT > + 0x01571CF0, > + 0x01571D11, > + 0x01571E11, > + 0x01571F41, > + //Pin widget 0x16 - LINE3 (Port-B) > + 0x01671CF0, > + 0x01671D11, > + 0x01671E11, > + 0x01671F41, > + //Pin widget 0x17 - I2S-OUT > + 0x01771C10, > + 0x01771D01, > + 0x01771E17, > + 0x01771F90, > + //Pin widget 0x18 - I2S-IN > + 0x01871CF0, > + 0x01871D11, > + 0x01871E11, > + 0x01871F41, > + //Pin widget 0x19 - MIC2 (Port-F) > + 0x01971C30, > + 0x01971D10, > + 0x01971EA1, > + 0x01971F04, > + //Pin widget 0x1A - LINE1 (Port-C) > + 0x01A71CF0, > + 0x01A71D11, > + 0x01A71E11, > + 0x01A71F41, > + //Pin widget 0x1B - LINE2 (Port-E) > + 0x01B71CF0, > + 0x01B71D11, > + 0x01B71E11, > + 0x01B71F41, > + //Pin widget 0x1D - PC-BEEP > + 0x01D71C05, > + 0x01D71D20, > + 0x01D71E62, > + 0x01D71F40, > + //Pin widget 0x1E - S/PDIF-OUT > + 0x01E71CF0, > + 0x01E71D11, > + 0x01E71E11, > + 0x01E71F41, > + //Pin widget 0x1F - S/PDIF-IN > + 0x01F71CF0, > + 0x01F71D11, > + 0x01F71E11, > + 0x01F71F41, > + //Pin widget 0x21 - HP-OUT (Port-I) > + 0x02171C20, > + 0x02171D10, > + 0x02171E21, > + 0x02171F04, > + //Pin widget 0x29 - I2S-IN > + 0x02971CF0, > + 0x02971D11, > + 0x02971E11, > + 0x02971F41, > + //Widget node 0x20 : > + 0x02050045, > + 0x02045289, > + 0x0205004A, > + 0x0204201B, > + //Widget node 0x20 - 1 : > + 0x05850000, > + 0x05843888, > + 0x0205006F, > + 0x02042C0B, > + > + > + //Widget node 0X20 for ALC1305 20160603 update > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040000, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040004, > + 0x02050028, > + 0x02040600, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FFD0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040080, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040880, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003A, > + 0x02050028, > + 0x02040DFE, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x0204005D, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x02040442, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040005, > + 0x02050028, > + 0x02040880, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040006, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040008, > + 0x02050028, > + 0x0204B000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204002E, > + 0x02050028, > + 0x02040800, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x020400C3, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x0204D4A0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x020400CC, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x0204400A, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x020400C1, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x02040320, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040039, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003B, > + 0x02050028, > + 0x0204FFFF, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FC20, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003A, > + 0x02050028, > + 0x02041DFE, > + 0x02050029, > + 0x0204B024, > + // > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C0, > + 0x02050028, > + 0x020401FA, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C1, > + 0x02050028, > + 0x0204DE23, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C2, > + 0x02050028, > + 0x02041C00, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C3, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C4, > + 0x02050028, > + 0x02040200, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C5, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C6, > + 0x02050028, > + 0x020403F5, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C7, > + 0x02050028, > + 0x0204AF1B, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C8, > + 0x02050028, > + 0x02041E0A, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C9, > + 0x02050028, > + 0x0204368E, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CA, > + 0x02050028, > + 0x020401FA, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CB, > + 0x02050028, > + 0x0204DE23, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CC, > + 0x02050028, > + 0x02041C00, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CD, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CE, > + 0x02050028, > + 0x02040200, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CF, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400D0, > + 0x02050028, > + 0x020403F5, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400D1, > + 0x02050028, > + 0x0204AF1B, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400D2, > + 0x02050028, > + 0x02041E0A, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400D3, > + 0x02050028, > + 0x0204368E, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040040, > + 0x02050028, > + 0x0204800F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040062, > + 0x02050028, > + 0x02048000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040063, > + 0x02050028, > + 0x02044848, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040064, > + 0x02050028, > + 0x02040800, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040065, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040066, > + 0x02050028, > + 0x02044004, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040067, > + 0x02050028, > + 0x02040802, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040068, > + 0x02050028, > + 0x0204890F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040069, > + 0x02050028, > + 0x0204E021, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040070, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040071, > + 0x02050000, > + 0x02043330, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040072, > + 0x02050000, > + 0x02043333, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040073, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040074, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040075, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040076, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040050, > + 0x02050028, > + 0x020402EC, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040051, > + 0x02050028, > + 0x02044909, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040052, > + 0x02050028, > + 0x020440B0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040046, > + 0x02050028, > + 0x0204C22E, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040047, > + 0x02050028, > + 0x02040C00, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040048, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040049, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204004A, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204004B, > + 0x02050028, > + 0x02041C00, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x02040090, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x0204721F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204009E, > + 0x02050028, > + 0x02040001, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040004, > + 0x02050028, > + 0x02040500, > + 0x02050029, > + 0x0204B024 > +); // HdaVerbTableAlc700 > + > +HDAUDIO_VERB_TABLE HdaVerbTableAlc701 =3D HDAUDIO_VERB_TABLE_INIT ( > + // > + // VerbTable: (Realtek ALC701) > + // Revision ID =3D 0xff > + // Codec Verb Table > + // Codec Address: CAd value (0/1/2) > + // Codec Vendor: 0x10EC0701 > + // > + 0x10EC, 0x0701, > + 0xFF, 0xFF, > + > //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + // > + // Realtek Semiconductor Corp. > + // > + > //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 > + //Realtek HD Audio Codec : ALC701 > + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 > + //HDA Codec PnP ID : > HDAUDIO\FUNC_01&VEN_10EC&DEV_0701&SUBSYS_10EC1124 > + //The number of verb command block : 17 > + > + // NID 0x12 : 0x411111F0 > + // NID 0x13 : 0x40000000 > + // NID 0x14 : 0x411111F0 > + // NID 0x15 : 0x411111F0 > + // NID 0x16 : 0x411111F0 > + // NID 0x17 : 0x90170110 > + // NID 0x18 : 0x411111F0 > + // NID 0x19 : 0x04A11030 > + // NID 0x1A : 0x411111F0 > + // NID 0x1B : 0x411111F0 > + // NID 0x1D : 0x40610041 > + // NID 0x1E : 0x411111F0 > + // NID 0x1F : 0x411111F0 > + // NID 0x21 : 0x04211020 > + // NID 0x29 : 0x411111F0 > + > + > + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D > + //HDA Codec Subsystem ID : 0x10EC1124 > + 0x00172024, > + 0x00172111, > + 0x001722EC, > + 0x00172310, > + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D > + //Widget node 0x01 : > + 0x0017FF00, > + 0x0017FF00, > + 0x0017FF00, > + 0x0017FF00, > + //Pin widget 0x12 - DMIC > + 0x01271C00, > + 0x01271D00, > + 0x01271E00, > + 0x01271F40, > + //Pin widget 0x13 - DMIC > + 0x01371C00, > + 0x01371D00, > + 0x01371E00, > + 0x01371F40, > + //Pin widget 0x14 - FRONT (Port-D) > + 0x01471CF0, > + 0x01471D11, > + 0x01471E11, > + 0x01471F41, > + //Pin widget 0x15 - I2S-OUT > + 0x01571CF0, > + 0x01571D11, > + 0x01571E11, > + 0x01571F41, > + //Pin widget 0x16 - LINE3 (Port-B) > + 0x01671CF0, > + 0x01671D11, > + 0x01671E11, > + 0x01671F41, > + //Pin widget 0x17 - I2S-OUT > + 0x01771C10, > + 0x01771D01, > + 0x01771E17, > + 0x01771F90, > + //Pin widget 0x18 - I2S-IN > + 0x01871CF0, > + 0x01871D11, > + 0x01871E11, > + 0x01871F41, > + //Pin widget 0x19 - MIC2 (Port-F) > + 0x01971C30, > + 0x01971D10, > + 0x01971EA1, > + 0x01971F04, > + //Pin widget 0x1A - LINE1 (Port-C) > + 0x01A71CF0, > + 0x01A71D11, > + 0x01A71E11, > + 0x01A71F41, > + //Pin widget 0x1B - LINE2 (Port-E) > + 0x01B71CF0, > + 0x01B71D11, > + 0x01B71E11, > + 0x01B71F41, > + //Pin widget 0x1D - PC-BEEP > + 0x01D71C41, > + 0x01D71D00, > + 0x01D71E61, > + 0x01D71F40, > + //Pin widget 0x1E - S/PDIF-OUT > + 0x01E71CF0, > + 0x01E71D11, > + 0x01E71E11, > + 0x01E71F41, > + //Pin widget 0x1F - S/PDIF-IN > + 0x01F71CF0, > + 0x01F71D11, > + 0x01F71E11, > + 0x01F71F41, > + //Pin widget 0x21 - HP-OUT (Port-I) > + 0x02171C20, > + 0x02171D10, > + 0x02171E21, > + 0x02171F04, > + //Pin widget 0x29 - I2S-IN > + 0x02971CF0, > + 0x02971D11, > + 0x02971E11, > + 0x02971F41, > + //Widget node 0x20 : > + 0x02050045, > + 0x02045289, > + 0x0205004A, > + 0x0204201B, > + //Widget node 0x20 - 1 : > + 0x05850000, > + 0x05843888, > + 0x0205006F, > + 0x02042C0B > +); // HdaVerbTableAlc701 > + > +HDAUDIO_VERB_TABLE HdaVerbTableAlc274 =3D HDAUDIO_VERB_TABLE_INIT ( > + // > + // VerbTable: (Realtek ALC274) > + // Revision ID =3D 0xff > + // Codec Verb Table > + // Codec Address: CAd value (0/1/2) > + // Codec Vendor: 0x10EC0274 > + // > + 0x10EC, 0x0274, > + 0xFF, 0xFF, > + > //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + // > + // Realtek Semiconductor Corp. > + // > + > //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 > + //Realtek HD Audio Codec : ALC274 > + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 > + //HDA Codec PnP ID : > HDAUDIO\FUNC_01&VEN_10EC&DEV_0274&SUBSYS_10EC10F6 > + //The number of verb command block : 16 > + > + // NID 0x12 : 0x40000000 > + // NID 0x13 : 0x411111F0 > + // NID 0x14 : 0x411111F0 > + // NID 0x15 : 0x411111F0 > + // NID 0x16 : 0x411111F0 > + // NID 0x17 : 0x411111F0 > + // NID 0x18 : 0x411111F0 > + // NID 0x19 : 0x04A11020 > + // NID 0x1A : 0x411111F0 > + // NID 0x1B : 0x411111F0 > + // NID 0x1D : 0x40451B05 > + // NID 0x1E : 0x411111F0 > + // NID 0x1F : 0x411111F0 > + // NID 0x21 : 0x04211010 > + > + > + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D > + //,DA Codec Subsystem ID : 0x10EC10F6 > + 0x001720F6, > + 0x00172110, > + 0x001722EC, > + 0x00172310, > + > + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D > + //Widget node 0x01 : > + 0x0017FF00, > + 0x0017FF00, > + 0x0017FF00, > + 0x0017FF00, > + //Pin widget 0x12 - DMIC > + 0x01271C00, > + 0x01271D00, > + 0x01271E00, > + 0x01271F40, > + //Pin widget 0x13 - DMIC > + 0x01371CF0, > + 0x01371D11, > + 0x01371E11, > + 0x01371F41, > + //Pin widget 0x14 - NPC > + 0x01471CF0, > + 0x01471D11, > + 0x01471E11, > + 0x01471F41, > + //Pin widget 0x15 - I2S_OUT2 > + 0x01571CF0, > + 0x01571D11, > + 0x01571E11, > + 0x01571F41, > + //Pin widget 0x16 - LINE3 (Port-B) > + 0x01671CF0, > + 0x01671D11, > + 0x01671E11, > + 0x01671F41, > + //Pin widget 0x17 - I2S_OUT1 > + 0x01771CF0, > + 0x01771D11, > + 0x01771E11, > + 0x01771F41, > + //Pin widget 0x18 - I2S_IN > + 0x01871CF0, > + 0x01871D11, > + 0x01871E11, > + 0x01871F41, > + //Pin widget 0x19 - MIC2 (Port-F) > + 0x01971C20, > + 0x01971D10, > + 0x01971EA1, > + 0x01971F04, > + //Pin widget 0x1A - LINE1 (Port-C) > + 0x01A71CF0, > + 0x01A71D11, > + 0x01A71E11, > + 0x01A71F41, > + //Pin widget 0x1B - LINE2 (Port-E) > + 0x01B71CF0, > + 0x01B71D11, > + 0x01B71E11, > + 0x01B71F41, > + //Pin widget 0x1D - PC-BEEP > + 0x01D71C05, > + 0x01D71D1B, > + 0x01D71E45, > + 0x01D71F40, > + //Pin widget 0x1E - S/PDIF-OUT > + 0x01E71CF0, > + 0x01E71D11, > + 0x01E71E11, > + 0x01E71F41, > + //Pin widget 0x1F - S/PDIF-IN > + 0x01F71CF0, > + 0x01F71D11, > + 0x01F71E11, > + 0x01F71F41, > + //Pin widget 0x21 - HP-OUT (Port-I) > + 0x02171C10, > + 0x02171D10, > + 0x02171E21, > + 0x02171F04, > + //Widget node 0x20 : > + 0x02050045, > + 0x02045289, > + 0x0205006F, > + 0x02042C0B, > + //Widget node 0x20 - 1 : > + 0x02050035, > + 0x02048968, > + 0x05B50001, > + 0x05B48540, > + //Widget node 0x20 - 2 : > + 0x05850000, > + 0x05843888, > + 0x05850000, > + 0x05843888, > + //Widget node 0x20 - 3 : > + 0x0205004A, > + 0x0204201B, > + 0x0205004A, > + 0x0204201B > +); //HdaVerbTableAlc274 > + > +// > +// CFL S Audio Codec > +// > +STATIC HDAUDIO_VERB_TABLE CflSHdaVerbTableAlc700 =3D > HDAUDIO_VERB_TABLE_INIT ( > + // > + // VerbTable: (Realtek ALC700) CFL S RVP > + // Revision ID =3D 0xff > + // Codec Verb Table > + // Codec Address: CAd value (0/1/2) > + // Codec Vendor: 0x10EC0700 > + // > + 0x10EC, 0x0700, > + 0xFF, 0xFF, > + > + > //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + // > + // Realtek Semiconductor Corp. > + // > + > //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > + //Realtek High Definition Audio Configuration - Version : 5.0.3.1 > + //Realtek HD Audio Codec : ALC700 > + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 > + //HDA Codec PnP ID : > HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC112C > + //The number of verb command block : 17 > + > + // NID 0x12 : 0x90A60130 > + // NID 0x13 : 0x40000000 > + // NID 0x14 : 0x411111F0 > + // NID 0x15 : 0x411111F0 > + // NID 0x16 : 0x03011010 > + // NID 0x17 : 0x90170120 > + // NID 0x18 : 0x411111F0 > + // NID 0x19 : 0x04A1103E > + // NID 0x1A : 0x411111F0 > + // NID 0x1B : 0x03A11040 > + // NID 0x1D : 0x40600001 > + // NID 0x1E : 0x411111F0 > + // NID 0x1F : 0x411111F0 > + // NID 0x21 : 0x0421102F > + // NID 0x29 : 0x411111F0 > + > + > + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D > + //HDA Codec Subsystem ID : 0x10EC112C > + 0x0017202C, > + 0x00172111, > + 0x001722EC, > + 0x00172310, > + > + > + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D > + //Widget node 0x01 : > + 0x0017FF00, > + 0x0017FF00, > + 0x0017FF00, > + 0x0017FF00, > + //Pin widget 0x12 - DMIC > + 0x01271C30, > + 0x01271D01, > + 0x01271EA6, > + 0x01271F90, > + //Pin widget 0x13 - DMIC > + 0x01371C00, > + 0x01371D00, > + 0x01371E00, > + 0x01371F40, > + //Pin widget 0x14 - FRONT (Port-D) > + 0x01471CF0, > + 0x01471D11, > + 0x01471E11, > + 0x01471F41, > + //Pin widget 0x15 - I2S-OUT > + 0x01571CF0, > + 0x01571D11, > + 0x01571E11, > + 0x01571F41, > + //Pin widget 0x16 - LINE3 (Port-B) > + 0x01671C10, > + 0x01671D10, > + 0x01671E01, > + 0x01671F03, > + //Pin widget 0x17 - I2S-OUT > + 0x01771C20, > + 0x01771D01, > + 0x01771E17, > + 0x01771F90, > + //Pin widget 0x18 - I2S-IN > + 0x01871CF0, > + 0x01871D11, > + 0x01871E11, > + 0x01871F41, > + //Pin widget 0x19 - MIC2 (Port-F) > + 0x01971C3E, > + 0x01971D10, > + 0x01971EA1, > + 0x01971F04, > + //Pin widget 0x1A - LINE1 (Port-C) > + 0x01A71CF0, > + 0x01A71D11, > + 0x01A71E11, > + 0x01A71F41, > + //Pin widget 0x1B - LINE2 (Port-E) > + 0x01B71C40, > + 0x01B71D10, > + 0x01B71EA1, > + 0x01B71F03, > + //Pin widget 0x1D - PC-BEEP > + 0x01D71C01, > + 0x01D71D00, > + 0x01D71E60, > + 0x01D71F40, > + //Pin widget 0x1E - S/PDIF-OUT > + 0x01E71CF0, > + 0x01E71D11, > + 0x01E71E11, > + 0x01E71F41, > + //Pin widget 0x1F - S/PDIF-IN > + 0x01F71CF0, > + 0x01F71D11, > + 0x01F71E11, > + 0x01F71F41, > + //Pin widget 0x21 - HP-OUT (Port-I) > + 0x02171C2F, > + 0x02171D10, > + 0x02171E21, > + 0x02171F04, > + //Pin widget 0x29 - I2S-IN > + 0x02971CF0, > + 0x02971D11, > + 0x02971E11, > + 0x02971F41, > + > + //Widget node 0x20 - 0 FAKE JD unplug > + 0x02050008, > + 0x0204A80F, > + 0x02050008, > + 0x0204A80F, > + //Widget node 0x20 - 1 : LINE2-VREFO( MIC2-vrefo-R) base on verb_707h = of > NID 1Bh , HP-JD gating MIC2-vrefo-L, bypass DAC02 DRE(NID5B bit14) > + 0x0205006B, > + 0x02044260, > + 0x0205006B, > + 0x02044260, > + //Widget node 0x20 - 2 : //remove NID 58 realted setting for ALC700 > + 0x05B50010, > + 0x05B45C1D, > + 0x0205006F, > + 0x02040F8B, //Zeek, 0F8Bh > + //Widget node 0x20 -3 : MIC2-Vrefo-R and MIC2-vrefo-L to independent > control > + 0x02050045, > + 0x02045089, > + 0x0205004A, > + 0x0204201B, > + //Widget node 0x20 - 4 From JD detect > + 0x02050008, > + 0x0204A807, > + 0x02050008, > + 0x0204A807, > + //Widget node 0x20 - 5 Pull high ALC700 GPIO5 for AMP1305 PD pin and > enable I2S BCLK first > + 0x02050090, > + 0x02040424, > + 0x00171620, > + 0x00171720, > + > + 0x00171520, > + 0x01770740, > + 0x01770740, > + 0x01770740, > + > + > + //Widget node 0X20 for ALC1305 20181023 update 2W/4ohm to remove > ALC1305 EQ setting > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040000, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x020400CF, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x02045548, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003F, > + 0x02050028, > + 0x02041000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040004, > + 0x02050028, > + 0x02040600, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FFD0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040080, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040880, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003A, > + 0x02050028, > + 0x02040DFE, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x0204005D, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x02040442, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040005, > + 0x02050028, > + 0x02040880, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040006, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040008, > + 0x02050028, > + 0x0204B000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204002E, > + 0x02050028, > + 0x02040800, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x020400C3, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x0204D4A0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x020400CC, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x0204400A, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x020400C1, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x02040320, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040039, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003B, > + 0x02050028, > + 0x0204FFFF, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FC20, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x02040006, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x020400C0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FCA0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FCE0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FCF0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040080, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040880, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040880, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FCE0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FCA0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FC20, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x02040006, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C0, > + 0x02050028, > + 0x020401F0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C1, > + 0x02050028, > + 0x0204C1C7, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C2, > + 0x02050028, > + 0x02041C00, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C3, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C4, > + 0x02050028, > + 0x02040200, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C5, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C6, > + 0x02050028, > + 0x020403E1, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C7, > + 0x02050028, > + 0x02040F5A, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C8, > + 0x02050028, > + 0x02041E1E, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C9, > + 0x02050028, > + 0x0204083F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CA, > + 0x02050028, > + 0x020401F0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CB, > + 0x02050028, > + 0x0204C1C7, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CC, > + 0x02050028, > + 0x02041C00, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CD, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CE, > + 0x02050028, > + 0x02040200, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CF, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400D0, > + 0x02050028, > + 0x020403E1, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400D1, > + 0x02050028, > + 0x02040F5A, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400D2, > + 0x02050028, > + 0x02041E1E, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400D3, > + 0x02050028, > + 0x0204083F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040062, > + 0x02050028, > + 0x02048000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040063, > + 0x02050028, > + 0x02045F5F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040064, > + 0x02050028, > + 0x02042000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040065, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040066, > + 0x02050028, > + 0x02044004, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040067, > + 0x02050028, > + 0x02040802, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040068, > + 0x02050028, > + 0x0204890F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040069, > + 0x02050028, > + 0x0204E021, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040070, > + 0x02050028, > + 0x02048012, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040071, > + 0x02050028, > + 0x02043450, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040072, > + 0x02050028, > + 0x02040123, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040073, > + 0x02050028, > + 0x02044543, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040074, > + 0x02050028, > + 0x02042100, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040075, > + 0x02050028, > + 0x02044321, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040076, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040050, > + 0x02050028, > + 0x02048200, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040051, > + 0x02050028, > + 0x02040707, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040052, > + 0x02050028, > + 0x02044090, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x02040090, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x0204721F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040012, > + 0x02050028, > + 0x0204DFDF, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204009E, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040004, > + 0x02050028, > + 0x02040500, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040060, > + 0x02050028, > + 0x02042213, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003A, > + 0x02050028, > + 0x02041DFE, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003F, > + 0x02050028, > + 0x02043000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040040, > + 0x02050028, > + 0x0204000C, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040046, > + 0x02050028, > + 0x0204C22E, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204004B, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024 > +); > + > + > +// > +// WHL codecs verb tables > +// > +HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 =3D > HDAUDIO_VERB_TABLE_INIT ( > + // > + // VerbTable: (Realtek ALC700) WHL RVP > + // Revision ID =3D 0xff > + // Codec Verb Table for WHL PCH boards > + // Codec Address: CAd value (0/1/2) > + // Codec Vendor: 0x10EC0700 > + // > + 0x10EC, 0x0700, > + 0xFF, 0xFF, > + > //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + // > + // Realtek Semiconductor Corp. > + // > + > //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + > + //Realtek High Definition Audio Configuration - Version : 5.0.3.1 > + //Realtek HD Audio Codec : ALC700 > + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 > + //HDA Codec PnP ID : > HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2 > + //The number of verb command block : 17 > + > + // NID 0x12 : 0x411111F0 > + // NID 0x13 : 0x40000000 > + // NID 0x14 : 0x411111F0 > + // NID 0x15 : 0x411111F0 > + // NID 0x16 : 0x411111F0 > + // NID 0x17 : 0x90170110 > + // NID 0x18 : 0x411111F0 > + // NID 0x19 : 0x02A19040 > + // NID 0x1A : 0x411111F0 > + // NID 0x1B : 0x411111F0 > + // NID 0x1D : 0x40638029 > + // NID 0x1E : 0x411111F0 > + // NID 0x1F : 0x411111F0 > + // NID 0x21 : 0x02211020 > + // NID 0x29 : 0x411111F0 > + > + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D > + //HDA Codec Subsystem ID : 0x10EC10F2 > + 0x001720F2, > + 0x00172110, > + 0x001722EC, > + 0x00172310, > + > + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D > + //Widget node 0x01 : > + 0x0017FF00, > + 0x0017FF00, > + 0x0017FF00, > + 0x0017FF00, > + //Pin widget 0x12 - DMIC > + 0x01271CF0, > + 0x01271D11, > + 0x01271E11, > + 0x01271F41, > + //Pin widget 0x13 - DMIC > + 0x01371C00, > + 0x01371D00, > + 0x01371E00, > + 0x01371F40, > + //Pin widget 0x14 - FRONT (Port-D) > + 0x01471CF0, > + 0x01471D11, > + 0x01471E11, > + 0x01471F41, > + //Pin widget 0x15 - I2S-OUT > + 0x01571CF0, > + 0x01571D11, > + 0x01571E11, > + 0x01571F41, > + //Pin widget 0x16 - LINE3 (Port-B) > + 0x01671CF0, > + 0x01671D11, > + 0x01671E11, > + 0x01671F41, > + //Pin widget 0x17 - I2S-OUT > + 0x01771C10, > + 0x01771D01, > + 0x01771E17, > + 0x01771F90, > + //Pin widget 0x18 - I2S-IN > + 0x01871CF0, > + 0x01871D11, > + 0x01871E11, > + 0x01871F41, > + //Pin widget 0x19 - MIC2 (Port-F) > + 0x01971C40, > + 0x01971D90, > + 0x01971EA1, > + 0x01971F02, > + //Pin widget 0x1A - LINE1 (Port-C) > + 0x01A71CF0, > + 0x01A71D11, > + 0x01A71E11, > + 0x01A71F41, > + //Pin widget 0x1B - LINE2 (Port-E) > + 0x01B71CF0, > + 0x01B71D11, > + 0x01B71E11, > + 0x01B71F41, > + //Pin widget 0x1D - PC-BEEP > + 0x01D71C29, > + 0x01D71D80, > + 0x01D71E63, > + 0x01D71F40, > + //Pin widget 0x1E - S/PDIF-OUT > + 0x01E71CF0, > + 0x01E71D11, > + 0x01E71E11, > + 0x01E71F41, > + //Pin widget 0x1F - S/PDIF-IN > + 0x01F71CF0, > + 0x01F71D11, > + 0x01F71E11, > + 0x01F71F41, > + //Pin widget 0x21 - HP-OUT (Port-I) > + 0x02171C20, > + 0x02171D10, > + 0x02171E21, > + 0x02171F02, > + //Pin widget 0x29 - I2S-IN > + 0x02971CF0, > + 0x02971D11, > + 0x02971E11, > + 0x02971F41, > + //Widget node 0x20 - 0 FAKE JD unplug > + 0x02050008, > + 0x0204A80F, > + 0x02050008, > + 0x0204A80F, > + > + //Widget node 0x20 - 1 : //remove NID 58 realted setting for ALC700 b= ypass > DAC02 DRE(NID5B bit14) > + 0x05B50010, > + 0x05B45C1D, > + 0x0205006F, > + 0x02040F8B, //Zeek, 0F8Bh > + > + //Widget node 0x20 -2: > + 0x02050045, > + 0x02045089, > + 0x0205004A, > + 0x0204201B, > + > + //Widget node 0x20 - 3 From JD detect > + 0x02050008, > + 0x0204A807, > + 0x02050008, > + 0x0204A807, > + > + //Widget node 0x20 - 4 Pull high ALC700 GPIO5 for AMP1305 PD pin and > enable I2S BCLK first > + 0x02050090, > + 0x02040424, > + 0x00171620, > + 0x00171720, > + > + 0x00171520, > + 0x01770740, > + 0x01770740, > + 0x01770740, > + > + //Widget node 0x20 for ALC1305 20181105 update 2W/4ohm to remove > ALC1305 EQ setting and enable ALC1305 silencet detect to prevent I2S nois= e > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040000, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x020400CF, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x02045548, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003F, > + 0x02050028, > + 0x02041000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040004, > + 0x02050028, > + 0x02040600, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FFD0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040080, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040880, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003A, > + 0x02050028, > + 0x02040DFE, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x0204005D, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x02040442, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040005, > + 0x02050028, > + 0x02040880, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040006, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040008, > + 0x02050028, > + 0x0204B000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204002E, > + 0x02050028, > + 0x02040800, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x020400C3, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x0204D4A0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x020400CC, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x0204400A, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x020400C1, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x02040320, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040039, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003B, > + 0x02050028, > + 0x0204FFFF, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FC20, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x02040006, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x020400C0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FCA0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FCE0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FCF0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040080, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040880, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040880, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FCE0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FCA0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003C, > + 0x02050028, > + 0x0204FC20, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x02040006, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040080, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C0, > + 0x02050028, > + 0x020401F0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C1, > + 0x02050028, > + 0x0204C1C7, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C2, > + 0x02050028, > + 0x02041C00, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C3, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C4, > + 0x02050028, > + 0x02040200, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C5, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C6, > + 0x02050028, > + 0x020403E1, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C7, > + 0x02050028, > + 0x02040F5A, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C8, > + 0x02050028, > + 0x02041E1E, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400C9, > + 0x02050028, > + 0x0204083F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CA, > + 0x02050028, > + 0x020401F0, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CB, > + 0x02050028, > + 0x0204C1C7, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CC, > + 0x02050028, > + 0x02041C00, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CD, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CE, > + 0x02050028, > + 0x02040200, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400CF, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400D0, > + 0x02050028, > + 0x020403E1, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400D1, > + 0x02050028, > + 0x02040F5A, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400D2, > + 0x02050028, > + 0x02041E1E, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x020400D3, > + 0x02050028, > + 0x0204083F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040062, > + 0x02050028, > + 0x02048000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040063, > + 0x02050028, > + 0x02045F5F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040064, > + 0x02050028, > + 0x02042000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040065, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040066, > + 0x02050028, > + 0x02044004, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040067, > + 0x02050028, > + 0x02040802, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040068, > + 0x02050028, > + 0x0204890F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040069, > + 0x02050028, > + 0x0204E021, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040070, > + 0x02050028, > + 0x02048012, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040071, > + 0x02050028, > + 0x02043450, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040072, > + 0x02050028, > + 0x02040123, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040073, > + 0x02050028, > + 0x02044543, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040074, > + 0x02050028, > + 0x02042100, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040075, > + 0x02050028, > + 0x02044321, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040076, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040050, > + 0x02050028, > + 0x02048200, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040051, > + 0x02050028, > + 0x02040707, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040052, > + 0x02050028, > + 0x02044090, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006A, > + 0x02050028, > + 0x02040090, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204006C, > + 0x02050028, > + 0x0204721F, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040012, > + 0x02050028, > + 0x0204DFDF, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204009E, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040004, > + 0x02050028, > + 0x02040500, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040060, > + 0x02050028, > + 0x0204E213, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003A, > + 0x02050028, > + 0x02041DFE, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204003F, > + 0x02050028, > + 0x02043000, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040040, > + 0x02050028, > + 0x0204000C, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x02040046, > + 0x02050028, > + 0x0204422E, > + 0x02050029, > + 0x0204B024, > + > + 0x02050024, > + 0x02040010, > + 0x02050026, > + 0x0204004B, > + 0x02050028, > + 0x02040000, > + 0x02050029, > + 0x0204B024 > +); // WhlHdaVerbTableAlc700 > + > +#endif // _PCH_HDA_VERB_TABLES_H_ > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeMePolicyUpdate.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeMePolicyUpdate.h > new file mode 100644 > index 0000000000..8cbcace075 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeMePolicyUpdate.h > @@ -0,0 +1,91 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _DXE_ME_POLICY_UPDATE_H_ > +#define _DXE_ME_POLICY_UPDATE_H_ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define PLATFORM_BOOT_TABLE_PTR_TYPE 0x1001 > +#define PLATFORM_BOOT_RECORD_TYPE 0x1022 > +// > +// Timeout values based on HPET > +// > +#define HECI_MSG_DELAY 2000000 ///< show warning msg an= d > stay for 2 seconds. > +#define CONVERSION_MULTIPLIER 1000000 ///< msec to nanosec > multiplier > +#define PLATFORM_BOOT_TABLE_SIGNATURE SIGNATURE_32 ('P', 'B', 'P', 'T') > + > +// > +// Platform Boot Performance Table Record > +// > + > +typedef struct { > + UINT16 Type; > + UINT8 Length; > + UINT8 Revision; > + UINT32 Reserved; > + UINT64 TimestampDelta1; > + UINT64 TimestampDelta2; > + UINT64 TimestampDelta3; > +} PLATFORM_BOOT_TABLE_RECORD; > + > +// > +// Platform boot Performance Table > +// > + > +typedef struct { > + EFI_ACPI_COMMON_HEADER Header; > + PLATFORM_BOOT_TABLE_RECORD PlatformBoot; > +} PLATFORM_BOOT_PERFORMANCE_TABLE; > + > +/** > + Update ME Policy while MePlatformProtocol is installed. > + > + @param[in] MePolicyInstance Instance of ME Policy Protocol > + > +**/ > +VOID > +UpdateMePolicyFromMeSetup ( > + IN ME_POLICY_PROTOCOL *MePolicyInstance > + ); > + > +/** > + Update ME Policy if Setup variable exists. > + > + @param[in, out] MePolicyInstance Instance of ME Policy Protocol > + > +**/ > +VOID > +UpdateMePolicyFromSetup ( > + IN OUT ME_POLICY_PROTOCOL *MePolicyInstance > + ); > + > +/** > + Functions performs HECI exchange with FW to update MePolicy settings. > + > + @param[in] Event A pointer to the Event that triggered the cal= lback. > + @param[in] Context A pointer to private data registered with the > callback function. > + > +**/ > +VOID > +EFIAPI > +UpdateMeSetupCallback ( > + IN EFI_EVENT Event, > + IN VOID *Context > + ); > + > +#endif > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeSaPolicyUpdate.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeSaPolicyUpdate.h > new file mode 100644 > index 0000000000..4521d83567 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeSaPolicyUpdate.h > @@ -0,0 +1,25 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _DXE_SA_POLICY_UPDATE_H_ > +#define _DXE_SA_POLICY_UPDATE_H_ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#endif > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiCpuPolicyInit.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiCpuPolicyInit.h > new file mode 100644 > index 0000000000..25c5213c2d > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiCpuPolicyInit.h > @@ -0,0 +1,37 @@ > +/** @file > + Header file for the PeiCpuPolicyInit. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_CPU_POLICY_INIT_H_ > +#define _PEI_CPU_POLICY_INIT_H_ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + This function performs CPU PEI Policy initialization in PreMem. > + > + @param[in, out] SiPreMemPolicyPpi The Si Pre-Mem Policy PPI instance > + > + @retval EFI_SUCCESS The PPI is installed and initialized. > + @retval EFI ERRORS The PPI is not successfully installed. > + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver > +**/ > +EFI_STATUS > +EFIAPI > +UpdatePeiCpuPolicyPreMem ( > + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi > + ); > +#endif > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiMePolicyInit.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiMePolicyInit.h > new file mode 100644 > index 0000000000..7f3fde9fd8 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiMePolicyInit.h > @@ -0,0 +1,23 @@ > +/** @file > + Header file for the PeiMePolicyInit > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_ME_POLICY_INIT_H_ > +#define _PEI_ME_POLICY_INIT_H_ > + > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > + > +#endif // _PEI_ME_POLICY_INIT_H_ > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiPolicyInit.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiPolicyInit.h > new file mode 100644 > index 0000000000..9c18f85735 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiPolicyInit.h > @@ -0,0 +1,23 @@ > +/** @file > + Header file for the PolicyInitPei PEIM. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_POLICY_INIT_H_ > +#define _PEI_POLICY_INIT_H_ > + > +#include > +#include > +#include > + > +#include "PeiCpuPolicyInit.h" > +#include "PeiMePolicyInit.h" > +#include "PeiSaPolicyInit.h" > +#include "PeiSiPolicyInit.h" > +#include > +#include > +#endif > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiSaPolicyInit.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiSaPolicyInit.h > new file mode 100644 > index 0000000000..83b18bf533 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiSaPolicyInit.h > @@ -0,0 +1,58 @@ > +/** @file > + Header file for the SaPolicyInitPei PEIM. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _SA_POLICY_INIT_PEI_H_ > +#define _SA_POLICY_INIT_PEI_H_ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +// > +// Functions > +// > +/** > +PCIe GPIO Write > + > +@param[in] Gpio - GPIO Number > +@param[in] Active - GPIO Active Information; High/Low > +@param[in] Level - Write GPIO value (0/1) > + > +**/ > +VOID > +PcieGpioWrite( > +IN UINT32 Gpio, > +IN BOOLEAN Active, > +IN BOOLEAN Level > +); > + > +/** > +PcieCardResetWorkAround performs PCIe Card reset on root port > + > +@param[in out] SiPreMemPolicyPpi - SI_PREMEM_POLICY_PPI > + > +@retval EFI_SUCCESS The policy is installed and initialized= . > +**/ > +EFI_STATUS > +PcieCardResetWorkAround( > +IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi > +); > +#endif > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiSiPolicyInit.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiSiPolicyInit.h > new file mode 100644 > index 0000000000..1a28f426d6 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiSiPolicyInit.h > @@ -0,0 +1,22 @@ > +/** @file > + Header file for the PeiSiPolicyInit > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _SI_POLICY_INIT_PEI_H_ > +#define _SI_POLICY_INIT_PEI_H_ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#endif // _SI_POLICY_INIT_PEI_H_ > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiCpuPolicyUpdate.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiCpuPolicyUpdate.h > new file mode 100644 > index 0000000000..254e58edb7 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiCpuPolicyUpdate.h > @@ -0,0 +1,32 @@ > +/** @file > + Header file for PEI CpuPolicyUpdate. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_CPU_POLICY_UPDATE_H_ > +#define _PEI_CPU_POLICY_UPDATE_H_ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "PeiPchPolicyUpdate.h" > +#include > + > +#endif > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiMePolicyUpdate.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiMePolicyUpdate.h > new file mode 100644 > index 0000000000..37cd373c78 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiMePolicyUpdate.h > @@ -0,0 +1,14 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_ME_POLICY_UPDATE_H_ > +#define _PEI_ME_POLICY_UPDATE_H_ > + > +#include > +#include > + > +#endif > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiPchPolicyUpdate.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiPchPolicyUpdate.h > new file mode 100644 > index 0000000000..5a69852801 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiPchPolicyUpdate.h > @@ -0,0 +1,25 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_PCH_POLICY_UPDATE_H_ > +#define _PEI_PCH_POLICY_UPDATE_H_ > + > +// > +// External include files do NOT need to be explicitly specified in real= EDKII > +// environment > +// > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#endif > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSaPolicyUpdate.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSaPolicyUpdate.h > new file mode 100644 > index 0000000000..8cf24ed24d > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSaPolicyUpdate.h > @@ -0,0 +1,53 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_SA_POLICY_UPDATE_H_ > +#define _PEI_SA_POLICY_UPDATE_H_ > + > +// > +// External include files do NOT need to be explicitly specified in real= EDKII > +// environment > +// > +#include > +#include > +#include > +#include > +#include > +#include > +#include "PeiPchPolicyUpdate.h" > +#include > +#include > +#include > + > +#define WDT_TIMEOUT 60 > + > +// BClk Frequency Limitations (in Hz) > +#define BCLK_MAX 538000000 > +#define BCLK_100 100000000 > +#define BCLK_GRANULARITY 1000000 > +#define BCLK_100_KHZ 100000 > + > + > +/** > + PeiGetSectionFromFv finds the file in FV and gets file Address and Siz= e > + > + @param[in] NameGuid - File GUID > + @param[out] Address - Pointer to the File Address > + @param[out] Size - Pointer to File Size > + > + @retval EFI_SUCCESS Successfull in reading the section = from FV > +**/ > +EFI_STATUS > +EFIAPI > +PeiGetSectionFromFv ( > + IN CONST EFI_GUID NameGuid, > + OUT VOID **Address, > + OUT UINT32 *Size > + ); > + > +#endif > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSiPolicyUpdate.h > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSiPolicyUpdate.h > new file mode 100644 > index 0000000000..38ea081166 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSiPolicyUpdate.h > @@ -0,0 +1,19 @@ > +/** @file > + Header file for PEI SiPolicyUpdate. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_SI_POLICY_UPDATE_H_ > +#define _PEI_SI_POLICY_UPDATE_H_ > + > +#include > +#include > +#include > +#include > +#include > + > +#endif > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPo > licyLib/DxeTbtPolicyLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPo > licyLib/DxeTbtPolicyLib.c > new file mode 100644 > index 0000000000..c185cda4ce > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPo > licyLib/DxeTbtPolicyLib.c > @@ -0,0 +1,148 @@ > +/** @file > + This file is DxeTbtPolicyLib library. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > + > + > +/** > + Update Tbt Policy Callback > +**/ > + > +VOID > +EFIAPI > +UpdateTbtPolicyCallback ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig; > + > + DxeTbtConfig =3D NULL; > + Status =3D EFI_NOT_FOUND; > + DEBUG ((DEBUG_INFO, "UpdateTbtPolicyCallback\n")); > + > + Status =3D gBS->LocateProtocol ( > + &gDxeTbtPolicyProtocolGuid, > + NULL, > + (VOID **) &DxeTbtConfig > + ); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not > installed!!!\n")); > + } else { > + > + } > + > + return; > +} > + > +/** > + Print DXE TBT Policy > +**/ > +VOID > +TbtPrintDxePolicyConfig ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + UINT8 Index; > + DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig; > + > + DEBUG ((DEBUG_INFO, "TbtPrintDxePolicyConfig Start\n")); > + > + DxeTbtConfig =3D NULL; > + Status =3D EFI_NOT_FOUND; > + Status =3D gBS->LocateProtocol ( > + &gDxeTbtPolicyProtocolGuid, > + NULL, > + (VOID **) &DxeTbtConfig > + ); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not > installed!!!\n")); > + } > + ASSERT_EFI_ERROR (Status); > + // > + // Print DTBT Policy > + // > + DEBUG ((DEBUG_ERROR, " =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D DXE TBT POLICY > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D \n")); > + for (Index =3D 0; Index < MAX_DTBT_CONTROLLER_NUMBER; Index++) { > + DEBUG ((DEBUG_INFO, > "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieExtraBusRsvd =3D %x\n", > Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPcieExtraBusRsvd)); > + DEBUG ((DEBUG_INFO, > "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieMemRsvd =3D %x\n", Index, > DxeTbtConfig->DTbtResourceConfig[Index].DTbtPcieMemRsvd)); > + DEBUG ((DEBUG_INFO, > "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieMemAddrRngMax =3D %x\n", > Index, > DxeTbtConfig->DTbtResourceConfig[Index].DTbtPcieMemAddrRngMax)); > + DEBUG ((DEBUG_INFO, > "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPciePMemRsvd =3D %x\n", Index, > DxeTbtConfig->DTbtResourceConfig[Index].DTbtPciePMemRsvd)); > + DEBUG ((DEBUG_INFO, > "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPciePMemAddrRngMax =3D > %x\n", Index, > DxeTbtConfig->DTbtResourceConfig[Index].DTbtPciePMemAddrRngMax)); > + } > + > + // > + // Print TBT Common Policy > + // > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAspm =3D > %x\n", DxeTbtConfig->TbtCommonConfig.TbtAspm)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtL1SubStates > =3D %x\n", DxeTbtConfig->TbtCommonConfig.TbtL1SubStates)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotNotify =3D > %x\n", DxeTbtConfig->TbtCommonConfig.TbtHotNotify)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotSMI =3D > %x\n", DxeTbtConfig->TbtCommonConfig.TbtHotSMI)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtLtr =3D %x\n", > DxeTbtConfig->TbtCommonConfig.TbtLtr)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtPtm =3D %x\n", > DxeTbtConfig->TbtCommonConfig.TbtPtm)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtSetClkReq =3D > %x\n", DxeTbtConfig->TbtCommonConfig.TbtSetClkReq)); > + DEBUG ((DEBUG_INFO, > "DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport =3D %x\n", > DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.SecurityMode =3D > %x\n", DxeTbtConfig->TbtCommonConfig.SecurityMode)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Gpio5Filter =3D > %x\n", DxeTbtConfig->TbtCommonConfig.Gpio5Filter)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TrA0OsupWa =3D > %x\n", DxeTbtConfig->TbtCommonConfig.TrA0OsupWa)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch > =3D %x\n", DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3Tbt =3D > %x\n", DxeTbtConfig->TbtCommonConfig.Rtd3Tbt)); > + DEBUG ((DEBUG_INFO, > "DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay =3D %x\n", > DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq > =3D %x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq)); > + DEBUG ((DEBUG_INFO, > "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay =3D %x\n", > DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Win10Support > =3D %x\n", DxeTbtConfig->TbtCommonConfig.Win10Support)); > + DEBUG ((DEBUG_INFO, > "DxeTbtConfig->TbtCommonConfig.TbtVtdBaseSecurity =3D %x\n", > DxeTbtConfig->TbtCommonConfig.TbtVtdBaseSecurity)); > + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.ControlIommu > =3D %x\n", DxeTbtConfig->TbtCommonConfig.ControlIommu)); > + return; > +} > + > +/** > + Install Tbt Policy > + > + @param[in] ImageHandle Image handle of this driver. > + > + @retval EFI_SUCCESS The policy is installed. > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer > + > +**/ > +EFI_STATUS > +EFIAPI > +InstallTbtPolicy ( > + IN EFI_HANDLE ImageHandle > + ) > +{ > + EFI_STATUS Status; > + DXE_TBT_POLICY_PROTOCOL *DxeTbtPolicy; > + > + DEBUG ((DEBUG_INFO, "Install DXE TBT Policy\n")); > + > + DxeTbtPolicy =3D NULL; > + //Alloc memory for DxeTbtPolicy > + DxeTbtPolicy =3D (DXE_TBT_POLICY_PROTOCOL *) AllocateZeroPool (sizeof > (DXE_TBT_POLICY_PROTOCOL)); > + if (DxeTbtPolicy =3D=3D NULL) { > + return EFI_OUT_OF_RESOURCES; > + } > + > + Status =3D gBS->InstallProtocolInterface ( > + &ImageHandle, > + &gDxeTbtPolicyProtocolGuid, > + EFI_NATIVE_INTERFACE, > + DxeTbtPolicy > + ); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Install Tbt Secure Boot List protocol failed\n= ")); > + } > + return Status; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSm > mTbtCommonLib/TbtCommonLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSm > mTbtCommonLib/TbtCommonLib.c > new file mode 100644 > index 0000000000..690c9acf95 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSm > mTbtCommonLib/TbtCommonLib.c > @@ -0,0 +1,316 @@ > +/** @file > + PeiTbtInit library implementition with empty functions. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > + > +/** > + Selects the proper TBT Root port to assign resources > + based on the user input value > + > + @param[in] SetupData Pointer to Setup data > + > + @retval TbtSelectorChosen Rootport number. > +**/ > +VOID > +GetRootporttoSetResourcesforTbt ( > + IN UINTN RpIndex, > + OUT UINT8 *RsvdExtraBusNum, > + OUT UINT16 *RsvdPcieMegaMem, > + OUT UINT8 *PcieMemAddrRngMax, > + OUT UINT16 *RsvdPciePMegaMem, > + OUT UINT8 *PciePMemAddrRngMax, > + OUT BOOLEAN *SetResourceforTbt > + ) > +{ > + UINTN TbtRpNumber; > + TbtRpNumber =3D (UINTN) PcdGet8 (PcdDTbtPcieRpNumber); > + > + if (RpIndex =3D=3D (TbtRpNumber - 1)) { > + *RsvdExtraBusNum =3D PcdGet8 (PcdDTbtPcieExtraBusRsvd); > + *RsvdPcieMegaMem =3D PcdGet16 (PcdDTbtPcieMemRsvd); > + *PcieMemAddrRngMax =3D PcdGet8 (PcdDTbtPcieMemAddrRngMax); > + *RsvdPciePMegaMem =3D PcdGet16 (PcdDTbtPciePMemRsvd); > + *PciePMemAddrRngMax =3D PcdGet8 (PcdDTbtPciePMemAddrRngMax); > + *SetResourceforTbt =3D TRUE; > + } > + else { > + *SetResourceforTbt =3D FALSE; > + } > + } > + > +/** > + Internal function to Wait for Tbt2PcieDone Bit.to Set or clear > + @param[in] CommandOffsetAddress Tbt2Pcie Register Address > + @param[in] TimeOut Time out with 100 ms garnularity > + @param[in] Tbt2PcieDone Wait condition (wait for Bit to > Clear/Set) > + @param[out] *Tbt2PcieValue Function Register value > +**/ > +BOOLEAN > +InternalWaitforCommandCompletion( > + IN UINT64 CommandOffsetAddress, > + IN UINT32 TimeOut, > + IN BOOLEAN Tbt2PcieDone, > + OUT UINT32 *Tbt2PcieValue > + ) > +{ > + BOOLEAN ReturnFlag; > + UINT32 Tbt2PcieCheck; > + > + ReturnFlag =3D FALSE; > + while (TimeOut-- > 0) { > + *Tbt2PcieValue =3D PciSegmentRead32 (CommandOffsetAddress); > + > + if (0xFFFFFFFF =3D=3D *Tbt2PcieValue ) { > + // > + // Device is not here return now > + // > + ReturnFlag =3D FALSE; > + break; > + } > + > + if(Tbt2PcieDone) { > + Tbt2PcieCheck =3D *Tbt2PcieValue & TBT2PCIE_DON_R; > + } else { > + Tbt2PcieCheck =3D !(*Tbt2PcieValue & TBT2PCIE_DON_R); > + } > + > + if (Tbt2PcieCheck) { > + ReturnFlag =3D TRUE; > + break; > + } > + > + MicroSecondDelay(TBT_MAIL_BOX_DELAY); > + } > + return ReturnFlag; > +} > +/** > + Get Security Level. > + @param[in] Bus Bus number Host Router (DTBT) > + @param[in] Device Device number for Host Router (DTBT) > + @param[in] Function Function number for Host Router (DTBT) > + @param[in] Command Command for Host Router (DTBT) > + @param[in] Timeout Time out with 100 ms garnularity > +**/ > +UINT8 > +GetSecLevel ( > + IN UINT8 Bus, > + IN UINT8 Device, > + IN UINT8 Function, > + IN UINT8 Command, > + IN UINT32 Timeout > + ) > +{ > + UINT64 Pcie2Tbt; > + UINT64 Tbt2Pcie; > + UINT32 RegisterValue; > + UINT8 ReturnFlag; > + > + ReturnFlag =3D 0xFF; > + > + DEBUG ((DEBUG_INFO, "GetSecLevel() \n")); > + > + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) > + GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) > + > + PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B); > + > + if(InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, > &RegisterValue)) { > + ReturnFlag =3D (UINT8) (0xFF & (RegisterValue >> 8)); > + } > + > + PciSegmentWrite32 (Pcie2Tbt, 0); > + > + InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, > &RegisterValue); > + DEBUG ((DEBUG_INFO, "Security Level configured to %x \n", ReturnFlag))= ; > + > + return ReturnFlag; > +} > + > +/** > + Set Security Level. > + @param[in] Data Security State > + @param[in] Bus Bus number for Host Router (DTBT) > + @param[in] Device Device number for Host Router (DTBT) > + @param[in] Function Function number for Host Router (DTBT) > + @param[in] Command Command for Host Router (DTBT) > + @param[in] Timeout Time out with 100 ms garnularity > +**/ > +BOOLEAN > +SetSecLevel ( > + IN UINT8 Data, > + IN UINT8 Bus, > + IN UINT8 Device, > + IN UINT8 Function, > + IN UINT8 Command, > + IN UINT32 Timeout > + ) > +{ > + UINT64 Pcie2Tbt; > + UINT64 Tbt2Pcie; > + UINT32 RegisterValue; > + BOOLEAN ReturnFlag; > + > + ReturnFlag =3D FALSE; > + > + DEBUG ((DEBUG_INFO, "SetSecLevel() \n")); > + > + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) > + GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) > + > + PciSegmentWrite32 (Pcie2Tbt, (Data << 8) | Command | PCIE2TBT_VLD_B); > + > + ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, > TRUE, &RegisterValue); > + DEBUG ((DEBUG_INFO, "RegisterValue %x \n", RegisterValue)); > + PciSegmentWrite32 (Pcie2Tbt, 0); > + > + InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, > &RegisterValue); > + DEBUG ((DEBUG_INFO, "Return value %x \n", ReturnFlag)); > + return ReturnFlag; > +} > + > +/** > +Based on the Security Mode Selection, BIOS drives FORCE_PWR. > + > +@param[in] GpioNumber > +@param[in] Value > +**/ > +VOID > +ForceDtbtPower( > + IN UINT8 GpioAccessType, > + IN UINT8 Expander, > + IN UINT32 GpioNumber, > + IN BOOLEAN Value > +) > +{ > + if (GpioAccessType =3D=3D 0x01) { > + // PCH > + GpioSetOutputValue (GpioNumber, (UINT32)Value); > + } else if (GpioAccessType =3D=3D 0x02) { > + // IoExpander {TCA6424A} > + GpioExpSetOutput (Expander, (UINT8)GpioNumber, (UINT8)Value); > + } > +} > + > +/** > +Execute TBT Mail Box Command > + > +@param[in] Command TBT Command > +@param[in] Bus Bus number for Host Router (DTBT) > +@param[in] Device Device number for Host Router (DTBT) > +@param[in] Function Function number for Host Router (DTBT) > +@param[in] Timeout Time out with 100 ms garnularity > +@Retval true if command executes succesfully > +**/ > +BOOLEAN > +TbtSetPcie2TbtCommand( > + IN UINT8 Command, > + IN UINT8 Bus, > + IN UINT8 Device, > + IN UINT8 Function, > + IN UINT32 Timeout > +) > +{ > + UINT64 Pcie2Tbt; > + UINT64 Tbt2Pcie; > + UINT32 RegisterValue; > + BOOLEAN ReturnFlag; > + > + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) > + GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) > + > + PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B); > + > + ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, > TRUE, &RegisterValue); > + > + PciSegmentWrite32(Pcie2Tbt, 0); > + > + return ReturnFlag; > +} > +/** > + Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root > Port physical Number > + > + @param[in] RpNumber Root port physical number. (0-based) > + @param[out] RpDev Return corresponding root port devic= e > number. > + @param[out] RpFun Return corresponding root port funct= ion > number. > + > + @retval EFI_SUCCESS Root port device and function is ret= rieved > + @retval EFI_INVALID_PARAMETER If Invalid Root Port Number or TYPE = is > Passed > +**/ > +EFI_STATUS > +EFIAPI > +GetDTbtRpDevFun ( > + IN BOOLEAN Type, > + IN UINTN RpNumber, > + OUT UINTN *RpDev, > + OUT UINTN *RpFunc > + ) > +{ > + EFI_STATUS Status; > + UINTN TbtRpDev; > + UINTN TbtRpFunc; > + > + Status =3D EFI_INVALID_PARAMETER; // Update the Status to EFI_SUCCESS = if > valid input found. > + // > + // PCH-H can support up to 24 root ports. PEG0,PEG1 and PEG2 will be > + // with device number 0x1 and Function number 0,1 and 2 respectively. > + // > + if (Type =3D=3D DTBT_TYPE_PEG) > + { > + // > + // PEG Rootport > + // > + if (RpNumber <=3D 2) { > + *RpDev =3D 0x01; > + *RpFunc =3D RpNumber; > + Status =3D EFI_SUCCESS; > + } > + } > + if (Type =3D=3D DTBT_TYPE_PCH) > + { > + // > + // PCH Rootport > + // > + if (RpNumber <=3D 23) { > + Status =3D GetPchPcieRpDevFun (RpNumber, &TbtRpDev, &TbtRpFunc); > + *RpDev =3D TbtRpDev; > + *RpFunc =3D TbtRpFunc; > + } > + } > + > + ASSERT_EFI_ERROR (Status); > + return Status; > +} > + > +BOOLEAN > +IsTbtHostRouter ( > + IN UINT16 DeviceID > + ) > +{ > + switch (DeviceID) { > + case AR_HR_2C: > + case AR_HR_4C: > + case AR_HR_LP: > + case AR_HR_C0_2C: > + case AR_HR_C0_4C: > + case TR_HR_2C: > + case TR_HR_4C: > + return TRUE; > + } > + > + return FALSE; > +} // IsTbtHostRouter > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol > icyLib/PeiTbtPolicyLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol > icyLib/PeiTbtPolicyLib.c > new file mode 100644 > index 0000000000..ffd8416660 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol > icyLib/PeiTbtPolicyLib.c > @@ -0,0 +1,206 @@ > +/** @file > + This file is PeiTbtPolicyLib library. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Update PEI TBT Policy Callback > +**/ > +VOID > +EFIAPI > +UpdatePeiTbtPolicy ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; > + PEI_TBT_POLICY *PeiTbtConfig; > + > + PeiTbtConfig =3D NULL; > + Status =3D EFI_NOT_FOUND; > + > + DEBUG ((DEBUG_INFO, "UpdatePeiTbtPolicy \n")); > + > + Status =3D PeiServicesLocatePpi ( > + &gEfiPeiReadOnlyVariable2PpiGuid, > + 0, > + NULL, > + (VOID **) &VariableServices > + ); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D PeiServicesLocatePpi ( > + &gPeiTbtPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &PeiTbtConfig > + ); > + if (EFI_ERROR(Status)) { > + DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); > + } > + ASSERT_EFI_ERROR (Status); > + > + // > + // Update DTBT Policy > + // > + PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn =3D PcdGet8 > (PcdDTbtControllerEn); > + if (PcdGet8 (PcdDTbtControllerType) =3D=3D TYPE_PEG) > + { > + PeiTbtConfig-> DTbtControllerConfig.Type =3D (UINT8) TYPE_PEG; > + PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber =3D 1; // PEG RP 1 > (Function no. 0) > + } > + else { > + PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber =3D PcdGet8 > (PcdDTbtPcieRpNumber); > + PeiTbtConfig-> DTbtControllerConfig.Type =3D PcdGet8 > (PcdDTbtControllerType); > + } > + PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.GpioPad =3D > (GPIO_PAD) PcdGet32 (PcdDTbtCioPlugEventGpioPad); > + if > (GpioCheckFor2Tier(PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio. > GpioPad)) { > + > PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePor > ting =3D 0; > + > PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature =3D > SIGNATURE_32('X', 'T', 'B', 'T'); > + } > + else { > + > PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePor > ting =3D 1; > + // > + // Update Signature based on platform GPIO. > + // > + > PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature =3D > SIGNATURE_32('X', 'T', 'B', 'T'); > + } > + PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D PcdGet8 > (PcdDTbtBootOn); > + PeiTbtConfig->DTbtCommonConfig.TbtUsbOn =3D PcdGet8 (PcdDTbtUsbOn); > + PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr =3D PcdGet8 > (PcdDTbtGpio3ForcePwr); > + PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly =3D PcdGet16 > (PcdDTbtGpio3ForcePwrDly); > + > + return; > +} > + > +/** > + Print PEI TBT Policy > +**/ > +VOID > +EFIAPI > +TbtPrintPeiPolicyConfig ( > + VOID > + ) > +{ > + DEBUG_CODE_BEGIN (); > + EFI_STATUS Status; > + PEI_TBT_POLICY *PeiTbtConfig; > + > + PeiTbtConfig =3D NULL; > + Status =3D EFI_NOT_FOUND; > + DEBUG ((DEBUG_INFO, "TbtPrintPolicyConfig Start\n")); > + > + Status =3D PeiServicesLocatePpi ( > + &gPeiTbtPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &PeiTbtConfig > + ); > + if (EFI_ERROR(Status)) { > + DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); > + } > + ASSERT_EFI_ERROR (Status); > + > + // > + // Print DTBT Policy > + // > + DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print= BEGIN > -----------------\n")); > + DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", PEI_TBT_POLICY_REVISION)); > + DEBUG ((DEBUG_INFO, "------------------------ PEI_TBT_CONFIG > -----------------\n")); > + DEBUG ((DEBUG_INFO, " Revision : %d\n", PEI_TBT_POLICY_REVISION)); > + > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtControllerConfig.DTbtControllerEn =3D %x\n", > PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn)); > + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.Type =3D %x\n"= , > PeiTbtConfig-> DTbtControllerConfig.Type)); > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtControllerConfig.PcieRpNumber =3D %x\n", PeiTbtConfig-= > > DTbtControllerConfig.PcieRpNumber)); > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.GpioPad =3D %x\n", > PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad)); > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.GpioLevel =3D %x\n", > PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioLevel)); > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.GpioPad =3D %x\n", > PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioPad)); > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.GpioLevel =3D %x\n", > PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioLevel)); > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.GpioPad =3D %x\n", > PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.GpioPad)); > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature =3D > %x\n", PeiTbtConfig-> > DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature)); > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePo > rting =3D %x\n", PeiTbtConfig-> > DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorting)); > + > + > + // > + // Print DTBT Common Policy > + // > + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D > %x\n", PeiTbtConfig->DTbtCommonConfig.TbtBootOn)); > + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtUsbOn =3D > %x\n", PeiTbtConfig->DTbtCommonConfig.TbtUsbOn)); > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr =3D %x\n", > PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr)); > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly =3D %x\n", > PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly)); > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfiguration =3D %x\n", > PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfiguration)); > + DEBUG ((DEBUG_INFO, > "PeiTbtConfig->DTbtCommonConfig.PcieRstSupport =3D %x\n", > PeiTbtConfig->DTbtCommonConfig.PcieRstSupport)); > + > + DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print= END > -----------------\n")); > + DEBUG_CODE_END (); > + > + return; > +} > + > +/** > + Install Tbt Policy > + > + @retval EFI_SUCCESS The policy is installed. > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer > + > +**/ > +EFI_STATUS > +EFIAPI > +InstallPeiTbtPolicy ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + EFI_PEI_PPI_DESCRIPTOR *PeiTbtPolicyPpiDesc; > + PEI_TBT_POLICY *PeiTbtConfig; > + > + DEBUG ((DEBUG_INFO, "Install PEI TBT Policy\n")); > + > + PeiTbtConfig =3D NULL; > + > + // > + // Allocate memory for PeiTbtPolicyPpiDesc > + // > + PeiTbtPolicyPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (s= izeof > (EFI_PEI_PPI_DESCRIPTOR)); > + ASSERT (PeiTbtPolicyPpiDesc !=3D NULL); > + if (PeiTbtPolicyPpiDesc =3D=3D NULL) { > + return EFI_OUT_OF_RESOURCES; > + } > + > + // > + // Allocate memory and initialize all default to zero for PeiTbtPolicy > + // > + PeiTbtConfig =3D (PEI_TBT_POLICY *) AllocateZeroPool (sizeof > (PEI_TBT_POLICY)); > + ASSERT (PeiTbtConfig !=3D NULL); > + if (PeiTbtConfig =3D=3D NULL) { > + return EFI_OUT_OF_RESOURCES; > + } > + > + // > + // Initialize PPI > + // > + PeiTbtPolicyPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; > + PeiTbtPolicyPpiDesc->Guid =3D &gPeiTbtPolicyPpiGuid; > + PeiTbtPolicyPpiDesc->Ppi =3D PeiTbtConfig; > + > + Status =3D PeiServicesInstallPpi (PeiTbtPolicyPpiDesc); > + ASSERT_EFI_ERROR (Status); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Install PEI TBT Policy failed\n")); > + } > + return Status; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/P > eiDTbtInitLib/PeiDTbtInitLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/P > eiDTbtInitLib/PeiDTbtInitLib.c > new file mode 100644 > index 0000000000..f33ddebdb3 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/P > eiDTbtInitLib/PeiDTbtInitLib.c > @@ -0,0 +1,567 @@ > +/** @file > + Thunderbolt(TM) Pei Library > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > +Is host router (For dTBT) or End Point (For iTBT) present before sleep > + > +@param[in] ControllerType - DTBT_CONTROLLER or ITBT_CONTROLLER > +@param[in] Controller - Controller begin offset of CMOS > + > +@Retval TRUE There is a TBT HostRouter presented before sleep > +@Retval FALSE There is no TBT HostRouter presented before sleep > + > +BOOLEAN > +IsHostRouterPresentBeforeSleep( > +IN UINT8 ControllerType, > +IN UINT8 Controller > +) > +{ > + UINT8 SavedState; > + > + SavedState =3D (UINT8)GetTbtHostRouterStatus(); > + if (ControllerType =3D=3D DTBT_CONTROLLER){ > + return ((SavedState & (DTBT_SAVE_STATE_OFFSET << Controller)) =3D=3D > (DTBT_SAVE_STATE_OFFSET << Controller)); > + } else { > + if (ControllerType =3D=3D ITBT_CONTROLLER) { > + return ((SavedState & (ITBT_SAVE_STATE_OFFSET << Controller)) =3D= =3D > (ITBT_SAVE_STATE_OFFSET << Controller)); > + } > + } > + return 0; > +} > +**/ > + > +/** > +Execute TBT PCIE2TBT_SX_EXIT_TBT_CONNECTED Mail Box Command for S4 > mode with PreBootAclEnable > + > +@param[in] Bus Bus number for Host Router (DTBT) > +@param[in] Device Device number for Host Router (DTBT) > +@param[in] Function Function number for Host Router (DTBT) > +@param[in] Timeout Time out with 100 ms garnularity > +@Retval true if command executes succesfully > +**/ > +BOOLEAN > +TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable( > + IN UINT8 Bus, > + IN UINT8 Device, > + IN UINT8 Function, > + IN UINT32 Timeout > +) > +{ > + UINT64 Pcie2Tbt; > + UINT64 Tbt2Pcie; > + UINT32 RegisterValue; > + BOOLEAN ReturnFlag; > + UINT32 Command; > + > + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) > + GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) > + > +// If PreBootAcl is Enable, we need to enable DATA bit while sending SX = EXIT > MAIL BOX Command > + Command =3D (1 << 8) | PCIE2TBT_SX_EXIT_TBT_CONNECTED; > + PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B); > + > + ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, > TRUE, &RegisterValue); > + > + PciSegmentWrite32(Pcie2Tbt, 0); > + > + return ReturnFlag; > +} > + > +/** > +Set the Sleep Mode if the HR is up. > +@param[in] Bus Bus number for Host Router (DTBT) > +@param[in] Device Device number for Host Router (DTBT) > +@param[in] Function Function number for Host Router (DTBT) > +**/ > +VOID > +TbtSetSxMode( > +IN UINT8 Bus, > +IN UINT8 Device, > +IN UINT8 Function, > +IN UINT8 TbtBootOn > +) > +{ > + UINT64 TbtUsDevId; > + UINT64 Tbt2Pcie; > + UINT32 RegVal; > + UINT32 MaxLoopCount; > + UINTN Delay; > + UINT8 RetCode; > + EFI_BOOT_MODE BootMode; > + EFI_STATUS Status; > + > + TbtUsDevId =3D PCI_SEGMENT_LIB_ADDRESS(0, Bus, Device, Function, 0); > + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) > + > + MaxLoopCount =3D TBT_5S_TIMEOUT; // Wait 5 sec > + Delay =3D 100 * 1000; > + RetCode =3D 0x62; > + > + Status =3D PeiServicesGetBootMode(&BootMode); > + ASSERT_EFI_ERROR(Status); > + > + if ((BootMode =3D=3D BOOT_ON_S4_RESUME) && (TbtBootOn =3D=3D 2)) { > + MaxLoopCount =3D TBT_3S_TIMEOUT; > + if (!TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(Bus, Device, > Function, MaxLoopCount)) { > + // > + // Nothing to wait, HR is not responsive > + // > + return; > + } > + } > + else { > + if (!TbtSetPcie2TbtCommand(PCIE2TBT_SX_EXIT_TBT_CONNECTED, Bus, > Device, Function, MaxLoopCount)) { > + // > + // Nothing to wait, HR is not responsive > + // > + return; > + } > + } > + > + DEBUG((DEBUG_INFO, "Wait for Dev ID !=3D 0xFF\n")); > + > + while (MaxLoopCount-- > 0) { > + // > + // Check what HR still here > + // > + RegVal =3D PciSegmentRead32(Tbt2Pcie); > + if (0xFFFFFFFF =3D=3D RegVal) { > + RetCode =3D 0x6F; > + break; > + } > + // > + // Check completion of TBT link > + // > + RegVal =3D PciSegmentRead32(TbtUsDevId); > + if (0xFFFFFFFF !=3D RegVal) { > + RetCode =3D 0x61; > + break; > + } > + > + MicroSecondDelay(Delay); > + } > + > + DEBUG((DEBUG_INFO, "Return code =3D 0x%x\n", RetCode)); > +} > +/** > + set tPCH25 Timing to 10 ms for DTBT. > + > + @param[in] PEI_TBT_POLICY PeiTbtConfig > + > + @retval EFI_SUCCESS The function completes successfully > + @retval EFI_UNSUPPORTED dTBT is not supported. > +**/ > +EFI_STATUS > +EFIAPI > +DTbtSetTPch25Timing ( > + IN PEI_TBT_POLICY *PeiTbtConfig > +) > +{ > + DEBUG ((DEBUG_INFO, "DTbtSetTPch25Timing call Inside\n")); > + UINT32 PchPwrmBase; > + > + // > + //During boot, reboot and wake tPCH25 Timing should be set to 10 ms > + // > + MmioOr32 ( > + (UINTN) (PchPwrmBase + R_PCH_PWRM_CFG), > + (BIT0 | BIT1) > + ); > + > + DEBUG((DEBUG_INFO, "DTbtSetTPch25Timing call Return\n")); > + return EFI_SUCCESS; > +} > + > +/** > + Do ForcePower for DTBT Controller > + > + @param[in] PEI_TBT_POLICY PeiTbtConfig > + > + @retval EFI_SUCCESS The function completes successfully > + @retval EFI_UNSUPPORTED dTBT is not supported. > +**/ > +EFI_STATUS > +EFIAPI > +DTbtForcePower ( > + IN PEI_TBT_POLICY *PeiTbtConfig > +) > +{ > + > + DEBUG ((DEBUG_INFO, "DTbtForcePower call Inside\n")); > + > + if (PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr) { > + DEBUG((DEBUG_INFO, "ForcePwrGpio.GpioPad =3D %x \n", > PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad)); > + ForceDtbtPower(PeiTbtConfig-> > DTbtControllerConfig.ForcePwrGpio.GpioAccessType,PeiTbtConfig-> > DTbtControllerConfig.ForcePwrGpio.Expander, PeiTbtConfig-> > DTbtControllerConfig.ForcePwrGpio.GpioPad, PeiTbtConfig-> > DTbtControllerConfig.ForcePwrGpio.GpioLevel); > + DEBUG((DEBUG_INFO, "ForceDtbtPower asserted \n")); > + > MicroSecondDelay(PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly * > 1000); > + DEBUG((DEBUG_INFO, "Delay after ForceDtbtPower =3D 0x%x ms \n", > PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly)); > + } > + > + DEBUG ((DEBUG_INFO, "DTbtForcePower call Return\n")); > + return EFI_SUCCESS; > +} > + > +/** > + Clear VGA Registers for DTBT. > + > + @param[in] PEI_TBT_POLICY PeiTbtConfig > + > + @retval EFI_SUCCESS The function completes successfully > + @retval EFI_UNSUPPORTED dTBT is not supported. > +**/ > +EFI_STATUS > +EFIAPI > +DTbtClearVgaRegisters ( > + IN PEI_TBT_POLICY *PeiTbtConfig > +) > +{ > + UINTN RpDev; > + UINTN RpFunc; > + EFI_STATUS Status; > + UINT64 BridngeBaseAddress; > + UINT16 Data16; > + > + DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Inside\n")); > + > + Status =3D EFI_SUCCESS; > + > + Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, > PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); > + ASSERT_EFI_ERROR(Status); > + // > + // VGA Enable and VGA 16-bit decode registers of Bridge control regist= er of > Root port where > + // Host router resides should be cleaned > + // > + > + BridngeBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(0, 0, (UINT32)RpDev, > (UINT32)RpFunc, 0); > + Data16 =3D PciSegmentRead16(BridngeBaseAddress + > PCI_BRIDGE_CONTROL_REGISTER_OFFSET); > + Data16 &=3D (~(EFI_PCI_BRIDGE_CONTROL_VGA | > EFI_PCI_BRIDGE_CONTROL_VGA_16)); > + PciSegmentWrite16(BridngeBaseAddress + > PCI_BRIDGE_CONTROL_REGISTER_OFFSET, Data16); > + > + DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Return\n")); > + return Status; > +} > + > +/** > + Exectue Mail box command "Boot On". > + > + @param[in] PEI_TBT_POLICY PeiTbtConfig > + > + @retval EFI_SUCCESS The function completes successfully > + @retval EFI_UNSUPPORTED dTBT is not supported. > +**/ > +EFI_STATUS > +EFIAPI > +DTbtBootOn( > + IN PEI_TBT_POLICY *PeiTbtConfig > +) > +{ > + EFI_STATUS Status; > + UINT32 OrgBusNumberConfiguration; > + UINTN RpDev; > + UINTN RpFunc; > + > + DEBUG((DEBUG_INFO, "DTbtBootOn call Inside\n")); > + > + Status =3D EFI_SUCCESS; > + > + Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Typ= e, > PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); > + ASSERT_EFI_ERROR(Status); > + OrgBusNumberConfiguration =3D PciSegmentRead32 > (PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, > PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)); > + // > + // Set Sec/Sub buses to 0xF0 > + // > + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, > PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000); > + // > + //When Thunderbolt(TM) boot [TbtBootOn] is enabled in bios setup w= e > need to do the below: > + //Bios should send "Boot On" message through PCIE2TBT register > + //The Boot On command as described above would include the > command and acknowledge from FW (with the default timeout in BIOS), > + //once the Boot On command is completed it is guaranteed that the > AlpineRidge(AR) device is there and the PCI tunneling was done by FW, > + //next step from BIOS is enumeration using SMI > + // > + > + if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) { > + // > + // Exectue Mail box command "Boot On / Pre-Boot ACL" > + // > + //Command may be executed only during boot/reboot and not during > Sx exit flow > + if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 1) { > + if (!TbtSetPcie2TbtCommand(PCIE2TBT_BOOT_ON, 0xF0, 0, 0, > TBT_5S_TIMEOUT)) { > + // > + // Nothing to wait, HR is not responsive > + // > + DEBUG((DEBUG_INFO, " DTbtBootOn - Boot On message > sent failed \n")); > + } > + } > + if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 2) { > + if (!TbtSetPcie2TbtCommand(PCIE2TBT_PREBOOTACL, 0xF0, 0, 0, > TBT_3S_TIMEOUT)) { > + // > + // Nothing to wait, HR is not responsive > + // > + DEBUG((DEBUG_INFO, " DTbtBootOn - Pre-Boot ACL > message sent failed \n")); > + } > + } > + } > + // > + // Reset Sec/Sub buses to original value > + // > + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, > PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), > OrgBusNumberConfiguration); > + > + DEBUG((DEBUG_INFO, "DTbtBootOn call Return\n")); > + return Status; > +} > + > +/** > + Exectue Mail box command "USB On". > + > + @param[in] PEI_TBT_POLICY PeiTbtConfig > + > + @retval EFI_SUCCESS The function completes successfully > + @retval EFI_UNSUPPORTED dTBT is not supported. > +**/ > +EFI_STATUS > +EFIAPI > +DTbtUsbOn( > + IN PEI_TBT_POLICY *PeiTbtConfig > +) > +{ > + EFI_STATUS Status; > + UINTN RpDev; > + UINTN RpFunc; > + UINT32 OrgBusNumberConfiguration; > + UINT64 TbtBaseAddress; > + UINT32 MaxWaitIter; > + UINT32 RegVal; > + EFI_BOOT_MODE BootMode; > + > + DEBUG((DEBUG_INFO, "DTbtUsbOn call Inside\n")); > + > + Status =3D EFI_SUCCESS; > + > + Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Typ= e, > PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); > + ASSERT_EFI_ERROR(Status); > + OrgBusNumberConfiguration =3D > PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, > PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)); > + // > + // Set Sec/Sub buses to 0xF0 > + // > + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, > PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000); > + > + // > + //When Thunderbolt(TM) Usb boot [TbtUsbOn] is enabled in bios setu= p > we need to do the below: > + //Bios should send "Usb On" message through PCIE2TBT register > + //The Usb On command as described above would include the command > and acknowledge from FW (with the default timeout in BIOS), > + //once the Usb On command is completed it is guaranteed that the > AlpineRidge(AR) device is there and the PCI tunneling was done by FW, > + //next step from BIOS is enumeration using SMI > + // > + if (PeiTbtConfig->DTbtCommonConfig.TbtUsbOn) { > + if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) { > + MaxWaitIter =3D 50; // Wait 5 sec > + TbtBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(0, 0xF0, 0, 0, 0); > + // > + // Driver clears the PCIe2TBT Valid bit to support two consicu= tive > mailbox commands > + // > + PciSegmentWrite32(TbtBaseAddress + PCIE2TBT_DTBT_R, 0); > + DEBUG((DEBUG_INFO, "TbtBaseAddress + PCIE2TBT_DTBT_R =3D 0x%lx > \n", TbtBaseAddress + PCIE2TBT_DTBT_R)); > + while (MaxWaitIter-- > 0) { > + RegVal =3D PciSegmentRead32(TbtBaseAddress + TBT2PCIE_DTBT_R= ); > + if (0xFFFFFFFF =3D=3D RegVal) { > + // > + // Device is not here return now > + // > + DEBUG((DEBUG_INFO, "TBT device is not present \n")); > + break; > + } > + > + if (!(RegVal & TBT2PCIE_DON_R)) { > + break; > + } > + MicroSecondDelay(100 * 1000); > + } > + } > + > + Status =3D PeiServicesGetBootMode(&BootMode); > + ASSERT_EFI_ERROR(Status); > + > + // > + // Exectue Mail box command "Usb On" > + // > + //Command may be executed only during boot/reboot and not during > S3 exit flow > + //In case of S4 Exit send USB ON cmd only if Host Router was > inactive/not present during S4 entry > + if ((BootMode =3D=3D BOOT_ON_S4_RESUME) ) { > + // USB_ON cmd not required > + } else { > + if (!TbtSetPcie2TbtCommand(PCIE2TBT_USB_ON, 0xF0, 0, 0, > TBT_5S_TIMEOUT)) { > + // > + // Nothing to wait, HR is not responsive > + // > + DEBUG((DEBUG_INFO, " TbtBootSupport - Usb On message > sent failed \n")); > + } > + } > + } > + // > + // Reset Sec/Sub buses to original value > + // > + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, > PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), > OrgBusNumberConfiguration); > + > + DEBUG((DEBUG_INFO, "DTbtUsbOn call return\n")); > + return Status; > +} > + > +/** > + Exectue Mail box command "Sx Exit". > + > + @param[in] PEI_TBT_POLICY PeiTbtConfig > + > + @retval EFI_SUCCESS The function completes successfully > + @retval EFI_UNSUPPORTED dTBT is not supported. > +**/ > +EFI_STATUS > +EFIAPI > +DTbtSxExitFlow( > + IN PEI_TBT_POLICY *PeiTbtConfig > +) > +{ > + EFI_STATUS Status; > + UINT32 OrgBusNumberConfiguration; > + UINTN RpDev; > + UINTN RpFunc; > + UINT32 Count; > + > + DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Inside\n")); > + > + Status =3D EFI_SUCCESS; > + Count =3D 0; > + > + Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Typ= e, > PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); > + ASSERT_EFI_ERROR(Status); > + OrgBusNumberConfiguration =3D > PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, > PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)); > + // > + // Set Sec/Sub buses to 0xF0 > + // > + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, > PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000); > + > + if ( (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 2)) { > + // > + // WA: When system with TBT 3.1 device, resume SX system need to= wait > device ready. In document that maximum time out should be 500ms. > + // > + while (PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS(0, 0xf0, 0x0, > 0x0, 0x08)) =3D=3D 0xffffffff) { //End Device will be with Device Number = 0x0, Function > Number 0x0. > + MicroSecondDelay(STALL_ONE_MICRO_SECOND * 1000); // 1000usec > + Count++; > + if (Count > 10000) { //Allowing Max Delay of 10 sec for CFL-S = board. > + break; > + } > + } > + > + // > + // Upon wake, if BIOS saved pre-Sx Host Router state as active (= system > went to sleep with > + // attached devices), BIOS should: > + // 1. Execute "Sx_Exit_TBT_Connected" mailbox command. > + // 2. If procedure above returns true, BIOS should perform "wait= for fast > link bring-up" loop > + // 3. Continue regular wake flow. > + // > + // > + // Exectue Mail box command and perform "wait for fast link brin= g-up" > loop > + // > + TbtSetSxMode(0xF0, 0, 0, > PeiTbtConfig->DTbtCommonConfig.TbtBootOn); > + } > + // > + // Reset Sec/Sub buses to original value > + // > + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, > PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), > OrgBusNumberConfiguration); > + > + DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Return\n")); > + return Status; > +} > + > + > +/** > + Initialize Thunderbolt(TM) > + > + @retval EFI_SUCCESS The function completes successfully > + @retval others > +**/ > +EFI_STATUS > +EFIAPI > +TbtInit ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + PEI_TBT_POLICY *PeiTbtConfig; > + > + // > + // Get the TBT Policy > + // > + Status =3D PeiServicesLocatePpi ( > + &gPeiTbtPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &PeiTbtConfig > + ); > + if (EFI_ERROR(Status)) { > + DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); > + } > + ASSERT_EFI_ERROR (Status); > + // > + // Exectue Mail box command "Boot On" > + // > + Status =3D DTbtBootOn (PeiTbtConfig); > + // > + // Exectue Mail box command "Usb On" > + // > + Status =3D DTbtUsbOn (PeiTbtConfig); > + // > + //During boot, reboot and wake (bits [1:0]) of PCH PM_CFG register sh= ould > be > + //set to 11b - 10 ms (default value is 0b - 10 us) > + // > + Status =3D DTbtSetTPch25Timing (PeiTbtConfig); > + // > + // Configure Tbt Force Power > + // > + Status =3D DTbtForcePower (PeiTbtConfig); > + // > + // VGA Enable and VGA 16-bit decode registers of Bridge control regist= er of > Root port where > + // Host router resides should be cleaned > + // > + Status =3D DTbtClearVgaRegisters (PeiTbtConfig); > + // > + // Upon wake, if BIOS saved pre-Sx Host Router state as active (system= went > to sleep with > + // attached devices), BIOS should: > + // 1. Execute "Sx_Exit_TBT_Connected" mailbox command. > + // 2. If procedure above returns true, BIOS should perform "wait for f= ast link > bring-up" loop > + // 3. Continue regular wake flow. > + // > + Status =3D DTbtSxExitFlow (PeiTbtConfig); > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspCpuPolicyInitLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspCpuPolicyInitLib.c > new file mode 100644 > index 0000000000..f38901f2ae > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspCpuPolicyInitLib.c > @@ -0,0 +1,461 @@ > +/** @file > + Implementation of Fsp CPU Policy Initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Performs FSP CPU PEI Policy initialization. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspCpuPolicyInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ) > +{ > + EFI_STATUS Status; > + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > + CPU_OVERCLOCKING_PREMEM_CONFIG > *CpuOverClockingPreMemConfig; > + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem > Start\n")); > + > + // > + // Locate SiPreMemPolicyPpi > + // > + SiPreMemPolicyPpi =3D NULL; > + Status =3D PeiServicesLocatePpi ( > + &gSiPreMemPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPreMemPolicyPpi > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gCpuOverclockingPreMemConfigGuid, (VOID *) > &CpuOverClockingPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + > + /// > + /// > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem > End\n")); > + > + // > + // Overclocking PreMem policies > + // > + FspmUpd->FspmConfig.OcSupport =3D (UINT8) > CpuOverClockingPreMemConfig->OcSupport; > + FspmUpd->FspmConfig.OcLock =3D (UINT8) > CpuOverClockingPreMemConfig->OcLock; > + FspmUpd->FspmConfig.CoreMaxOcRatio =3D (UINT8) > CpuOverClockingPreMemConfig->CoreMaxOcRatio; > + FspmUpd->FspmConfig.CoreVoltageMode =3D (UINT8) > CpuOverClockingPreMemConfig->CoreVoltageMode; > + FspmUpd->FspmConfig.CoreVoltageOverride =3D (UINT16) > CpuOverClockingPreMemConfig->CoreVoltageOverride; > + FspmUpd->FspmConfig.CoreVoltageAdaptive =3D (UINT16) > CpuOverClockingPreMemConfig->CoreVoltageAdaptive; > + FspmUpd->FspmConfig.CoreVoltageOffset =3D (UINT16) > CpuOverClockingPreMemConfig->CoreVoltageOffset; > + FspmUpd->FspmConfig.CorePllVoltageOffset =3D (UINT8) > CpuOverClockingPreMemConfig->CorePllVoltageOffset; > + FspmUpd->FspmConfig.RingMaxOcRatio =3D (UINT8) > CpuOverClockingPreMemConfig->RingMaxOcRatio; > + FspmUpd->FspmConfig.RingVoltageOverride =3D (UINT16) > CpuOverClockingPreMemConfig->RingVoltageOverride; > + FspmUpd->FspmConfig.RingVoltageAdaptive =3D (UINT16) > CpuOverClockingPreMemConfig->RingVoltageAdaptive; > + FspmUpd->FspmConfig.RingVoltageOffset =3D (UINT16) > CpuOverClockingPreMemConfig->RingVoltageOffset; > + FspmUpd->FspmConfig.RingPllVoltageOffset =3D (UINT8) > CpuOverClockingPreMemConfig->RingPllVoltageOffset; > + FspmUpd->FspmConfig.GtPllVoltageOffset =3D (UINT8) > CpuOverClockingPreMemConfig->GtPllVoltageOffset; > + FspmUpd->FspmConfig.RingPllVoltageOffset =3D (UINT8) > CpuOverClockingPreMemConfig->RingPllVoltageOffset; > + FspmUpd->FspmConfig.SaPllVoltageOffset =3D (UINT8) > CpuOverClockingPreMemConfig->SaPllVoltageOffset; > + FspmUpd->FspmConfig.McPllVoltageOffset =3D (UINT8) > CpuOverClockingPreMemConfig->McPllVoltageOffset; > + FspmUpd->FspmConfig.RingDownBin =3D (UINT8) > CpuOverClockingPreMemConfig->RingDownBin; > + FspmUpd->FspmConfig.RingVoltageMode =3D (UINT8) > CpuOverClockingPreMemConfig->RingVoltageMode; > + FspmUpd->FspmConfig.Avx2RatioOffset =3D (UINT8) > CpuOverClockingPreMemConfig->Avx2RatioOffset; > + FspmUpd->FspmConfig.Avx3RatioOffset =3D (UINT8) > CpuOverClockingPreMemConfig->Avx3RatioOffset; > + FspmUpd->FspmConfig.BclkAdaptiveVoltage =3D (UINT8) > CpuOverClockingPreMemConfig->BclkAdaptiveVoltage; > + FspmUpd->FspmConfig.TjMaxOffset =3D (UINT8) > CpuOverClockingPreMemConfig->TjMaxOffset; > + FspmUpd->FspmConfig.TvbRatioClipping =3D (UINT8) > CpuOverClockingPreMemConfig->TvbRatioClipping; > + FspmUpd->FspmConfig.TvbVoltageOptimization =3D (UINT8) > CpuOverClockingPreMemConfig->TvbVoltageOptimization; > + > + // > + // Cpu Config Lib policies > + // > + FspmUpd->FspmConfig.HyperThreading =3D (UINT8) > CpuConfigLibPreMemConfig->HyperThreading; > + FspmUpd->FspmConfig.BootFrequency =3D (UINT8) > CpuConfigLibPreMemConfig->BootFrequency; > + FspmUpd->FspmConfig.ActiveCoreCount =3D (UINT8) > CpuConfigLibPreMemConfig->ActiveCoreCount; > + FspmUpd->FspmConfig.JtagC10PowerGateDisable =3D (UINT8) > CpuConfigLibPreMemConfig->JtagC10PowerGateDisable; > + FspmUpd->FspmConfig.FClkFrequency =3D (UINT8) > CpuConfigLibPreMemConfig->FClkFrequency; > + FspmUpd->FspmConfig.BistOnReset =3D (UINT8) > CpuConfigLibPreMemConfig->BistOnReset; > + FspmUpd->FspmConfig.VmxEnable =3D (UINT8) > CpuConfigLibPreMemConfig->VmxEnable; > + FspmUpd->FspmConfig.CpuRatio =3D (UINT8) > CpuConfigLibPreMemConfig->CpuRatio; > + FspmUpd->FspmConfig.PeciSxReset =3D (UINT8) > CpuConfigLibPreMemConfig->PeciSxReset; > + FspmUpd->FspmConfig.PeciC10Reset =3D (UINT8) > CpuConfigLibPreMemConfig->PeciC10Reset; > + FspmUpd->FspmConfig.SkipMpInit =3D (UINT8) > CpuConfigLibPreMemConfig->SkipMpInit; > + FspmUpd->FspmConfig.DpSscMarginEnable =3D (UINT8) > CpuConfigLibPreMemConfig->DpSscMarginEnable; > + > + // > + // DisableMtrrProgram <1> Disable Mtrrs program. <0> Program Mtrrs in = FSP > + // > + FspmUpd->FspmConfig.DisableMtrrProgram =3D (UINT8) 0; > + > + return EFI_SUCCESS; > +} > + > +/** > + This routine is used to get Sec Platform Information Record2 Pointer. > + > + @param[in] PeiServices Pointer to the PEI services table > + > + @retval GetSecPlatformInformation2 - The pointer of Sec Platform > Information Record2 Pointer. > + **/ > + > +EFI_SEC_PLATFORM_INFORMATION_RECORD2 * > GetSecPlatformInformation2( > + IN EFI_PEI_SERVICES **PeiServices > + ) > +{ > + EFI_SEC_PLATFORM_INFORMATION2_PPI *SecPlatformInformation2Ppi; > + EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2 =3D > NULL; > + UINT64 InformationSize; > + EFI_STATUS Status; > + > + // > + // Get BIST information from Sec Platform Information2 Ppi firstly > + // > + Status =3D PeiServicesLocatePpi ( > + &gEfiSecPlatformInformation2PpiGuid, // GUID > + 0, // Instance > + NULL, // EFI_PEI_PPI_DESCR= IPTOR > + (VOID ** ) &SecPlatformInformation2Ppi // PPI > + ); > + > + DEBUG((DEBUG_INFO, "LocatePpi SecPlatformInformationPpi2 Status - > %x\n", Status)); > + if (EFI_ERROR(Status)) { > + return NULL; > + } > + > + InformationSize =3D 0; > + > + Status =3D SecPlatformInformation2Ppi->PlatformInformation2 ( > + (CONST EFI_PEI_SERVICES **) Pe= iServices, > + &InformationSize, > + SecPlatformInformation2 > + ); > + > + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); > + if (Status !=3D EFI_BUFFER_TOO_SMALL) { > + return NULL; > + } > + > + SecPlatformInformation2 =3D AllocatePool((UINTN)InformationSize); > + ASSERT (SecPlatformInformation2 !=3D NULL); > + if (SecPlatformInformation2 =3D=3D NULL) { > + return NULL; > + } > + > + // > + // Retrieve BIST data from SecPlatform2 > + // > + Status =3D SecPlatformInformation2Ppi->PlatformInformation2 ( > + PeiServices, > + &InformationSize, > + SecPlatformInformation2 > + ); > + DEBUG((DEBUG_INFO, > "SecPlatformInformation2Ppi->PlatformInformation2 Status - %x\n", Status)= ); > + ASSERT_EFI_ERROR (Status); > + if (EFI_ERROR (Status)) { > + return NULL; > + } > + > + return SecPlatformInformation2; > +} > + > +/** > + This routine is used to get Sec Platform Information Record Pointer. > + > + @param[in] PeiServices Pointer to the PEI services table > + > + @retval GetSecPlatformInformation2 - The pointer of Sec Platform > Information Record Pointer. > + **/ > +EFI_SEC_PLATFORM_INFORMATION_RECORD2 * > GetSecPlatformInformationInfoInFormat2( > + IN EFI_PEI_SERVICES **PeiServices > + ) > +{ > + EFI_SEC_PLATFORM_INFORMATION_PPI *SecPlatformInformationPpi; > + EFI_SEC_PLATFORM_INFORMATION_RECORD *SecPlatformInformation =3D > NULL; > + EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2; > + UINT64 InformationSize; > + EFI_STATUS Status; > + > + // > + // Get BIST information from Sec Platform Information > + // > + Status =3D PeiServicesLocatePpi ( > + &gEfiSecPlatformInformationPpiGuid, // GUID > + 0, // Instance > + NULL, // EFI_PEI_PPI_DESCR= IPTOR > + (VOID ** ) &SecPlatformInformationPpi // PPI > + ); > + > + DEBUG((DEBUG_INFO, "LocatePpi SecPlatformInformationPpi Status - > %x\n", Status)); > + if (EFI_ERROR(Status)) { > + return NULL; > + } > + > + InformationSize =3D 0; > + Status =3D SecPlatformInformationPpi->PlatformInformation ( > + (CONST EFI_PEI_SERVICES **) Pei= Services, > + &InformationSize, > + SecPlatformInformation > + ); > + > + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); > + if (Status !=3D EFI_BUFFER_TOO_SMALL) { > + return NULL; > + } > + > + SecPlatformInformation =3D AllocatePool((UINTN)InformationSize); > + ASSERT (SecPlatformInformation !=3D NULL); > + if (SecPlatformInformation =3D=3D NULL) { > + return NULL; > + } > + > + // > + // Retrieve BIST data from SecPlatform > + // > + Status =3D SecPlatformInformationPpi->PlatformInformation ( > + PeiServices, > + &InformationSize, > + SecPlatformInformation > + ); > + DEBUG((DEBUG_INFO, "FSP > SecPlatformInformation2Ppi->PlatformInformation Status - %x\n", Status)); > + ASSERT_EFI_ERROR (Status); > + if (EFI_ERROR (Status)) { > + return NULL; > + } > + > + SecPlatformInformation2 =3D AllocatePool(sizeof > (EFI_SEC_PLATFORM_INFORMATION_RECORD2)); > + ASSERT (SecPlatformInformation2 !=3D NULL); > + if (SecPlatformInformation2 =3D=3D NULL) { > + return NULL; > + } > + > + SecPlatformInformation2->NumberOfCpus =3D 1; > + SecPlatformInformation2->CpuInstance[0].CpuLocation =3D 0; > + > SecPlatformInformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32 > =3D SecPlatformInformation->x64HealthFlags.Uint32; > + > + FreePool(SecPlatformInformation); > + > + return SecPlatformInformation2; > +} > + > + > +/** > + Performs FSP CPU PEI Policy post memory initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspCpuPolicyInit ( > + IN OUT FSPS_UPD *FspsUpd > + ) > +{ > + EFI_STATUS Status; > + SI_POLICY_PPI *SiPolicyPpi; > + CPU_CONFIG *CpuConfig; > + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig; > + CPU_POWER_MGMT_CUSTOM_CONFIG > *CpuPowerMgmtCustomConfig; > + CPU_TEST_CONFIG *CpuTestConfig; > + CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig; > + UINTN Index; > + EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2; > + EFI_PEI_SERVICES **PeiServices; > + > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy\n")); > + PeiServices =3D (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (); > + // > + // Locate gSiPolicyPpiGuid > + // > + SiPolicyPpi =3D NULL; > + Status =3D PeiServicesLocatePpi ( > + &gSiPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPolicyPpi > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOI= D *) > &CpuConfig); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, > &gCpuPowerMgmtBasicConfigGuid, (VOID *) &CpuPowerMgmtBasicConfig); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, > &gCpuPowerMgmtCustomConfigGuid, (VOID *) > &CpuPowerMgmtCustomConfig); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuTestConfigGuid, = (VOID > *) &CpuTestConfig); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, > &gCpuPowerMgmtTestConfigGuid, (VOID *) &CpuPowerMgmtTestConfig); > + ASSERT_EFI_ERROR (Status); > + /// > + ///Production RC Policies > + /// > + > + FspsUpd->FspsConfig.AesEnable =3D (UINT8) > CpuConfig->AesEnable; > + FspsUpd->FspsConfig.DebugInterfaceEnable =3D (UINT8) > CpuConfig->DebugInterfaceEnable; > + > + FspsUpd->FspsConfig.TurboMode =3D (UINT8) > CpuPowerMgmtBasicConfig->TurboMode; > + > + /// > + /// Test RC Policies > + /// > + FspsUpd->FspsTestConfig.MlcStreamerPrefetcher =3D (UINT8) > CpuTestConfig->MlcStreamerPrefetcher; > + FspsUpd->FspsTestConfig.MlcSpatialPrefetcher =3D (UINT8) > CpuTestConfig->MlcSpatialPrefetcher; > + FspsUpd->FspsTestConfig.MonitorMwaitEnable =3D (UINT8) > CpuTestConfig->MonitorMwaitEnable; > + FspsUpd->FspsTestConfig.DebugInterfaceLockEnable =3D (UINT8) > CpuTestConfig->DebugInterfaceLockEnable; > + FspsUpd->FspsTestConfig.ApIdleManner =3D PcdGet8 > (PcdCpuApLoopMode); > + FspsUpd->FspsTestConfig.ProcessorTraceOutputScheme =3D (UINT8) > CpuTestConfig->ProcessorTraceOutputScheme; > + FspsUpd->FspsTestConfig.ProcessorTraceEnable =3D (UINT8) > CpuTestConfig->ProcessorTraceEnable; > + FspsUpd->FspsTestConfig.ProcessorTraceMemBase =3D > CpuTestConfig->ProcessorTraceMemBase; > + FspsUpd->FspsTestConfig.ProcessorTraceMemLength =3D (UINT32) > CpuTestConfig->ProcessorTraceMemLength; > + FspsUpd->FspsTestConfig.VoltageOptimization =3D (UINT8) > CpuTestConfig->VoltageOptimization; > + FspsUpd->FspsTestConfig.ThreeStrikeCounterDisable =3D (UINT8) > CpuTestConfig->ThreeStrikeCounterDisable; > + FspsUpd->FspsTestConfig.MachineCheckEnable =3D (UINT8) > CpuTestConfig->MachineCheckEnable; > + FspsUpd->FspsTestConfig.CpuWakeUpTimer =3D (UINT8) > CpuTestConfig->CpuWakeUpTimer; > + > + FspsUpd->FspsTestConfig.OneCoreRatioLimit =3D (UINT8) > CpuPowerMgmtBasicConfig->OneCoreRatioLimit; > + FspsUpd->FspsTestConfig.TwoCoreRatioLimit =3D (UINT8) > CpuPowerMgmtBasicConfig->TwoCoreRatioLimit; > + FspsUpd->FspsTestConfig.ThreeCoreRatioLimit =3D (UINT8) > CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit; > + FspsUpd->FspsTestConfig.FourCoreRatioLimit =3D (UINT8) > CpuPowerMgmtBasicConfig->FourCoreRatioLimit; > + FspsUpd->FspsTestConfig.FiveCoreRatioLimit =3D (UINT8) > CpuPowerMgmtBasicConfig->FiveCoreRatioLimit; > + FspsUpd->FspsTestConfig.SixCoreRatioLimit =3D (UINT8) > CpuPowerMgmtBasicConfig->SixCoreRatioLimit; > + FspsUpd->FspsTestConfig.SevenCoreRatioLimit =3D (UINT8) > CpuPowerMgmtBasicConfig->SevenCoreRatioLimit; > + FspsUpd->FspsTestConfig.EightCoreRatioLimit =3D (UINT8) > CpuPowerMgmtBasicConfig->EightCoreRatioLimit; > + FspsUpd->FspsTestConfig.Hwp =3D (UINT8) > CpuPowerMgmtBasicConfig->Hwp; > + FspsUpd->FspsTestConfig.HdcControl =3D (UINT8) > CpuPowerMgmtBasicConfig->HdcControl; > + FspsUpd->FspsTestConfig.PowerLimit1Time =3D (UINT8) > CpuPowerMgmtBasicConfig->PowerLimit1Time; > + FspsUpd->FspsTestConfig.PowerLimit2 =3D (UINT8) > CpuPowerMgmtBasicConfig->PowerLimit2; > + FspsUpd->FspsTestConfig.TurboPowerLimitLock =3D (UINT8) > CpuPowerMgmtBasicConfig->TurboPowerLimitLock; > + FspsUpd->FspsTestConfig.PowerLimit3Time =3D (UINT8) > CpuPowerMgmtBasicConfig->PowerLimit3Time; > + FspsUpd->FspsTestConfig.PowerLimit3DutyCycle =3D (UINT8) > CpuPowerMgmtBasicConfig->PowerLimit3DutyCycle; > + FspsUpd->FspsTestConfig.PowerLimit3Lock =3D (UINT8) > CpuPowerMgmtBasicConfig->PowerLimit3Lock; > + FspsUpd->FspsTestConfig.PowerLimit4Lock =3D (UINT8) > CpuPowerMgmtBasicConfig->PowerLimit4Lock; > + FspsUpd->FspsTestConfig.TccActivationOffset =3D (UINT8) > CpuPowerMgmtBasicConfig->TccActivationOffset; > + FspsUpd->FspsTestConfig.TccOffsetClamp =3D (UINT8) > CpuPowerMgmtBasicConfig->TccOffsetClamp; > + FspsUpd->FspsTestConfig.TccOffsetLock =3D (UINT8) > CpuPowerMgmtBasicConfig->TccOffsetLock; > + FspsUpd->FspsTestConfig.PowerLimit1 =3D (UINT32) > (CpuPowerMgmtBasicConfig->PowerLimit1 * 125); > + FspsUpd->FspsTestConfig.PowerLimit2Power =3D (UINT32) > (CpuPowerMgmtBasicConfig->PowerLimit2Power * 125); > + FspsUpd->FspsTestConfig.PowerLimit3 =3D (UINT32) > (CpuPowerMgmtBasicConfig->PowerLimit3 * 125); > + FspsUpd->FspsTestConfig.PowerLimit4 =3D (UINT32) > (CpuPowerMgmtBasicConfig->PowerLimit4 * 125); > + FspsUpd->FspsTestConfig.TccOffsetTimeWindowForRatl =3D (UINT32) > CpuPowerMgmtBasicConfig->TccOffsetTimeWindowForRatl; > + FspsUpd->FspsTestConfig.HwpInterruptControl =3D (UINT8) > CpuPowerMgmtBasicConfig->HwpInterruptControl; > + FspsUpd->FspsTestConfig.EnableItbm =3D (UINT8) > CpuPowerMgmtBasicConfig->EnableItbm; > + FspsUpd->FspsTestConfig.EnableItbmDriver =3D (UINT8) > CpuPowerMgmtBasicConfig->EnableItbmDriver; > + FspsUpd->FspsTestConfig.MinRingRatioLimit =3D (UINT8) > CpuPowerMgmtBasicConfig->MinRingRatioLimit; > + FspsUpd->FspsTestConfig.MaxRingRatioLimit =3D (UINT8) > CpuPowerMgmtBasicConfig->MaxRingRatioLimit; > + FspsUpd->FspsTestConfig.NumberOfEntries =3D (UINT8) > CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries; > + FspsUpd->FspsTestConfig.Custom1PowerLimit1Time =3D (UINT8) > CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimi > t1Time; > + FspsUpd->FspsTestConfig.Custom2PowerLimit1Time =3D (UINT8) > CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimi > t1Time; > + FspsUpd->FspsTestConfig.Custom3PowerLimit1Time =3D (UINT8) > CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimi > t1Time; > + FspsUpd->FspsTestConfig.Custom1TurboActivationRatio =3D (UINT8) > CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomTurboActiv > ationRatio; > + FspsUpd->FspsTestConfig.Custom2TurboActivationRatio =3D (UINT8) > CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomTurboActiv > ationRatio; > + FspsUpd->FspsTestConfig.Custom3TurboActivationRatio =3D (UINT8) > CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomTurboActiv > ationRatio; > + FspsUpd->FspsTestConfig.ConfigTdpLock =3D (UINT8) > CpuPowerMgmtCustomConfig->ConfigTdpLock; > + FspsUpd->FspsTestConfig.ConfigTdpBios =3D (UINT8) > CpuPowerMgmtCustomConfig->ConfigTdpBios; > + FspsUpd->FspsTestConfig.MaxRatio =3D (UINT8) > CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio; > + for (Index =3D 0; Index < > CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries; > Index++) { > + FspsUpd->FspsTestConfig.StateRatio[Index] =3D (UINT8) > CpuPowerMgmtCustomConfig->CustomRatioTable.StateRatio[Index]; > + } > + for (Index =3D 0; Index < MAX_16_CUSTOM_RATIO_TABLE_ENTRIES; Index++) = { > + FspsUpd->FspsTestConfig.StateRatioMax16[Index] =3D (UINT8) > CpuPowerMgmtCustomConfig->CustomRatioTable.StateRatioMax16[Index]; > + } > + FspsUpd->FspsTestConfig.Custom1PowerLimit1 =3D (UINT32) > (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLim > it1 * 125); > + FspsUpd->FspsTestConfig.Custom1PowerLimit2 =3D (UINT32) > (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLim > it2 * 125); > + FspsUpd->FspsTestConfig.Custom2PowerLimit1 =3D (UINT32) > (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLim > it1 * 125); > + FspsUpd->FspsTestConfig.Custom2PowerLimit2 =3D (UINT32) > (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLim > it2 * 125); > + FspsUpd->FspsTestConfig.Custom3PowerLimit1 =3D (UINT32) > (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLim > it1 * 125); > + FspsUpd->FspsTestConfig.Custom3PowerLimit2 =3D (UINT32) > (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLim > it2 * 125); > + > + FspsUpd->FspsTestConfig.Eist =3D (UINT8) > CpuPowerMgmtTestConfig->Eist; > + FspsUpd->FspsTestConfig.EnergyEfficientPState =3D (UINT8) > CpuPowerMgmtTestConfig->EnergyEfficientPState; > + FspsUpd->FspsTestConfig.EnergyEfficientTurbo =3D (UINT8) > CpuPowerMgmtTestConfig->EnergyEfficientTurbo; > + FspsUpd->FspsTestConfig.TStates =3D (UINT8) > CpuPowerMgmtTestConfig->TStates; > + FspsUpd->FspsTestConfig.BiProcHot =3D (UINT8) > CpuPowerMgmtTestConfig->BiProcHot; > + FspsUpd->FspsTestConfig.DisableProcHotOut =3D (UINT8) > CpuPowerMgmtTestConfig->DisableProcHotOut; > + FspsUpd->FspsTestConfig.ProcHotResponse =3D (UINT8) > CpuPowerMgmtTestConfig->ProcHotResponse; > + FspsUpd->FspsTestConfig.DisableVrThermalAlert =3D (UINT8) > CpuPowerMgmtTestConfig->DisableVrThermalAlert; > + FspsUpd->FspsTestConfig.AutoThermalReporting =3D (UINT8) > CpuPowerMgmtTestConfig->AutoThermalReporting; > + FspsUpd->FspsTestConfig.ThermalMonitor =3D (UINT8) > CpuPowerMgmtTestConfig->ThermalMonitor; > + FspsUpd->FspsTestConfig.Cx =3D (UINT8) > CpuPowerMgmtTestConfig->Cx; > + FspsUpd->FspsTestConfig.PmgCstCfgCtrlLock =3D (UINT8) > CpuPowerMgmtTestConfig->PmgCstCfgCtrlLock; > + FspsUpd->FspsTestConfig.C1e =3D (UINT8) > CpuPowerMgmtTestConfig->C1e; > + FspsUpd->FspsTestConfig.C1StateAutoDemotion =3D (UINT8) > CpuPowerMgmtTestConfig->C1AutoDemotion; > + FspsUpd->FspsTestConfig.C1StateUnDemotion =3D (UINT8) > CpuPowerMgmtTestConfig->C1UnDemotion; > + FspsUpd->FspsTestConfig.C3StateAutoDemotion =3D (UINT8) > CpuPowerMgmtTestConfig->C3AutoDemotion; > + FspsUpd->FspsTestConfig.C3StateUnDemotion =3D (UINT8) > CpuPowerMgmtTestConfig->C3UnDemotion; > + FspsUpd->FspsTestConfig.CstateLatencyControl0TimeUnit =3D (UINT8) > CpuPowerMgmtTestConfig->CstateLatencyControl0TimeUnit; > + FspsUpd->FspsTestConfig.CstateLatencyControl0Irtl =3D (UINT16) > CpuPowerMgmtTestConfig->CstateLatencyControl0Irtl; > + FspsUpd->FspsTestConfig.PkgCStateDemotion =3D (UINT8) > CpuPowerMgmtTestConfig->PkgCStateDemotion; > + FspsUpd->FspsTestConfig.PkgCStateUnDemotion =3D (UINT8) > CpuPowerMgmtTestConfig->PkgCStateUnDemotion; > + FspsUpd->FspsTestConfig.CStatePreWake =3D (UINT8) > CpuPowerMgmtTestConfig->CStatePreWake; > + FspsUpd->FspsTestConfig.TimedMwait =3D (UINT8) > CpuPowerMgmtTestConfig->TimedMwait; > + FspsUpd->FspsTestConfig.CstCfgCtrIoMwaitRedirection =3D (UINT8) > CpuPowerMgmtTestConfig->CstCfgCtrIoMwaitRedirection; > + FspsUpd->FspsTestConfig.PkgCStateLimit =3D (UINT8) > CpuPowerMgmtTestConfig->PkgCStateLimit; > + FspsUpd->FspsTestConfig.CstateLatencyControl1TimeUnit =3D (UINT8) > CpuPowerMgmtTestConfig->CstateLatencyControl1TimeUnit; > + FspsUpd->FspsTestConfig.CstateLatencyControl2TimeUnit =3D (UINT8) > CpuPowerMgmtTestConfig->CstateLatencyControl2TimeUnit; > + FspsUpd->FspsTestConfig.CstateLatencyControl3TimeUnit =3D (UINT8) > CpuPowerMgmtTestConfig->CstateLatencyControl3TimeUnit; > + FspsUpd->FspsTestConfig.CstateLatencyControl4TimeUnit =3D (UINT8) > CpuPowerMgmtTestConfig->CstateLatencyControl4TimeUnit; > + FspsUpd->FspsTestConfig.CstateLatencyControl5TimeUnit =3D (UINT8) > CpuPowerMgmtTestConfig->CstateLatencyControl5TimeUnit; > + FspsUpd->FspsTestConfig.PpmIrmSetting =3D (UINT8) > CpuPowerMgmtTestConfig->PpmIrmSetting; > + FspsUpd->FspsTestConfig.ProcHotLock =3D (UINT8) > CpuPowerMgmtTestConfig->ProcHotLock; > + FspsUpd->FspsTestConfig.RaceToHalt =3D (UINT8) > CpuPowerMgmtTestConfig->RaceToHalt; > + FspsUpd->FspsTestConfig.ConfigTdpLevel =3D (UINT8) > CpuPowerMgmtTestConfig->ConfigTdpLevel; > + FspsUpd->FspsTestConfig.CstateLatencyControl1Irtl =3D (UINT16) > CpuPowerMgmtTestConfig->CstateLatencyControl1Irtl; > + FspsUpd->FspsTestConfig.CstateLatencyControl2Irtl =3D (UINT16) > CpuPowerMgmtTestConfig->CstateLatencyControl2Irtl; > + FspsUpd->FspsTestConfig.CstateLatencyControl3Irtl =3D (UINT16) > CpuPowerMgmtTestConfig->CstateLatencyControl3Irtl; > + FspsUpd->FspsTestConfig.CstateLatencyControl4Irtl =3D (UINT16) > CpuPowerMgmtTestConfig->CstateLatencyControl4Irtl; > + FspsUpd->FspsTestConfig.CstateLatencyControl5Irtl =3D (UINT16) > CpuPowerMgmtTestConfig->CstateLatencyControl5Irtl; > + > + // > + // Get BIST information from Sec Platform Information > + // > + SecPlatformInformation2 =3D GetSecPlatformInformation2 (PeiServices); > + if (SecPlatformInformation2 =3D=3D NULL) { > + SecPlatformInformation2 =3D GetSecPlatformInformationInfoInFormat2 > (PeiServices); > + } > + > + ASSERT (SecPlatformInformation2 !=3D NULL); > + > + if (SecPlatformInformation2 !=3D NULL) { > + FspsUpd->FspsConfig.CpuBistData =3D (UINT32)SecPlatformInformation2; > + DEBUG((DEBUG_INFO, "SecPlatformInformation NumberOfCpus - %x\n", > SecPlatformInformation2->NumberOfCpus)); > + DEBUG ((DEBUG_INFO, "SecPlatformInformation BIST - %x\n", > SecPlatformInformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32 > )); > + } > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspMePolicyInitLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspMePolicyInitLib.c > new file mode 100644 > index 0000000000..97d9842aff > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspMePolicyInitLib.c > @@ -0,0 +1,121 @@ > +/** @file > + Implementation of Fsp Me Policy Initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > + > +/** > + Performs FSP ME PEI Policy pre mem initialization. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspMePolicyInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ) > +{ > + EFI_STATUS Status; > + SI_PREMEM_POLICY_PPI *SiPreMemPolicy; > + ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig; > + > + DEBUG ((DEBUG_INFO, "PeiFspMePolicyInitPreMem\n")); > + > + // > + // Locate gSiPreMemPolicyPpi > + // > + SiPreMemPolicy =3D NULL; > + Status =3D PeiServicesLocatePpi ( > + &gSiPreMemPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPreMemPolicy > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gMePeiPreMemConfigGuid, (VOID *) &MePeiPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + > + FspmUpd->FspmConfig.HeciTimeouts =3D (UINT8) > MePeiPreMemConfig->HeciTimeouts; > + // > + // Test policies > + // > + FspmUpd->FspmTestConfig.DidInitStat =3D (UINT8) > MePeiPreMemConfig->DidInitStat; > + FspmUpd->FspmTestConfig.DisableCpuReplacedPolling =3D (UINT8) > MePeiPreMemConfig->DisableCpuReplacedPolling; > + FspmUpd->FspmTestConfig.SendDidMsg =3D (UINT8) > MePeiPreMemConfig->SendDidMsg; > + FspmUpd->FspmTestConfig.DisableHeciRetry =3D (UINT8) > MePeiPreMemConfig->DisableHeciRetry; > + FspmUpd->FspmTestConfig.DisableMessageCheck =3D (UINT8) > MePeiPreMemConfig->DisableMessageCheck; > + FspmUpd->FspmTestConfig.SkipMbpHob =3D (UINT8) > MePeiPreMemConfig->SkipMbpHob; > + > + FspmUpd->FspmTestConfig.HeciCommunication2 =3D (UINT8) > MePeiPreMemConfig->HeciCommunication2; > + FspmUpd->FspmTestConfig.KtDeviceEnable =3D (UINT8) > MePeiPreMemConfig->KtDeviceEnable; > + > + FspmUpd->FspmConfig.Heci1BarAddress =3D > MePeiPreMemConfig->Heci1BarAddress; > + FspmUpd->FspmConfig.Heci2BarAddress =3D > MePeiPreMemConfig->Heci2BarAddress; > + FspmUpd->FspmConfig.Heci3BarAddress =3D > MePeiPreMemConfig->Heci3BarAddress; > + > + return EFI_SUCCESS; > +} > + > +/** > + Performs FSP ME PEI Policy initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspMePolicyInit ( > + IN OUT FSPS_UPD *FspsUpd > + ) > +{ > + EFI_STATUS Status; > + SI_POLICY_PPI *SiPolicyPpi; > + ME_PEI_CONFIG *MePeiConfig; > + > + DEBUG ((DEBUG_INFO, "PeiFspMePolicyInit \n")); > + // > + // Locate gSiPolicyPpiGuid > + // > + SiPolicyPpi =3D NULL; > + Status =3D PeiServicesLocatePpi ( > + &gSiPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPolicyPpi > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (V= OID *) > &MePeiConfig); > + ASSERT_EFI_ERROR (Status); > + > + FspsUpd->FspsConfig.Heci3Enabled =3D (UINT8) > MePeiConfig->Heci3Enabled; > + FspsUpd->FspsConfig.MeUnconfigOnRtcClear =3D (UINT8) > MePeiConfig->MeUnconfigOnRtcClear; > + > + // > + // Test policies > + // > + FspsUpd->FspsTestConfig.MctpBroadcastCycle =3D (UINT8) > MePeiConfig->MctpBroadcastCycle; > + FspsUpd->FspsTestConfig.EndOfPostMessage =3D (UINT8) > MePeiConfig->EndOfPostMessage; > + FspsUpd->FspsTestConfig.DisableD0I3SettingForHeci =3D (UINT8) > MePeiConfig->DisableD0I3SettingForHeci; > + > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspMiscUpdInitLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspMiscUpdInitLib.c > new file mode 100644 > index 0000000000..9545e3df0b > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspMiscUpdInitLib.c > @@ -0,0 +1,77 @@ > +/** @file > + Implementation of Fsp Misc UPD Initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +#include > +#include > + > +#define STATUS_CODE_USE_RAM BIT0 > +#define STATUS_CODE_USE_ISA_SERIAL BIT1 > +#define STATUS_CODE_USE_USB BIT2 > +#define STATUS_CODE_USE_USB3 BIT3 > +#define STATUS_CODE_USE_SERIALIO BIT4 > +#define STATUS_CODE_USE_TRACEHUB BIT5 > +#define STATUS_CODE_CMOS_INVALID BIT6 > +#define STATUS_CODE_CMOS_VALID BIT7 > +/** > + Performs FSP Misc UPD initialization. > + > + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspMiscUpdInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ) > +{ > + EFI_STATUS Status; > + EFI_PEI_HOB_POINTERS Hob; > + DEBUG_CONFIG_DATA_HOB *DebugConfigData; > + UINT8 DebugInterfaces; > + > + FspmUpd->FspmArchUpd.StackBase =3D (VOID > *)(UINTN)(PcdGet32(PcdTemporaryRamBase) + > PcdGet32(PcdTemporaryRamSize) - (PcdGet32(PcdFspTemporaryRamSize) + > PcdGet32(PcdFspReservedBufferSize))); > + FspmUpd->FspmArchUpd.StackSize =3D PcdGet32(PcdFspTemporaryRamSize); > + > + Status =3D PeiServicesGetBootMode > (&(FspmUpd->FspmArchUpd.BootMode)); > + if (EFI_ERROR (Status)) { > + FspmUpd->FspmArchUpd.BootMode =3D > BOOT_WITH_FULL_CONFIGURATION; > + } > + > + FspmUpd->FspmArchUpd.BootLoaderTolumSize =3D 0x0; > + > + // > + // Initialize DebugConfigData > + // > + DebugInterfaces =3D 0x00; > + Hob.Guid =3D GetFirstGuidHob (&gDebugConfigHobGuid); > + if (Hob.Guid !=3D NULL) { > + DebugConfigData =3D (DEBUG_CONFIG_DATA_HOB *) GET_GUID_HOB_DATA > (Hob.Guid); > + if (DebugConfigData !=3D NULL) { > + // Debug Interfaces > + if (DebugConfigData->RamDebugInterface) { DebugInterfaces |= =3D > STATUS_CODE_USE_RAM; } > + if (DebugConfigData->UartDebugInterface) { DebugInterfaces |= =3D > STATUS_CODE_USE_ISA_SERIAL; } > + if (DebugConfigData->Usb3DebugInterface) { DebugInterfaces |= =3D > STATUS_CODE_USE_USB3; } > + if (DebugConfigData->SerialIoDebugInterface) { DebugInterfaces |= =3D > STATUS_CODE_USE_SERIALIO; } > + if (DebugConfigData->TraceHubDebugInterface) { DebugInterfaces |= =3D > STATUS_CODE_USE_TRACEHUB; } > + FspmUpd->FspmConfig.PcdDebugInterfaceFlags =3D DebugInterfaces; > + // Serial debug message baud rate > + FspmUpd->FspmConfig.PcdSerialDebugBaudRate =3D > DebugConfigData->SerialDebugBaudRate; > + //Serial debug message level > + FspmUpd->FspmConfig.PcdSerialDebugLevel =3D > DebugConfigData->SerialDebug; > + } > + } > + DEBUG ((DEBUG_INFO, "FspmConfig.PcdDebugInterfaceFlags is 0x%X\n", > FspmUpd->FspmConfig.PcdDebugInterfaceFlags)); > + DEBUG ((DEBUG_INFO, "FspmUpd->FspmConfig.PcdSerialDebugBaudRate > is 0x%X\n", FspmUpd->FspmConfig.PcdSerialDebugBaudRate)); > + DEBUG ((DEBUG_INFO, "FspmUpd->FspmConfig.PcdSerialDebugLevel is > 0x%X\n", FspmUpd->FspmConfig.PcdSerialDebugLevel)); > + > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspPchPolicyInitLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspPchPolicyInitLib.c > new file mode 100644 > index 0000000000..e2022929cd > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspPchPolicyInitLib.c > @@ -0,0 +1,736 @@ > +/** @file > + Implementation of Fsp PCH Policy Initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > + > +/** > + Performs FSP PCH PEI Policy pre mem initialization. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspPchPolicyInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ) > +{ > + EFI_STATUS Status; > + UINTN Index; > + UINTN MaxPcieRootPorts; > + SI_PREMEM_POLICY_PPI *SiPreMemPolicy; > + PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig; > + PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig; > + PCH_DCI_PREMEM_CONFIG *DciPreMemConfig; > + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; > + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; > + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig; > + PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig; > + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; > + PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig; > + PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig; > + PCH_ISH_PREMEM_CONFIG *IshPreMemConfig; > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP > UpdatePeiPchPolicyPreMem\n")); > + DEBUG((DEBUG_INFO | DEBUG_INIT, "FspmUpd =3D 0x%x\n", FspmUpd)); > + // > + // Locate PchPreMemPolicyPpi > + // > + SiPreMemPolicy =3D NULL; > + Status =3D PeiServicesLocatePpi ( > + &gSiPreMemPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPreMemPolicy > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gPchTraceHubPreMemConfigGuid, (VOID *) &PchTraceHubPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gSmbusPreMemConfigGuid, (VOID *) &SmbusPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gDciPreMemConfigGuid, (VOID *) &DciPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gLpcPreMemConfigGuid, (VOID *) &LpcPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gWatchDogPreMemConfigGuid, (VOID *) &WdtPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gHdAudioPreMemConfigGuid, (VOID *) &HdaPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gIshPreMemConfigGuid, (VOID *) &IshPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ > UpdatePeiPchPolicyPreMem\n")); > + // > + // Update PCIE RP policies > + // > +// MaxPcieRootPorts =3D 16; > + > + MaxPcieRootPorts =3D GetPchMaxPciePortNum (); > +// MaxPcieRootPorts =3D 16; > + FspmUpd->FspmConfig.PcieRpEnableMask =3D > PcieRpPreMemConfig->RpEnabledMask & ((1 << MaxPcieRootPorts) - 1); > + FspmUpd->FspmConfig.PcieImrEnabled =3D > PcieRpPreMemConfig->PcieImrEnabled; > + FspmUpd->FspmConfig.PcieImrSize =3D PcieRpPreMemConfig->PcieImrSize; > + FspmUpd->FspmConfig.ImrRpSelection =3D > PcieRpPreMemConfig->ImrRpSelection; > + // > + // Update TraceHub policies > + // > + FspmUpd->FspmConfig.PchTraceHubMode =3D (UINT8) > PchTraceHubPreMemConfig->EnableMode; > + FspmUpd->FspmConfig.PchTraceHubMemReg0Size =3D (UINT8) > PchTraceHubPreMemConfig->MemReg0Size; > + FspmUpd->FspmConfig.PchTraceHubMemReg1Size =3D (UINT8) > PchTraceHubPreMemConfig->MemReg1Size; > + > + // > + // Update Smbus policies > + // > + FspmUpd->FspmConfig.SmbusEnable =3D > (UINT8)SmbusPreMemConfig->Enable; > + FspmUpd->FspmConfig.SmbusArpEnable =3D > (UINT8)SmbusPreMemConfig->ArpEnable; > + FspmUpd->FspmTestConfig.SmbusDynamicPowerGating =3D > (UINT8)SmbusPreMemConfig->DynamicPowerGating; > + FspmUpd->FspmTestConfig.SmbusSpdWriteDisable =3D > (UINT8)SmbusPreMemConfig->SpdWriteDisable; > + FspmUpd->FspmConfig.PchSmbAlertEnable =3D > (UINT8)SmbusPreMemConfig->SmbAlertEnable; > + FspmUpd->FspmConfig.PchSmbusIoBase =3D > (UINT16)SmbusPreMemConfig->SmbusIoBase; > + FspmUpd->FspmConfig.PchNumRsvdSmbusAddresses =3D > (UINT8)SmbusPreMemConfig->NumRsvdSmbusAddresses; > + FspmUpd->FspmConfig.RsvdSmbusAddressTablePtr =3D > (UINT32)SmbusPreMemConfig->RsvdSmbusAddressTable; > + > + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ1 > UpdatePeiPchPolicyPreMem\n")); > + // > + // Update Dci policies > + // > + FspmUpd->FspmConfig.PlatformDebugConsent =3D > (UINT8)DciPreMemConfig->PlatformDebugConsent; > + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ11 > UpdatePeiPchPolicyPreMem\n")); > + FspmUpd->FspmConfig.DciUsb3TypecUfpDbg =3D > (UINT8)DciPreMemConfig->DciUsb3TypecUfpDbg; > + // > + // Update HSIO PCIE policies > + // > + for (Index =3D 0; Index < MaxPcieRootPorts; Index ++) { > + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable; > + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle; > + FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmpEnable[Index] > =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEna > ble; > + FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmp[Index] =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp; > + FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmpEnable[Index] > =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEna > ble; > + FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmp[Index] =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp; > + FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmpEnable[Index] > =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEna > ble; > + FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmp[Index] =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp; > + FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmphEnable[Index] =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable; > + FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmph[Index] =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph; > + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5Enable[Index] > =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable; > + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5[Index] =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5; > + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0Enable[Index] > =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable; > + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0[Index] =3D > (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0; > + } > + > + // > + // Update HSIO SATA policies > + // > + for (Index =3D 0; Index < PCH_MAX_SATA_PORTS; Index ++) { > + FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMagEnable[Index] > =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEn > able; > + FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMag[Index] =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag; > + FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMagEnable[Index] > =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEn > able; > + FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMag[Index] =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag; > + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] > =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEn > able; > + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag; > + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] > =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp > Enable; > + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp > ; > + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] > =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp > Enable; > + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp > ; > + FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmpEnable[Index] > =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp > Enable; > + FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmp[Index] =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp > ; > + FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmphEnable[Index] =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable > ; > + FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmph[Index] =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph; > + FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmphEnable[Index] =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable > ; > + FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmph[Index] =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph; > + FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmphEnable[Index] =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable > ; > + FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmph[Index] =3D > (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph; > + } > + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ2 > UpdatePeiPchPolicyPreMem\n")); > + // Update LPC policies > + // > + FspmUpd->FspmConfig.PchLpcEnhancePort8xhDecoding =3D > (UINT8)LpcPreMemConfig->EnhancePort8xhDecoding; > + > + // > + // Update Pch General Premem policies > + // > + FspmUpd->FspmConfig.PchPort80Route =3D > (UINT8)PchGeneralPreMemConfig->Port80Route; > + > + // > + // Update Wdt policies > + // > + FspmUpd->FspmTestConfig.WdtDisableAndLock =3D > (UINT8)WdtPreMemConfig->DisableAndLock; > + > + // > + // HdAudioConfig > + // > + FspmUpd->FspmConfig.PchHdaEnable =3D > (UINT8)HdaPreMemConfig->Enable; > + > + // > + // IshConfig > + // > + FspmUpd->FspmConfig.PchIshEnable =3D (UINT8)IshPreMemConfig->Enable; > + > + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ3 > UpdatePeiPchPolicyPreMem\n")); > + return EFI_SUCCESS; > +} > + > +/** > + Performs FSP PCH PEI Policy initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspPchPolicyInit ( > + IN OUT FSPS_UPD *FspsUpd > + ) > +{ > + EFI_STATUS Status; > + UINTN Index; > + UINTN MaxPcieRootPorts; > + UINT8 Data8; > + SI_POLICY_PPI *SiPolicy; > + PCH_LAN_CONFIG *LanConfig; > + PCH_HDAUDIO_CONFIG *HdAudioConfig; > + PCH_SCS_CONFIG *ScsConfig; > + PCH_ISH_CONFIG *IshConfig; > + PCH_SATA_CONFIG *SataConfig; > + USB_CONFIG *UsbConfig; > + PCH_SERIAL_IO_CONFIG *SerialIoConfig; > + PCH_INTERRUPT_CONFIG *InterruptConfig; > + PCH_LOCK_DOWN_CONFIG *LockDownConfig; > + PCH_CNVI_CONFIG *CnviConfig; > + PCH_HSIO_CONFIG *HsioConfig; > + PCH_ESPI_CONFIG *EspiConfig; > + PCH_PCIE_CONFIG *PcieRpConfig; > + PCH_DMI_CONFIG *DmiConfig; > + PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; > + PCH_IOAPIC_CONFIG *IoApicConfig; > + PCH_P2SB_CONFIG *P2sbConfig; > + PCH_GENERAL_CONFIG *PchGeneralConfig; > + PCH_PM_CONFIG *PmConfig; > + PCH_LPC_SIRQ_CONFIG *PchSerialIrqConfig; > + PCH_THERMAL_CONFIG *PchThermalConfig; > + > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n")); > + // > + // Locate SiPolicyPpi > + // > + SiPolicy =3D NULL; > + Status =3D PeiServicesLocatePpi ( > + &gSiPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPolicy > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *= ) > &LanConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VO= ID *) > &HdAudioConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *= ) > &ScsConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *= ) > &IshConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID = *) > &SataConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *= ) > &UsbConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (V= OID *) > &SerialIoConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (= VOID *) > &InterruptConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (V= OID *) > &LockDownConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOI= D *) > &PcieRpConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *= ) > &DmiConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigG= uid, > (VOID *) &FlashProtectionConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOI= D *) > &IoApicConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gP2sbConfigGuid, (VOID = *) > &P2sbConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, = (VOID > *) &PchGeneralConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) > &PmConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (= VOID *) > &PchSerialIrqConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VO= ID *) > &PchThermalConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID = *) > &CnviConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gHsioConfigGuid, (VOID = *) > &HsioConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID = *) > &EspiConfig); > + ASSERT_EFI_ERROR (Status); > + > + // > + // Update LAN policies > + // > + FspsUpd->FspsConfig.PchLanEnable =3D (UINT8)LanConfig->Enable= ; > + FspsUpd->FspsConfig.PchLanLtrEnable =3D (UINT8)LanConfig->LtrEna= ble; > + > + // > + // Update HDA policies > + // > + FspsUpd->FspsConfig.PchHdaDspEnable =3D > (UINT8)HdAudioConfig->DspEnable; > + FspsUpd->FspsConfig.PchHdaPme =3D > (UINT8)HdAudioConfig->Pme; > + FspsUpd->FspsConfig.PchHdaVcType =3D > (UINT8)HdAudioConfig->VcType; > + FspsUpd->FspsConfig.PchHdaLinkFrequency =3D > (UINT8)HdAudioConfig->HdAudioLinkFrequency; > + FspsUpd->FspsConfig.PchHdaIDispLinkFrequency =3D > (UINT8)HdAudioConfig->IDispLinkFrequency; > + FspsUpd->FspsConfig.PchHdaIDispLinkTmode =3D > (UINT8)HdAudioConfig->IDispLinkTmode; > + FspsUpd->FspsConfig.PchHdaDspUaaCompliance =3D > (UINT8)HdAudioConfig->DspUaaCompliance; > + FspsUpd->FspsConfig.PchHdaIDispCodecDisconnect =3D > (UINT8)HdAudioConfig->IDispCodecDisconnect; > + FspsUpd->FspsConfig.PchHdaCodecSxWakeCapability =3D > (UINT8)HdAudioConfig->CodecSxWakeCapability; > + FspsUpd->FspsTestConfig.PchHdaResetWaitTimer =3D > (UINT16)HdAudioConfig->ResetWaitTimer; > + FspsUpd->FspsConfig.PchHdaVerbTableEntryNum =3D > HdAudioConfig->VerbTableEntryNum; > + FspsUpd->FspsConfig.PchHdaVerbTablePtr =3D > HdAudioConfig->VerbTablePtr; > + FspsUpd->FspsConfig.PchHdaAudioLinkHda =3D > (UINT8)HdAudioConfig->AudioLinkHda; > + FspsUpd->FspsConfig.PchHdaAudioLinkDmic0 =3D > (UINT8)HdAudioConfig->AudioLinkDmic0; > + FspsUpd->FspsConfig.PchHdaAudioLinkDmic1 =3D > (UINT8)HdAudioConfig->AudioLinkDmic1; > + FspsUpd->FspsConfig.PchHdaAudioLinkSsp0 =3D > (UINT8)HdAudioConfig->AudioLinkSsp0; > + FspsUpd->FspsConfig.PchHdaAudioLinkSsp1 =3D > (UINT8)HdAudioConfig->AudioLinkSsp1; > + FspsUpd->FspsConfig.PchHdaAudioLinkSsp2 =3D > (UINT8)HdAudioConfig->AudioLinkSsp2; > + FspsUpd->FspsConfig.PchHdaAudioLinkSndw1 =3D > (UINT8)HdAudioConfig->AudioLinkSndw1; > + FspsUpd->FspsConfig.PchHdaAudioLinkSndw2 =3D > (UINT8)HdAudioConfig->AudioLinkSndw2; > + FspsUpd->FspsConfig.PchHdaAudioLinkSndw3 =3D > (UINT8)HdAudioConfig->AudioLinkSndw3; > + FspsUpd->FspsConfig.PchHdaAudioLinkSndw4 =3D > (UINT8)HdAudioConfig->AudioLinkSndw4; > + FspsUpd->FspsConfig.PchHdaSndwBufferRcomp =3D > (UINT8)HdAudioConfig->SndwBufferRcomp; > + > + // > + // Update SCS policies > + // > + FspsUpd->FspsConfig.ScsEmmcEnabled =3D > (UINT8)ScsConfig->ScsEmmcEnabled; > + FspsUpd->FspsConfig.ScsEmmcHs400Enabled =3D > (UINT8)ScsConfig->ScsEmmcHs400Enabled; > + FspsUpd->FspsConfig.ScsSdCardEnabled =3D > (UINT8)ScsConfig->ScsSdcardEnabled; > + FspsUpd->FspsConfig.SdCardPowerEnableActiveHigh =3D > (UINT8)ScsConfig->SdCardPowerEnableActiveHigh; > +#ifdef CFL_SIMICS > + FspsUpd->FspsConfig.ScsUfsEnabled =3D 0; > +#else > + FspsUpd->FspsConfig.ScsUfsEnabled =3D > (UINT8)ScsConfig->ScsUfsEnabled; > +#endif > + FspsUpd->FspsConfig.PchScsEmmcHs400TuningRequired =3D > (UINT8)ScsConfig->ScsEmmcHs400TuningRequired; > + FspsUpd->FspsConfig.PchScsEmmcHs400DllDataValid =3D > (UINT8)ScsConfig->ScsEmmcHs400DllDataValid; > + FspsUpd->FspsConfig.PchScsEmmcHs400RxStrobeDll1 =3D > (UINT8)ScsConfig->ScsEmmcHs400RxStrobeDll1; > + FspsUpd->FspsConfig.PchScsEmmcHs400TxDataDll =3D > (UINT8)ScsConfig->ScsEmmcHs400TxDataDll; > + FspsUpd->FspsConfig.PchScsEmmcHs400DriverStrength =3D > (UINT8)ScsConfig->ScsEmmcHs400DriverStrength; > + > + // > + // Update ISH policies > + // > + FspsUpd->FspsConfig.PchIshSpiGpioAssign =3D > (UINT8)IshConfig->SpiGpioAssign; > + FspsUpd->FspsConfig.PchIshUart0GpioAssign =3D > (UINT8)IshConfig->Uart0GpioAssign; > + FspsUpd->FspsConfig.PchIshUart1GpioAssign =3D > (UINT8)IshConfig->Uart1GpioAssign; > + FspsUpd->FspsConfig.PchIshI2c0GpioAssign =3D > (UINT8)IshConfig->I2c0GpioAssign; > + FspsUpd->FspsConfig.PchIshI2c1GpioAssign =3D > (UINT8)IshConfig->I2c1GpioAssign; > + FspsUpd->FspsConfig.PchIshI2c2GpioAssign =3D > (UINT8)IshConfig->I2c2GpioAssign; > + FspsUpd->FspsConfig.PchIshGp0GpioAssign =3D > (UINT8)IshConfig->Gp0GpioAssign; > + FspsUpd->FspsConfig.PchIshGp1GpioAssign =3D > (UINT8)IshConfig->Gp1GpioAssign; > + FspsUpd->FspsConfig.PchIshGp2GpioAssign =3D > (UINT8)IshConfig->Gp2GpioAssign; > + FspsUpd->FspsConfig.PchIshGp3GpioAssign =3D > (UINT8)IshConfig->Gp3GpioAssign; > + FspsUpd->FspsConfig.PchIshGp4GpioAssign =3D > (UINT8)IshConfig->Gp4GpioAssign; > + FspsUpd->FspsConfig.PchIshGp5GpioAssign =3D > (UINT8)IshConfig->Gp5GpioAssign; > + FspsUpd->FspsConfig.PchIshGp6GpioAssign =3D > (UINT8)IshConfig->Gp6GpioAssign; > + FspsUpd->FspsConfig.PchIshGp7GpioAssign =3D > (UINT8)IshConfig->Gp7GpioAssign; > + FspsUpd->FspsConfig.PchIshPdtUnlock =3D > (UINT8)IshConfig->PdtUnlock; > + > + // > + // Update PCIE RP RootPort policies > + // > + MaxPcieRootPorts =3D GetPchMaxPciePortNum (); > + FspsUpd->FspsConfig.PcieRpDpcMask =3D 0; > + FspsUpd->FspsConfig.PcieRpDpcExtensionsMask =3D 0; > + FspsUpd->FspsConfig.PcieRpPtmMask =3D 0; > + for (Index =3D 0; Index < MaxPcieRootPorts; Index ++) { > + FspsUpd->FspsConfig.PcieRpHotPlug[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].HotPlug; > + FspsUpd->FspsConfig.PcieRpSlotImplemented[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].SlotImplemented; > + FspsUpd->FspsConfig.PcieRpPmSci[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].PmSci; > + FspsUpd->FspsConfig.PcieRpExtSync[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].ExtSync; > + FspsUpd->FspsConfig.PcieRpTransmitterHalfSwing[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].TransmitterHalfSwing; > + FspsUpd->FspsConfig.PcieRpClkReqDetect[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].ClkReqDetect; > + FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].AdvancedErrorReporting; > + FspsUpd->FspsConfig.PcieRpUnsupportedRequestReport[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].UnsupportedRequestReport; > + FspsUpd->FspsConfig.PcieRpFatalErrorReport[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].FatalErrorReport; > + FspsUpd->FspsConfig.PcieRpNoFatalErrorReport[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].NoFatalErrorReport; > + FspsUpd->FspsConfig.PcieRpCorrectableErrorReport[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].CorrectableErrorReport; > + FspsUpd->FspsConfig.PcieRpSystemErrorOnFatalError[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnFatalError; > + FspsUpd->FspsConfig.PcieRpSystemErrorOnNonFatalError[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnNonFatalError; > + FspsUpd->FspsConfig.PcieRpSystemErrorOnCorrectableError[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnCorrectableError; > + FspsUpd->FspsConfig.PcieRpMaxPayload[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].MaxPayload; > + if (PcieRpConfig->RootPort[Index].DpcEnabled) { > + FspsUpd->FspsConfig.PcieRpDpcMask |=3D (BIT0< + } > + if (PcieRpConfig->RootPort[Index].RpDpcExtensionsEnabled) { > + FspsUpd->FspsConfig.PcieRpDpcExtensionsMask |=3D (BIT0< + } > + if (PcieRpConfig->RootPort[Index].PtmEnabled) { > + FspsUpd->FspsConfig.PcieRpPtmMask |=3D (BIT0< + } > + FspsUpd->FspsConfig.PcieRpPcieSpeed[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].PcieSpeed; > + FspsUpd->FspsConfig.PcieRpGen3EqPh3Method[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].Gen3EqPh3Method; > + FspsUpd->FspsConfig.PcieRpPhysicalSlotNumber[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].PhysicalSlotNumber; > + FspsUpd->FspsConfig.PcieRpCompletionTimeout[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].CompletionTimeout; > + FspsUpd->FspsConfig.PcieRpAspm[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].Aspm; > + FspsUpd->FspsConfig.PcieRpL1Substates[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].L1Substates; > + FspsUpd->FspsConfig.PcieRpLtrEnable[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].LtrEnable; > + FspsUpd->FspsConfig.PcieRpLtrConfigLock[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].LtrConfigLock; > + FspsUpd->FspsConfig.PcieRpAcsEnabled[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].AcsEnabled; > + FspsUpd->FspsConfig.PcieRpDetectTimeoutMs[Index] =3D > (UINT16)PcieRpConfig->RootPort[Index].DetectTimeoutMs; > + FspsUpd->FspsConfig.PcieRootPortGen2PllL1CgDisable[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].PcieRootPortGen2PllL1CgDisable; > + > + FspsUpd->FspsTestConfig.PcieRpLtrMaxSnoopLatency[Index] =3D > (UINT16)PcieRpConfig->RootPort[Index].LtrMaxSnoopLatency; > + FspsUpd->FspsTestConfig.PcieRpLtrMaxNoSnoopLatency[Index] =3D > (UINT16)PcieRpConfig->RootPort[Index].LtrMaxNoSnoopLatency; > + > + FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMode[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMode; > + FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMultiplier[Index] > =3D (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMultiplier; > + FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideValue[Index] =3D > (UINT16)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideValue; > + > + FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMode[Index] > =3D (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMode; > + > FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMultiplier[Index] > =3D > (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier; > + FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideValue[Index] > =3D (UINT16)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideValue; > + > + FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitScale[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].SlotPowerLimitScale; > + FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitValue[Index] =3D > (UINT16)PcieRpConfig->RootPort[Index].SlotPowerLimitValue; > + FspsUpd->FspsTestConfig.PcieRpUptp[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].Uptp; > + FspsUpd->FspsTestConfig.PcieRpDptp[Index] =3D > (UINT8)PcieRpConfig->RootPort[Index].Dptp; > + > + } > + for (Index =3D 0; Index < GetPchMaxPcieClockNum (); Index ++) { > + FspsUpd->FspsConfig.PcieClkSrcUsage[Index] =3D > PcieRpConfig->PcieClock[Index].Usage; > + FspsUpd->FspsConfig.PcieClkSrcClkReq[Index] =3D > PcieRpConfig->PcieClock[Index].ClkReq; > + } > + > + // > + // Update PCIE RP EqPh3LaneParam policies > + // > + for (Index =3D 0; Index < MaxPcieRootPorts; Index ++) { > + FspsUpd->FspsConfig.PcieEqPh3LaneParamCm[Index] =3D > (UINT8)PcieRpConfig->EqPh3LaneParam[Index].Cm; > + FspsUpd->FspsConfig.PcieEqPh3LaneParamCp[Index] =3D > (UINT8)PcieRpConfig->EqPh3LaneParam[Index].Cp; > + } > + > + // > + // Update PCIE RP SwEqCoeffList policies > + // > + for (Index =3D 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index ++) { > + FspsUpd->FspsConfig.PcieSwEqCoeffListCm[Index] =3D > (UINT8)PcieRpConfig->SwEqCoeffList[Index].Cm; > + FspsUpd->FspsConfig.PcieSwEqCoeffListCp[Index] =3D > (UINT8)PcieRpConfig->SwEqCoeffList[Index].Cp; > + } > + > + // > + // Update PCIE RP policies > + // > + FspsUpd->FspsTestConfig.PcieEnablePort8xhDecode =3D > (UINT8)PcieRpConfig->EnablePort8xhDecode; > + FspsUpd->FspsTestConfig.PchPciePort8xhDecodePortIndex =3D > (UINT8)PcieRpConfig->PchPciePort8xhDecodePortIndex; > + FspsUpd->FspsConfig.PcieDisableRootPortClockGating =3D > (UINT8)PcieRpConfig->DisableRootPortClockGating; > + FspsUpd->FspsConfig.PcieEnablePeerMemoryWrite =3D > (UINT8)PcieRpConfig->EnablePeerMemoryWrite; > + FspsUpd->FspsConfig.PcieComplianceTestMode =3D > (UINT8)PcieRpConfig->ComplianceTestMode; > + FspsUpd->FspsConfig.PcieRpFunctionSwap =3D > (UINT8)PcieRpConfig->RpFunctionSwap; > + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr =3D > PcieRpConfig->PcieDeviceOverrideTablePtr; > + > + // > + // Update Sata Policies > + // > + FspsUpd->FspsConfig.SataEnable =3D > (UINT8)SataConfig->Enable; > + FspsUpd->FspsTestConfig.SataTestMode =3D > (UINT8)SataConfig->TestMode; > + FspsUpd->FspsConfig.SataSalpSupport =3D > (UINT8)SataConfig->SalpSupport; > + FspsUpd->FspsConfig.SataPwrOptEnable =3D > (UINT8)SataConfig->PwrOptEnable; > + FspsUpd->FspsConfig.EsataSpeedLimit =3D > (UINT8)SataConfig->EsataSpeedLimit; > + FspsUpd->FspsConfig.SataLedEnable =3D (UINT8)SataConfig->LedEnable; > + FspsUpd->FspsConfig.SataMode =3D (UINT8)SataConfig->SataMode; > + FspsUpd->FspsConfig.SataSpeedLimit =3D (UINT8)SataConfig->SpeedLimit= ; > + > + for (Index =3D 0; Index < PCH_MAX_SATA_PORTS; Index++) { > + FspsUpd->FspsConfig.SataPortsEnable[Index] =3D > (UINT8)SataConfig->PortSettings[Index].Enable; > + FspsUpd->FspsConfig.SataPortsHotPlug[Index] =3D > (UINT8)SataConfig->PortSettings[Index].HotPlug; > + FspsUpd->FspsConfig.SataPortsInterlockSw[Index] =3D > (UINT8)SataConfig->PortSettings[Index].InterlockSw; > + FspsUpd->FspsConfig.SataPortsExternal[Index] =3D > (UINT8)SataConfig->PortSettings[Index].External; > + FspsUpd->FspsConfig.SataPortsSpinUp[Index] =3D > (UINT8)SataConfig->PortSettings[Index].SpinUp; > + FspsUpd->FspsConfig.SataPortsSolidStateDrive[Index] =3D > (UINT8)SataConfig->PortSettings[Index].SolidStateDrive; > + FspsUpd->FspsConfig.SataPortsDevSlp[Index] =3D > (UINT8)SataConfig->PortSettings[Index].DevSlp; > + FspsUpd->FspsConfig.SataPortsEnableDitoConfig[Index] =3D > (UINT8)SataConfig->PortSettings[Index].EnableDitoConfig; > + FspsUpd->FspsConfig.SataPortsDmVal[Index] =3D > (UINT8)SataConfig->PortSettings[Index].DmVal; > + FspsUpd->FspsConfig.SataPortsDitoVal[Index] =3D > (UINT16)SataConfig->PortSettings[Index].DitoVal; > + FspsUpd->FspsConfig.SataPortsZpOdd[Index] =3D > (UINT8)SataConfig->PortSettings[Index].ZpOdd; > + } > + > + FspsUpd->FspsConfig.SataRstRaidDeviceId =3D > (UINT8)SataConfig->Rst.RaidDeviceId; > + FspsUpd->FspsConfig.SataRstInterrupt =3D > (UINT8)SataConfig->Rst.SataRstInterrupt; > + FspsUpd->FspsConfig.SataRstRaid0 =3D > (UINT8)SataConfig->Rst.Raid0; > + FspsUpd->FspsConfig.SataRstRaid1 =3D > (UINT8)SataConfig->Rst.Raid1; > + FspsUpd->FspsConfig.SataRstRaid10 =3D > (UINT8)SataConfig->Rst.Raid10; > + FspsUpd->FspsConfig.SataRstRaid5 =3D > (UINT8)SataConfig->Rst.Raid5; > + FspsUpd->FspsConfig.SataRstIrrt =3D > (UINT8)SataConfig->Rst.Irrt; > + FspsUpd->FspsConfig.SataRstOromUiBanner =3D > (UINT8)SataConfig->Rst.OromUiBanner; > + FspsUpd->FspsConfig.SataRstOromUiDelay =3D > (UINT8)SataConfig->Rst.OromUiDelay; > + FspsUpd->FspsConfig.SataRstHddUnlock =3D > (UINT8)SataConfig->Rst.HddUnlock; > + FspsUpd->FspsConfig.SataRstLedLocate =3D > (UINT8)SataConfig->Rst.LedLocate; > + FspsUpd->FspsConfig.SataRstIrrtOnly =3D > (UINT8)SataConfig->Rst.IrrtOnly; > + FspsUpd->FspsConfig.SataRstSmartStorage =3D > (UINT8)SataConfig->Rst.SmartStorage; > + FspsUpd->FspsConfig.SataRstOptaneMemory =3D > (UINT8)SataConfig->Rst.OptaneMemory; > + FspsUpd->FspsConfig.SataRstLegacyOrom =3D > (UINT8)SataConfig->Rst.LegacyOrom; > + FspsUpd->FspsConfig.SataRstCpuAttachedStorage =3D > (UINT8)SataConfig->Rst.CpuAttachedStorage; > + > + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { > + FspsUpd->FspsConfig.SataRstPcieEnable[Index] =3D > (UINT8)SataConfig->RstPcieStorageRemap[Index].Enable; > + FspsUpd->FspsConfig.SataRstPcieStoragePort[Index] =3D > (UINT8)SataConfig->RstPcieStorageRemap[Index].RstPcieStoragePort; > + FspsUpd->FspsConfig.SataRstPcieDeviceResetDelay[Index] =3D > (UINT8)SataConfig->RstPcieStorageRemap[Index].DeviceResetDelay; > + } > + > + FspsUpd->FspsConfig.SataP0T1M =3D > (UINT8)SataConfig->ThermalThrottling.P0T1M; > + FspsUpd->FspsConfig.SataP0T2M =3D > (UINT8)SataConfig->ThermalThrottling.P0T2M; > + FspsUpd->FspsConfig.SataP0T3M =3D > (UINT8)SataConfig->ThermalThrottling.P0T3M; > + FspsUpd->FspsConfig.SataP0TDisp =3D > (UINT8)SataConfig->ThermalThrottling.P0TDisp; > + FspsUpd->FspsConfig.SataP1T1M =3D > (UINT8)SataConfig->ThermalThrottling.P1T1M; > + FspsUpd->FspsConfig.SataP1T2M =3D > (UINT8)SataConfig->ThermalThrottling.P1T2M; > + FspsUpd->FspsConfig.SataP1T3M =3D > (UINT8)SataConfig->ThermalThrottling.P1T3M; > + FspsUpd->FspsConfig.SataP1TDisp =3D > (UINT8)SataConfig->ThermalThrottling.P1TDisp; > + FspsUpd->FspsConfig.SataP0Tinact =3D > (UINT8)SataConfig->ThermalThrottling.P0Tinact; > + FspsUpd->FspsConfig.SataP0TDispFinit =3D > (UINT8)SataConfig->ThermalThrottling.P0TDispFinit; > + FspsUpd->FspsConfig.SataP1Tinact =3D > (UINT8)SataConfig->ThermalThrottling.P1Tinact; > + FspsUpd->FspsConfig.SataP1TDispFinit =3D > (UINT8)SataConfig->ThermalThrottling.P1TDispFinit; > + FspsUpd->FspsConfig.SataThermalSuggestedSetting =3D > (UINT8)SataConfig->ThermalThrottling.SuggestedSetting; > + > + // > + // Update USB policies > + // > + FspsUpd->FspsConfig.PchEnableComplianceMode =3D > (UINT8)UsbConfig->EnableComplianceMode; > + FspsUpd->FspsConfig.UsbPdoProgramming =3D > (UINT8)UsbConfig->PdoProgramming; > + FspsUpd->FspsConfig.PchUsbOverCurrentEnable =3D > (UINT8)UsbConfig->OverCurrentEnable; > + FspsUpd->FspsConfig.PchUsb2PhySusPgEnable =3D > (UINT8)UsbConfig->Usb2PhySusPgEnable; > + FspsUpd->FspsTestConfig.PchXhciOcLock =3D > (UINT8)UsbConfig->XhciOcLock; > + for (Index =3D 0; Index < PCH_MAX_USB2_PORTS; Index++) { > + FspsUpd->FspsConfig.PortUsb20Enable[Index] =3D > (UINT8)UsbConfig->PortUsb20[Index].Enable; > + FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] =3D > (UINT8)UsbConfig->PortUsb20[Index].OverCurrentPin; > + FspsUpd->FspsConfig.Usb2AfePetxiset[Index] =3D > (UINT8)UsbConfig->PortUsb20[Index].Afe.Petxiset; > + FspsUpd->FspsConfig.Usb2AfeTxiset[Index] =3D > (UINT8)UsbConfig->PortUsb20[Index].Afe.Txiset; > + FspsUpd->FspsConfig.Usb2AfePredeemp[Index] =3D > (UINT8)UsbConfig->PortUsb20[Index].Afe.Predeemp; > + FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] =3D > (UINT8)UsbConfig->PortUsb20[Index].Afe.Pehalfbit; > + } > + for (Index =3D 0; Index < PCH_MAX_USB3_PORTS; Index++) { > + FspsUpd->FspsConfig.PortUsb30Enable[Index] =3D > (UINT8)UsbConfig->PortUsb30[Index].Enable; > + FspsUpd->FspsConfig.Usb3OverCurrentPin[Index] =3D > (UINT8)UsbConfig->PortUsb30[Index].OverCurrentPin; > + FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[Index] =3D > (UINT8)UsbConfig->PortUsb30[Index].HsioTxDeEmphEnable; > + FspsUpd->FspsConfig.Usb3HsioTxDeEmph[Index] =3D > (UINT8)UsbConfig->PortUsb30[Index].HsioTxDeEmph; > + FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmpEnable[Index] =3D > (UINT8)UsbConfig->PortUsb30[Index].HsioTxDownscaleAmpEnable; > + FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmp[Index] =3D > (UINT8)UsbConfig->PortUsb30[Index].HsioTxDownscaleAmp; > + > + Data8 =3D 0; > + Data8 |=3D > UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfgEnable ? > B_XHCI_HSIO_CTRL_ADAPT_OFFSET_CFG_EN : 0; > + Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelNEnable ? > B_XHCI_HSIO_FILTER_SELECT_N_EN : 0; > + Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelPEnable ? > B_XHCI_HSIO_FILTER_SELECT_P_EN : 0; > + Data8 |=3D > UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnResEnable ? > B_XHCI_HSIO_LFPS_CFG_PULLUP_DWN_RES_EN : 0; > + FspsUpd->FspsConfig.PchUsbHsioRxTuningEnable[Index] =3D Data8; > + > + Data8 =3D ((UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfg= & > 0x1F) << N_XHCI_UPD_HSIO_CTRL_ADAPT_OFFSET_CFG) | > + ((UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnRes > & 0x7) << N_XHCI_UPD_HSIO_LFPS_CFG_PULLUP_DWN_RES); > + FspsUpd->FspsConfig.PchUsbHsioRxTuningParameters[Index] =3D Data8; > + > + Data8 =3D ((UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelN & 0x7) = << > N_XHCI_UPD_HSIO_FILTER_SELECT_N) | > + ((UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelP & 0x7) << > N_XHCI_UPD_HSIO_FILTER_SELECT_P); > + FspsUpd->FspsConfig.PchUsbHsioFilterSel[Index] =3D Data8; > + } > + > + FspsUpd->FspsConfig.XdciEnable =3D > (UINT8)UsbConfig->XdciConfig.Enable; > + > + // > + // Update SerialIo policies > + // > + for (Index =3D 0; Index < GetPchMaxSerialIoControllersNum (); Index++)= { > + FspsUpd->FspsConfig.SerialIoDevMode[Index] =3D > SerialIoConfig->DevMode[Index]; > + } > + for (Index =3D 0; Index < GetPchMaxSerialIoSpiControllersNum (); Index= ++) { > + FspsUpd->FspsConfig.SerialIoSpiCsPolarity[Index] =3D > SerialIoConfig->SpiCsPolarity[Index]; > + } > + for (Index =3D 0; Index < GetPchMaxSerialIoUartControllersNum (); Inde= x++) { > + FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[Index] =3D > SerialIoConfig->UartHwFlowCtrl[Index]; > + } > + for (Index =3D 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index= ++) { > + FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[Index] =3D > SerialIoConfig->I2cPadsTermination[Index]; > + } > + > + FspsUpd->FspsConfig.SerialIoDebugUartNumber =3D > (UINT8)SerialIoConfig->DebugUartNumber; > + FspsUpd->FspsConfig.SerialIoEnableDebugUartAfterPost =3D > (UINT8)SerialIoConfig->EnableDebugUartAfterPost; > + FspsUpd->FspsConfig.SerialIoUart0PinMuxing =3D > (UINT8)SerialIoConfig->Uart0PinMuxing; > + > + // > + // Update Interrupt policies > + // > + FspsUpd->FspsConfig.DevIntConfigPtr =3D > (UINT32)InterruptConfig->DevIntConfig; > + FspsUpd->FspsConfig.NumOfDevIntConfig =3D > InterruptConfig->NumOfDevIntConfig; > + for (Index =3D 0; Index < PCH_MAX_PXRC_CONFIG; Index ++) { > + FspsUpd->FspsConfig.PxRcConfig[Index] =3D > (UINT8)InterruptConfig->PxRcConfig[Index]; > + } > + FspsUpd->FspsConfig.GpioIrqRoute =3D > (UINT8)InterruptConfig->GpioIrqRoute; > + FspsUpd->FspsConfig.SciIrqSelect =3D (UINT8)InterruptConfig->SciIrqSel= ect; > + FspsUpd->FspsConfig.TcoIrqSelect =3D (UINT8)InterruptConfig->TcoIrqSel= ect; > + FspsUpd->FspsConfig.TcoIrqEnable =3D > (UINT8)InterruptConfig->TcoIrqEnable; > + > + // > + // Update LockDown policies > + // > + FspsUpd->FspsTestConfig.PchLockDownGlobalSmi =3D > (UINT8)LockDownConfig->GlobalSmi; > + FspsUpd->FspsTestConfig.PchLockDownBiosInterface =3D > (UINT8)LockDownConfig->BiosInterface; > + FspsUpd->FspsConfig.PchLockDownBiosLock =3D > (UINT8)LockDownConfig->BiosLock; > + FspsUpd->FspsConfig.PchLockDownRtcMemoryLock =3D > (UINT8)LockDownConfig->RtcMemoryLock; > + FspsUpd->FspsTestConfig.PchUnlockGpioPads =3D > (UINT8)LockDownConfig->UnlockGpioPads; > + > + // > + // Update Dmi policies > + // > + FspsUpd->FspsConfig.PchPwrOptEnable =3D > (UINT8)DmiConfig->PwrOptEnable; > + FspsUpd->FspsConfig.PchDmiAspmCtrl =3D (UINT8)DmiConfig->DmiAspmCtrl; > + > + // > + // Update Flash Protection policies > + // > + for (Index =3D 0; Index < PCH_FLASH_PROTECTED_RANGES; Index ++) { > + FspsUpd->FspsConfig.PchWriteProtectionEnable[Index] =3D > (UINT8)FlashProtectionConfig->ProtectRange[Index].WriteProtectionEnable; > + FspsUpd->FspsConfig.PchReadProtectionEnable[Index] =3D > (UINT8)FlashProtectionConfig->ProtectRange[Index].ReadProtectionEnable; > + FspsUpd->FspsConfig.PchProtectedRangeLimit[Index] =3D > (UINT16)FlashProtectionConfig->ProtectRange[Index].ProtectedRangeLimit; > + FspsUpd->FspsConfig.PchProtectedRangeBase[Index] =3D > (UINT16)FlashProtectionConfig->ProtectRange[Index].ProtectedRangeBase; > + } > + > + // > + // Update IO Apic policies > + // > + FspsUpd->FspsConfig.PchIoApicEntry24_119 =3D > (UINT8)IoApicConfig->IoApicEntry24_119; > + FspsUpd->FspsConfig.Enable8254ClockGating =3D > (UINT8)IoApicConfig->Enable8254ClockGating; > + FspsUpd->FspsConfig.Enable8254ClockGatingOnS3 =3D > (UINT8)IoApicConfig->Enable8254ClockGatingOnS3; > + FspsUpd->FspsConfig.PchIoApicId =3D > (UINT8)IoApicConfig->IoApicId; > + > + // > + // Update P2sb policies > + // > + FspsUpd->FspsTestConfig.PchSbAccessUnlock =3D > (UINT8)P2sbConfig->SbAccessUnlock; > + > + // > + // Update Pch General policies > + // > + FspsUpd->FspsConfig.PchCrid =3D (UINT8)PchGeneralConfig-= >Crid; > + FspsUpd->FspsConfig.PchLegacyIoLowLatency =3D > (UINT8)PchGeneralConfig->LegacyIoLowLatency; > + > + // > + // Update Pm policies > + // > + FspsUpd->FspsConfig.PchPmPmeB0S5Dis =3D > (UINT8)PmConfig->WakeConfig.PmeB0S5Dis; > + FspsUpd->FspsConfig.PchPmWolEnableOverride =3D > (UINT8)PmConfig->WakeConfig.WolEnableOverride; > + FspsUpd->FspsConfig.PchPmPcieWakeFromDeepSx =3D > (UINT8)PmConfig->WakeConfig.PcieWakeFromDeepSx; > + FspsUpd->FspsConfig.PchPmWoWlanEnable =3D > (UINT8)PmConfig->WakeConfig.WoWlanEnable; > + FspsUpd->FspsConfig.PchPmWoWlanDeepSxEnable =3D > (UINT8)PmConfig->WakeConfig.WoWlanDeepSxEnable; > + FspsUpd->FspsConfig.PchPmLanWakeFromDeepSx =3D > (UINT8)PmConfig->WakeConfig.LanWakeFromDeepSx; > + > + FspsUpd->FspsConfig.PchPmDeepSxPol =3D > (UINT8)PmConfig->PchDeepSxPol; > + FspsUpd->FspsConfig.PchPmSlpS3MinAssert =3D > (UINT8)PmConfig->PchSlpS3MinAssert; > + FspsUpd->FspsConfig.PchPmSlpS4MinAssert =3D > (UINT8)PmConfig->PchSlpS4MinAssert; > + FspsUpd->FspsConfig.PchPmSlpSusMinAssert =3D > (UINT8)PmConfig->PchSlpSusMinAssert; > + FspsUpd->FspsConfig.PchPmSlpAMinAssert =3D > (UINT8)PmConfig->PchSlpAMinAssert; > + FspsUpd->FspsConfig.PchPmLpcClockRun =3D > (UINT8)PmConfig->LpcClockRun; > + FspsUpd->FspsConfig.PchPmSlpStrchSusUp =3D > (UINT8)PmConfig->SlpStrchSusUp; > + FspsUpd->FspsConfig.PchPmSlpLanLowDc =3D > (UINT8)PmConfig->SlpLanLowDc; > + FspsUpd->FspsConfig.PchPmPwrBtnOverridePeriod =3D > (UINT8)PmConfig->PwrBtnOverridePeriod; > + FspsUpd->FspsTestConfig.PchPmDisableEnergyReport =3D > (UINT8)PmConfig->DisableEnergyReport; > + FspsUpd->FspsConfig.PchPmDisableDsxAcPresentPulldown =3D > (UINT8)PmConfig->DisableDsxAcPresentPulldown; > + FspsUpd->FspsConfig.PchPmDisableNativePowerButton =3D > (UINT8)PmConfig->DisableNativePowerButton; > + FspsUpd->FspsConfig.PmcPowerButtonDebounce =3D > PmConfig->PowerButtonDebounce; > + FspsUpd->FspsConfig.PchPmSlpS0Enable =3D > (UINT8)PmConfig->SlpS0Enable; > + FspsUpd->FspsConfig.PchPmMeWakeSts =3D > (UINT8)PmConfig->MeWakeSts; > + FspsUpd->FspsConfig.PchPmWolOvrWkSts =3D > (UINT8)PmConfig->WolOvrWkSts; > + FspsUpd->FspsConfig.EnableTcoTimer =3D > (UINT8)PmConfig->EnableTcoTimer; > + FspsUpd->FspsConfig.PchPmVrAlert =3D (UINT8)PmConfig->VrAle= rt; > + FspsUpd->FspsConfig.PchPmPwrCycDur =3D > (UINT8)PmConfig->PchPwrCycDur; > + FspsUpd->FspsConfig.PchPmPciePllSsc =3D > (UINT8)PmConfig->PciePllSsc; > + FspsUpd->FspsConfig.PchPmSlpS0VmRuntimeControl =3D > (UINT8)PmConfig->SlpS0VmRuntimeControl; > + FspsUpd->FspsConfig.PchPmSlpS0Vm070VSupport =3D > (UINT8)PmConfig->SlpS0Vm070VSupport; > + FspsUpd->FspsConfig.PchPmSlpS0Vm075VSupport =3D > (UINT8)PmConfig->SlpS0Vm075VSupport; > + FspsUpd->FspsConfig.SlpS0Override =3D > (UINT8)PmConfig->SlpS0Override; > + FspsUpd->FspsConfig.SlpS0DisQForDebug =3D > (UINT8)PmConfig->SlpS0DisQForDebug; > + FspsUpd->FspsConfig.PmcDbgMsgEn =3D > (UINT8)PmConfig->PmcDbgMsgEn; > + FspsUpd->FspsConfig.PsOnEnable =3D > (UINT8)PmConfig->PsOnEnable; > + FspsUpd->FspsConfig.PmcCpuC10GatePinEnable =3D > (UINT8)PmConfig->CpuC10GatePinEnable; > + FspsUpd->FspsConfig.PmcModPhySusPgEnable =3D > (UINT8)PmConfig->ModPhySusPgEnable; > + FspsUpd->FspsConfig.SlpS0WithGbeSupport =3D > (UINT8)PmConfig->SlpS0WithGbeSupport; > + // > + // Update Pch Serial IRQ policies > + // > + FspsUpd->FspsConfig.PchSirqEnable =3D > (UINT8)PchSerialIrqConfig->SirqEnable; > + FspsUpd->FspsConfig.PchSirqMode =3D > (UINT8)PchSerialIrqConfig->SirqMode; > + FspsUpd->FspsConfig.PchStartFramePulse =3D > (UINT8)PchSerialIrqConfig->StartFramePulse; > + // > + // Update Pch Thermal policies > + // > + FspsUpd->FspsConfig.PchTsmicLock =3D > (UINT8)PchThermalConfig->TsmicLock; > + FspsUpd->FspsConfig.PchHotEnable =3D > (UINT8)PchThermalConfig->PchHotEnable; > + > + FspsUpd->FspsConfig.PchT0Level =3D > (UINT16)PchThermalConfig->TTLevels.T0Level; > + FspsUpd->FspsConfig.PchT1Level =3D > (UINT16)PchThermalConfig->TTLevels.T1Level; > + FspsUpd->FspsConfig.PchT2Level =3D > (UINT16)PchThermalConfig->TTLevels.T2Level; > + FspsUpd->FspsConfig.PchTTEnable =3D > (UINT8)PchThermalConfig->TTLevels.TTEnable; > + FspsUpd->FspsConfig.PchTTState13Enable =3D > (UINT8)PchThermalConfig->TTLevels.TTState13Enable; > + FspsUpd->FspsConfig.PchTTLock =3D > (UINT8)PchThermalConfig->TTLevels.TTLock; > + FspsUpd->FspsConfig.TTSuggestedSetting =3D > (UINT8)PchThermalConfig->TTLevels.SuggestedSetting; > + FspsUpd->FspsConfig.TTCrossThrottling =3D > (UINT8)PchThermalConfig->TTLevels.PchCrossThrottling; > + > + FspsUpd->FspsConfig.PchDmiTsawEn =3D > (UINT8)PchThermalConfig->DmiHaAWC.DmiTsawEn; > + FspsUpd->FspsConfig.DmiSuggestedSetting =3D > (UINT8)PchThermalConfig->DmiHaAWC.SuggestedSetting; > + FspsUpd->FspsConfig.DmiTS0TW =3D > (UINT8)PchThermalConfig->DmiHaAWC.TS0TW; > + FspsUpd->FspsConfig.DmiTS1TW =3D > (UINT8)PchThermalConfig->DmiHaAWC.TS1TW; > + FspsUpd->FspsConfig.DmiTS2TW =3D > (UINT8)PchThermalConfig->DmiHaAWC.TS2TW; > + FspsUpd->FspsConfig.DmiTS3TW =3D > (UINT8)PchThermalConfig->DmiHaAWC.TS3TW; > + > + FspsUpd->FspsConfig.PchMemoryThrottlingEnable =3D > (UINT8)PchThermalConfig->MemoryThrottling.Enable; > + FspsUpd->FspsConfig.PchMemoryPmsyncEnable[0] =3D > (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].PmsyncEn > able; > + FspsUpd->FspsConfig.PchMemoryPmsyncEnable[1] =3D > (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].PmsyncEn > able; > + FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[0] =3D > (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].C0Transm > itEnable; > + FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[1] =3D > (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].C0Transm > itEnable; > + FspsUpd->FspsConfig.PchMemoryPinSelection[0] =3D > (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].PinSelecti > on; > + FspsUpd->FspsConfig.PchMemoryPinSelection[1] =3D > (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].PinSelecti > on; > + > + FspsUpd->FspsConfig.PchTemperatureHotLevel =3D > (UINT16)PchThermalConfig->PchHotLevel; > + > + // > + // Update Pch CNVi policies > + // > + FspsUpd->FspsConfig.PchCnviMode =3D (UINT8)CnviConfig->Mode; > + FspsUpd->FspsConfig.PchCnviMfUart1Type =3D > (UINT8)CnviConfig->MfUart1Type; > + > + // > + // Update Pch HSIO policies > + // > + FspsUpd->FspsConfig.ChipsetInitBinPtr =3D HsioConfig->ChipsetInitBinPt= r; > + FspsUpd->FspsConfig.ChipsetInitBinLen =3D HsioConfig->ChipsetInitBinLe= n; > + > + // > + // Update Pch Espi policies > + // > + FspsUpd->FspsConfig.PchEspiLgmrEnable =3D > (UINT8)EspiConfig->LgmrEnable; > + > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspPolicyInitLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspPolicyInitLib.c > new file mode 100644 > index 0000000000..ce34325781 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspPolicyInitLib.c > @@ -0,0 +1,223 @@ > +/** @file > + Instance of Fsp Policy Initialization Library. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > + > +VOID > +EFIAPI > +FspPolicyInitPreMem( > + IN FSPM_UPD *FspmUpdDataPtr > +); > + > +VOID * > +EFIAPI > +SiliconPolicyInitPreMem( > + IN OUT VOID *FspmUpd > +) > +{ > + FspPolicyInitPreMem((FSPM_UPD *)FspmUpd); > + return FspmUpd; > +} > + > +RETURN_STATUS > +EFIAPI > +SiliconPolicyDonePreMem( > + IN VOID *FspmUpd > +) > +{ > + EFI_STATUS Status; > + > + Status =3D SpiServiceInit(); > + ASSERT_EFI_ERROR(Status); > + > + return RETURN_SUCCESS; > +} > + > +/** > + Performs FSP PEI Policy Pre-memory initialization. > + > + @param[in] FspmUpdDataPtr Pointer to FSPM UPD data. > +**/ > +VOID > +EFIAPI > +FspPolicyInitPreMem ( > + IN FSPM_UPD *FspmUpdDataPtr > + ) > +{ > + EFI_STATUS Status; > + > + // > + // SI Pei Fsp Policy Initialization > + // > + Status =3D PeiFspSiPolicyInitPreMem (FspmUpdDataPtr); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "ERROR - SI Pei Fsp Policy in Pre-Memory > Initialization fail, Status =3D %r\n", Status)); > + } > + > + // > + // PCH Pei Fsp Policy Initialization > + // > + Status =3D PeiFspPchPolicyInitPreMem (FspmUpdDataPtr); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy in Pre-Memory > Initialization fail, Status =3D %r\n", Status)); > + } > + > + // > + // Cpu Pei Fsp Policy Initialization > + // > + Status =3D PeiFspCpuPolicyInitPreMem (FspmUpdDataPtr); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy in Pre-Memory > Initialization fail, Status =3D %r\n", Status)); > + } > + > + // > + // Security Pei Fsp Policy Initialization > + // > + Status =3D PeiFspSecurityPolicyInitPreMem (FspmUpdDataPtr); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy in Pre-Memory > Initialization fail, Status =3D %r\n", Status)); > + } > + > + // > + // ME Pei Fsp Policy Initialization > + // > + Status =3D PeiFspMePolicyInitPreMem (FspmUpdDataPtr); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy in Pre-Memory > Initialization fail, Status =3D %r\n", Status)); > + } > + > + // > + // SystemAgent Pei Fsp Policy Initialization > + // > + Status =3D PeiFspSaPolicyInitPreMem (FspmUpdDataPtr); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy in > Pre-Memory Initialization fail, Status =3D %r\n", Status)); > + } > + > + // > + // Other Upd Initialization > + // > + Status =3D PeiFspMiscUpdInitPreMem (FspmUpdDataPtr); > + > +} > + > +/** > + Performs FSP PEI Policy initialization. > + > + @param[in][out] FspsUpd Pointer UPD data region > + > +**/ > +VOID > +EFIAPI > +FspPolicyInit ( > + IN OUT FSPS_UPD *FspsUpd > + ) > +{ > + EFI_STATUS Status; > + > + // > + // SI Pei Fsp Policy Initialization > + // > + Status =3D PeiFspSiPolicyInit (FspsUpd); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "ERROR - SI Pei Fsp Policy iInitialization fail= , > Status =3D %r\n", Status)); > + } > + > + // > + // PCH Pei Fsp Policy Initialization > + // > + Status =3D PeiFspPchPolicyInit (FspsUpd); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy iInitialization fai= l, > Status =3D %r\n", Status)); > + } > + > + // > + // ME Pei Fsp Policy Initialization > + // > + Status =3D PeiFspMePolicyInit (FspsUpd); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy Initialization fail, > Status =3D %r\n", Status)); > + } > + > + // > + // SystemAgent Pei Fsp Policy Initialization > + // > + Status =3D PeiFspSaPolicyInit (FspsUpd); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy > Initialization fail, Status =3D %r\n", Status)); > + } > + > + // > + // Cpu Pei Fsp Policy Initialization > + // > + Status =3D PeiFspCpuPolicyInit (FspsUpd); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy Initialization fail= , > Status =3D %r\n", Status)); > + } > + > + // > + // Security Pei Fsp Policy Initialization > + // > + Status =3D PeiFspSecurityPolicyInit(FspsUpd); > + if (EFI_ERROR(Status)) { > + DEBUG((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy Initialization = fail, > Status =3D %r\n", Status)); > + } > + > +} > + > +/** > +Performs silicon post-mem policy initialization. > + > +The meaning of Policy is defined by silicon code. > +It could be the raw data, a handle, a PPI, etc. > + > +The returned data must be used as input data for > SiliconPolicyDonePostMem(), > +and SiliconPolicyUpdateLib.SiliconPolicyUpdatePostMem(). > + > +1) In FSP path, the input Policy should be FspsUpd. > +Value of FspsUpd has been initialized by FSP binary default value. > +Only a subset of FspsUpd needs to be updated for different silicon sku. > +The return data is same FspsUpd. > + > +2) In non-FSP path, the input policy could be NULL. > +The return data is the initialized policy. > + > +@param[in, out] Policy Pointer to policy. > + > +@return the initialized policy. > +**/ > +VOID * > +EFIAPI > +SiliconPolicyInitPostMem( > + IN OUT VOID *FspsUpd > +) > +{ > + FspPolicyInit((FSPS_UPD *)FspsUpd); > + return FspsUpd; > +} > + > +/* > +The silicon post-mem policy is finalized. > +Silicon code can do initialization based upon the policy data. > + > +The input Policy must be returned by SiliconPolicyInitPostMem(). > + > +@param[in] Policy Pointer to policy. > + > +@retval EFI_SUCCESS The policy is handled consumed by silicon code. > +*/ > +EFI_STATUS > +EFIAPI > +SiliconPolicyDonePostMem( > + IN OUT VOID *FspsUpd > +) > +{ > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspSaPolicyInitLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspSaPolicyInitLib.c > new file mode 100644 > index 0000000000..0bfc379386 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspSaPolicyInitLib.c > @@ -0,0 +1,848 @@ > +/** @file > + Implementation of Fsp SA Policy Initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define MAX_SPD_PAGE_COUNT (2) > +#define MAX_SPD_PAGE_SIZE (256) > +#define MAX_SPD_SIZE (MAX_SPD_PAGE_SIZE * > MAX_SPD_PAGE_COUNT) > +#define SPD_PAGE_ADDRESS_0 (0x6C) > +#define SPD_PAGE_ADDRESS_1 (0x6E) > +#define SPD_DDR3_SDRAM_TYPE_OFFSET (0x02) > +#define SPD_DDR3_SDRAM_TYPE_NUMBER (0x0B) > +#define SPD_DDR4_SDRAM_TYPE_NUMBER (0x0C) > +#define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0xF1) > +#define SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER (0x0F) > +#define XMP_ID_STRING (0x4A0C) > +#define SPD3_MANUF_START (117) > +#define SPD3_MANUF_END (127) > +#define SPD4_MANUF_START (320) > +#define SPD4_MANUF_END (328) > +#define SPDLP_MANUF_START (320) > +#define SPDLP_MANUF_END (328) > + > +GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE > mSpdDdr3Table[] =3D { > + { 0, 1, (1 << SpdCold),}, > + { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, > + { 3, 41, (1 << SpdCold),}, > + { 60, 63, (1 << SpdCold),}, > + { SPD3_MANUF_START, SPD3_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, > + { 128, 145, (1 << SpdCold),}, > + { 39, 59, (1 << SpdCold),}, > + { 64, 125, (1 << SpdCold),}, > + { 176, 179, (1 << SpdCold),}, > + { 180, 184, (1 << SpdCold),}, > + { 185, 215, (1 << SpdCold),}, > + { 220, 250, (1 << SpdCold),}, > +}; > + > +GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE > mSpdDdr4Table[] =3D { > + { 0, 1, (1 << SpdCold),}, > + { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, > + { 3, 40, (1 << SpdCold),}, > + { 117, 131, (1 << SpdCold),}, > + { SPD4_MANUF_START, SPD4_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, > + { 329, 348, (1 << SpdCold),}, > + { 32, 119, (1 << SpdCold),}, > + { 126, 255, (1 << SpdCold),}, > + { 349, 383, (1 << SpdCold),}, > + { 384, 387, (1 << SpdCold),}, > + { 388, 389, (1 << SpdCold),}, > + { 393, 431, (1 << SpdCold),}, > + { 440, 478, (1 << SpdCold),}, > +}; > + > +GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE > mSpdLpddrTable[] =3D { > + { 0, 1, (1 << SpdCold),}, > + { 2, 2, (1 << SpdCold) | (1 << SpdFast),= }, > + { 3, 32, (1 << SpdCold),}, > + { 120, 130, (1 << SpdCold),}, > + { SPDLP_MANUF_START, SPDLP_MANUF_END, (1 << SpdCold) | (1 << > SpdFast),}, > + { 329, 348, (1 << SpdCold),}, > + { 31, 121, (1 << SpdCold),}, > + { 126, 255, (1 << SpdCold),}, > + { 349, 383, (1 << SpdCold),}, > + { 384, 387, (1 << SpdCold),}, > + { 388, 389, (1 << SpdCold),}, > + { 393, 431, (1 << SpdCold),}, > + { 440, 478, (1 << SpdCold),}, > +}; > + > + > +/** > + Update Spd Data > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + @param[in] MemConfigNoCrc Pointer to Mem Config No Crc. > + @param[in] MiscPeiPreMemConfig Pointer to Misc Config. > + > + @retval EFI_SUCCESS The function completes successful= ly > + @retval Other The function fail > +**/ > +VOID > +EFIAPI > +InternalUpdateSpdInfo ( > + IN OUT FSPM_UPD *FspmUpd, > + IN MEMORY_CONFIG_NO_CRC *MemConfigNoCrc, > + IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig > + ) > +{ > + > + DEBUG ((DEBUG_INFO, "Updating UPD:Memory Spd Pointers...\n")); > + if ((FspmUpd =3D=3D NULL) || (MemConfigNoCrc =3D=3D NULL) || > (MiscPeiPreMemConfig =3D=3D NULL)) { > + DEBUG ((DEBUG_ERROR, "EFI_INVALID_PARAMETER.\n")); > + DEBUG ((DEBUG_ERROR, "Fail to access SPD from SiPolicyPpi\n")); > + return; > + } > + > + // > + // Update MemorySpdPtrXX if SpdAddressTable is zero > + // > + if (MiscPeiPreMemConfig->SpdAddressTable[0] =3D=3D 0x0) { > + FspmUpd->FspmConfig.MemorySpdPtr00 =3D > (UINT32)MemConfigNoCrc->SpdData->SpdData; > + } else { > + FspmUpd->FspmConfig.SpdAddressTable[0] =3D > MiscPeiPreMemConfig->SpdAddressTable[0]; > + } > + > + if (MiscPeiPreMemConfig->SpdAddressTable[1] =3D=3D 0x0) { > + FspmUpd->FspmConfig.MemorySpdPtr01 =3D > (UINT32)MemConfigNoCrc->SpdData->SpdData + (1 * > SA_MC_MAX_SPD_SIZE); > + } else { > + FspmUpd->FspmConfig.SpdAddressTable[1] =3D > MiscPeiPreMemConfig->SpdAddressTable[1]; > + } > + > + if (MiscPeiPreMemConfig->SpdAddressTable[2] =3D=3D 0x0) { > + FspmUpd->FspmConfig.MemorySpdPtr10 =3D > (UINT32)MemConfigNoCrc->SpdData->SpdData + (2 * > SA_MC_MAX_SPD_SIZE); > + } else { > + FspmUpd->FspmConfig.SpdAddressTable[2] =3D > MiscPeiPreMemConfig->SpdAddressTable[2]; > + } > + > + if (MiscPeiPreMemConfig->SpdAddressTable[3] =3D=3D 0x0) { > + FspmUpd->FspmConfig.MemorySpdPtr11 =3D > (UINT32)MemConfigNoCrc->SpdData->SpdData + (3 * > SA_MC_MAX_SPD_SIZE); > + } else { > + FspmUpd->FspmConfig.SpdAddressTable[3] =3D > MiscPeiPreMemConfig->SpdAddressTable[3]; > + } > + > + DEBUG ((DEBUG_INFO, "UPD:MemorySpdPtr Updated\n")); > +} > + > +/** > + PeiGetSectionFromFv finds the file in FV and gets file Address and Siz= e > + > + @param[in] NameGuid - File GUID > + @param[out] Address - Pointer to the File Address > + @param[out] Size - Pointer to File Size > + > + @retval EFI_SUCCESS Successfull in reading the section = from FV > +**/ > +EFI_STATUS > +EFIAPI > +PeiGetSectionFromFv ( > + IN CONST EFI_GUID NameGuid, > + OUT VOID **Address, > + OUT UINT32 *Size > + ) > +{ > + EFI_STATUS Status; > + EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi; > + EFI_FV_FILE_INFO FvFileInfo; > + PEI_CORE_INSTANCE *PrivateData; > + UINTN CurrentFv; > + PEI_CORE_FV_HANDLE *CoreFvHandle; > + EFI_PEI_FILE_HANDLE VbtFileHandle; > + EFI_GUID *VbtGuid; > + EFI_COMMON_SECTION_HEADER *Section; > + CONST EFI_PEI_SERVICES **PeiServices; > + > + PeiServices =3D GetPeiServicesTablePointer (); > + > + PrivateData =3D PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices); > + > + Status =3D PeiServicesLocatePpi ( > + &gEfiFirmwareFileSystem2Guid, > + 0, > + NULL, > + (VOID **) &FvPpi > + ); > + ASSERT_EFI_ERROR (Status); > + > + CurrentFv =3D PrivateData->CurrentPeimFvCount; > + CoreFvHandle =3D &(PrivateData->Fv[CurrentFv]); > + > + Status =3D FvPpi->FindFileByName (FvPpi, &NameGuid, > &CoreFvHandle->FvHandle, &VbtFileHandle); > + if (!EFI_ERROR(Status) && VbtFileHandle !=3D NULL) { > + > + DEBUG ((DEBUG_INFO, "Find SectionByType \n")); > + > + Status =3D FvPpi->FindSectionByType (FvPpi, EFI_SECTION_RAW, > VbtFileHandle, (VOID **) &VbtGuid); > + if (!EFI_ERROR (Status)) { > + > + DEBUG ((DEBUG_INFO, "GetFileInfo \n")); > + > + Status =3D FvPpi->GetFileInfo (FvPpi, VbtFileHandle, &FvFileInfo); > + Section =3D (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer; > + > + if (IS_SECTION2 (Section)) { > + ASSERT (SECTION2_SIZE (Section) > 0x00FFFFFF); > + *Size =3D SECTION2_SIZE (Section) - sizeof > (EFI_COMMON_SECTION_HEADER2); > + *Address =3D ((UINT8 *)Section + sizeof > (EFI_COMMON_SECTION_HEADER2)); > + } else { > + *Size =3D SECTION_SIZE (Section) - sizeof > (EFI_COMMON_SECTION_HEADER); > + *Address =3D ((UINT8 *)Section + sizeof > (EFI_COMMON_SECTION_HEADER)); > + } > + } > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + Performs FSP SA PEI Policy initialization in pre-memory. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSaPolicyInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ) > +{ > + EFI_STATUS Status; > + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; > + MEMORY_CONFIGURATION *MemConfig; > + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; > + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > + PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig; > + SWITCHABLE_GRAPHICS_CONFIG *SgGpioData; > + GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig; > + OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig; > + VTD_CONFIG *Vtd; > + IPU_PREMEM_CONFIG *IpuPreMemPolicy; > + UINT8 Index; > + VOID *Buffer; > + > + SiPreMemPolicyPpi =3D NULL; > + MiscPeiPreMemConfig =3D NULL; > + MemConfig =3D NULL; > + MemConfigNoCrc =3D NULL; > + PciePeiPreMemConfig =3D NULL; > + SgGpioData =3D NULL; > + GtPreMemConfig =3D NULL; > + OcPreMemConfig =3D NULL; > + Vtd =3D NULL; > + IpuPreMemPolicy =3D NULL; > + > + > + > + // > + // Locate SiPreMemPolicyPpi > + // > + Status =3D PeiServicesLocatePpi( > + &gSiPreMemPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPreMemPolicyPpi > + ); > + ASSERT_EFI_ERROR (Status); > + if ((Status =3D=3D EFI_SUCCESS) && (SiPreMemPolicyPpi !=3D NULL)) { > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gMemoryConfigGuid, (VOID *) &MemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gGraphicsPeiPreMemConfigGuid, (VOID *) &GtPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gSaPciePeiPreMemConfigGuid, (VOID *) &PciePeiPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gSwitchableGraphicsConfigGuid, (VOID *) &SgGpioData); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gVtdConfigGu= id, > (VOID *) &Vtd); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gIpuPreMemConfigGuid, (VOID *) &IpuPreMemPolicy); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gSaOverclockingPreMemConfigGuid, (VOID *) &OcPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + > + } > + > + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling > Settings...\n")); > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); > + if (Buffer) { > + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12); > + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) > Buffer + 12, 12); > + } > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); > + if (Buffer) { > + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, > 8); > + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, > (UINT8*) Buffer + 8, 8); > + } > + > + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & > Rcomp Target Settings...\n")); > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); > + if (Buffer) { > + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6); > + } > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); > + if (Buffer) { > + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10); > + } > + > + // > + // Update UPD:MemorySpdPtrXX and SpdAddressTable > + // > + InternalUpdateSpdInfo (FspmUpd, MemConfigNoCrc, > MiscPeiPreMemConfig); > + > + // > + // Update UPD:MemorySpdDataLen > + // > + FspmUpd->FspmConfig.MemorySpdDataLen =3D SA_MC_MAX_SPD_SIZE; > + > + if (MemConfigNoCrc !=3D NULL) { > + // > + // Update UPD:PlatformMemorySize > + // > + // > + // @todo: This value is used since #183932. Revisit. > + // > + FspmUpd->FspmConfig.PlatformMemorySize =3D > MemConfigNoCrc->PlatformMemorySize; > + FspmUpd->FspmConfig.CleanMemory =3D (UINT8) > MemConfigNoCrc->CleanMemory; > + FspmUpd->FspmConfig.MemTestOnWarmBoot =3D (UINT8) > MemConfigNoCrc->MemTestOnWarmBoot; > + } > + > + if (MemConfig !=3D NULL) { > + // > + // Update UPD:DqPinsInterleaved > + // > + FspmUpd->FspmConfig.DqPinsInterleaved =3D (UINT8) > MemConfig->DqPinsInterleaved; > + > + FspmUpd->FspmConfig.ProbelessTrace =3D > MemConfig->ProbelessTrace; > + FspmUpd->FspmConfig.GdxcIotSize =3D MemConfig->GdxcIotSize= ; > + FspmUpd->FspmConfig.GdxcMotSize =3D > MemConfig->GdxcMotSize; > + FspmUpd->FspmConfig.DualDimmPerChannelBoardType =3D(UINT8) > MemConfig->DualDimmPerChannelBoardType; > + FspmUpd->FspmConfig.Ddr4MixedUDimm2DpcLimit =3D(UINT8) > MemConfig->Ddr4MixedUDimm2DpcLimit; > + // > + // Update UPD:CaVrefConfig > + // > + FspmUpd->FspmConfig.CaVrefConfig =3D MemConfig->CaVrefConfi= g; > + FspmUpd->FspmConfig.SaGv =3D MemConfig->SaGv; > + FspmUpd->FspmConfig.FreqSaGvLow =3D > MemConfig->FreqSaGvLow; > + FspmUpd->FspmConfig.FreqSaGvMid =3D > MemConfig->FreqSaGvMid; > + FspmUpd->FspmConfig.RMT =3D (UINT8) MemConfig->RMT= ; > + FspmUpd->FspmConfig.DdrFreqLimit =3D MemConfig->DdrFreqLimi= t; > + > + FspmUpd->FspmConfig.SpdProfileSelected =3D > MemConfig->SpdProfileSelected; > + FspmUpd->FspmConfig.VddVoltage =3D MemConfig->VddVoltage; > + FspmUpd->FspmConfig.RefClk =3D MemConfig->RefClk; > + FspmUpd->FspmConfig.Ratio =3D MemConfig->Ratio; > + FspmUpd->FspmConfig.OddRatioMode =3D (UINT8) > MemConfig->OddRatioMode; > + FspmUpd->FspmConfig.tCL =3D (UINT8) MemConfig->tCL= ; > + FspmUpd->FspmConfig.tCWL =3D (UINT8) MemConfig->tCW= L; > + FspmUpd->FspmConfig.tFAW =3D MemConfig->tFAW; > + FspmUpd->FspmConfig.tRAS =3D MemConfig->tRAS; > + FspmUpd->FspmConfig.tRCDtRP =3D (UINT8) > MemConfig->tRCDtRP; > + FspmUpd->FspmConfig.tREFI =3D MemConfig->tREFI; > + FspmUpd->FspmConfig.tRFC =3D MemConfig->tRFC; > + FspmUpd->FspmConfig.tRRD =3D (UINT8) MemConfig->tRR= D; > + FspmUpd->FspmConfig.tRTP =3D (UINT8) MemConfig->tRT= P; > + FspmUpd->FspmConfig.tWR =3D (UINT8) MemConfig->tWR= ; > + FspmUpd->FspmConfig.tWTR =3D (UINT8) MemConfig->tWT= R; > + FspmUpd->FspmConfig.NModeSupport =3D > MemConfig->NModeSupport; > + FspmUpd->FspmConfig.DllBwEn0 =3D MemConfig->DllBwEn0; > + FspmUpd->FspmConfig.DllBwEn1 =3D MemConfig->DllBwEn1; > + FspmUpd->FspmConfig.DllBwEn2 =3D MemConfig->DllBwEn2; > + FspmUpd->FspmConfig.DllBwEn3 =3D MemConfig->DllBwEn3; > + FspmUpd->FspmConfig.MrcSafeConfig =3D (UINT8) > MemConfig->MrcSafeConfig; // Typecasting as MrcSafeConfig is of UINT32 in > MEMORY_CONFIGURATION > + FspmUpd->FspmConfig.LpDdrDqDqsReTraining =3D (UINT8) > MemConfig->Lp4DqsOscEn; > + FspmUpd->FspmConfig.RmtPerTask =3D (UINT8) > MemConfig->RmtPerTask; > + FspmUpd->FspmConfig.TrainTrace =3D (UINT8) > MemConfig->TrainTrace; > + FspmUpd->FspmConfig.ScramblerSupport =3D (UINT8) > MemConfig->ScramblerSupport; > + FspmUpd->FspmConfig.SafeMode =3D (UINT8) > MemConfig->SafeMode; > + > + // > + // Update UPD:SmramMask and DisableDimmChannel > + // > + FspmUpd->FspmConfig.SmramMask =3D > MemConfig->SmramMask; > + FspmUpd->FspmConfig.DisableDimmChannel0 =3D > MemConfig->DisableDimmChannel[0]; > + FspmUpd->FspmConfig.DisableDimmChannel1 =3D > MemConfig->DisableDimmChannel[1]; > + FspmUpd->FspmConfig.HobBufferSize =3D > MemConfig->HobBufferSize; > + > + FspmUpd->FspmConfig.ECT =3D (UINT8) MemConfig->E= CT; > + FspmUpd->FspmConfig.SOT =3D (UINT8) MemConfig->S= OT; > + FspmUpd->FspmConfig.ERDMPRTC2D =3D (UINT8) > MemConfig->ERDMPRTC2D; > + FspmUpd->FspmConfig.RDMPRT =3D (UINT8) > MemConfig->RDMPRT; > + FspmUpd->FspmConfig.RCVET =3D (UINT8) > MemConfig->RCVET; > + FspmUpd->FspmConfig.JWRL =3D (UINT8) MemConfig->J= WRL; > + FspmUpd->FspmConfig.EWRTC2D =3D (UINT8) > MemConfig->EWRTC2D; > + FspmUpd->FspmConfig.ERDTC2D =3D (UINT8) > MemConfig->ERDTC2D; > + FspmUpd->FspmConfig.WRTC1D =3D (UINT8) > MemConfig->WRTC1D; > + FspmUpd->FspmConfig.WRVC1D =3D (UINT8) > MemConfig->WRVC1D; > + FspmUpd->FspmConfig.RDTC1D =3D (UINT8) > MemConfig->RDTC1D; > + FspmUpd->FspmConfig.DIMMODTT =3D (UINT8) > MemConfig->DIMMODTT; > + FspmUpd->FspmConfig.DIMMRONT =3D (UINT8) > MemConfig->DIMMRONT; > + FspmUpd->FspmConfig.WRSRT =3D (UINT8) > MemConfig->WRSRT; > + FspmUpd->FspmConfig.RDODTT =3D (UINT8) > MemConfig->RDODTT; > + FspmUpd->FspmConfig.RDEQT =3D (UINT8) > MemConfig->RDEQT; > + FspmUpd->FspmConfig.RDAPT =3D (UINT8) > MemConfig->RDAPT; > + FspmUpd->FspmConfig.WRTC2D =3D (UINT8) > MemConfig->WRTC2D; > + FspmUpd->FspmConfig.RDTC2D =3D (UINT8) > MemConfig->RDTC2D; > + FspmUpd->FspmConfig.WRVC2D =3D (UINT8) > MemConfig->WRVC2D; > + FspmUpd->FspmConfig.RDVC2D =3D (UINT8) > MemConfig->RDVC2D; > + FspmUpd->FspmConfig.CMDVC =3D (UINT8) > MemConfig->CMDVC; > + FspmUpd->FspmConfig.LCT =3D (UINT8) MemConfig->L= CT; > + FspmUpd->FspmConfig.RTL =3D (UINT8) MemConfig->R= TL; > + FspmUpd->FspmConfig.TAT =3D (UINT8) MemConfig->T= AT; > + FspmUpd->FspmConfig.RCVENC1D =3D (UINT8) > MemConfig->RCVENC1D; > + FspmUpd->FspmConfig.RMT =3D (UINT8) MemConfig->R= MT; > + FspmUpd->FspmConfig.MEMTST =3D (UINT8) > MemConfig->MEMTST; > + FspmUpd->FspmConfig.ALIASCHK =3D (UINT8) > MemConfig->ALIASCHK; > + FspmUpd->FspmConfig.RMC =3D (UINT8) MemConfig->R= MC; > + FspmUpd->FspmConfig.WRDSUDT =3D (UINT8) > MemConfig->WRDSUDT; > + FspmUpd->FspmConfig.EnBER =3D (UINT8) > MemConfig->EnBER; > + FspmUpd->FspmConfig.EccSupport =3D (UINT8) > MemConfig->EccSupport; > + FspmUpd->FspmConfig.RemapEnable =3D (UINT8) > MemConfig->RemapEnable; > + FspmUpd->FspmConfig.ScramblerSupport =3D (UINT8) > MemConfig->ScramblerSupport; > + FspmUpd->FspmConfig.MrcFastBoot =3D (UINT8) > MemConfig->MrcFastBoot; > + FspmUpd->FspmConfig.RankInterleave =3D (UINT8) > MemConfig->RankInterleave; > + FspmUpd->FspmConfig.EnhancedInterleave =3D (UINT8) > MemConfig->EnhancedInterleave; > + FspmUpd->FspmConfig.MemoryTrace =3D (UINT8) > MemConfig->MemoryTrace; > + FspmUpd->FspmConfig.ChHashEnable =3D (UINT8) > MemConfig->ChHashEnable; > + FspmUpd->FspmConfig.EnableExtts =3D (UINT8) > MemConfig->EnableExtts; > + FspmUpd->FspmConfig.EnableCltm =3D (UINT8) > MemConfig->EnableCltm; > + FspmUpd->FspmConfig.EnableOltm =3D (UINT8) > MemConfig->EnableOltm; > + FspmUpd->FspmConfig.EnablePwrDn =3D (UINT8) > MemConfig->EnablePwrDn; > + FspmUpd->FspmConfig.EnablePwrDnLpddr =3D (UINT8) > MemConfig->EnablePwrDnLpddr; > + FspmUpd->FspmConfig.UserPowerWeightsEn =3D (UINT8) > MemConfig->UserPowerWeightsEn; > + FspmUpd->FspmConfig.RaplLim2Lock =3D (UINT8) > MemConfig->RaplLim2Lock; > + FspmUpd->FspmConfig.RaplLim2Ena =3D (UINT8) > MemConfig->RaplLim2Ena; > + FspmUpd->FspmConfig.RaplLim1Ena =3D (UINT8) > MemConfig->RaplLim1Ena; > + FspmUpd->FspmConfig.SrefCfgEna =3D (UINT8) > MemConfig->SrefCfgEna; > + FspmUpd->FspmConfig.ThrtCkeMinDefeatLpddr =3D (UINT8) > MemConfig->ThrtCkeMinDefeatLpddr; > + FspmUpd->FspmConfig.ThrtCkeMinDefeat =3D (UINT8) > MemConfig->ThrtCkeMinDefeat; > + FspmUpd->FspmConfig.RhPrevention =3D (UINT8) > MemConfig->RhPrevention; > + FspmUpd->FspmConfig.ExitOnFailure =3D (UINT8) > MemConfig->ExitOnFailure; > + FspmUpd->FspmConfig.DdrThermalSensor =3D (UINT8) > MemConfig->DdrThermalSensor; > + FspmUpd->FspmConfig.Ddr4DdpSharedClock =3D (UINT8) > MemConfig->Ddr4DdpSharedClock; > + FspmUpd->FspmConfig.Ddr4DdpSharedZq =3D (UINT8) > MemConfig->SharedZqPin; > + FspmUpd->FspmConfig.BClkFrequency =3D > MemConfig->BClkFrequency; > + FspmUpd->FspmConfig.ChHashInterleaveBit =3D > MemConfig->ChHashInterleaveBit; > + FspmUpd->FspmConfig.ChHashMask =3D > MemConfig->ChHashMask; > + FspmUpd->FspmConfig.EnergyScaleFact =3D > MemConfig->EnergyScaleFact; > + FspmUpd->FspmConfig.Idd3n =3D MemConfig->Idd3n; > + FspmUpd->FspmConfig.Idd3p =3D MemConfig->Idd3p; > + FspmUpd->FspmConfig.CMDSR =3D (UINT8) > MemConfig->CMDSR; > + FspmUpd->FspmConfig.CMDDSEQ =3D (UINT8) > MemConfig->CMDDSEQ; > + FspmUpd->FspmConfig.CMDNORM =3D (UINT8) > MemConfig->CMDNORM; > + FspmUpd->FspmConfig.EWRDSEQ =3D (UINT8) > MemConfig->EWRDSEQ; > + FspmUpd->FspmConfig.FreqSaGvLow =3D > MemConfig->FreqSaGvLow; > + FspmUpd->FspmConfig.RhActProbability =3D > MemConfig->RhActProbability; > + FspmUpd->FspmConfig.RaplLim2WindX =3D > MemConfig->RaplLim2WindX; > + FspmUpd->FspmConfig.RaplLim2WindY =3D > MemConfig->RaplLim2WindY; > + FspmUpd->FspmConfig.RaplLim1WindX =3D > MemConfig->RaplLim1WindX; > + FspmUpd->FspmConfig.RaplLim1WindY =3D > MemConfig->RaplLim1WindY; > + FspmUpd->FspmConfig.RaplLim2Pwr =3D > MemConfig->RaplLim2Pwr; > + FspmUpd->FspmConfig.RaplLim1Pwr =3D > MemConfig->RaplLim1Pwr; > + FspmUpd->FspmConfig.WarmThresholdCh0Dimm0 =3D > MemConfig->WarmThresholdCh0Dimm0; > + FspmUpd->FspmConfig.WarmThresholdCh0Dimm1 =3D > MemConfig->WarmThresholdCh0Dimm1; > + FspmUpd->FspmConfig.WarmThresholdCh1Dimm0 =3D > MemConfig->WarmThresholdCh1Dimm0; > + FspmUpd->FspmConfig.WarmThresholdCh1Dimm1 =3D > MemConfig->WarmThresholdCh1Dimm1; > + FspmUpd->FspmConfig.HotThresholdCh0Dimm0 =3D > MemConfig->HotThresholdCh0Dimm0; > + FspmUpd->FspmConfig.HotThresholdCh0Dimm1 =3D > MemConfig->HotThresholdCh0Dimm1; > + FspmUpd->FspmConfig.HotThresholdCh1Dimm0 =3D > MemConfig->HotThresholdCh1Dimm0; > + FspmUpd->FspmConfig.HotThresholdCh1Dimm1 =3D > MemConfig->HotThresholdCh1Dimm1; > + FspmUpd->FspmConfig.WarmBudgetCh0Dimm0 =3D > MemConfig->WarmBudgetCh0Dimm0; > + FspmUpd->FspmConfig.WarmBudgetCh0Dimm1 =3D > MemConfig->WarmBudgetCh0Dimm1; > + FspmUpd->FspmConfig.WarmBudgetCh1Dimm0 =3D > MemConfig->WarmBudgetCh1Dimm0; > + FspmUpd->FspmConfig.WarmBudgetCh1Dimm1 =3D > MemConfig->WarmBudgetCh1Dimm1; > + FspmUpd->FspmConfig.HotBudgetCh0Dimm0 =3D > MemConfig->HotBudgetCh0Dimm0; > + FspmUpd->FspmConfig.HotBudgetCh0Dimm1 =3D > MemConfig->HotBudgetCh0Dimm1; > + FspmUpd->FspmConfig.HotBudgetCh1Dimm0 =3D > MemConfig->HotBudgetCh1Dimm0; > + FspmUpd->FspmConfig.HotBudgetCh1Dimm1 =3D > MemConfig->HotBudgetCh1Dimm1; > + FspmUpd->FspmConfig.IdleEnergyCh0Dimm0 =3D > MemConfig->IdleEnergyCh0Dimm0; > + FspmUpd->FspmConfig.IdleEnergyCh0Dimm1 =3D > MemConfig->IdleEnergyCh0Dimm1; > + FspmUpd->FspmConfig.IdleEnergyCh1Dimm0 =3D > MemConfig->IdleEnergyCh1Dimm0; > + FspmUpd->FspmConfig.IdleEnergyCh1Dimm1 =3D > MemConfig->IdleEnergyCh1Dimm1; > + FspmUpd->FspmConfig.PdEnergyCh0Dimm0 =3D > MemConfig->PdEnergyCh0Dimm0; > + FspmUpd->FspmConfig.PdEnergyCh0Dimm1 =3D > MemConfig->PdEnergyCh0Dimm1; > + FspmUpd->FspmConfig.PdEnergyCh1Dimm0 =3D > MemConfig->PdEnergyCh1Dimm0; > + FspmUpd->FspmConfig.PdEnergyCh1Dimm1 =3D > MemConfig->PdEnergyCh1Dimm1; > + FspmUpd->FspmConfig.ActEnergyCh0Dimm0 =3D > MemConfig->ActEnergyCh0Dimm0; > + FspmUpd->FspmConfig.ActEnergyCh0Dimm1 =3D > MemConfig->ActEnergyCh0Dimm1; > + FspmUpd->FspmConfig.ActEnergyCh1Dimm0 =3D > MemConfig->ActEnergyCh1Dimm0; > + FspmUpd->FspmConfig.ActEnergyCh1Dimm1 =3D > MemConfig->ActEnergyCh1Dimm1; > + FspmUpd->FspmConfig.RdEnergyCh0Dimm0 =3D > MemConfig->RdEnergyCh0Dimm0; > + FspmUpd->FspmConfig.RdEnergyCh0Dimm1 =3D > MemConfig->RdEnergyCh0Dimm1; > + FspmUpd->FspmConfig.RdEnergyCh1Dimm0 =3D > MemConfig->RdEnergyCh1Dimm0; > + FspmUpd->FspmConfig.RdEnergyCh1Dimm1 =3D > MemConfig->RdEnergyCh1Dimm1; > + FspmUpd->FspmConfig.WrEnergyCh0Dimm0 =3D > MemConfig->WrEnergyCh0Dimm0; > + FspmUpd->FspmConfig.WrEnergyCh0Dimm1 =3D > MemConfig->WrEnergyCh0Dimm1; > + FspmUpd->FspmConfig.WrEnergyCh1Dimm0 =3D > MemConfig->WrEnergyCh1Dimm0; > + FspmUpd->FspmConfig.WrEnergyCh1Dimm1 =3D > MemConfig->WrEnergyCh1Dimm1; > + FspmUpd->FspmConfig.ThrtCkeMinTmr =3D > MemConfig->ThrtCkeMinTmr; > + FspmUpd->FspmConfig.CkeRankMapping =3D > MemConfig->CkeRankMapping; > + FspmUpd->FspmConfig.CaVrefConfig =3D > MemConfig->CaVrefConfig; > + FspmUpd->FspmConfig.RaplPwrFlCh1 =3D > MemConfig->RaplPwrFlCh1; > + FspmUpd->FspmConfig.RaplPwrFlCh0 =3D > MemConfig->RaplPwrFlCh0; > + FspmUpd->FspmConfig.EnCmdRate =3D > MemConfig->EnCmdRate; > + FspmUpd->FspmConfig.Refresh2X =3D MemConfig->Refresh2X= ; > + FspmUpd->FspmConfig.EpgEnable =3D MemConfig->EpgEnable= ; > + FspmUpd->FspmConfig.RhSolution =3D MemConfig->RhSolutio= n; > + FspmUpd->FspmConfig.UserThresholdEnable =3D > MemConfig->UserThresholdEnable; > + FspmUpd->FspmConfig.UserBudgetEnable =3D > MemConfig->UserBudgetEnable; > + FspmUpd->FspmConfig.TsodTcritMax =3D > MemConfig->TsodTcritMax; > + FspmUpd->FspmConfig.TsodEventMode =3D > MemConfig->TsodEventMode; > + FspmUpd->FspmConfig.TsodEventPolarity =3D > MemConfig->TsodEventPolarity; > + FspmUpd->FspmConfig.TsodCriticalEventOnly =3D > MemConfig->TsodCriticalEventOnly; > + FspmUpd->FspmConfig.TsodEventOutputControl =3D > MemConfig->TsodEventOutputControl; > + FspmUpd->FspmConfig.TsodAlarmwindowLockBit =3D > MemConfig->TsodAlarmwindowLockBit; > + FspmUpd->FspmConfig.TsodCriticaltripLockBit =3D > MemConfig->TsodCriticaltripLockBit; > + FspmUpd->FspmConfig.TsodShutdownMode =3D > MemConfig->TsodShutdownMode; > + FspmUpd->FspmConfig.TsodThigMax =3D > MemConfig->TsodThigMax; > + FspmUpd->FspmConfig.TsodManualEnable =3D > MemConfig->TsodManualEnable; > + FspmUpd->FspmConfig.IsvtIoPort =3D MemConfig->IsvtIoPor= t; > + FspmUpd->FspmConfig.ForceOltmOrRefresh2x =3D > MemConfig->ForceOltmOrRefresh2x; > + FspmUpd->FspmConfig.PwdwnIdleCounter =3D > MemConfig->PwdwnIdleCounter; > + FspmUpd->FspmConfig.CmdRanksTerminated =3D > MemConfig->CmdRanksTerminated; > + FspmUpd->FspmConfig.GdxcEnable =3D MemConfig->GdxcEnabl= e; > + FspmUpd->FspmConfig.RMTLoopCount =3D > MemConfig->RMTLoopCount; > + > + // DDR4 Memory Timings > + FspmUpd->FspmTestConfig.tRRD_L =3D (UINT8) MemConfig->tRRD_L; > + FspmUpd->FspmTestConfig.tRRD_S =3D (UINT8) MemConfig->tRRD_S; > + FspmUpd->FspmTestConfig.tWTR_L =3D (UINT8) MemConfig->tWTR_L; > + FspmUpd->FspmTestConfig.tWTR_S =3D (UINT8) MemConfig->tWTR_S; > + > + // TurnAround Timing > + // Read-to-Read > + FspmUpd->FspmTestConfig.tRd2RdSG =3D MemConfig->tRd2RdSG; > + FspmUpd->FspmTestConfig.tRd2RdDG =3D MemConfig->tRd2RdDG; > + FspmUpd->FspmTestConfig.tRd2RdDR =3D MemConfig->tRd2RdDR; > + FspmUpd->FspmTestConfig.tRd2RdDD =3D MemConfig->tRd2RdDD; > + // Write-to-Read > + FspmUpd->FspmTestConfig.tWr2RdSG =3D MemConfig->tWr2RdSG; > + FspmUpd->FspmTestConfig.tWr2RdDG =3D MemConfig->tWr2RdDG; > + FspmUpd->FspmTestConfig.tWr2RdDR =3D MemConfig->tWr2RdDR; > + FspmUpd->FspmTestConfig.tWr2RdDD =3D MemConfig->tWr2RdDD; > + // Write-to-Write > + FspmUpd->FspmTestConfig.tWr2WrSG =3D MemConfig->tWr2WrSG; > + FspmUpd->FspmTestConfig.tWr2WrDG =3D MemConfig->tWr2WrDG; > + FspmUpd->FspmTestConfig.tWr2WrDR =3D MemConfig->tWr2WrDR; > + FspmUpd->FspmTestConfig.tWr2WrDD =3D MemConfig->tWr2WrDD; > + // Read-to-Write > + FspmUpd->FspmTestConfig.tRd2WrSG =3D MemConfig->tRd2WrSG; > + FspmUpd->FspmTestConfig.tRd2WrDG =3D MemConfig->tRd2WrDG; > + FspmUpd->FspmTestConfig.tRd2WrDR =3D MemConfig->tRd2WrDR; > + FspmUpd->FspmTestConfig.tRd2WrDD =3D MemConfig->tRd2WrDD; > + } > + > + if (MiscPeiPreMemConfig !=3D NULL) { > + FspmUpd->FspmConfig.IedSize =3D > MiscPeiPreMemConfig->IedSize; > + FspmUpd->FspmConfig.UserBd =3D > MiscPeiPreMemConfig->UserBd; > + FspmUpd->FspmConfig.SgDelayAfterPwrEn =3D > MiscPeiPreMemConfig->SgDelayAfterPwrEn; > + FspmUpd->FspmConfig.SgDelayAfterHoldReset =3D > MiscPeiPreMemConfig->SgDelayAfterHoldReset; > + FspmUpd->FspmConfig.MmioSize =3D > MiscPeiPreMemConfig->MmioSize; > + FspmUpd->FspmConfig.MmioSizeAdjustment =3D > MiscPeiPreMemConfig->MmioSizeAdjustment; > + FspmUpd->FspmConfig.TsegSize =3D > MiscPeiPreMemConfig->TsegSize; > + > + FspmUpd->FspmTestConfig.SkipExtGfxScan =3D (UINT8) > MiscPeiPreMemConfig->SkipExtGfxScan; > + FspmUpd->FspmTestConfig.BdatEnable =3D (UINT8) > MiscPeiPreMemConfig->BdatEnable; > + FspmUpd->FspmTestConfig.BdatTestType =3D (UINT8) > MiscPeiPreMemConfig->BdatTestType; > + FspmUpd->FspmTestConfig.ScanExtGfxForLegacyOpRom =3D (UINT8) > MiscPeiPreMemConfig->ScanExtGfxForLegacyOpRom; > + FspmUpd->FspmTestConfig.LockPTMregs =3D (UINT8) > MiscPeiPreMemConfig->LockPTMregs; > + } > + > + if (Vtd !=3D NULL) { > + FspmUpd->FspmConfig.X2ApicOptOut =3D (UINT8) Vtd->X2ApicOptOut; > + FspmUpd->FspmConfig.VtdBaseAddress[0] =3D Vtd->BaseAddress[0]; > + FspmUpd->FspmConfig.VtdBaseAddress[1] =3D Vtd->BaseAddress[1]; > + FspmUpd->FspmConfig.VtdBaseAddress[2] =3D Vtd->BaseAddress[2]; > + FspmUpd->FspmTestConfig.VtdDisable =3D (UINT8) Vtd->VtdDisable; > + } > + > + if (PciePeiPreMemConfig !=3D NULL) { > + FspmUpd->FspmConfig.DmiGen3ProgramStaticEq =3D (UINT8) > PciePeiPreMemConfig->DmiGen3ProgramStaticEq; > + FspmUpd->FspmConfig.Peg0Enable =3D (UINT8) > PciePeiPreMemConfig->Peg0Enable; > + FspmUpd->FspmConfig.Peg1Enable =3D (UINT8) > PciePeiPreMemConfig->Peg1Enable; > + FspmUpd->FspmConfig.Peg2Enable =3D (UINT8) > PciePeiPreMemConfig->Peg2Enable; > + FspmUpd->FspmConfig.Peg3Enable =3D (UINT8) > PciePeiPreMemConfig->Peg3Enable; > + FspmUpd->FspmConfig.Peg0MaxLinkSpeed =3D (UINT8) > PciePeiPreMemConfig->Peg0MaxLinkSpeed; > + FspmUpd->FspmConfig.Peg1MaxLinkSpeed =3D (UINT8) > PciePeiPreMemConfig->Peg1MaxLinkSpeed; > + FspmUpd->FspmConfig.Peg2MaxLinkSpeed =3D (UINT8) > PciePeiPreMemConfig->Peg2MaxLinkSpeed; > + FspmUpd->FspmConfig.Peg3MaxLinkSpeed =3D (UINT8) > PciePeiPreMemConfig->Peg3MaxLinkSpeed; > + FspmUpd->FspmConfig.Peg0MaxLinkWidth =3D (UINT8) > PciePeiPreMemConfig->Peg0MaxLinkWidth; > + FspmUpd->FspmConfig.Peg1MaxLinkWidth =3D (UINT8) > PciePeiPreMemConfig->Peg1MaxLinkWidth; > + FspmUpd->FspmConfig.Peg2MaxLinkWidth =3D (UINT8) > PciePeiPreMemConfig->Peg2MaxLinkWidth; > + FspmUpd->FspmConfig.Peg3MaxLinkWidth =3D (UINT8) > PciePeiPreMemConfig->Peg3MaxLinkWidth; > + FspmUpd->FspmConfig.Peg0PowerDownUnusedLanes =3D (UINT8) > PciePeiPreMemConfig->Peg0PowerDownUnusedLanes; > + FspmUpd->FspmConfig.Peg1PowerDownUnusedLanes =3D (UINT8) > PciePeiPreMemConfig->Peg1PowerDownUnusedLanes; > + FspmUpd->FspmConfig.Peg2PowerDownUnusedLanes =3D (UINT8) > PciePeiPreMemConfig->Peg2PowerDownUnusedLanes; > + FspmUpd->FspmConfig.Peg3PowerDownUnusedLanes =3D (UINT8) > PciePeiPreMemConfig->Peg3PowerDownUnusedLanes; > + FspmUpd->FspmConfig.InitPcieAspmAfterOprom =3D (UINT8) > PciePeiPreMemConfig->InitPcieAspmAfterOprom; > + FspmUpd->FspmConfig.PegDisableSpreadSpectrumClocking =3D (UINT8) > PciePeiPreMemConfig->PegDisableSpreadSpectrumClocking; > + for (Index =3D 0; Index < SA_DMI_MAX_LANE; Index++) { > + FspmUpd->FspmConfig.DmiGen3RootPortPreset[Index] =3D > PciePeiPreMemConfig->DmiGen3RootPortPreset[Index]; > + FspmUpd->FspmConfig.DmiGen3EndPointPreset[Index] =3D > PciePeiPreMemConfig->DmiGen3EndPointPreset[Index]; > + FspmUpd->FspmConfig.DmiGen3EndPointHint[Index] =3D > PciePeiPreMemConfig->DmiGen3EndPointHint[Index]; > + } > + for (Index =3D 0; Index < SA_DMI_MAX_BUNDLE; Index++) { > + FspmUpd->FspmConfig.DmiGen3RxCtlePeaking[Index] =3D > PciePeiPreMemConfig->DmiGen3RxCtlePeaking[Index]; > + } > + for (Index =3D 0; Index < SA_PEG_MAX_BUNDLE ; Index++) { > + FspmUpd->FspmConfig.PegGen3RxCtlePeaking[Index] =3D > PciePeiPreMemConfig->PegGen3RxCtlePeaking[Index]; > + } > + FspmUpd->FspmConfig.PegDataPtr =3D (UINT32) > PciePeiPreMemConfig->PegDataPtr; > + CopyMem((VOID *)FspmUpd->FspmConfig.PegGpioData, > &PciePeiPreMemConfig->PegGpioData, sizeof (PEG_GPIO_DATA)); > + FspmUpd->FspmConfig.DmiDeEmphasis =3D > PciePeiPreMemConfig->DmiDeEmphasis; > + > + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { > + FspmUpd->FspmConfig.PegRootPortHPE[Index] =3D > PciePeiPreMemConfig->PegRootPortHPE[Index]; > + } > + FspmUpd->FspmTestConfig.DmiMaxLinkSpeed =3D (UINT8) > PciePeiPreMemConfig->DmiMaxLinkSpeed; > + FspmUpd->FspmTestConfig.DmiGen3EqPh2Enable =3D (UINT8) > PciePeiPreMemConfig->DmiGen3EqPh2Enable; > + FspmUpd->FspmTestConfig.DmiGen3EqPh3Method =3D (UINT8) > PciePeiPreMemConfig->DmiGen3EqPh3Method; > + FspmUpd->FspmTestConfig.Peg0Gen3EqPh2Enable =3D (UINT8) > PciePeiPreMemConfig->Peg0Gen3EqPh2Enable; > + FspmUpd->FspmTestConfig.Peg1Gen3EqPh2Enable =3D (UINT8) > PciePeiPreMemConfig->Peg1Gen3EqPh2Enable; > + FspmUpd->FspmTestConfig.Peg2Gen3EqPh2Enable =3D (UINT8) > PciePeiPreMemConfig->Peg2Gen3EqPh2Enable; > + FspmUpd->FspmTestConfig.Peg3Gen3EqPh2Enable =3D (UINT8) > PciePeiPreMemConfig->Peg3Gen3EqPh2Enable; > + FspmUpd->FspmTestConfig.Peg0Gen3EqPh3Method =3D (UINT8) > PciePeiPreMemConfig->Peg0Gen3EqPh3Method; > + FspmUpd->FspmTestConfig.Peg1Gen3EqPh3Method =3D (UINT8) > PciePeiPreMemConfig->Peg1Gen3EqPh3Method; > + FspmUpd->FspmTestConfig.Peg2Gen3EqPh3Method =3D (UINT8) > PciePeiPreMemConfig->Peg2Gen3EqPh3Method; > + FspmUpd->FspmTestConfig.Peg3Gen3EqPh3Method =3D (UINT8) > PciePeiPreMemConfig->Peg3Gen3EqPh3Method; > + FspmUpd->FspmTestConfig.PegGen3ProgramStaticEq =3D (UINT8) > PciePeiPreMemConfig->PegGen3ProgramStaticEq; > + FspmUpd->FspmTestConfig.Gen3SwEqAlwaysAttempt =3D (UINT8) > PciePeiPreMemConfig->Gen3SwEqAlwaysAttempt; > + FspmUpd->FspmTestConfig.Gen3SwEqNumberOfPresets =3D (UINT8) > PciePeiPreMemConfig->Gen3SwEqNumberOfPresets; > + FspmUpd->FspmTestConfig.Gen3SwEqEnableVocTest =3D (UINT8) > PciePeiPreMemConfig->Gen3SwEqEnableVocTest; > + FspmUpd->FspmTestConfig.PegRxCemTestingMode =3D (UINT8) > PciePeiPreMemConfig->PegRxCemTestingMode; > + FspmUpd->FspmTestConfig.PegRxCemLoopbackLane =3D (UINT8) > PciePeiPreMemConfig->PegRxCemLoopbackLane; > + FspmUpd->FspmTestConfig.PegGenerateBdatMarginTable =3D (UINT8) > PciePeiPreMemConfig->PegGenerateBdatMarginTable; > + FspmUpd->FspmTestConfig.PegRxCemNonProtocolAwareness =3D (UINT8) > PciePeiPreMemConfig->PegRxCemNonProtocolAwareness; > + FspmUpd->FspmTestConfig.PegGen3RxCtleOverride =3D (UINT8) > PciePeiPreMemConfig->PegGen3RxCtleOverride; > + for (Index =3D 0; Index < SA_PEG_MAX_LANE; Index++) { > + FspmUpd->FspmTestConfig.PegGen3RootPortPreset[Index] =3D > PciePeiPreMemConfig->PegGen3RootPortPreset[Index]; > + FspmUpd->FspmTestConfig.PegGen3EndPointPreset[Index] =3D > PciePeiPreMemConfig->PegGen3EndPointPreset[Index]; > + FspmUpd->FspmTestConfig.PegGen3EndPointHint[Index] =3D > PciePeiPreMemConfig->PegGen3EndPointHint[Index]; > + } > + FspmUpd->FspmTestConfig.Gen3SwEqJitterDwellTime =3D > PciePeiPreMemConfig->Gen3SwEqJitterDwellTime; > + FspmUpd->FspmTestConfig.Gen3SwEqJitterErrorTarget =3D > PciePeiPreMemConfig->Gen3SwEqJitterErrorTarget; > + FspmUpd->FspmTestConfig.Gen3SwEqVocDwellTime =3D > PciePeiPreMemConfig->Gen3SwEqVocDwellTime; > + FspmUpd->FspmTestConfig.Gen3SwEqVocErrorTarget =3D > PciePeiPreMemConfig->Gen3SwEqVocErrorTarget; > + } > + > + if (GtPreMemConfig !=3D NULL) { > + FspmUpd->FspmConfig.PrimaryDisplay =3D (UINT8) > GtPreMemConfig->PrimaryDisplay; > + FspmUpd->FspmConfig.InternalGfx =3D (UINT8) > GtPreMemConfig->InternalGraphics; > + FspmUpd->FspmConfig.IgdDvmt50PreAlloc =3D (UINT8) > GtPreMemConfig->IgdDvmt50PreAlloc; > + FspmUpd->FspmConfig.ApertureSize =3D (UINT8) > GtPreMemConfig->ApertureSize; > + FspmUpd->FspmConfig.GttMmAdr =3D GtPreMemConfig->GttMmAdr; > + FspmUpd->FspmConfig.GmAdr =3D GtPreMemConfig->GmAdr; > + FspmUpd->FspmConfig.GttSize =3D GtPreMemConfig->GttSize; > + FspmUpd->FspmConfig.PsmiRegionSize =3D (UINT8) > GtPreMemConfig->PsmiRegionSize; > + FspmUpd->FspmConfig.GtPsmiSupport =3D > (UINT8)GtPreMemConfig->GtPsmiSupport; > + FspmUpd->FspmTestConfig.PanelPowerEnable =3D (UINT8) > GtPreMemConfig->PanelPowerEnable; > + FspmUpd->FspmTestConfig.DeltaT12PowerCycleDelayPreMem =3D (UINT16) > GtPreMemConfig->DeltaT12PowerCycleDelayPreMem; > + } > + > + if (SgGpioData !=3D NULL) { > + CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie0Gpio, > &SgGpioData->SaRtd3Pcie0Gpio, sizeof (SA_PCIE_RTD3_GPIO)); > + CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie1Gpio, > &SgGpioData->SaRtd3Pcie1Gpio, sizeof (SA_PCIE_RTD3_GPIO)); > + CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie2Gpio, > &SgGpioData->SaRtd3Pcie2Gpio, sizeof (SA_PCIE_RTD3_GPIO)); > + FspmUpd->FspmConfig.RootPortIndex =3D SgGpioData->RootPortIndex; > + } > + > + if (IpuPreMemPolicy !=3D NULL) { > + FspmUpd->FspmConfig.SaIpuEnable =3D (UINT8) > IpuPreMemPolicy->SaIpuEnable; > + FspmUpd->FspmConfig.SaIpuImrConfiguration =3D (UINT8) > IpuPreMemPolicy->SaIpuImrConfiguration; > + } > + > + if (OcPreMemConfig !=3D NULL) { > + FspmUpd->FspmConfig.SaOcSupport =3D (UINT8) > OcPreMemConfig->OcSupport; > + FspmUpd->FspmConfig.RealtimeMemoryTiming =3D (UINT8) > OcPreMemConfig->RealtimeMemoryTiming; > + FspmUpd->FspmConfig.GtVoltageMode =3D (UINT8) > OcPreMemConfig->GtVoltageMode; > + FspmUpd->FspmConfig.GtMaxOcRatio =3D > OcPreMemConfig->GtMaxOcRatio; > + FspmUpd->FspmConfig.GtVoltageOffset =3D > OcPreMemConfig->GtVoltageOffset; > + FspmUpd->FspmConfig.GtVoltageOverride =3D > OcPreMemConfig->GtVoltageOverride; > + FspmUpd->FspmConfig.GtExtraTurboVoltage =3D > OcPreMemConfig->GtExtraTurboVoltage; > + FspmUpd->FspmConfig.SaVoltageOffset =3D > OcPreMemConfig->SaVoltageOffset; > + FspmUpd->FspmConfig.GtusMaxOcRatio =3D > OcPreMemConfig->GtusMaxOcRatio; > + FspmUpd->FspmConfig.GtusVoltageMode =3D (UINT8) > OcPreMemConfig->GtusVoltageMode; > + FspmUpd->FspmConfig.GtusVoltageOffset =3D > OcPreMemConfig->GtusVoltageOffset; > + FspmUpd->FspmConfig.GtusVoltageOverride =3D > OcPreMemConfig->GtusVoltageOverride; > + FspmUpd->FspmConfig.GtusExtraTurboVoltage =3D > OcPreMemConfig->GtusExtraTurboVoltage; > + } > + > + > + > + > + return EFI_SUCCESS; > +} > + > + > +/** > + Performs FSP SA PEI Policy initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSaPolicyInit ( > + IN OUT FSPS_UPD *FspsUpd > + ) > +{ > + EFI_STATUS Status; > + SI_POLICY_PPI *SiPolicyPpi; > + SA_MISC_PEI_CONFIG *MiscPeiConfig; > + GRAPHICS_PEI_CONFIG *GtConfig; > + PCIE_PEI_CONFIG *PciePeiConfig; > + GNA_CONFIG *GnaConfig; > + UINT8 Index; > + EFI_BOOT_MODE BootMode; > + > + MiscPeiConfig =3D NULL; > + GtConfig =3D NULL; > + PciePeiConfig =3D NULL; > + GnaConfig =3D NULL; > + > + // > + // @todo This could be cleared up after FSP provides ExitBootServices > NotifyPhase. > + // > + Status =3D PeiServicesGetBootMode (&BootMode); > + ASSERT_EFI_ERROR (Status); > + > + // > + // Locate SiPolicyPpi > + // > + SiPolicyPpi =3D NULL; > + Status =3D PeiServicesLocatePpi( > + &gSiPolicyPpiGuid, > + 0, > + NULL, > + (VOID **)&SiPolicyPpi > + ); > + if ((Status =3D=3D EFI_SUCCESS) && (SiPolicyPpi !=3D NULL)) { > + MiscPeiConfig =3D NULL; > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGu= id, > (VOID *) &MiscPeiConfig); > + ASSERT_EFI_ERROR (Status); > + > + GtConfig =3D NULL; > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfig= Guid, > (VOID *) &GtConfig); > + ASSERT_EFI_ERROR (Status); > + > + GnaConfig =3D NULL; > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGnaConfigGuid, (V= OID *) > &GnaConfig); > + ASSERT_EFI_ERROR (Status); > + > + PciePeiConfig =3D NULL; > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaPciePeiConfigGu= id, > (VOID *) &PciePeiConfig); > + ASSERT_EFI_ERROR (Status); > + > + } > + > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Wrapper UpdatePeiSaPolicy\n")); > + > + > + if (MiscPeiConfig !=3D NULL) { > + FspsUpd->FspsConfig.Device4Enable =3D (UINT8) > MiscPeiConfig->Device4Enable; > + FspsUpd->FspsConfig.CridEnable =3D (UINT8) MiscPeiConfig->CridEnable= ; > + FspsUpd->FspsTestConfig.ChapDeviceEnable =3D (UINT8) > MiscPeiConfig->ChapDeviceEnable; > + FspsUpd->FspsTestConfig.SkipPamLock =3D (UINT8) > MiscPeiConfig->SkipPamLock; > + FspsUpd->FspsTestConfig.EdramTestMode =3D (UINT8) > MiscPeiConfig->EdramTestMode; > + } > + > + if (PciePeiConfig !=3D NULL) { > + FspsUpd->FspsConfig.DmiAspm =3D (UINT8) PciePeiConfig->DmiAspm; > + FspsUpd->FspsTestConfig.DmiExtSync =3D (UINT8) > PciePeiConfig->DmiExtSync; > + FspsUpd->FspsTestConfig.DmiIot =3D (UINT8) PciePeiConfig->DmiIot; > + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { > + FspsUpd->FspsConfig.PegDeEmphasis[Index] =3D > PciePeiConfig->PegDeEmphasis[Index]; > + FspsUpd->FspsConfig.PegSlotPowerLimitValue[Index] =3D > PciePeiConfig->PegSlotPowerLimitValue[Index]; > + FspsUpd->FspsConfig.PegSlotPowerLimitScale[Index] =3D > PciePeiConfig->PegSlotPowerLimitScale[Index]; > + FspsUpd->FspsConfig.PegPhysicalSlotNumber[Index] =3D > PciePeiConfig->PegPhysicalSlotNumber[Index]; > + FspsUpd->FspsTestConfig.PegMaxPayload[Index] =3D > PciePeiConfig->PegMaxPayload[Index]; > + } > + } > + > + if (GtConfig !=3D NULL) { > + FspsUpd->FspsConfig.PavpEnable =3D (UINT8) GtConfig->PavpEnable; > + FspsUpd->FspsConfig.CdClock =3D (UINT8) GtConfig->CdClock; > + FspsUpd->FspsTestConfig.RenderStandby =3D (UINT8) > GtConfig->RenderStandby; > + FspsUpd->FspsTestConfig.PmSupport =3D (UINT8) GtConfig->PmSupport; > + FspsUpd->FspsTestConfig.CdynmaxClampEnable =3D (UINT8) > GtConfig->CdynmaxClampEnable; > + FspsUpd->FspsTestConfig.GtFreqMax =3D (UINT8) GtConfig->GtFreqMax; > + FspsUpd->FspsTestConfig.DisableTurboGt =3D (UINT8) > GtConfig->DisableTurboGt; > + FspsUpd->FspsConfig.SkipS3CdClockInit =3D > (UINT8)GtConfig->SkipS3CdClockInit; > + > + // > + // For FSP, FspsUpd->FspsConfig.PeiGraphicsPeimInit is always enable= d as > default. > + // > + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D (UINT8) > GtConfig->PeiGraphicsPeimInit; // SA: InternalOnly: For Internal validati= on we > still need to enable both Enable/Disable Cases > + > + // > + // Update UPD: VBT & LogoPtr > + // > + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { > + FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32) NULL; > + } else { > + FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32) > GtConfig->GraphicsConfigPtr; > + } > + DEBUG(( DEBUG_INFO, "VbtPtr from GraphicsPeiConfig is 0x%x\n", > FspsUpd->FspsConfig.GraphicsConfigPtr)); > + > + FspsUpd->FspsConfig.LogoPtr =3D (UINT32) GtConfig->LogoPtr; > + FspsUpd->FspsConfig.LogoSize =3D GtConfig->LogoSize; > + DEBUG(( DEBUG_INFO, "LogoPtr from PeiFspSaPolicyInit > GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoPtr)); > + DEBUG(( DEBUG_INFO, "LogoSize from PeiFspSaPolicyInit > GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoSize)); > + > + FspsUpd->FspsConfig.BltBufferAddress =3D (UINT32) > GtConfig->BltBufferAddress; > + FspsUpd->FspsConfig.BltBufferSize =3D (UINT32) GtConfig->BltBuff= erSize; > + > + // > + // Update DDI/DDC configuration > + // > + FspsUpd->FspsConfig.DdiPortEdp =3D > GtConfig->DdiConfiguration.DdiPortEdp; > + FspsUpd->FspsConfig.DdiPortBHpd =3D > GtConfig->DdiConfiguration.DdiPortBHpd; > + FspsUpd->FspsConfig.DdiPortCHpd =3D > GtConfig->DdiConfiguration.DdiPortCHpd; > + FspsUpd->FspsConfig.DdiPortDHpd =3D > GtConfig->DdiConfiguration.DdiPortDHpd; > + FspsUpd->FspsConfig.DdiPortFHpd =3D > GtConfig->DdiConfiguration.DdiPortFHpd; > + FspsUpd->FspsConfig.DdiPortBDdc =3D > GtConfig->DdiConfiguration.DdiPortBDdc; > + FspsUpd->FspsConfig.DdiPortCDdc =3D > GtConfig->DdiConfiguration.DdiPortCDdc; > + FspsUpd->FspsConfig.DdiPortDDdc =3D > GtConfig->DdiConfiguration.DdiPortDDdc; > + FspsUpd->FspsConfig.DdiPortFDdc =3D > GtConfig->DdiConfiguration.DdiPortFDdc; > + > + } > + > + if (GnaConfig !=3D NULL) { > + FspsUpd->FspsConfig.GnaEnable =3D (UINT8) GnaConfig->GnaEnable; > +#ifdef TESTMENU_FLAG > +#endif // TESTMENU_FLAG > + } > + > + > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspSecurityPolicyInitLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspSecurityPolicyInitLib.c > new file mode 100644 > index 0000000000..80d20d74a9 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspSecurityPolicyInitLib.c > @@ -0,0 +1,70 @@ > +/** @file > + Implementation of Fsp Security Policy Initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > + > +/** > + Performs FSP Security PEI Policy initialization. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSecurityPolicyInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ) > +{ > + EFI_STATUS Status; > + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > + > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem > Start\n")); > + > + // > + // Locate SiPreMemPolicyPpi > + // > + SiPreMemPolicyPpi =3D NULL; > + Status =3D PeiServicesLocatePpi ( > + &gSiPreMemPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPreMemPolicyPpi > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + > + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem > End\n")); > + > + return EFI_SUCCESS; > +} > + > +/** > + Performs FSP Security PEI Policy post memory initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSecurityPolicyInit ( > + IN OUT FSPS_UPD *FspsUpd > + ) > +{ > + > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspSiPolicyInitLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspSiPolicyInitLib.c > new file mode 100644 > index 0000000000..98658782aa > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPoli > cyInitLib/PeiFspSiPolicyInitLib.c > @@ -0,0 +1,95 @@ > +/** @file > + Implementation of Fsp SI Policy Initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > + > +/** > + Performs FSP SI PEI Policy pre mem initialization. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSiPolicyInitPreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ) > +{ > + EFI_STATUS Status; > + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > + > + // > + // Locate SiPreMemPolicyPpi > + // > + SiPreMemPolicyPpi =3D NULL; > + Status =3D PeiServicesLocatePpi ( > + &gSiPreMemPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPreMemPolicyPpi > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + Performs FSP SI PEI Policy initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSiPolicyInit ( > + IN OUT FSPS_UPD *FspsUpd > + ) > +{ > + EFI_STATUS Status; > + SI_POLICY_PPI *SiPolicy; > + SI_CONFIG *SiConfig; > + > + // > + // Locate SiPolicyPpi > + // > + SiPolicy =3D NULL; > + Status =3D PeiServicesLocatePpi ( > + &gSiPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPolicy > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSiConfigGuid, (VOID *) > &SiConfig); > + ASSERT_EFI_ERROR (Status); > + > + // > + // Update SiConfig policies > + // > + FspsUpd->FspsConfig.SiCsmFlag =3D (UINT8)SiConfig->CsmF= lag; > + FspsUpd->FspsConfig.SiSsidTablePtr =3D > (UINT32)(UINTN)SiConfig->SsidTablePtr; > + FspsUpd->FspsConfig.SiNumberOfSsidTableEntry =3D > (UINT16)SiConfig->NumberOfSsidTableEntry; > + FspsUpd->FspsConfig.TraceHubMemBase =3D > SiConfig->TraceHubMemBase; > + > + return EFI_SUCCESS; > +} > + > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP > olicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c > new file mode 100644 > index 0000000000..a341a58930 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c > @@ -0,0 +1,100 @@ > +/** @file > + Implementation of Fsp Misc UPD Initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "PeiMiscPolicyUpdate.h" > + > +/** > + Performs FSP Misc UPD initialization. > + > + @param[in,out] FspmUpd Pointer to FSPM_UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND An instance of > gEfiPeiReadOnlyVariable2PpiGuid > + could not be located. > + @retval EFI_OUT_OF_RESOURCES Insufficent resources to > allocate a memory buffer. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspMiscUpdUpdatePreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ) > +{ > + EFI_STATUS Status; > + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; > + UINTN VariableSize; > + VOID *MemorySavedData; > + > + Status =3D PeiServicesLocatePpi ( > + &gEfiPeiReadOnlyVariable2PpiGuid, > + 0, > + NULL, > + (VOID **) &VariableServices > + ); > + if (EFI_ERROR (Status)) { > + ASSERT_EFI_ERROR (Status); > + return Status; > + } > + > + VariableSize =3D 0; > + MemorySavedData =3D NULL; > + Status =3D VariableServices->GetVariable ( > + VariableServices, > + L"MemoryConfig", > + &gFspNonVolatileStorageHobGuid, > + NULL, > + &VariableSize, > + MemorySavedData > + ); > + if (Status =3D=3D EFI_BUFFER_TOO_SMALL) { > + MemorySavedData =3D AllocatePool (VariableSize); > + if (MemorySavedData =3D=3D NULL) { > + ASSERT (MemorySavedData !=3D NULL); > + return EFI_OUT_OF_RESOURCES; > + } > + > + DEBUG ((DEBUG_INFO, "VariableSize is 0x%x\n", VariableSize)); > + Status =3D VariableServices->GetVariable ( > + VariableServices, > + L"MemoryConfig", > + &gFspNonVolatileStorageHobGuid, > + NULL, > + &VariableSize, > + MemorySavedData > + ); > + if (Status =3D=3D EFI_SUCCESS) { > + FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData; > + } else { > + DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable:\"MemoryConfig\" > gMemoryConfigVariableGuid, Status =3D %r\n", Status)); > + ASSERT_EFI_ERROR (Status); > + } > + } > + FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData; > + > + return EFI_SUCCESS; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP > olicyUpdateLibFsp/PeiFspPolicyUpdateLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c > new file mode 100644 > index 0000000000..5119e934a2 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c > @@ -0,0 +1,124 @@ > +/** @file > + Provide FSP wrapper platform related function. > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#include "PeiMiscPolicyUpdate.h" > + > +/** > + Performs FSP PCH PEI Policy initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspPchPolicyUpdate ( > + IN OUT FSPS_UPD *FspsUpd > + ); > + > +VOID > +InternalPrintVariableData ( > + IN UINT8 *Data8, > + IN UINTN DataSize > + ) > +{ > + UINTN Index; > + > + for (Index =3D 0; Index < DataSize; Index++) { > + if (Index % 0x10 =3D=3D 0) { > + DEBUG ((DEBUG_INFO, "\n%08X:", Index)); > + } > + DEBUG ((DEBUG_INFO, " %02X", *Data8++)); > + } > + DEBUG ((DEBUG_INFO, "\n")); > +} > + > +/** > + Performs silicon pre-mem policy update. > + > + The meaning of Policy is defined by silicon code. > + It could be the raw data, a handle, a PPI, etc. > + > + The input Policy must be returned by SiliconPolicyDonePreMem(). > + > + 1) In FSP path, the input Policy should be FspmUpd. > + A platform may use this API to update the FSPM UPD policy initialized > + by the silicon module or the default UPD data. > + The output of FSPM UPD data from this API is the final UPD data. > + > + 2) In non-FSP path, the board may use additional way to get > + the silicon policy data field based upon the input Policy. > + > + @param[in, out] Policy Pointer to policy. > + > + @return the updated policy. > +**/ > +VOID * > +EFIAPI > +SiliconPolicyUpdatePreMem ( > + IN OUT VOID *FspmUpd > + ) > +{ > + FSPM_UPD *FspmUpdDataPtr; > + > + FspmUpdDataPtr =3D FspmUpd; > + > + PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr); > + InternalPrintVariableData ((VOID *) FspmUpdDataPtr, sizeof (FSPM_UPD))= ; > + > + return FspmUpd; > +} > + > +/** > + Performs silicon post-mem policy update. > + > + The meaning of Policy is defined by silicon code. > + It could be the raw data, a handle, a PPI, etc. > + > + The input Policy must be returned by SiliconPolicyDonePostMem(). > + > + 1) In FSP path, the input Policy should be FspsUpd. > + A platform may use this API to update the FSPS UPD policy initialized > + by the silicon module or the default UPD data. > + The output of FSPS UPD data from this API is the final UPD data. > + > + 2) In non-FSP path, the board may use additional way to get > + the silicon policy data field based upon the input Policy. > + > + @param[in, out] Policy Pointer to policy. > + > + @return the updated policy. > +**/ > +VOID * > +EFIAPI > +SiliconPolicyUpdatePostMem ( > + IN OUT VOID *FspsUpd > + ) > +{ > + FSPS_UPD *FspsUpdDataPtr; > + > + FspsUpdDataPtr =3D FspsUpd; > + > + PeiFspPchPolicyUpdate (FspsUpd); > + InternalPrintVariableData ((VOID * )FspsUpdDataPtr, sizeof (FSPS_UPD))= ; > + > + return FspsUpd; > +} > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP > olicyUpdateLibFsp/PeiPchPolicyUpdate.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiPchPolicyUpdate.c > new file mode 100644 > index 0000000000..455467dc25 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiPchPolicyUpdate.c > @@ -0,0 +1,60 @@ > +/** @file > + This file is SampleCode of the library for Intel PCH PEI Policy initia= lization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiPchPolicyUpdate.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Performs FSP PCH PEI Policy initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspPchPolicyUpdate ( > + IN OUT FSPS_UPD *FspsUpd > + ) > +{ > + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr =3D (UINT32) > mPcieDeviceTable; > + > + AddPlatformVerbTables ( > + PchHdaCodecPlatformOnboard, > + &(FspsUpd->FspsConfig.PchHdaVerbTableEntryNum), > + &(FspsUpd->FspsConfig.PchHdaVerbTablePtr) > + ); > + > +DEBUG_CODE_BEGIN(); > +if ((PcdGet8 (PcdSerialIoUartDebugEnable) =3D=3D 1) && > + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + > PcdGet8 (PcdSerialIoUartNumber)] =3D=3D PchSerialIoDisabled ) { > + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 > (PcdSerialIoUartNumber)] =3D PchSerialIoHidden; > + } > +DEBUG_CODE_END(); > + > + return EFI_SUCCESS; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP > olicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c > new file mode 100644 > index 0000000000..cbb818c875 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c > @@ -0,0 +1,39 @@ > +/** @file > + This file is SampleCode of the library for Intel PCH PEI Policy initia= lization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiPchPolicyUpdate.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Performs FSP PCH PEI Policy pre mem initialization. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspPchPolicyUpdatePreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ) > +{ > + return EFI_SUCCESS; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP > olicyUpdateLibFsp/PeiSaPolicyUpdate.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiSaPolicyUpdate.c > new file mode 100644 > index 0000000000..2114479030 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiSaPolicyUpdate.c > @@ -0,0 +1,85 @@ > +/** @file > +Do Platform Stage System Agent initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiSaPolicyUpdate.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Performs FSP SA PEI Policy initialization. > + > + @param[in][out] FspsUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSaPolicyUpdate ( > + IN OUT FSPS_UPD *FspsUpd > + ) > +{ > + VOID *Buffer; > + VOID *MemBuffer; > + UINT32 Size; > + > + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); > + > + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; > + > + Size =3D 0; > + Buffer =3D NULL; > + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), > EFI_SECTION_RAW, 0, &Buffer, &Size); > + if (Buffer =3D=3D NULL) { > + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); > + } else { > + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Siz= e)); > + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { > + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); > + FspsUpd->FspsConfig.GraphicsConfigPtr =3D > (UINT32)(UINTN)MemBuffer; > + } else { > + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); > + FspsUpd->FspsConfig.GraphicsConfigPtr =3D 0; > + } > + } > + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", > FspsUpd->FspsConfig.GraphicsConfigPtr)); > + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", > Size)); > + > + Size =3D 0; > + Buffer =3D NULL; > + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, > &Buffer, &Size); > + if (Buffer =3D=3D NULL) { > + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); > + } else { > + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Siz= e)); > + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { > + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); > + FspsUpd->FspsConfig.LogoPtr =3D (UINT32)(UINTN)MemBuffer; > + FspsUpd->FspsConfig.LogoSize =3D Size; > + } else { > + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); > + FspsUpd->FspsConfig.LogoPtr =3D 0; > + FspsUpd->FspsConfig.LogoSize =3D 0; > + } > + } > + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", > FspsUpd->FspsConfig.LogoPtr)); > + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", > FspsUpd->FspsConfig.LogoSize)); > + > + return EFI_SUCCESS; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP > olicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c > new file mode 100644 > index 0000000000..946182864e > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSilicon > PolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c > @@ -0,0 +1,87 @@ > +/** @file > +Do Platform Stage System Agent initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiSaPolicyUpdate.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > + > +/** > + Performs FSP SA PEI Policy initialization in pre-memory. > + > + @param[in][out] FspmUpd Pointer to FSP UPD Data. > + > + @retval EFI_SUCCESS FSP UPD Data is updated. > + @retval EFI_NOT_FOUND Fail to locate required PPI. > + @retval Other FSP UPD Data update process fail. > +**/ > +EFI_STATUS > +EFIAPI > +PeiFspSaPolicyUpdatePreMem ( > + IN OUT FSPM_UPD *FspmUpd > + ) > +{ > + VOID *Buffer; > + > + // > + // If SpdAddressTable are not all 0, it means DIMM slots implemented a= nd > + // MemorySpdPtr* already updated by reading SPD from DIMM in > SiliconPolicyInitPreMem. > + // > + // If SpdAddressTable all 0, this is memory down design and hardcoded > SpdData > + // should be applied to MemorySpdPtr*. > + // > + if ((PcdGet8 (PcdMrcSpdAddressTable0) =3D=3D 0) && (PcdGet8 > (PcdMrcSpdAddressTable1) =3D=3D 0) > + && (PcdGet8 (PcdMrcSpdAddressTable2) =3D=3D 0) && (PcdGet8 > (PcdMrcSpdAddressTable3) =3D=3D 0)) { > + DEBUG ((DEBUG_INFO, "Overriding SPD data for down memory.\n")); > + CopyMem ( > + (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr00, > + (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData), > + PcdGet16 (PcdMrcSpdDataSize) > + ); > + CopyMem ( > + (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr10, > + (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData), > + PcdGet16 (PcdMrcSpdDataSize) > + ); > + } > + > + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling > Settings...\n")); > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); > + if (Buffer) { > + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12); > + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) > Buffer + 12, 12); > + } > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); > + if (Buffer) { > + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, > 8); > + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, > (UINT8*) Buffer + 8, 8); > + } > + > + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & > Rcomp Target Settings...\n")); > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); > + if (Buffer) { > + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6); > + } > + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); > + if (Buffer) { > + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10); > + } > + return EFI_SUCCESS; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra > pperPlatformSecLib/FspWrapperPlatformSecLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/FspWrapperPlatformSecLib.c > new file mode 100644 > index 0000000000..a767289bc5 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/FspWrapperPlatformSecLib.c > @@ -0,0 +1,163 @@ > +/** @file > + Provide FSP wrapper platform sec related function. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > + > +/** > + This interface conveys state information out of the Security (SEC) pha= se into > PEI. > + > + @param[in] PeiServices Pointer to the PEI Services T= able. > + @param[in,out] StructureSize Pointer to the variable descr= ibing > size of the input buffer. > + @param[out] PlatformInformationRecord Pointer to the > EFI_SEC_PLATFORM_INFORMATION_RECORD. > + > + @retval EFI_SUCCESS The data was successfully returned. > + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. > + > +**/ > +EFI_STATUS > +EFIAPI > +SecPlatformInformation ( > + IN CONST EFI_PEI_SERVICES **PeiServices, > + IN OUT UINT64 *StructureSize, > + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD > *PlatformInformationRecord > + ); > + > +/** > + This interface conveys performance information out of the Security (SE= C) > phase into PEI. > + > + This service is published by the SEC phase. The SEC phase handoff has = an > optional > + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is pass= ed > from SEC into the > + PEI Foundation. As such, if the platform supports collecting performan= ce > data in SEC, > + this information is encapsulated into the data structure abstracted by= this > service. > + This information is collected for the boot-strap processor (BSP) on IA= -32. > + > + @param[in] PeiServices The pointer to the PEI Services Table. > + @param[in] This The pointer to this instance of the > PEI_SEC_PERFORMANCE_PPI. > + @param[out] Performance The pointer to performance data collected in > SEC phase. > + > + @retval EFI_SUCCESS The data was successfully returned. > + > +**/ > +EFI_STATUS > +EFIAPI > +SecGetPerformance ( > + IN CONST EFI_PEI_SERVICES **PeiServices, > + IN PEI_SEC_PERFORMANCE_PPI *This, > + OUT FIRMWARE_SEC_PERFORMANCE *Performance > + ); > + > +PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi =3D { > + SecGetPerformance > +}; > + > +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] =3D { > + { > + EFI_PEI_PPI_DESCRIPTOR_PPI, > + &gTopOfTemporaryRamPpiGuid, > + NULL // To be patched later. > + }, > + { > + EFI_PEI_PPI_DESCRIPTOR_PPI | > EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, > + &gPeiSecPerformancePpiGuid, > + &mSecPerformancePpi > + }, > +}; > + > +#define LEGACY_8259_MASK_REGISTER_MASTER 0x21 > +#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1 > +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0 > +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1 > + > +/** > + Write to mask and edge/level triggered registers of master and slave 8= 259 > PICs. > + > + @param[in] Mask low byte for master PIC mask register, > + high byte for slave PIC mask register. > + @param[in] EdgeLevel low byte for master PIC edge/level triggered > register, > + high byte for slave PIC edge/level triggered re= gister. > + > +**/ > +VOID > +Interrupt8259WriteMask ( > + IN UINT16 Mask, > + IN UINT16 EdgeLevel > + ) > +{ > + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask); > + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8)); > + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, > (UINT8) EdgeLevel); > + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, > (UINT8) (EdgeLevel >> 8)); > +} > + > +/** > + A developer supplied function to perform platform specific operations. > + > + It's a developer supplied function to perform any operations appropria= te to > a > + given platform. It's invoked just before passing control to PEI core b= y SEC > + core. Platform developer may modify the SecCoreData passed to PEI Core= . > + It returns a platform specific PPI list that platform wishes to pass t= o PEI core. > + The Generic SEC core module will merge this list to join the final lis= t passed > to > + PEI core. > + > + @param[in,out] SecCoreData The same parameter as passing to = PEI > core. It > + could be overridden by this funct= ion. > + > + @return The platform specific PPI list to be passed to PEI core or > + NULL if there is no need of such platform specific PPI list. > + > +**/ > +EFI_PEI_PPI_DESCRIPTOR * > +EFIAPI > +SecPlatformMain ( > + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData > + ) > +{ > + EFI_PEI_PPI_DESCRIPTOR *PpiList; > + > + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", > SecCoreData->BootFirmwareVolumeBase)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", > SecCoreData->BootFirmwareVolumeSize)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", > SecCoreData->TemporaryRamBase)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", > SecCoreData->TemporaryRamSize)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", > SecCoreData->PeiTemporaryRamBase)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", > SecCoreData->PeiTemporaryRamSize)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", > SecCoreData->StackBase)); > + DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", > SecCoreData->StackSize)); > + > + InitializeApicTimer (0, (UINT32) -1, TRUE, 5); > + > + // > + // Set all 8259 interrupts to edge triggered and disabled > + // > + Interrupt8259WriteMask (0xFFFF, 0x0000); > + > + // > + // Use middle of Heap as temp buffer, it will be copied by caller. > + // Do not use Stack, because it will cause wrong calculation on stack = by > PeiCore > + // > + PpiList =3D (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + > (UINTN)SecCoreData->PeiTemporaryRamSize/2); > + CopyMem (PpiList, mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi)); > + > + // > + // Patch TopOfTemporaryRamPpi > + // > + PpiList[0].Ppi =3D (VOID *)((UINTN)SecCoreData->TemporaryRamBase + > SecCoreData->TemporaryRamSize); > + > + return PpiList; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra > pperPlatformSecLib/PlatformInit.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/PlatformInit.c > new file mode 100644 > index 0000000000..06ca63c19a > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/PlatformInit.c > @@ -0,0 +1,54 @@ > +/** @file > + Provide platform init function. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Platform initialization. > + > + @param[in] FspHobList HobList produced by FSP. > + @param[in] StartOfRange Start of temporary RAM. > + @param[in] EndOfRange End of temporary RAM. > +**/ > +VOID > +EFIAPI > +PlatformInit ( > + IN VOID *FspHobList, > + IN VOID *StartOfRange, > + IN VOID *EndOfRange > + ) > +{ > + /// > + /// Halt the TCO timer as early as possible > + /// > + IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, > B_TCO_IO_TCO1_CNT_TMR_HLT); > + > + // > + // Platform initialization > + // Enable Serial port here > + // > + if (PcdGetBool(PcdSecSerialPortDebugEnable)) { > + SerialPortInitialize (); > + } > + > + DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n")); > + DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList)); > + DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange)); > + DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange)); > + > + BoardAfterTempRamInit (); > + > + TestPointTempMemoryFunction (StartOfRange, EndOfRange); > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra > pperPlatformSecLib/SecGetPerformance.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/SecGetPerformance.c > new file mode 100644 > index 0000000000..67bdd232bb > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/SecGetPerformance.c > @@ -0,0 +1,90 @@ > +/** @file > + Sample to provide SecGetPerformance function. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +#include > +#include > + > +#include > +#include > +#include > + > +/** > + This interface conveys performance information out of the Security (SE= C) > phase into PEI. > + > + This service is published by the SEC phase. The SEC phase handoff has = an > optional > + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is pass= ed > from SEC into the > + PEI Foundation. As such, if the platform supports collecting performan= ce > data in SEC, > + this information is encapsulated into the data structure abstracted by= this > service. > + This information is collected for the boot-strap processor (BSP) on IA= -32. > + > + @param[in] PeiServices The pointer to the PEI Services Table. > + @param[in] This The pointer to this instance of the > PEI_SEC_PERFORMANCE_PPI. > + @param[out] Performance The pointer to performance data collected in > SEC phase. > + > + @retval EFI_SUCCESS The data was successfully returned. > + > +**/ > +EFI_STATUS > +EFIAPI > +SecGetPerformance ( > + IN CONST EFI_PEI_SERVICES **PeiServices, > + IN PEI_SEC_PERFORMANCE_PPI *This, > + OUT FIRMWARE_SEC_PERFORMANCE *Performance > + ) > +{ > + UINT32 Size; > + UINT32 Count; > + UINT32 TopOfTemporaryRam; > + UINT64 Ticker; > + VOID *TopOfTemporaryRamPpi; > + EFI_STATUS Status; > + > + DEBUG ((DEBUG_INFO, "SecGetPerformance\n")); > + > + Status =3D (*PeiServices)->LocatePpi ( > + PeiServices, > + &gTopOfTemporaryRamPpiGuid, > + 0, > + NULL, > + (VOID **) &TopOfTemporaryRamPpi > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + // > + // |--------------| <- TopOfTemporaryRam - BL > + // | List Ptr | > + // |--------------| > + // | BL RAM Start | > + // |--------------| > + // | BL RAM End | > + // |--------------| > + // |Number of BSPs| > + // |--------------| > + // | BIST | > + // |--------------| > + // | .... | > + // |--------------| > + // | TSC[63:32] | > + // |--------------| > + // | TSC[31:00] | > + // |--------------| > + // > + TopOfTemporaryRam =3D (UINT32)(UINTN)TopOfTemporaryRamPpi - > sizeof(UINT32); > + TopOfTemporaryRam -=3D sizeof(UINT32) * 2; > + Count =3D *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof > (UINT32)); > + Size =3D Count * sizeof (UINT32); > + > + Ticker =3D *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - = Size - > sizeof (UINT32) * 2); > + Performance->ResetEnd =3D GetTimeInNanoSecond (Ticker); > + > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra > pperPlatformSecLib/SecPlatformInformation.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/SecPlatformInformation.c > new file mode 100644 > index 0000000000..e05daa8784 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/SecPlatformInformation.c > @@ -0,0 +1,79 @@ > +/** @file > + Provide SecPlatformInformation function. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +#include > +#include > + > +#include > +#include > + > +/** > + This interface conveys state information out of the Security (SEC) pha= se into > PEI. > + > + @param[in] PeiServices Pointer to the PEI Services T= able. > + @param[in,out] StructureSize Pointer to the variable descr= ibing > size of the input buffer. > + @param[out] PlatformInformationRecord Pointer to the > EFI_SEC_PLATFORM_INFORMATION_RECORD. > + > + @retval EFI_SUCCESS The data was successfully returned. > + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. > + > +**/ > +EFI_STATUS > +EFIAPI > +SecPlatformInformation ( > + IN CONST EFI_PEI_SERVICES **PeiServices, > + IN OUT UINT64 *StructureSize, > + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD > *PlatformInformationRecord > + ) > +{ > + UINT32 *Bist; > + UINT32 Size; > + UINT32 Count; > + UINT32 TopOfTemporaryRam; > + VOID *TopOfTemporaryRamPpi; > + EFI_STATUS Status; > + > + DEBUG ((DEBUG_INFO, "SecPlatformInformation\n")); > + > + Status =3D (*PeiServices)->LocatePpi ( > + PeiServices, > + &gTopOfTemporaryRamPpiGuid, > + 0, > + NULL, > + (VOID **) &TopOfTemporaryRamPpi > + ); > + if (EFI_ERROR (Status)) { > + return EFI_NOT_FOUND; > + } > + > + // > + // The entries of BIST information, together with the number of them, > + // reside in the bottom of stack, left untouched by normal stack opera= tion. > + // This routine copies the BIST information to the buffer pointed by > + // PlatformInformationRecord for output. > + // > + TopOfTemporaryRam =3D (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof > (UINT32); > + TopOfTemporaryRam -=3D sizeof(UINT32) * 2; > + Count =3D *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof > (UINT32))); > + Size =3D Count * sizeof (IA32_HANDOFF_STATUS); > + > + if ((*StructureSize) < (UINT64) Size) { > + *StructureSize =3D Size; > + return EFI_BUFFER_TOO_SMALL; > + } > + > + *StructureSize =3D Size; > + Bist =3D (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - = Size); > + > + CopyMem (PlatformInformationRecord, Bist, Size); > + > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra > pperPlatformSecLib/SecRamInitData.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/SecRamInitData.c > new file mode 100644 > index 0000000000..04f12a9438 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/SecRamInitData.c > @@ -0,0 +1,37 @@ > +/** @file > + Provide TempRamInitParams data. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include "FsptCoreUpd.h" > + > +typedef struct { > + FSP_UPD_HEADER FspUpdHeader; > + FSPT_CORE_UPD FsptCoreUpd; > +} FSPT_UPD_CORE_DATA; > + > +GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA > FsptUpdDataPtr =3D { > + { > + 0x4450555F54505346, > + 0x00, > + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > + } > + }, > + { > + ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + > FixedPcdGet32 (PcdFlashMicrocodeOffset)), > + ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - > FixedPcdGet32 (PcdFlashMicrocodeOffset)), > + 0, // Set CodeRegionBase as 0, so that caching will be > 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used. > + FixedPcdGet32 (PcdFlashCodeCacheSize), > + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > + } > + } > +}; > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra > pperPlatformSecLib/SecTempRamDone.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/SecTempRamDone.c > new file mode 100644 > index 0000000000..6d65d7d23f > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/SecTempRamDone.c > @@ -0,0 +1,48 @@ > +/** @file > + Provide SecTemporaryRamDone function. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > +This interface disables temporary memory in SEC Phase. > +**/ > +VOID > +EFIAPI > +SecPlatformDisableTemporaryMemory ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + VOID *TempRamExitParam; > + > + DEBUG((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n")); > + > + Status =3D BoardInitBeforeTempRamExit (); > + ASSERT_EFI_ERROR (Status); > + > + TempRamExitParam =3D UpdateTempRamExitParam (); > + Status =3D CallTempRamExit (TempRamExitParam); > + DEBUG((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status)); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D BoardInitAfterTempRamExit (); > + ASSERT_EFI_ERROR (Status); > + > + return ; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpi > TimerLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpi > TimerLib.c > new file mode 100644 > index 0000000000..7bdb3943e5 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpi > TimerLib.c > @@ -0,0 +1,48 @@ > +/** @file > + ACPI Timer implements one instance of Timer Library. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > + > +/** > + Calculate TSC frequency. > + > + The TSC counting frequency is determined by comparing how far it count= s > + during a 101.4 us period as determined by the ACPI timer. > + The ACPI timer is used because it counts at a known frequency. > + The TSC is sampled, followed by waiting 363 counts of the ACPI timer, > + or 101.4 us. The TSC is then sampled again. The difference multiplied = by > + 9861 is the TSC frequency. There will be a small error because of the > + overhead of reading the ACPI timer. An attempt is made to determine an= d > + compensate for this error. > + > + @return The number of TSC counts per second. > + > +**/ > +UINT64 > +InternalCalculateTscFrequency ( > + VOID > + ); > + > +/** > + Internal function to retrieves the 64-bit frequency in Hz. > + > + Internal function to retrieves the 64-bit frequency in Hz. > + > + @return The frequency in Hz. > + > +**/ > +UINT64 > +InternalGetPerformanceCounterFrequency ( > + VOID > + ) > +{ > + return InternalCalculateTscFrequency (); > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/ > BaseGpioExpanderLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/ > BaseGpioExpanderLib.c > new file mode 100644 > index 0000000000..8498952888 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/ > BaseGpioExpanderLib.c > @@ -0,0 +1,310 @@ > +/** @file > + Support for IO expander TCA6424. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > + > +// > +// Addresses of registers inside expander > +// > +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mInputRegister[3] =3D > {0x0,0x1,0x2}; > +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mOutputRegister[3] =3D > {0x4,0x5,0x6}; > +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mConfigRegister[3] =3D > {0xC,0xD,0xE}; > +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPolarityRegister[3] =3D > {0x8,0x9,0xA}; > + > +#define PCH_SERIAL_IO_I2C4 4 > +#define TCA6424_I2C_ADDRESS 0x22 > +#define PINS_PER_REGISTER 8 > +#define GPIO_EXP_PIN_DIRECTION_OUT 1 > +#define GPIO_EXP_PIN_DIRECTION_IN 0 > +#define GPIO_EXP_PIN_POLARITY_NORMAL 0 > +#define GPIO_EXP_PIN_POLARITY_INVERTED 1 > +#define GPIO_EXP_SET_OUTPUT 0 > +#define GPIO_EXP_SET_DIR 1 > +#define GPIO_EXP_GET_INPUT 2 > +#define GPIO_EXP_SET_POLARITY 3 > +#define AUTO_INCREMENT 0x80 > + > +/** > + Returns the Controller on which GPIO expander is present. > + > + This function returns the Controller value > + > + @param[out] Controller Pointer to a Controller value on > + which I2C expander is configured. > + > + @retval EFI_SUCCESS non. > +**/ > +EFI_STATUS > +GpioExpGetController ( > + OUT UINT8 *Controller > + ) > +{ > + *Controller =3D PCH_SERIAL_IO_I2C4; > + return EFI_SUCCESS; > +} > + > +/** > + Returns the data from register value giving in the input. > + > + This function is to get the data from the Expander > + Registers by following the I2C Protocol communication > + > + > + @param[in] Bar0 Bar address of the SerialIo Controller > + @param[in] Address Expander Value with in the Contoller > + @param[in] Register Address of Input/Output/Configure/Polarity > + registers with in the Expander > + > + @retval UINT8 Value returned from the register > +**/ > +UINT8 > +GpioExpGetRegister ( > + IN UINTN Bar0, > + IN UINT8 Address, > + IN UINT8 Register > + ) > +{ > + EFI_STATUS Status; > + UINT8 WriBuf[1]; > + UINT8 ReBuf[1] =3D {0}; > + > + WriBuf[0] =3D Register; > + Status =3D I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 1, WriBuf,= 1, > ReBuf, WAIT_1_SECOND); > + > + return ReBuf[0]; > +} > +/** > + Set the input register to a give value mentioned in the function. > + > + This function is to Programm the data value to the Expander > + Register by following the I2C Protocol communication. > + > + @param[in] Bar0 Bar address of the SerialIo Controller > + @param[in] Address Expander Value with in the Contoller > + @param[in] Register Address of Input/Output/Configure/Polarity > + registers with in the Expander > + @param[in] Value Value to set in the mentioned the register > +**/ > +VOID > +GpioExpSetRegister ( > + IN UINTN Bar0, > + IN UINT8 Address, > + IN UINT8 Register, > + IN UINT8 Value > + ) > +{ > + EFI_STATUS Status; > + UINT8 WriBuf[2]; > + > + WriBuf[0] =3D Register; > + WriBuf[1] =3D Value; > + Status =3D I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 2, WriBuf,= 0, > NULL, WAIT_1_SECOND); > + > +} > +/** > + Set the input register to a give value mentioned in the function. > + > + This function is to update the status of the Gpio Expander > + pin based on the input Operation value of the caller.This > + function calculates the exact address of the register with > + the help of the Register Bank > + > + @param[in] Controller SerialIo Controller value > + @param[in] Expander Expander Value with in the Contoller > + @param[in] Pin Pin with in the Expnader Value > + @param[in] Value none > + @param[in] Operation Type of operation (Setoutput/Setdirection > + /Getinput/Setpolarity) > + @retval UINT8 Final Value returned from the register > +**/ > +UINT8 > +GpioExpDecodeRegAccess ( > + IN UINT8 Controller, > + IN UINT8 Expander, > + IN UINT8 Pin, > + IN UINT8 Value, > + IN UINT8 Operation > + ) > +{ > + UINT8* RegisterBank; > + UINT8 OldValue; > + UINT8 NewValue; > + UINT8 RegisterAddress; > + UINT8 PinNumber; > + UINT8 ReturnValue =3D 0; > + > + DEBUG ((DEBUG_INFO, "GpioExpDecodeRegAccess() %x:%x:%x:%x:%x\n", > Controller, Expander, Pin, Value, Operation)); > + ASSERT(Controller<6); > + ASSERT(Expander<2); > + ASSERT(Pin<24); > + ASSERT(Value<2); > + ASSERT(Operation<4); > + // > + // Find the register Address value based on the OPeration > + // > + switch(Operation) { > + case GPIO_EXP_SET_OUTPUT: > + RegisterBank =3D mOutputRegister; > + break; > + case GPIO_EXP_SET_DIR: > + RegisterBank =3D mConfigRegister; > + break; > + case GPIO_EXP_GET_INPUT: > + RegisterBank =3D mInputRegister; > + break; > + case GPIO_EXP_SET_POLARITY: > + RegisterBank =3D mPolarityRegister; > + break; > + default: > + ASSERT(FALSE); > + return 0; > + } > + // > + // Each bit of register represents each Pin > + // calaulate the register address and Pinnumber(offset with in registe= r) > + // > + if (Pin >=3D 24) { > + // > + // Avoid out-of-bound usage of RegisterBank > + // > + return 0; > + } > + > + RegisterAddress =3D RegisterBank[(Pin/PINS_PER_REGISTER)]; > + PinNumber =3D Pin%PINS_PER_REGISTER; > + > + OldValue =3D GpioExpGetRegister(FindSerialIoBar(Controller, 0), Expand= er, > RegisterAddress); > + // > + // If it to get the data ,just returned otherwise mark the input value= and > write the register > + // > + if (Operation =3D=3D GPIO_EXP_GET_INPUT) { > + ReturnValue =3D 0x1 & (OldValue>>PinNumber); > + } else { > + NewValue =3D OldValue; > + NewValue &=3D ~(BIT0< + NewValue |=3D (Value< + if(NewValue!=3DOldValue) { > + GpioExpSetRegister(FindSerialIoBar(Controller, 0), Expander, > RegisterAddress, NewValue); > + } > + } > + return ReturnValue; > +} > +/** > + Set the Output value for the given Expander Gpio pin. > + > + This function is to Set the Output value for the GPIO > + Pin within the giving Expander. > + > + @param[in] Expander Expander Value with in the Contoller > + @param[in] Pin Pin with in the Expnader Value > + @param[in] Value none > + > +**/ > +VOID > +GpioExpSetOutput ( > + IN UINT8 Expander, > + IN UINT8 Pin, > + IN UINT8 Value > + ) > +{ > + UINT8 Controller; > + if(!EFI_ERROR(GpioExpGetController(&Controller))) { > + > GpioExpDecodeRegAccess(Controller,Expander,Pin,Value,GPIO_EXP_SET_OUT > PUT); > + } > +} > +/** > + Set the Direction value for the given Expander Gpio pin. > + > + This function is to Set the direction value for the GPIO > + Pin within the giving Expander. > + > + @param[in] Expander Expander Value with in the Contoller > + @param[in] Pin Pin with in the Expnader Value > + @param[in] Value none > +**/ > +VOID > +GpioExpSetDirection ( > + IN UINT8 Expander, > + IN UINT8 Pin, > + IN UINT8 Value > + ) > +{ > + > + UINT8 Controller; > + if(!EFI_ERROR(GpioExpGetController(&Controller))) { > + > GpioExpDecodeRegAccess(Controller,Expander,Pin,Value,GPIO_EXP_SET_DIR) > ; > + } > +} > + > + > +/** > + Get the input value for the given Expander Gpio pin. > + > + This function is to get the input value for the GPIO > + Pin within the giving Expander. > + > + @param[in] Expander Expander Value with in the Contoller > + @param[in] Pin Pin with in the Expnader Value > + > + @retval UINT8 Final Value returned from the register > +**/ > +UINT8 > +GpioExpGetInput ( > + IN UINT8 Expander, > + IN UINT8 Pin > + ) > +{ > + UINT8 Controller; > + if(!EFI_ERROR(GpioExpGetController(&Controller))) { > + return > GpioExpDecodeRegAccess(Controller,Expander,Pin,0,GPIO_EXP_GET_INPUT); > + } > + return 0; > +} > + > +/** > + Configures all registers of a single IO Expander in one go. > + > + @param[in] Expander Expander number (0/1) > + @param[in] Direction Bit-encoded direction values. BIT0 is for pin0= , etc. > 0=3Doutput, 1=3Dinput > + @param[in] Polarity Bit-encoded input inversion values. BIT0 is fo= r pin0, > etc. 0=3Dnormal, 1=3Dinversion > + @param[in] Output Bit-encoded output state, ignores polarity, on= ly > applicable if direction=3DINPUT. BIT0 is for pin0, etc. 0=3Dlow, 1=3Dhigh > + > +**/ > +VOID > +GpioExpBulkConfig ( > + IN UINT8 Expander, > + IN UINT32 Direction, > + IN UINT32 Polarity, > + IN UINT32 Output > + ) > +{ > + UINT8 WriteBuf[4]; > + UINT8 Controller; > + > + GpioExpGetController(&Controller); > + > + WriteBuf[0] =3D mOutputRegister[0] + AUTO_INCREMENT; > + WriteBuf[1] =3D Output & 0xFF; > + WriteBuf[2] =3D (Output>>8) & 0xFF; > + WriteBuf[3] =3D (Output>>16) & 0xFF; > + I2cWriteRead( FindSerialIoBar(Controller,0), > TCA6424_I2C_ADDRESS+Expander, 4, WriteBuf, 0, NULL, WAIT_1_SECOND); > + WriteBuf[0] =3D mPolarityRegister[0] + AUTO_INCREMENT; > + WriteBuf[1] =3D Polarity & 0xFF; > + WriteBuf[2] =3D (Polarity>>8) & 0xFF; > + WriteBuf[3] =3D (Polarity>>16) & 0xFF; > + I2cWriteRead( FindSerialIoBar(Controller,0), > TCA6424_I2C_ADDRESS+Expander, 4, WriteBuf, 0, NULL, WAIT_1_SECOND); > + WriteBuf[0] =3D mConfigRegister[0] + AUTO_INCREMENT; > + WriteBuf[1] =3D Direction & 0xFF; > + WriteBuf[2] =3D (Direction>>8) & 0xFF; > + WriteBuf[3] =3D (Direction>>16) & 0xFF; > + I2cWriteRead( FindSerialIoBar(Controller,0), > TCA6424_I2C_ADDRESS+Expander, 4, WriteBuf, 0, NULL, WAIT_1_SECOND); > + > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei > HdaVerbTableLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pe > iHdaVerbTableLib.c > new file mode 100644 > index 0000000000..b8afd791f0 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pe > iHdaVerbTableLib.c > @@ -0,0 +1,132 @@ > +/** @file > + This file is SampleCode of the library for Intel HD Audio Verb Table > configuration. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "PchHdaVerbTables.h" > + > +/** > + Add verb table helper function. > + This function calculates verbtable number and shows verb table > information. > + > + @param[in,out] VerbTableEntryNum Input current VerbTable number > and output the number after adding new table > + @param[in,out] VerbTableArray Pointer to array of VerbTable > + @param[in] VerbTable VerbTable which is going to add = into > array > +**/ > +STATIC > +VOID > +InternalAddVerbTable ( > + IN OUT UINT8 *VerbTableEntryNum, > + IN OUT UINT32 *VerbTableArray, > + IN HDAUDIO_VERB_TABLE *VerbTable > + ) > +{ > + if (VerbTable =3D=3D NULL) { > + DEBUG ((DEBUG_INFO, "InternalAddVerbTable wrong input: VerbTable =3D= =3D > NULL\n")); > + return; > + } > + > + VerbTableArray[*VerbTableEntryNum] =3D (UINT32) VerbTable; > + *VerbTableEntryNum +=3D 1; > + > + DEBUG ((DEBUG_INFO, > + "HDA: Add verb table for vendor =3D 0x%04X devId =3D 0x%04X (size = =3D %d > DWords)\n", > + VerbTable->Header.VendorId, > + VerbTable->Header.DeviceId, > + VerbTable->Header.DataDwords) > + ); > +} > + > +/** > + Add verb table function. > + This function update the verb table number and verb table ptr of polic= y. > + > + @param[in] HdAudioConfig HD Audio config block > + @param[out] VerbTableEntryNum Number of verb table entries > + @param[out] HdaVerbTablePtr Pointer to the verb table > +**/ > +VOID > +AddPlatformVerbTables ( > + IN UINT8 CodecType, > + OUT UINT8 *VerbTableEntryNum, > + OUT UINT32 *HdaVerbTablePtr > + ) > +{ > + UINT8 VerbTableEntries; > + UINT32 VerbTableArray[6]; > + UINT32 *VerbTablePtr; > + > + VerbTableEntries =3D 0; > + > + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN= TN) > PcdGet32 (PcdDisplayAudioHdaVerbTable)); > + > + if (CodecType =3D=3D PchHdaCodecPlatformOnboard) { > + DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n")); > + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) > (UINTN) PcdGet32 (PcdHdaVerbTable)); > + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) > (UINTN) PcdGet32 (PcdHdaVerbTable2)); > + } else { > + DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n")); > + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) > (UINTN) PcdGet32 (PcdCommonHdaVerbTable1)); > + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) > (UINTN) PcdGet32 (PcdCommonHdaVerbTable2)); > + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) > (UINTN) PcdGet32 (PcdCommonHdaVerbTable3)); > + } > + > + *VerbTableEntryNum =3D VerbTableEntries; > + > + VerbTablePtr =3D (UINT32 *) AllocateZeroPool (sizeof (UINT32) * > VerbTableEntries); > + CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * > VerbTableEntries); > + *HdaVerbTablePtr =3D (UINT32) VerbTablePtr; > +} > + > +/** > + HDA VerbTable init function for PEI post memory phase. > + > + @param[in] BoardId An unsigned integrer represent the board id. > + > + @retval EFI_SUCCESS The function completed successfully. > +**/ > +EFI_STATUS > +HdaVerbTableInit ( > + IN UINT16 BoardId > + ) > +{ > + HDAUDIO_VERB_TABLE *VerbTable; > + HDAUDIO_VERB_TABLE *VerbTable2; > + > + VerbTable =3D NULL; > + VerbTable2 =3D NULL; > + > + switch (BoardId) { > + > + case BoardIdWhiskeyLakeRvp: > + VerbTable =3D &WhlHdaVerbTableAlc700; > + break; > + > + default: > + DEBUG ((DEBUG_INFO, "HDA: Init default verb tables (Realtek ALC700 > and ALC701)\n")); > + VerbTable =3D &HdaVerbTableAlc700; > + VerbTable2 =3D &HdaVerbTableAlc701; > + break; > + } > + > + PcdSet32S (PcdHdaVerbTable, (UINT32) VerbTable); > + PcdSet32S (PcdHdaVerbTable2, (UINT32) VerbTable2); > + PcdSet32S (PcdDisplayAudioHdaVerbTable, (UINT32) > &HdaVerbTableDisplayAudio); > + > + // Codecs - Realtek ALC700, ALC701, ALC274 (external - connected via H= DA > header) > + PcdSet32S (PcdCommonHdaVerbTable1, (UINT32) &HdaVerbTableAlc700); > + PcdSet32S (PcdCommonHdaVerbTable2, (UINT32) &HdaVerbTableAlc701); > + PcdSet32S (PcdCommonHdaVerbTable3, (UINT32) &HdaVerbTableAlc274); > + > + return EFI_SUCCESS; > +} > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cA > ccessLib.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cA > ccessLib.c > new file mode 100644 > index 0000000000..70f531daca > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cA > ccessLib.c > @@ -0,0 +1,115 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +EFI_STATUS > +I2cWriteRead ( > + IN UINTN MmioBase, > + IN UINT8 SlaveAddress, > + IN UINT8 WriteLength, > + IN UINT8 *WriteBuffer, > + IN UINT8 ReadLength, > + IN UINT8 *ReadBuffer, > + IN UINT64 TimeBudget > + //TODO: add Speed parameter > + ) > +{ > + UINT8 ReadsNeeded =3D ReadLength; > + UINT64 CutOffTime; > + > + if ((WriteLength =3D=3D 0 && ReadLength =3D=3D 0) || > + (WriteLength !=3D 0 && WriteBuffer =3D=3D NULL) || > + (ReadLength !=3D 0 && ReadBuffer =3D=3D NULL) ) { > + DEBUG ((DEBUG_ERROR, "I2cWR Invalid Parameters\n")); > + return EFI_INVALID_PARAMETER; > + } > + > + // > + // Sanity checks to verify the I2C controller is alive > + // Conveniently, ICON register's values of 0 or FFFFFFFF indicate > + // I2c controller is out-of-order: either disabled, in D3 or in reset. > + // > + if (MmioRead32(MmioBase+R_IC_CON) =3D=3D 0xFFFFFFFF || > MmioRead32(MmioBase+R_IC_CON) =3D=3D 0x0) { > + DEBUG ((DEBUG_ERROR, "I2cWR Device Error\n")); > + return EFI_DEVICE_ERROR; > + } > + > + MmioWrite32(MmioBase+R_IC_ENABLE, 0x0); > + MmioRead32(MmioBase+0x40); > + MmioRead32(MmioBase+R_IC_CLR_TX_ABRT); > + MmioWrite32(MmioBase+R_IC_SDA_HOLD, 0x001C001C); > + // > + // Set I2C Bus Speed at 400 kHz for GPIO Expander > + // > + MmioWrite32(MmioBase + R_IC_FS_SCL_HCNT, 128); > + MmioWrite32(MmioBase + R_IC_FS_SCL_LCNT, 160); > + MmioWrite32(MmioBase + R_IC_TAR, SlaveAddress); > + MmioWrite32(MmioBase + R_IC_CON, B_IC_MASTER_MODE | > V_IC_SPEED_FAST | B_IC_RESTART_EN | B_IC_SLAVE_DISABLE ); > + MmioWrite32(MmioBase+R_IC_ENABLE, 0x1); > + CutOffTime =3D AsmReadTsc() + TimeBudget; > + > + while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D0 ) { > + if (AsmReadTsc() > CutOffTime) { > + DEBUG ((DEBUG_ERROR, "I2cWR timeout\n")); > + return EFI_TIMEOUT; > + } > + } > + > + while(1) { > + if(MmioRead32(MmioBase+R_IC_INTR_STAT) & B_IC_INTR_TX_ABRT) { > + DEBUG ((DEBUG_ERROR, "I2cWR Transfer aborted, reason =3D > 0x%08x\n",MmioRead32(MmioBase+R_IC_TX_ABRT_SOURCE))); > + MmioRead32(MmioBase+R_IC_CLR_TX_ABRT); > + MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE); > + while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {} > + return EFI_DEVICE_ERROR; > + } > + if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_TFNF) { > + if (WriteLength > 1) { > + MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer); > + WriteBuffer++; > + WriteLength--; > + } else if (WriteLength=3D=3D1 && ReadLength !=3D 0) { > + MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer); > + WriteBuffer++; > + WriteLength--; > + } else if (WriteLength=3D=3D1 && ReadLength =3D=3D 0) { > + MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer | > B_IC_CMD_STOP); > + WriteBuffer++; > + WriteLength--; > + } else if (ReadLength > 1) { > + MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ); > + ReadLength--; > + } else if (ReadLength =3D=3D 1) { > + MmioWrite32(MmioBase+R_IC_DATA_CMD, > B_IC_CMD_READ|B_IC_CMD_STOP); > + ReadLength--; > + } > + } > + > + if (ReadsNeeded) { > + if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_RFNE) { > + *ReadBuffer =3D (UINT8)MmioRead32(MmioBase+R_IC_DATA_CMD); > + ReadBuffer++; > + ReadsNeeded--; > + } > + } > + if (WriteLength=3D=3D0 && ReadsNeeded=3D=3D0 > && !(MmioRead32(MmioBase+R_IC_STATUS)&B_IC_STATUS_ACTIVITY)) { > + MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE); > + while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {} > + DEBUG ((DEBUG_INFO, "I2cWR success\n")); > + return EFI_SUCCESS; > + } > + if (AsmReadTsc() > CutOffTime) { > + MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE); > + while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {} > + DEBUG ((DEBUG_ERROR, "I2cWR wrong ENST value\n")); > + return EFI_TIMEOUT; > + } > + > + } > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeCpuPolicyUpdate.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeCpuPolicyUpdate.c > new file mode 100644 > index 0000000000..7b9a32b3f5 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeCpuPolicyUpdate.c > @@ -0,0 +1,88 @@ > +/** @file > + This file is the library for CPU DXE Policy initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +/** > + This function prints the CPU DXE phase policy. > + > + @param[in] DxeCpuPolicy - CPU DXE Policy protocol > +**/ > +VOID > +CpuDxePrintPolicyProtocol ( > + IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy > + ) > +{ > + DEBUG_CODE_BEGIN (); > + DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print= BEGIN > -----------------\n")); > + DEBUG ((DEBUG_INFO, "Revision : %x\n", DxeCpuPolicy->Revision)); > + ASSERT (DxeCpuPolicy->Revision =3D=3D > DXE_CPU_POLICY_PROTOCOL_REVISION); > + DEBUG ((DEBUG_INFO, "\n------------------------ CPU_DXE_CONFIG > -----------------\n")); > + DEBUG ((DEBUG_INFO, "EnableDts : %x\n", DxeCpuPolicy->EnableDts)); > + DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print= END > -----------------\n")); > + DEBUG_CODE_END (); > +} > + > +/** > + Get data for CPU policy from setup options. > + > + @param[in] DxeCpuPolicy The pointer to get CPU Policy pro= tocol > instance > + > + @retval EFI_SUCCESS Operation success. > + > +**/ > +EFI_STATUS > +EFIAPI > +UpdateDxeSiCpuPolicy ( > + IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy > + ) > +{ > + return EFI_SUCCESS; > +} > + > +/** > + CpuInstallPolicyProtocol installs CPU Policy. > + While installed, RC assumes the Policy is ready and finalized. So plea= se > update and override > + any setting before calling this function. > + > + @param[in] ImageHandle Image handle of this driver. > + @param[in] DxeCpuPolicy The pointer to CPU Policy Protoc= ol > instance > + > + @retval EFI_SUCCESS The policy is installed. > + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create > buffer > + > +**/ > +EFI_STATUS > +EFIAPI > +CpuInstallPolicyProtocol ( > + IN EFI_HANDLE ImageHandle, > + IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy > + ) > +{ > + EFI_STATUS Status; > + > + /// > + /// Print CPU DXE Policy > + /// > + CpuDxePrintPolicyProtocol(DxeCpuPolicy); > + > + /// > + /// Install the DXE_CPU_POLICY_PROTOCOL interface > + /// > + Status =3D gBS->InstallMultipleProtocolInterfaces ( > + &ImageHandle, > + &gDxeCpuPolicyProtocolGuid, > + DxeCpuPolicy, > + NULL > + ); > + ASSERT_EFI_ERROR (Status); > + > + return Status; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeMePolicyUpdate.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeMePolicyUpdate.c > new file mode 100644 > index 0000000000..863df3328c > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeMePolicyUpdate.c > @@ -0,0 +1,105 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "DxeMePolicyUpdate.h" > + > +// > +// Record version > +// > +#define RECORD_REVISION_1 0x01 > +#define MAX_FW_UPDATE_BIOS_SELECTIONS 2 > + > +// > +// Function implementations executed during policy initialization phase > +// > + > +/** > + Update the ME Policy Library > + > + @param[in, out] DxeMePolicy The pointer to get ME Policy pro= tocol > instance > + > + @retval EFI_SUCCESS Initialization complete. > + @retval EFI_UNSUPPORTED The chipset is unsupported by th= is > driver. > + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver. > + @retval EFI_DEVICE_ERROR Device error, driver exits abnor= mally. > + > +**/ > +EFI_STATUS > +EFIAPI > +UpdateDxeMePolicy ( > + IN OUT ME_POLICY_PROTOCOL *DxeMePolicy > + ) > +{ > + EFI_STATUS Status; > + EFI_EVENT EndOfDxeEvent; > + > + DEBUG ((DEBUG_INFO, "UpdateDxeMePolicy\n")); > + UpdateMePolicyFromSetup (DxeMePolicy); > + UpdateMePolicyFromMeSetup (DxeMePolicy); > + > + // > + // Register End of DXE event > + // > + Status =3D gBS->CreateEventEx ( > + EVT_NOTIFY_SIGNAL, > + TPL_NOTIFY, > + UpdateMeSetupCallback, > + NULL, > + &gEfiEndOfDxeEventGroupGuid, > + &EndOfDxeEvent > + ); > + ASSERT_EFI_ERROR (Status); > + return Status; > +} > + > +/** > + Update ME Policy while MePlatformProtocol is installed. > + > + @param[in] MePolicyInstance Instance of ME Policy Protocol > + > +**/ > +VOID > +UpdateMePolicyFromMeSetup ( > + IN ME_POLICY_PROTOCOL *MePolicyInstance > + ) > +{ > + > +} > + > +/** > + Update ME Policy if Setup variable exists. > + > + @param[in, out] MePolicyInstance Instance of ME Policy Protocol > + > +**/ > +VOID > +UpdateMePolicyFromSetup ( > + IN OUT ME_POLICY_PROTOCOL *MePolicyInstance > + ) > +{ > + > +} > + > +/** > + Functions performs HECI exchange with FW to update MePolicy settings. > + > + @param[in] Event A pointer to the Event that triggered the cal= lback. > + @param[in] Context A pointer to private data registered with the > callback function. > + > +**/ > +VOID > +EFIAPI > +UpdateMeSetupCallback ( > + IN EFI_EVENT Event, > + IN VOID *Context > + ) > +{ > + gBS->CloseEvent (Event); > + > + return; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxePchPolicyUpdate.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxePchPolicyUpdate.c > new file mode 100644 > index 0000000000..7945986aaa > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxePchPolicyUpdate.c > @@ -0,0 +1,39 @@ > +/** @file > + This file is the library for PCH DXE Policy initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Get data for PCH policy from setup options. > + > + @param[in] PchPolicy The pointer to get PCH Policy pro= tocol > instance > + > + @retval EFI_SUCCESS Operation success. > + > +**/ > +EFI_STATUS > +EFIAPI > +UpdateDxePchPolicy ( > + IN OUT PCH_POLICY_PROTOCOL *PchPolicy > + ) > +{ > + EFI_STATUS Status; > + PCH_HDAUDIO_DXE_CONFIG *HdAudioDxeConfig; > + > + Status =3D GetConfigBlock ((VOID *)PchPolicy, &gHdAudioDxeConfigGuid, > (VOID *)&HdAudioDxeConfig); > + ASSERT_EFI_ERROR (Status); > + > + return Status; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeSaPolicyUpdate.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeSaPolicyUpdate.c > new file mode 100644 > index 0000000000..af4c76bcd0 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate > Lib/DxeSaPolicyUpdate.c > @@ -0,0 +1,57 @@ > +/** @file > + This file is the library for SA DXE Policy initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > + > +/** > + Get data for platform policy from setup options. > + > + @param[in] SaPolicy The pointer to get SA Policy prot= ocol > instance > + > + @retval EFI_SUCCESS Operation success. > + > +**/ > +EFI_STATUS > +EFIAPI > +UpdateDxeSaPolicy ( > + IN OUT SA_POLICY_PROTOCOL *SaPolicy > + ) > +{ > + EFI_STATUS Status; > + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; > + PCIE_DXE_CONFIG *PcieDxeConfig; > + MISC_DXE_CONFIG *MiscDxeConfig; > + MEMORY_DXE_CONFIG *MemoryDxeConfig; > + > + GraphicsDxeConfig =3D NULL; > + PcieDxeConfig =3D NULL; > + MiscDxeConfig =3D NULL; > + MemoryDxeConfig =3D NULL; > + // > + // Get requisite IP Config Blocks which needs to be used here > + // > + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gGraphicsDxeConfigGuid, = (VOID > *)&GraphicsDxeConfig); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOI= D > *)&MiscDxeConfig); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gPcieDxeConfigGuid, (VOI= D > *)&PcieDxeConfig); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gMemoryDxeConfigGuid, (V= OID > *)&MemoryDxeConfig); > + ASSERT_EFI_ERROR (Status); > + > + PcieDxeConfig->PegAspmL0s[0] =3D 3; > + PcieDxeConfig->PegAspmL0s[1] =3D 3; > + PcieDxeConfig->PegAspmL0s[2] =3D 3; > + > + return EFI_SUCCESS; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiPolicyInit.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiPolicyInit.c > new file mode 100644 > index 0000000000..93be38a832 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiPolicyInit.c > @@ -0,0 +1,65 @@ > +/** @file > + This file is SampleCode for Intel PEI Platform Policy initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiPolicyInit.h" > + > +/** > + Initialize Intel PEI Platform Policy > + > + @param[in] PeiServices General purpose services available t= o every > PEIM. > + @param[in] FirmwareConfiguration It uses to skip specific policy init= that > depends > + on the 'FirmwareConfiguration' varai= ble. > +**/ > +VOID > +EFIAPI > +PeiPolicyInit ( > + IN UINT8 FirmwareConfiguration > + ) > +{ > + EFI_STATUS Status; > + SI_POLICY_PPI *SiPolicyPpi; > + > + // > + // Call SiCreateConfigBlocks to initialize Silicon Policy structure > + // and get all Intel default policy settings. > + // > + Status =3D SiCreateConfigBlocks (&SiPolicyPpi); > + ASSERT_EFI_ERROR (Status); > + if (EFI_ERROR(Status)) { > + return; > + } > + > + if (PcdGetBool (PcdDumpDefaultSiliconPolicy)) { > + DEBUG ((DEBUG_INFO, "Dump Default Silicon Policy...\n")); > + DumpSiPolicy (SiPolicyPpi); > + } > + > + // > + // Update policy by board configuration > + // > + UpdatePeiSiPolicyBoardConfig (SiPolicyPpi); > + UpdatePeiPchPolicyBoardConfig (SiPolicyPpi); > + UpdatePeiSaPolicyBoardConfig (SiPolicyPpi); > + UpdatePeiCpuPolicyBoardConfig (SiPolicyPpi); > + UpdatePeiMePolicyBoardConfig (SiPolicyPpi); > + > + UpdatePeiSiPolicy(SiPolicyPpi); > + UpdatePeiPchPolicy(SiPolicyPpi); > + UpdatePeiSaPolicy(SiPolicyPpi); > + UpdatePeiCpuPolicy(SiPolicyPpi); > + UpdatePeiMePolicy(SiPolicyPpi); > + > + // > + // Install SiPolicyPpi. > + // While installed, RC assumes the Policy is ready and finalized. So p= lease > + // update and override any setting before calling this function. > + // > + Status =3D SiInstallPolicyPpi (SiPolicyPpi); > + ASSERT_EFI_ERROR (Status); > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiPolicyInitPreMem.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiPolicyInitPreMem.c > new file mode 100644 > index 0000000000..9f8014b72a > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiPolicyInitPreMem.c > @@ -0,0 +1,60 @@ > +/** @file > + This file is SampleCode for Intel PEI Platform Policy initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiPolicyInit.h" > + > +/** > + Initialize Intel PEI Platform Policy > + > + @param[in] FirmwareConfiguration It uses to skip specific policy ini= t that > depends > + on the 'FirmwareConfiguration' vara= ible. > +**/ > +VOID > +EFIAPI > +PeiPolicyInitPreMem ( > + IN UINT8 FirmwareConfiguration > + ) > +{ > + EFI_STATUS Status; > + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > + > + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in > Pre-Memory...\n")); > + // > + // Call SiCreatePreMemConfigBlocks to initialize platform policy struc= ture > + // and get all intel default policy settings. > + // > + Status =3D SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi); > + ASSERT_EFI_ERROR (Status); > + > + // > + // Update policy by board configuration > + // > + UpdatePeiPchPolicyBoardConfigPreMem (SiPreMemPolicyPpi); > + UpdatePeiMePolicyBoardConfigPreMem (SiPreMemPolicyPpi); > + UpdatePeiSaPolicyBoardConfigPreMem (SiPreMemPolicyPpi); > + UpdatePeiCpuPolicyBoardConfigPreMem (SiPreMemPolicyPpi); > + > + // > + // Update and override all platform related and customized settings be= low. > + // > + UpdatePeiPchPolicyPreMem (SiPreMemPolicyPpi); > + UpdatePeiMePolicyPreMem (SiPreMemPolicyPpi); > + UpdatePeiSaPolicyPreMem (SiPreMemPolicyPpi); > + UpdatePeiCpuPolicyPreMem (SiPreMemPolicyPpi); > + > + // > + // Install SiPreMemPolicyPpi. > + // While installed, RC assumes the Policy is ready and finalized. So p= lease > + // update and override any setting before calling this function. > + // > + Status =3D SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi); > + ASSERT_EFI_ERROR (Status); > + > + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in > Pre-Memory\n")); > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiSaPolicyInit.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiSaPolicyInit.c > new file mode 100644 > index 0000000000..922bcd135f > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/ > PeiSaPolicyInit.c > @@ -0,0 +1,114 @@ > +/** @file > + This file is SampleCode for Intel SA PEI Policy initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiSaPolicyInit.h" > + > + > +/** > + PcieCardResetWorkAround performs PCIe Card reset on root port > + > + @param[in out] SiPreMemPolicyPpi SI_PREMEM_POLICY_PPI > + > + @retval EFI_SUCCESS The policy is installed and initializ= ed. > +**/ > +EFI_STATUS > + PcieCardResetWorkAround ( > + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi > + ) > +{ > + EFI_STATUS Status; > + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; > + SWITCHABLE_GRAPHICS_CONFIG *SgGpioData; > + > + Status =3D GetConfigBlock((VOID *)SiPreMemPolicyPpi, > &gSaMiscPeiPreMemConfigGuid, (VOID *)&MiscPeiPreMemConfig); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D GetConfigBlock((VOID *)SiPreMemPolicyPpi, > &gSwitchableGraphicsConfigGuid, (VOID *)&SgGpioData); > + ASSERT_EFI_ERROR(Status); > + > + if (SgGpioData->SaRtd3Pcie0Gpio.GpioSupport !=3D NotSupported) { > + /// > + /// dGPU is present. > + /// If PCIe Mode or SG Muxless > + /// Power on MXM > + /// Configure GPIOs to drive MXM in PCIe mode or SG Mux= less > + /// else > + /// Do Nothing > + /// > + if ((MiscPeiPreMemConfig->SgMode =3D=3D SgModeMuxless) || > + (MiscPeiPreMemConfig->SgMode =3D=3D SgModeDgpu)) { > + DEBUG((DEBUG_INFO, "Configure GPIOs for driving the dGPU.\n")); > + /// > + /// Drive DGPU HOLD RST Enable to make sure we hold reset > + /// > + PcieGpioWrite ( > + SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo, > + SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active, > + GP_ENABLE > + ); > + /// > + /// wait 100ms > + /// > + MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * > STALL_ONE_MILLI_SECOND); > + > + /// > + /// Drive DGPU PWR EN to Power On MXM > + /// > + PcieGpioWrite ( > + SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.GpioNo, > + SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.Active, > + GP_ENABLE > + ); > + /// > + /// wait 300ms > + /// > + MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterPwrEn) * > STALL_ONE_MILLI_SECOND); > + > + /// > + /// Drive DGPU HOLD RST Disabled to remove reset > + /// > + PcieGpioWrite ( > + SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo, > + SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active, > + GP_DISABLE > + ); > + /// > + /// wait 100ms > + /// > + MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * > STALL_ONE_MILLI_SECOND); > + } > + } > + return EFI_SUCCESS; > +} > + > +/** > + PCIe GPIO Write > + > + @param[in] Gpio - GPIO Number > + @param[in] Active - GPIO Active Information; High/Low > + @param[in] Level - Write GPIO value (0/1) > + > +**/ > +VOID > +PcieGpioWrite ( > + IN UINT32 Gpio, > + IN BOOLEAN Active, > + IN BOOLEAN Level > + ) > +{ > + EFI_STATUS Status; > + > + if (Active =3D=3D 0) { > + Level =3D (~Level) & 0x1; > + } > + Status =3D GpioSetOutputValue(Gpio, (UINT32)Level); > + if (Status !=3D EFI_SUCCESS) { > + return; > + } > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiCpuPolicyUpdate.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiCpuPolicyUpdate.c > new file mode 100644 > index 0000000000..144480a83d > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiCpuPolicyUpdate.c > @@ -0,0 +1,80 @@ > +/** @file > + CPU PEI Policy Update & initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiCpuPolicyUpdate.h" > +#include > +#include > +#include > +#include > + > +/** > + This function performs CPU PEI Policy initialization. > + > + @param[in] SiPolicyPpi The SI Policy PPI instance > + > + @retval EFI_SUCCESS The PPI is installed and initialized. > + @retval EFI ERRORS The PPI is not successfully installed= . > + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver > +**/ > +EFI_STATUS > +EFIAPI > +UpdatePeiCpuPolicy ( > + IN OUT SI_POLICY_PPI *SiPolicyPpi > + ) > +{ > + EFI_STATUS Status; > + CPU_CONFIG *CpuConfig; > + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig; > + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > + CPU_POWER_MGMT_CUSTOM_CONFIG > *CpuPowerMgmtCustomConfig; > + CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig; > + CPU_TEST_CONFIG *CpuTestConfig; > + > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOI= D *) > &CpuConfig); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, > &gCpuPowerMgmtBasicConfigGuid, (VOID *) &CpuPowerMgmtBasicConfig); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D GetConfigBlock((VOID *)SiPolicyPpi, > &gCpuPowerMgmtCustomConfigGuid, (VOID > *)&CpuPowerMgmtCustomConfig); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D GetConfigBlock((VOID *)SiPolicyPpi, &gCpuTestConfigGuid, (V= OID > *)&CpuTestConfig); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D PeiServicesLocatePpi ( > + &gSiPreMemPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPreMemPolicyPpi > + ); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D GetConfigBlock((VOID *)SiPolicyPpi, > &gCpuPowerMgmtTestConfigGuid, (VOID *)&CpuPowerMgmtTestConfig); > + ASSERT_EFI_ERROR(Status); > + > + // > + // Init Power Management Policy Variables > + // > + CpuPowerMgmtBasicConfig->HwpInterruptControl =3D 1; > + CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio =3D 0x4; > + CpuPowerMgmtBasicConfig->OneCoreRatioLimit =3D 0x22; > + CpuPowerMgmtBasicConfig->TwoCoreRatioLimit =3D 0x22; > + CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit =3D 0x22; > + CpuPowerMgmtBasicConfig->FourCoreRatioLimit =3D 0x22; > + CpuPowerMgmtBasicConfig->FiveCoreRatioLimit =3D 0; > + CpuPowerMgmtBasicConfig->SixCoreRatioLimit =3D 0; > + CpuPowerMgmtBasicConfig->SevenCoreRatioLimit =3D 0; > + CpuPowerMgmtBasicConfig->EightCoreRatioLimit =3D 0; > + CpuPowerMgmtBasicConfig->Hwp =3D 0x1; > + CpuTestConfig->CpuWakeUpTimer =3D 1; > + CpuPowerMgmtTestConfig->AutoThermalReporting =3D 0; > + > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiCpuPolicyUpdatePreMem.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiCpuPolicyUpdatePreMem.c > new file mode 100644 > index 0000000000..bce02a9c5a > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiCpuPolicyUpdatePreMem.c > @@ -0,0 +1,108 @@ > +/** @file > + This file is SampleCode of the library for Intel CPU PEI Policy initia= lization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiCpuPolicyUpdate.h" > +#include > +#include > +#include > +#include > +#include > + > +/** > + Check on the processor if SGX is supported. > + > + @retval True if SGX supported or FALSE if not > +**/ > +BOOLEAN > +IsSgxCapSupported ( > + VOID > + ) > +{ > + EFI_CPUID_REGISTER CpuidRegs; > + > + /// > + /// Processor support SGX feature by reading CPUID.(EAX=3D7,ECX=3D0):E= BX[2] > + /// > + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, > &CpuidRegs.RegEax,&CpuidRegs.RegEbx,&CpuidRegs.RegEcx,&CpuidRegs.Re > gEdx); > + > + /// > + /// SGX feature is supported only on WHL and later, > + /// with CPUID.(EAX=3D7,ECX=3D0):EBX[2]=3D1 > + /// PRMRR configuration enabled, MSR IA32_MTRRCAP (FEh) [12] =3D=3D 1 > + /// > + if ((CpuidRegs.RegEbx & BIT2) && (AsmReadMsr64 (MSR_IA32_MTRRCAP) & > BIT12)) { > + return TRUE; > + } > + > + return FALSE; > +} > + > +/** > + This function performs CPU PEI Policy initialization in Pre-memory. > + > + @param[in] SiPreMemPolicyPpi The SI Pre-Mem Policy PPI instance > + > + @retval EFI_SUCCESS The PPI is installed and initialized. > + @retval EFI ERRORS The PPI is not successfully installed= . > + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver > +**/ > +EFI_STATUS > +EFIAPI > +UpdatePeiCpuPolicyPreMem ( > + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi > + ) > +{ > + EFI_STATUS Status; > + EFI_BOOT_MODE BootMode; > + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; > + CPU_OVERCLOCKING_PREMEM_CONFIG > *CpuOverClockingPreMemConfig; > + UINT32 PchSpiBar0; > + UINT32 MaxLogicProcessors; > + > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, > &gCpuOverclockingPreMemConfigGuid, (VOID *) > &CpuOverClockingPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + > + DEBUG ((DEBUG_INFO, "UpdatePeiCpuPolicyPreMem Start\n")); > + > + // > + // Get current boot mode > + // > + Status =3D PeiServicesGetBootMode (&BootMode); > + ASSERT_EFI_ERROR (Status); > + > + SpiServiceInit (); > + > + PchSpiBar0 =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS ( > + DEFAULT_PCI_SEGMENT_NUMBER_PCH, > + DEFAULT_PCI_BUS_NUMBER_PCH, > + PCI_DEVICE_NUMBER_PCH_SPI, > + PCI_FUNCTION_NUMBER_PCH_SPI, > + R_SPI_CFG_BAR0 > + )); > + PchSpiBar0 &=3D ~(B_SPI_CFG_BAR0_MASK); > + > + if (PchSpiBar0 =3D=3D 0) { > + DEBUG ((DEBUG_ERROR, "ERROR : PchSpiBar0 is invalid!\n")); > + ASSERT (FALSE); > + } > + > + CpuConfigLibPreMemConfig->PeciC10Reset =3D 0; > + CpuConfigLibPreMemConfig->CpuRatio =3D 0; > + /// > + /// Set PcdCpuMaxLogicalProcessorNumber to max number of logical > processors enabled > + /// Read MSR_CORE_THREAD_COUNT (0x35) to check the total active > Threads > + /// > + MaxLogicProcessors =3D (UINT32) (AsmReadMsr64 > (MSR_CORE_THREAD_COUNT) & B_THREAD_COUNT_MASK); > + DEBUG ((DEBUG_INFO, "MaxLogicProcessors =3D %d\n", > MaxLogicProcessors)); > + PcdSet32S (PcdCpuMaxLogicalProcessorNumber, MaxLogicProcessors); > + > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiMePolicyUpdate.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiMePolicyUpdate.c > new file mode 100644 > index 0000000000..e557f04971 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiMePolicyUpdate.c > @@ -0,0 +1,49 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiMePolicyUpdate.h" > +#include > +#include > +#include > +#include > +#include > + > +/** > + Update the ME Policy Library > + > + @param[in, out] SiPolicyPpi The pointer to SiPolicyPpi > + > + @retval EFI_SUCCESS Update complete. > +**/ > +EFI_STATUS > +UpdatePeiMePolicy ( > + IN OUT SI_POLICY_PPI *SiPolicyPpi > + ) > +{ > + EFI_STATUS Status; > + ME_PEI_CONFIG *MePeiConfig; > + > + DEBUG ((DEBUG_INFO, "UpdatePeiMePolicy\n")); > + > + Status =3D EFI_SUCCESS; > + > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (V= OID *) > &MePeiConfig); > + ASSERT_EFI_ERROR (Status); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + if (!PmcIsRtcBatteryGood ()) { > + // > + // For non coin battery design, this can be skipped. > + // > + MePeiConfig->MeUnconfigOnRtcClear =3D 2; > + } > + > + return Status; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiMePolicyUpdatePreMem.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiMePolicyUpdatePreMem.c > new file mode 100644 > index 0000000000..de9849b807 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiMePolicyUpdatePreMem.c > @@ -0,0 +1,32 @@ > +/** @file > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiMePolicyUpdate.h" > +#include > +#include > +#include > + > +/** > + Update the ME Policy Library > + > + @param[in] SiPreMemPolicyPpi The pointer to SiPreMemPolicyPpi > + > + @retval EFI_SUCCESS Update complete. > +**/ > +EFI_STATUS > +UpdatePeiMePolicyPreMem ( > + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi > + ) > +{ > + EFI_STATUS Status; > + > + DEBUG ((DEBUG_INFO, "UpdatePeiMePolicyPreMem\n")); > + > + Status =3D EFI_SUCCESS; > + > + return Status; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiPchPolicyUpdate.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiPchPolicyUpdate.c > new file mode 100644 > index 0000000000..3e44c6cc29 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiPchPolicyUpdate.c > @@ -0,0 +1,523 @@ > +/** @file > + This file is SampleCode of the library for Intel PCH PEI Policy initia= lization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiPchPolicyUpdate.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +VOID > +UpdatePcieClockInfo ( > + PCH_PCIE_CONFIG *PcieRpConfig, > + UINTN Index, > + UINT64 Data > + ) > +{ > + PCD64_BLOB Pcd64; > + > + Pcd64.Blob =3D Data; > + DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, > Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, > Pcd64.PcieClock.ClkReqSupported)); > + > + PcieRpConfig->PcieClock[Index].Usage =3D > (UINT8)Pcd64.PcieClock.ClockUsage; > + if (Pcd64.PcieClock.ClkReqSupported) { > + PcieRpConfig->PcieClock[Index].ClkReq =3D (UINT8)Index; > + } else { > + PcieRpConfig->PcieClock[Index].ClkReq =3D 0xFF; > + } > +} > + > +/** > + This is helper function for getting I2C Pads Internal Termination sett= ings > from Pcd > + > + @param[in] Index I2C Controller Index > +**/ > +UINT8 > +GetSerialIoI2cPadsTerminationFromPcd ( > + IN UINT8 Index > +) > +{ > + switch (Index) { > + case 0: > + return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm); > + case 1: > + return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm); > + case 2: > + return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm); > + case 3: > + return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm); > + case 4: > + return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm); > + case 5: > + return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm); > + default: > + ASSERT (FALSE); // Invalid I2C Controller Index > + } > + return 0; > +} > +/** > + This is a helper function for updating USB Policy according to Blob da= ta > + > + @param[in] UsbConfig Pointer to USB_CONFIG data buffer > + @param[in] PortIndex USB Port index > + @param[in] Data32 Blob containing USB2 Afe (PCD32_BLOB) dat= a > +**/ > +VOID > +UpdateUsb20AfePolicy ( > + IN USB_CONFIG *UsbConfig, > + IN UINT8 PortIndex, > + UINT32 Data32 > +) > +{ > + PCD32_BLOB Pcd32; > + Pcd32.Blob =3D Data32; > + > + if (PortIndex < MAX_USB2_PORTS && Pcd32.Info.Petxiset !=3D 0) { > + UsbConfig->PortUsb20[PortIndex].Afe.Petxiset =3D Pcd32.Info.Petx= iset; > + UsbConfig->PortUsb20[PortIndex].Afe.Txiset =3D Pcd32.Info.Txis= et; > + UsbConfig->PortUsb20[PortIndex].Afe.Predeemp =3D > Pcd32.Info.Predeemp; > + UsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit =3D Pcd32.Info.Peha= lfbit; > + } > +} > + > +/** > + This function updates USB Policy per port OC Pin number > + > + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer > + @param[in] PortIndex USB Port index > + @param[in] Pin OverCurrent pin number > +**/ > +VOID > +UpdateUsb20OverCurrentPolicy ( > + IN USB_CONFIG *UsbConfig, > + IN UINT8 PortIndex, > + UINT8 Pin > +) > +{ > + if (PortIndex < MAX_USB2_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pi= n > =3D=3D UsbOverCurrentPinSkip))) { > + UsbConfig->PortUsb20[PortIndex].OverCurrentPin =3D Pin; > + } else { > + if (PortIndex >=3D MAX_USB2_PORTS) { > + DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: USB2 port > number %d is not a valid USB2 port number\n", PortIndex)); > + } else { > + DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: Invalid > OverCurrent pin specified USB2 port %d\n", PortIndex)); > + } > + } > +} > + > +/** > + This function updates USB Policy per port OC Pin number > + > + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer > + @param[in] PortIndex USB Port index > + @param[in] Pin OverCurrent pin number > +**/ > +VOID > +UpdateUsb30OverCurrentPolicy ( > + IN USB_CONFIG *UsbConfig, > + IN UINT8 PortIndex, > + UINT8 Pin > +) > +{ > + if (PortIndex < MAX_USB3_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pi= n > =3D=3D UsbOverCurrentPinSkip))) { > + UsbConfig->PortUsb30[PortIndex].OverCurrentPin =3D Pin; > + } else { > + if (PortIndex >=3D MAX_USB2_PORTS) { > + DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: USB3 port > number %d is not a valid USB3 port number\n", PortIndex)); > + } else { > + DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: Invalid > OverCurrent pin specified USB3 port %d\n", PortIndex)); > + } > + } > +} > + > +/** > + This function performs PCH USB Platform Policy initialization > + > + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer > + @param[in] PchSetup Pointer to PCH_SETUP data buffer > +**/ > +VOID > +UpdatePchUsbConfig ( > + IN USB_CONFIG *UsbConfig > + ) > +{ > + UINTN PortIndex; > + > + UsbConfig->OverCurrentEnable =3D TRUE; > + > + for (PortIndex =3D 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); > PortIndex++) { > + UsbConfig->PortUsb20[PortIndex].Enable =3D TRUE; > + } > + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortInd= ex++) > { > + UsbConfig->PortUsb30[PortIndex].Enable =3D TRUE; > + } > + > + UsbConfig->XdciConfig.Enable =3D FALSE; > + > + > + // > + // USB2 AFE settings. > + // > + UpdateUsb20AfePolicy (UsbConfig, 0, PcdGet32 (PcdUsb20Port0Afe)); > + UpdateUsb20AfePolicy (UsbConfig, 1, PcdGet32 (PcdUsb20Port1Afe)); > + UpdateUsb20AfePolicy (UsbConfig, 2, PcdGet32 (PcdUsb20Port2Afe)); > + UpdateUsb20AfePolicy (UsbConfig, 3, PcdGet32 (PcdUsb20Port3Afe)); > + UpdateUsb20AfePolicy (UsbConfig, 4, PcdGet32 (PcdUsb20Port4Afe)); > + UpdateUsb20AfePolicy (UsbConfig, 5, PcdGet32 (PcdUsb20Port5Afe)); > + UpdateUsb20AfePolicy (UsbConfig, 6, PcdGet32 (PcdUsb20Port6Afe)); > + UpdateUsb20AfePolicy (UsbConfig, 7, PcdGet32 (PcdUsb20Port7Afe)); > + UpdateUsb20AfePolicy (UsbConfig, 8, PcdGet32 (PcdUsb20Port8Afe)); > + UpdateUsb20AfePolicy (UsbConfig, 9, PcdGet32 (PcdUsb20Port9Afe)); > + UpdateUsb20AfePolicy (UsbConfig,10, PcdGet32 (PcdUsb20Port10Afe)); > + UpdateUsb20AfePolicy (UsbConfig,11, PcdGet32 (PcdUsb20Port11Afe)); > + UpdateUsb20AfePolicy (UsbConfig,12, PcdGet32 (PcdUsb20Port12Afe)); > + UpdateUsb20AfePolicy (UsbConfig,13, PcdGet32 (PcdUsb20Port13Afe)); > + UpdateUsb20AfePolicy (UsbConfig,14, PcdGet32 (PcdUsb20Port14Afe)); > + UpdateUsb20AfePolicy (UsbConfig,15, PcdGet32 (PcdUsb20Port15Afe)); > + > + // > + // Platform Board programming per the layout of each port. > + // > + UpdateUsb20OverCurrentPolicy (UsbConfig, 0, PcdGet8 > (PcdUsb20OverCurrentPinPort0)); > + UpdateUsb20OverCurrentPolicy (UsbConfig, 1, PcdGet8 > (PcdUsb20OverCurrentPinPort1)); > + UpdateUsb20OverCurrentPolicy (UsbConfig, 2, PcdGet8 > (PcdUsb20OverCurrentPinPort2)); > + UpdateUsb20OverCurrentPolicy (UsbConfig, 3, PcdGet8 > (PcdUsb20OverCurrentPinPort3)); > + UpdateUsb20OverCurrentPolicy (UsbConfig, 4, PcdGet8 > (PcdUsb20OverCurrentPinPort4)); > + UpdateUsb20OverCurrentPolicy (UsbConfig, 5, PcdGet8 > (PcdUsb20OverCurrentPinPort5)); > + UpdateUsb20OverCurrentPolicy (UsbConfig, 6, PcdGet8 > (PcdUsb20OverCurrentPinPort6)); > + UpdateUsb20OverCurrentPolicy (UsbConfig, 7, PcdGet8 > (PcdUsb20OverCurrentPinPort7)); > + UpdateUsb20OverCurrentPolicy (UsbConfig, 8, PcdGet8 > (PcdUsb20OverCurrentPinPort8)); > + UpdateUsb20OverCurrentPolicy (UsbConfig, 9, PcdGet8 > (PcdUsb20OverCurrentPinPort9)); > + UpdateUsb20OverCurrentPolicy (UsbConfig,10, PcdGet8 > (PcdUsb20OverCurrentPinPort10)); > + UpdateUsb20OverCurrentPolicy (UsbConfig,11, PcdGet8 > (PcdUsb20OverCurrentPinPort11)); > + UpdateUsb20OverCurrentPolicy (UsbConfig,12, PcdGet8 > (PcdUsb20OverCurrentPinPort12)); > + UpdateUsb20OverCurrentPolicy (UsbConfig,13, PcdGet8 > (PcdUsb20OverCurrentPinPort13)); > + UpdateUsb20OverCurrentPolicy (UsbConfig,14, PcdGet8 > (PcdUsb20OverCurrentPinPort14)); > + UpdateUsb20OverCurrentPolicy (UsbConfig,15, PcdGet8 > (PcdUsb20OverCurrentPinPort15)); > + > + UpdateUsb30OverCurrentPolicy (UsbConfig, 0, PcdGet8 > (PcdUsb30OverCurrentPinPort0)); > + UpdateUsb30OverCurrentPolicy (UsbConfig, 1, PcdGet8 > (PcdUsb30OverCurrentPinPort1)); > + UpdateUsb30OverCurrentPolicy (UsbConfig, 2, PcdGet8 > (PcdUsb30OverCurrentPinPort2)); > + UpdateUsb30OverCurrentPolicy (UsbConfig, 3, PcdGet8 > (PcdUsb30OverCurrentPinPort3)); > + UpdateUsb30OverCurrentPolicy (UsbConfig, 4, PcdGet8 > (PcdUsb30OverCurrentPinPort4)); > + UpdateUsb30OverCurrentPolicy (UsbConfig, 5, PcdGet8 > (PcdUsb30OverCurrentPinPort5)); > + UpdateUsb30OverCurrentPolicy (UsbConfig, 6, PcdGet8 > (PcdUsb30OverCurrentPinPort6)); > + UpdateUsb30OverCurrentPolicy (UsbConfig, 7, PcdGet8 > (PcdUsb30OverCurrentPinPort7)); > + UpdateUsb30OverCurrentPolicy (UsbConfig, 8, PcdGet8 > (PcdUsb30OverCurrentPinPort8)); > + UpdateUsb30OverCurrentPolicy (UsbConfig, 9, PcdGet8 > (PcdUsb30OverCurrentPinPort9)); > + > +} > + > +/** > + Return if input ImageGuid belongs to system FMP GUID list. > + > + @param[in] ImageGuid A pointer to GUID > + > + @retval TRUE ImageGuid is in the list of > PcdSystemFmpCapsuleImageTypeIdGuid > + @retval FALSE ImageGuid is not in the list of > PcdSystemFmpCapsuleImageTypeIdGuid > +**/ > +BOOLEAN > +IsSystemFmpGuid ( > + IN GUID *ImageGuid > + ) > +{ > + GUID *Guid; > + UINTN Count; > + UINTN Index; > + > + Guid =3D PcdGetPtr (PcdSystemFmpCapsuleImageTypeIdGuid); > + Count =3D PcdGetSize (PcdSystemFmpCapsuleImageTypeIdGuid) / sizeof > (GUID); > + > + for (Index =3D 0; Index < Count; Index++, Guid++) { > + if (CompareGuid (ImageGuid, Guid)) { > + return TRUE; > + } > + } > + > + return FALSE; > +} > + > +/** > + This function performs PCH PEI Policy initialization. > + > + @param[in, out] SiPolicy The SI Policy PPI instance > + > + @retval EFI_SUCCESS The PPI is installed and initialized. > + @retval EFI ERRORS The PPI is not successfully installed. > + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver > +**/ > +EFI_STATUS > +EFIAPI > +UpdatePeiPchPolicy ( > + IN OUT SI_POLICY_PPI *SiPolicy > + ) > +{ > + EFI_STATUS Status; > + UINT8 Index; > + DMI_HW_WIDTH_CONTROL *DmiHaAWC; > + UINT16 LpcDid; > + PCH_GENERAL_CONFIG *PchGeneralConfig; > + PCH_PCIE_CONFIG *PcieRpConfig; > + PCH_SATA_CONFIG *SataConfig; > + PCH_IOAPIC_CONFIG *IoApicConfig; > + PCH_DMI_CONFIG *DmiConfig; > + PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; > + PCH_HDAUDIO_CONFIG *HdAudioConfig; > + PCH_INTERRUPT_CONFIG *InterruptConfig; > + PCH_ISH_CONFIG *IshConfig; > + PCH_LAN_CONFIG *LanConfig; > + PCH_LOCK_DOWN_CONFIG *LockDownConfig; > + PCH_PM_CONFIG *PmConfig; > + PCH_SCS_CONFIG *ScsConfig; > + PCH_SERIAL_IO_CONFIG *SerialIoConfig; > + PCH_LPC_SIRQ_CONFIG *SerialIrqConfig; > + PCH_THERMAL_CONFIG *ThermalConfig; > + USB_CONFIG *UsbConfig; > + PCH_ESPI_CONFIG *EspiConfig; > + PCH_CNVI_CONFIG *CnviConfig; > + PEI_TBT_POLICY *PeiTbtPolicy; > + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; > + > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, = (VOID > *) &PchGeneralConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOI= D *) > &PcieRpConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID = *) > &SataConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOI= D *) > &IoApicConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *= ) > &DmiConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigG= uid, > (VOID *) &FlashProtectionConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VO= ID *) > &HdAudioConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (= VOID *) > &InterruptConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *= ) > &IshConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *= ) > &LanConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (V= OID *) > &LockDownConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) > &PmConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *= ) > &ScsConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (V= OID *) > &SerialIoConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (= VOID *) > &SerialIrqConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VO= ID *) > &ThermalConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *= ) > &UsbConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID = *) > &EspiConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID = *) > &CnviConfig); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D PeiServicesLocatePpi ( > + &gSiPreMemPolicyPpiGuid, > + 0, > + NULL, > + (VOID **) &SiPreMemPolicyPpi > + ); > + ASSERT_EFI_ERROR (Status); > + > + PeiTbtPolicy =3D NULL; > + LpcDid =3D PchGetLpcDid (); > + > + DmiConfig->PwrOptEnable =3D TRUE; > + PmConfig->PchSlpS3MinAssert =3D 0; > + PmConfig->PchSlpS4MinAssert =3D 0; > + PmConfig->PchSlpSusMinAssert =3D 0; > + PmConfig->PchSlpAMinAssert =3D 0; > + > + SataConfig->ThermalThrottling.P1T3M =3D 3; > + SataConfig->ThermalThrottling.P1T2M =3D 2; > + SataConfig->ThermalThrottling.P1T1M =3D 1; > + SataConfig->ThermalThrottling.P0T3M =3D 3; > + SataConfig->ThermalThrottling.P0T2M =3D 2; > + SataConfig->ThermalThrottling.P0T1M =3D 1; > + > + UpdatePcieClockInfo (PcieRpConfig, 0, PcdGet64 (PcdPcieClock0)); > + UpdatePcieClockInfo (PcieRpConfig, 1, PcdGet64 (PcdPcieClock1)); > + UpdatePcieClockInfo (PcieRpConfig, 2, PcdGet64 (PcdPcieClock2)); > + UpdatePcieClockInfo (PcieRpConfig, 3, PcdGet64 (PcdPcieClock3)); > + UpdatePcieClockInfo (PcieRpConfig, 4, PcdGet64 (PcdPcieClock4)); > + UpdatePcieClockInfo (PcieRpConfig, 5, PcdGet64 (PcdPcieClock5)); > + UpdatePcieClockInfo (PcieRpConfig, 6, PcdGet64 (PcdPcieClock6)); > + UpdatePcieClockInfo (PcieRpConfig, 7, PcdGet64 (PcdPcieClock7)); > + UpdatePcieClockInfo (PcieRpConfig, 8, PcdGet64 (PcdPcieClock8)); > + UpdatePcieClockInfo (PcieRpConfig, 9, PcdGet64 (PcdPcieClock9)); > + UpdatePcieClockInfo (PcieRpConfig, 10, PcdGet64 (PcdPcieClock10)); > + UpdatePcieClockInfo (PcieRpConfig, 11, PcdGet64 (PcdPcieClock11)); > + UpdatePcieClockInfo (PcieRpConfig, 12, PcdGet64 (PcdPcieClock12)); > + UpdatePcieClockInfo (PcieRpConfig, 13, PcdGet64 (PcdPcieClock13)); > + UpdatePcieClockInfo (PcieRpConfig, 14, PcdGet64 (PcdPcieClock14)); > + UpdatePcieClockInfo (PcieRpConfig, 15, PcdGet64 (PcdPcieClock15)); > + > + PcieRpConfig->PcieDeviceOverrideTablePtr =3D (UINT32) mPcieDeviceTable= ; > + PcieRpConfig->RootPort[0].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[1].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[2].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[3].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[4].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[5].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[6].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[7].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[8].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[9].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[10].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[11].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[12].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[13].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[14].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[15].ClkReqDetect =3D TRUE; > + PcieRpConfig->RootPort[0].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[1].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[2].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[3].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[4].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[5].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[6].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[7].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[8].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[9].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[10].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[11].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[12].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[13].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[14].AdvancedErrorReporting =3D TRUE; > + PcieRpConfig->RootPort[15].AdvancedErrorReporting =3D TRUE; > + > + // > + // Install HDA Link/iDisplay Codec Verb Table > + // > + AddPlatformVerbTables ( > + PchHdaCodecPlatformOnboard, > + &(HdAudioConfig->VerbTableEntryNum), > + &(HdAudioConfig->VerbTablePtr) > + ); > + > + LockDownConfig->BiosLock =3D FALSE; > + LockDownConfig->BiosInterface =3D FALSE; > + > + // > + // IOAPIC Config > + // > +// IoApicConfig->IoApicEntry24_119 =3D PchSetup.PchIoApic24119Entri= es; > + // > + // To support SLP_S0, it's required to disable 8254 timer. > + // Note that CSM may require this option to be disabled for correct > operation. > + // Once 8254 timer disabled, some legacy OPROM and legacy OS will fail > while using 8254 timer. > + // For some OS environment that it needs to set 8254CGE in late state = it > should > + // set this policy to FALSE and use PmcSet8254ClockGateState (TRUE) in > SMM later. > + // This is also required during S3 resume. > + // > + // The Enable8254ClockGatingOnS3 is only applicable when > Enable8254ClockGating is disabled. > + // If Enable8254ClockGating is enabled, RC will do 8254 CGE programmin= g > on S3 as well. > + // else, RC will do the programming on S3 when > Enable8254ClockGatingOnS3 is enabled. > + // This avoids the SMI requirement for the programming. > + // > + // If S0ix is not enabled, then disable 8254CGE for leagcy boot case. > + // > + IoApicConfig->Enable8254ClockGating =3D FALSE; > + IoApicConfig->Enable8254ClockGatingOnS3 =3D FALSE; > + > + // > + // SerialIo Config > + // > + SerialIoConfig->DevMode[0] =3D 1; > + SerialIoConfig->DevMode[1] =3D 1; > + SerialIoConfig->DevMode[2] =3D 0; > + SerialIoConfig->DevMode[3] =3D 0; > + SerialIoConfig->DevMode[4] =3D 1; > + SerialIoConfig->DevMode[5] =3D 0; > + SerialIoConfig->DevMode[6] =3D 0; > + SerialIoConfig->DevMode[7] =3D 0; > + SerialIoConfig->DevMode[8] =3D 0; > + SerialIoConfig->DevMode[9] =3D 0; > + SerialIoConfig->DevMode[10] =3D 0; > + SerialIoConfig->DevMode[11] =3D 3; > + > + SerialIoConfig->Uart0PinMuxing =3D 1; > + SerialIoConfig->SpiCsPolarity[0] =3D 1; > + SerialIoConfig->SpiCsPolarity[1] =3D 0; > + SerialIoConfig->SpiCsPolarity[2] =3D 0; > + > + SerialIoConfig->UartHwFlowCtrl[0] =3D 1; > + SerialIoConfig->UartHwFlowCtrl[1] =3D 1; > + SerialIoConfig->UartHwFlowCtrl[2] =3D 1; > + // > + // I2C4 and I2C5 don't exist in SPT-H chipset > + // > + if (IsPchH ()) { > + SerialIoConfig->DevMode[PchSerialIoIndexI2C4] =3D PchSerialIoDisable= d; > + SerialIoConfig->DevMode[PchSerialIoIndexI2C5] =3D PchSerialIoDisable= d; > + } > + > + for (Index =3D 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index= ++) { > + SerialIoConfig->I2cPadsTermination[Index] =3D > GetSerialIoI2cPadsTerminationFromPcd (Index); > + } > + > + PmConfig->SlpS0Override =3D 2; //PchSetup.SlpS= 0Override; > + PmConfig->SlpS0DisQForDebug =3D 3; > //PchSetup.SlpS0DisQForDebug; > + PmConfig->SlpS0Vm075VSupport =3D 1; // > PcdGetBool(PcdSlpS0Vm075VSupport); > + PmConfig->CpuC10GatePinEnable =3D 1; > + > + // > + // Thermal Config > + // > + ThermalConfig->TsmicLock =3D TRUE; > + ThermalConfig->PchHotEnable =3D PcdGetBool > (PcdPchThermalHotEnable); > + > + DmiHaAWC =3D &ThermalConfig->DmiHaAWC; > + DmiHaAWC->TS3TW =3D 0; > + DmiHaAWC->TS2TW =3D 1; > + DmiHaAWC->TS1TW =3D 2; > + DmiHaAWC->TS0TW =3D 3; > + // > + // Update Pch Usb Config > + // > + UpdatePchUsbConfig ( > + UsbConfig > + ); > + > + ScsConfig->ScsUfsEnabled =3D 0; > + ScsConfig->ScsEmmcHs400Enabled =3D 1; > + ScsConfig->ScsEmmcHs400TuningRequired =3D TRUE; > + > + IshConfig->I2c0GpioAssign =3D 1; > + IshConfig->I2c1GpioAssign =3D 1; > + IshConfig->Gp0GpioAssign =3D 1; > + IshConfig->Gp1GpioAssign =3D 1; > + IshConfig->Gp2GpioAssign =3D 1; > + IshConfig->Gp3GpioAssign =3D 1; > + IshConfig->Gp4GpioAssign =3D 1; > + IshConfig->Gp5GpioAssign =3D 1; > + IshConfig->Gp6GpioAssign =3D 1; > + > + return Status; > +} > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiPchPolicyUpdatePreMem.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiPchPolicyUpdatePreMem.c > new file mode 100644 > index 0000000000..968df0f55c > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiPchPolicyUpdatePreMem.c > @@ -0,0 +1,113 @@ > +/** @file > + This file is SampleCode of the library for Intel PCH PEI Policy initia= lization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiPchPolicyUpdate.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +// > +// Sawtooth Peak > +// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC > only) > +// > +#define DIMM_SMB_SPD_P0C0D0_STP 0xA2 > +#define DIMM_SMB_SPD_P0C0D1_STP 0xA0 > +#define DIMM_SMB_SPD_P0C1D0_STP 0xA2 > +#define DIMM_SMB_SPD_P0C1D1_STP 0xA0 > + > +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] =3D { > + DIMM_SMB_SPD_P0C0D0_STP, > + DIMM_SMB_SPD_P0C0D1_STP, > + DIMM_SMB_SPD_P0C1D0_STP, > + DIMM_SMB_SPD_P0C1D1_STP > +}; > + > + > +/** > + This function performs PCH PEI Policy initialization. > + > + @param[in, out] SiPreMemPolicy The SI PREMEM Policy PPI instance > + > + @retval EFI_SUCCESS The PPI is installed and initialized. > + @retval EFI ERRORS The PPI is not successfully installed. > + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to > initialize the driver > +**/ > +EFI_STATUS > +EFIAPI > +UpdatePeiPchPolicyPreMem ( > + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy > + ) > +{ > + EFI_STATUS Status; > + UINT8 *SmBusReservedTable; > + UINT8 SmBusReservedNum; > + > + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; > + PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig; > + PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig; > + PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig; > + PCH_WDT_PREMEM_CONFIG *WatchDogPreMemConfig; > + PCH_DCI_PREMEM_CONFIG *DciPreMemConfig; > + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig; > + PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig; > + PCH_ISH_PREMEM_CONFIG *IshPreMemConfig; > + > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gPchTraceHubPreMemConfigGuid, (VOID *) &PchTraceHubPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gSmbusPreMemConfigGuid, (VOID *) &SmbusPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gLpcPreMemConfigGuid, (VOID *) &LpcPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gWatchDogPreMemConfigGuid, (VOID *) &WatchDogPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gDciPreMemConfigGuid, (VOID *) &DciPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gHdAudioPreMemConfigGuid, (VOID *) &HdaPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, > &gIshPreMemConfigGuid, (VOID *) &IshPreMemConfig); > + ASSERT_EFI_ERROR (Status); > + > + DciPreMemConfig->DciUsb3TypecUfpDbg =3D 2; > + PchTraceHubPreMemConfig->MemReg0Size =3D 3; > + PchTraceHubPreMemConfig->MemReg1Size =3D 3; > + // > + // SMBUS > + // > + SmbusPreMemConfig->Enable =3D TRUE; > + SmbusPreMemConfig->SmbAlertEnable =3D PcdGetBool > (PcdSmbusAlertEnable); > + // > + // SMBUS reserved addresses > + // > + SmBusReservedTable =3D NULL; > + SmBusReservedNum =3D 0; > + SmbusPreMemConfig->SmbusIoBase =3D PcdGet16 (PcdSmbusBaseAddress); > + SmBusReservedTable =3D mSmbusSTPRsvdAddresses; > + SmBusReservedNum =3D sizeof (mSmbusSTPRsvdAddresses); > + > + if (SmBusReservedTable !=3D NULL) { > + SmbusPreMemConfig->NumRsvdSmbusAddresses =3D SmBusReservedNum; > + CopyMem ( > + SmbusPreMemConfig->RsvdSmbusAddressTable, > + SmBusReservedTable, > + SmBusReservedNum > + ); > + } > + > + return Status; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSaPolicyUpdate.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSaPolicyUpdate.c > new file mode 100644 > index 0000000000..c1ac7d890f > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSaPolicyUpdate.c > @@ -0,0 +1,242 @@ > +/** @file > +Do Platform Stage System Agent initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiSaPolicyUpdate.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + UpdatePeiSaPolicy performs SA PEI Policy initialization > + > + @param[in out] SiPolicyPpi - SI_POLICY PPI > + > + @retval EFI_SUCCESS The policy is installed and initializ= ed. > +**/ > +EFI_STATUS > +UpdatePeiSaPolicy ( > + IN OUT SI_POLICY_PPI *SiPolicyPpi > + ) > +{ > + EFI_STATUS Status; > + EFI_GUID FileGuid; > + VOID *Buffer; > + UINT8 SaDisplayConfigTable[9] =3D {0}; > + VOID *MemBuffer; > + BMP_IMAGE_HEADER *BmpHeader; > + UINT64 BltBufferSize; > + UINT32 Size; > + GRAPHICS_PEI_CONFIG *GtConfig; > + GNA_CONFIG *GnaConfig; > + WDT_PPI *gWdtPei; > + PCIE_PEI_CONFIG *PciePeiConfig; > + SA_MISC_PEI_CONFIG *MiscPeiConfig; > + EFI_BOOT_MODE BootMode; > + > + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); > + > + Size =3D 0; > + MemBuffer =3D NULL; > + BmpHeader =3D NULL; > + BltBufferSize =3D 0; > + GtConfig =3D NULL; > + GnaConfig =3D NULL; > + > + Status =3D GetConfigBlock((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGui= d, > (VOID *)&GtConfig); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D GetConfigBlock((VOID *) SiPolicyPpi, &gGnaConfigGuid, (VOID > *)&GnaConfig); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaPciePeiConfigGuid= , (VOID > *)&PciePeiConfig); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid= , > (VOID *)&MiscPeiConfig); > + ASSERT_EFI_ERROR (Status); > + > + > + // > + // Locate WDT_PPI (ICC WDT PPI) > + // > + gWdtPei =3D NULL; > + Status =3D PeiServicesLocatePpi( > + &gWdtPpiGuid, > + 0, > + NULL, > + (VOID **) &gWdtPei > + ); > + > + Status =3D PeiServicesGetBootMode(&BootMode); > + ASSERT_EFI_ERROR(Status); > + > + if (!EFI_ERROR (Status)) { > + Buffer =3D NULL; > + > + CopyMem(&FileGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), > sizeof(FileGuid)); > + PeiGetSectionFromFv(FileGuid, &Buffer, &Size); > + if (Buffer =3D=3D NULL) { > + DEBUG((DEBUG_ERROR, "Could not locate VBT\n")); > + } > + > + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); > + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { > + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); > + GtConfig->GraphicsConfigPtr =3D MemBuffer; > + } else { > + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); > + GtConfig->GraphicsConfigPtr =3D NULL; > + } > + > + GtConfig->PeiGraphicsPeimInit =3D 1; > + > + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", > GtConfig->GraphicsConfigPtr)); > + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", > Size)); > + > + PeiGetSectionFromFv (gTianoLogoGuid, &Buffer, &Size); > + if (Buffer =3D=3D NULL) { > + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); > + } > + > + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); > + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { > + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); > + GtConfig->LogoPtr =3D MemBuffer; > + GtConfig->LogoSize =3D Size; > + > + // > + // Calculate the BltBuffer needed size. > + // > + BmpHeader =3D (BMP_IMAGE_HEADER *) GtConfig->LogoPtr; > + > + if (BmpHeader->CharB =3D=3D 'B' && BmpHeader->CharM =3D=3D 'M') { > + BltBufferSize =3D MultU64x32 ((UINT64) BmpHeader->PixelWidth, > BmpHeader->PixelHeight); > + if (BltBufferSize < DivU64x32 ((UINTN) ~0, sizeof > (EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) { > + BltBufferSize =3D MultU64x32 (BltBufferSize, sizeof > (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)); > + GtConfig->BltBufferSize =3D (UINT32) BltBufferSize; > + GtConfig->BltBufferAddress =3D (VOID *) AllocatePages > (EFI_SIZE_TO_PAGES ((UINTN)GtConfig->BltBufferSize)); > + } else { > + DEBUG ((DEBUG_ERROR, "Blt Buffer Size overflow.\n")); > + ASSERT (FALSE); > + } > + } else { > + DEBUG ((DEBUG_ERROR, "Wrong Bmp Image Header.\n")); > + ASSERT (FALSE); > + } > + > + } else { > + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); > + GtConfig->LogoPtr =3D NULL; > + GtConfig->LogoSize =3D 0; > + } > + > + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", > GtConfig->LogoPtr)); > + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", > GtConfig->LogoSize)); > + > + // > + // Display DDI Initialization ( default Native GPIO as per board dur= ing AUTO > case) > + // > + if (PcdGet32 (PcdSaDisplayConfigTable) !=3D 0) { > + CopyMem (SaDisplayConfigTable, (VOID *) (UINTN) PcdGet32 > (PcdSaDisplayConfigTable), (UINTN)PcdGet16 (PcdSaDisplayConfigTableSize))= ; > + GtConfig->DdiConfiguration.DdiPortEdp =3D SaDisplayConfigTable= [0]; > + GtConfig->DdiConfiguration.DdiPortBHpd =3D SaDisplayConfigTable= [1]; > + GtConfig->DdiConfiguration.DdiPortCHpd =3D SaDisplayConfigTable= [2]; > + GtConfig->DdiConfiguration.DdiPortDHpd =3D SaDisplayConfigTable= [3]; > + GtConfig->DdiConfiguration.DdiPortFHpd =3D SaDisplayConfigTable= [4]; > + GtConfig->DdiConfiguration.DdiPortBDdc =3D SaDisplayConfigTable= [5]; > + GtConfig->DdiConfiguration.DdiPortCDdc =3D SaDisplayConfigTable= [6]; > + GtConfig->DdiConfiguration.DdiPortDDdc =3D SaDisplayConfigTable= [7]; > + GtConfig->DdiConfiguration.DdiPortFDdc =3D SaDisplayConfigTable= [8]; > + } > + } > + > + PciePeiConfig->DmiAspm =3D 0x3; > + > + return EFI_SUCCESS; > +} > + > +/** > + PeiGetSectionFromFv finds the file in FV and gets file Address and Siz= e > + > + @param[in] NameGuid - File GUID > + @param[out] Address - Pointer to the File Address > + @param[out] Size - Pointer to File Size > + > + @retval EFI_SUCCESS Successfull in reading the section = from FV > +**/ > +EFI_STATUS > +EFIAPI > +PeiGetSectionFromFv ( > + IN CONST EFI_GUID NameGuid, > + OUT VOID **Address, > + OUT UINT32 *Size > + ) > +{ > + EFI_STATUS Status; > + EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi; > + EFI_FV_FILE_INFO FvFileInfo; > + PEI_CORE_INSTANCE *PrivateData; > + UINTN CurrentFv; > + PEI_CORE_FV_HANDLE *CoreFvHandle; > + EFI_PEI_FILE_HANDLE VbtFileHandle; > + EFI_GUID *VbtGuid; > + EFI_COMMON_SECTION_HEADER *Section; > + CONST EFI_PEI_SERVICES **PeiServices; > + > + PeiServices =3D GetPeiServicesTablePointer(); > + > + PrivateData =3D PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices); > + > + Status =3D PeiServicesLocatePpi( > + &gEfiFirmwareFileSystem2Guid, > + 0, > + NULL, > + (VOID **)&FvPpi > + ); > + ASSERT_EFI_ERROR(Status); > + > + CurrentFv =3D PrivateData->CurrentPeimFvCount; > + CoreFvHandle =3D &(PrivateData->Fv[CurrentFv]); > + > + Status =3D FvPpi->FindFileByName(FvPpi, &NameGuid, > &CoreFvHandle->FvHandle, &VbtFileHandle); > + if (!EFI_ERROR(Status) && VbtFileHandle !=3D NULL) { > + > + DEBUG((DEBUG_INFO, "Find SectionByType \n")); > + > + Status =3D FvPpi->FindSectionByType(FvPpi, EFI_SECTION_RAW, > VbtFileHandle, (VOID **)&VbtGuid); > + if (!EFI_ERROR(Status)) { > + > + DEBUG((DEBUG_INFO, "GetFileInfo \n")); > + > + Status =3D FvPpi->GetFileInfo(FvPpi, VbtFileHandle, &FvFileInfo); > + Section =3D (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer; > + > + if (IS_SECTION2(Section)) { > + ASSERT(SECTION2_SIZE(Section) > 0x00FFFFFF); > + *Size =3D SECTION2_SIZE(Section) - sizeof > (EFI_COMMON_SECTION_HEADER2); > + *Address =3D ((UINT8 *)Section + sizeof > (EFI_COMMON_SECTION_HEADER2)); > + } else { > + *Size =3D SECTION_SIZE(Section) - sizeof > (EFI_COMMON_SECTION_HEADER); > + *Address =3D ((UINT8 *)Section + sizeof > (EFI_COMMON_SECTION_HEADER)); > + } > + } > + } > + > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSaPolicyUpdatePreMem.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSaPolicyUpdatePreMem.c > new file mode 100644 > index 0000000000..3dc455ab29 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSaPolicyUpdatePreMem.c > @@ -0,0 +1,221 @@ > +/** @file > +Do Platform Stage System Agent initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiSaPolicyUpdate.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > + > +/// > +/// Memory Reserved should be between 125% to 150% of the Current > required memory > +/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 res= ume > issues. > +/// > +GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION > mDefaultMemoryTypeInformation[] =3D { > + { EfiACPIReclaimMemory, FixedPcdGet32 > (PcdPlatformEfiAcpiReclaimMemorySize) }, // ASL > + { EfiACPIMemoryNVS, FixedPcdGet32 > (PcdPlatformEfiAcpiNvsMemorySize) }, // ACPI NVS (including S3 relat= ed) > + { EfiReservedMemoryType, FixedPcdGet32 > (PcdPlatformEfiReservedMemorySize) }, // BIOS Reserved (including S3 > related) > + { EfiRuntimeServicesData, FixedPcdGet32 > (PcdPlatformEfiRtDataMemorySize) }, // Runtime Service Data > + { EfiRuntimeServicesCode, FixedPcdGet32 > (PcdPlatformEfiRtCodeMemorySize) }, // Runtime Service Code > + { EfiMaxMemoryType, 0 } > +}; > + > + > +/** > + UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization > + > + @param[in out] SiPreMemPolicyPpi - SI_PREMEM_POLICY PPI > + > + @retval EFI_SUCCESS The policy is installed and initializ= ed. > +**/ > +EFI_STATUS > +UpdatePeiSaPolicyPreMem ( > + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi > + ) > +{ > + EFI_STATUS Status; > + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig =3D NULL; > + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc =3D NULL; > + SA_MEMORY_RCOMP *RcompData; > + WDT_PPI *gWdtPei; > + UINT8 Index; > + UINTN DataSize; > + EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + > 1]; > + EFI_BOOT_MODE BootMode; > + UINT8 MorControl; > + UINT32 TraceHubTotalMemSize; > + GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig =3D NULL; > + MEMORY_CONFIGURATION *MemConfig =3D NULL; > + PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig =3D NULL; > + SWITCHABLE_GRAPHICS_CONFIG *SgGpioData =3D NULL; > + IPU_PREMEM_CONFIG *IpuPreMemPolicy =3D NULL; > + OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig =3D NULL; > + VTD_CONFIG *Vtd =3D NULL; > + UINT32 ProcessorTraceTotalMemSize; > + UINT16 AdjustedMmioSize; > + CPU_FAMILY CpuFamilyId; > + CPU_STEPPING CpuStepping; > + > + TraceHubTotalMemSize =3D 0; > + ProcessorTraceTotalMemSize =3D 0; > + AdjustedMmioSize =3D PcdGet16 (PcdSaMiscMmioSizeAdjustment); > + CpuFamilyId =3D GetCpuFamily(); > + CpuStepping =3D GetCpuStepping(); > + > + DEBUG((DEBUG_INFO, "Entering Get Config Block function call from > UpdatePeiSaPolicyPreMem\n")); > + > + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, > &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, > &gGraphicsPeiPreMemConfigGuid, (VOID *) &GtPreMemConfig); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, > &gMemoryConfigGuid, (VOID *) &MemConfig); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, > &gSaPciePeiPreMemConfigGuid, (VOID *) &PciePeiPreMemConfig); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, > &gSwitchableGraphicsConfigGuid, (VOID *) &SgGpioData); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, > &gIpuPreMemConfigGuid, (VOID *) &IpuPreMemPolicy); > + ASSERT_EFI_ERROR (Status); > + > + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, > &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, > &gSaOverclockingPreMemConfigGuid, (VOID *) &OcPreMemConfig); > + ASSERT_EFI_ERROR(Status); > + > + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid, > (VOID *)&Vtd); > + ASSERT_EFI_ERROR(Status); > + > + > + RcompData =3D MemConfigNoCrc->RcompData; > + > + // > + // Locate WDT_PPI (ICC WDT PPI) > + // > + gWdtPei =3D NULL; > + Status =3D PeiServicesLocatePpi( > + &gWdtPpiGuid, > + 0, > + NULL, > + (VOID **) &gWdtPei > + ); > + > + Status =3D PeiServicesGetBootMode(&BootMode); > + ASSERT_EFI_ERROR(Status); > + > + MiscPeiPreMemConfig->S3DataPtr =3D NULL; > + MorControl =3D 0; > + MiscPeiPreMemConfig->UserBd =3D 0; // It's a CRB mobile board by defau= lt > (btCRBMB) > + > + PcdSetBoolS (PcdMobileDramPresent, (BOOLEAN) > (MemConfig->MobilePlatform)); > + MiscPeiPreMemConfig->SpdAddressTable[0] =3D PcdGet8 > (PcdMrcSpdAddressTable0); > + MiscPeiPreMemConfig->SpdAddressTable[1] =3D PcdGet8 > (PcdMrcSpdAddressTable1); > + MiscPeiPreMemConfig->SpdAddressTable[2] =3D PcdGet8 > (PcdMrcSpdAddressTable2); > + MiscPeiPreMemConfig->SpdAddressTable[3] =3D PcdGet8 > (PcdMrcSpdAddressTable3); > + MemConfig->CaVrefConfig =3D PcdGet8 (PcdMrcCaVrefConfi= g); > + MemConfig->DualDimmPerChannelBoardType =3D PcdGetBool > (PcdDualDimmPerChannelBoardType); > + if (PcdGet32 (PcdMrcRcompResistor)) { > + CopyMem((VOID *)RcompData->RcompResistor, (VOID *) (UINTN) > PcdGet32 (PcdMrcRcompResistor), sizeof (RcompData->RcompResistor)); > + } > + if (PcdGet32 (PcdMrcRcompTarget)) { > + CopyMem((VOID *)RcompData->RcompTarget, (VOID *) (UINTN) PcdGet32 > (PcdMrcRcompTarget), sizeof (RcompData->RcompTarget)); > + } > + if (PcdGet32 (PcdMrcDqByteMap)) { > + CopyMem((VOID *)MemConfigNoCrc->DqByteMap, (VOID *) (UINTN) > PcdGet32 (PcdMrcDqByteMap), sizeof (UINT8)* SA_MC_MAX_CHANNELS * > SA_MRC_ITERATION_MAX * 2); > + } > + if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) { > + CopyMem((VOID *)MemConfigNoCrc->DqsMap, (VOID *) (UINTN) > PcdGet32 (PcdMrcDqsMapCpu2Dram), sizeof (UINT8)* > SA_MC_MAX_CHANNELS * SA_MC_MAX_BYTES_NO_ECC); > + } > + if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) { > + MemConfig->DqPinsInterleaved =3D PcdGetBool > (PcdMrcDqPinsInterleaved); > + } > + if (PcdGet32 (PcdMrcSpdData)) { > + CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *) > (UINTN) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE); > + CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *) > (UINTN) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE); > + } > + > + MiscPeiPreMemConfig->MchBar =3D (UINTN) PcdGet64 > (PcdMchBaseAddress); > + MiscPeiPreMemConfig->DmiBar =3D (UINTN) PcdGet64 > (PcdDmiBaseAddress); > + MiscPeiPreMemConfig->EpBar =3D (UINTN) PcdGet64 (PcdEpBaseAddress); > + MiscPeiPreMemConfig->EdramBar =3D (UINTN) PcdGet64 > (PcdEdramBaseAddress); > + MiscPeiPreMemConfig->SmbusBar =3D PcdGet16(PcdSmbusBaseAddress); > + MiscPeiPreMemConfig->TsegSize =3D PcdGet32(PcdTsegSize); > + MiscPeiPreMemConfig->UserBd =3D PcdGet8 (PcdSaMiscUserBd); > + MiscPeiPreMemConfig->MmioSizeAdjustment =3D PcdGet16 > (PcdSaMiscMmioSizeAdjustment); > + if (PcdGetBool (PcdPegGpioResetControl)) { > + PciePeiPreMemConfig->PegGpioData.GpioSupport =3D PcdGetBool > (PcdPegGpioResetSupoort); > + } else { > + > + } > + PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.GpioPad =3D > PcdGet32 (PcdPeg0ResetGpioPad); > + PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.Active =3D > PcdGetBool (PcdPeg0ResetGpioActive); > + > + PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.GpioPad =3D > PcdGet32 (PcdPeg3ResetGpioPad); > + PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.Active =3D > PcdGetBool (PcdPeg3ResetGpioActive); > + > + MemConfig->CkeRankMapping =3D 0xAA; > + /// > + /// Initialize the VTD Configuration > + /// > + Vtd->VtdDisable =3D 0; > + > + MemConfig->RMT =3D 1; > + MemConfig->UserPowerWeightsEn =3D 0; > + MemConfig->RaplLim2WindY =3D 0x0A; > + MemConfig->ExitOnFailure =3D 1; > + > + MemConfigNoCrc->PlatformMemorySize =3D PEI_MIN_MEMORY_SIZE + > TraceHubTotalMemSize + ProcessorTraceTotalMemSize; > + DataSize =3D sizeof (mDefaultMemoryTypeInformation); > + CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize); > + > + if (BootMode !=3D BOOT_IN_RECOVERY_MODE) { > + for (Index =3D 0; Index < DataSize / sizeof > (EFI_MEMORY_TYPE_INFORMATION); Index++) { > + MemConfigNoCrc->PlatformMemorySize +=3D > MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE; > + } > + > + OcPreMemConfig->GtMaxOcRatio =3D 0; > + OcPreMemConfig->GtVoltageMode =3D 0; > + OcPreMemConfig->GtVoltageOverride =3D 0; > + OcPreMemConfig->GtExtraTurboVoltage =3D 0; > + OcPreMemConfig->GtVoltageOffset =3D 0; > + OcPreMemConfig->SaVoltageOffset =3D 0; > + OcPreMemConfig->GtusMaxOcRatio =3D 0; > + OcPreMemConfig->GtusVoltageMode =3D 0; > + OcPreMemConfig->GtusVoltageOverride =3D 0; > + OcPreMemConfig->GtusExtraTurboVoltage =3D 0; > + OcPreMemConfig->GtusVoltageOffset =3D 0; > + > + /// > + /// Build the GUID'd HOB for DXE > + /// > + BuildGuidDataHob ( > + &gEfiMemoryTypeInformationGuid, > + MemoryData, > + DataSize > + ); > + } > + > + return EFI_SUCCESS; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSiPolicyUpdate.c > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSiPolicyUpdate.c > new file mode 100644 > index 0000000000..3efbe2ccbd > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate > Lib/PeiSiPolicyUpdate.c > @@ -0,0 +1,168 @@ > +/** @file > + This file is SampleCode of the library for Intel Silicon PEI > + Platform Policy initialization. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PeiSiPolicyUpdate.h" > +#include > +#include > +#include > +#include > +#include > + > +STATIC SVID_SID_INIT_ENTRY mCdfSsidTablePtr[] =3D { > + // > + // SA Device(s) > + // > + {{{PCI_SVID_OFFSET, SA_MC_FUN, SA_MC_DEV, SA_MC_BUS, = 0, > SA_SEG_NUM, 0}}, {0, 0},0}, > + {{{R_SA_PEG_SS_OFFSET, SA_PEG0_FUN_NUM, SA_PEG0_DEV_NUM, > SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0}, > + {{{R_SA_PEG_SS_OFFSET, SA_PEG1_FUN_NUM, SA_PEG1_DEV_NUM, > SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0}, > + {{{R_SA_PEG_SS_OFFSET, SA_PEG2_FUN_NUM, SA_PEG2_DEV_NUM, > SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, SA_IGD_FUN_0, SA_IGD_DEV, SA_MC_BUS, = 0, > SA_SEG_NUM, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, SA_IPU_FUN_NUM, SA_IPU_DEV_NUM, > SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, SA_GNA_FUN_NUM, SA_GNA_DEV_NUM, > SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0}, > + // > + // PCH Device(s) > + // > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LPC, > PCI_DEVICE_NUMBER_PCH_LPC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_P2SB, > PCI_DEVICE_NUMBER_PCH_P2SB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_PMC, > PCI_DEVICE_NUMBER_PCH_PMC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_HDA, > PCI_DEVICE_NUMBER_PCH_HDA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_1, > PCI_DEVICE_NUMBER_CDF_PCH_SATA_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_2, > PCI_DEVICE_NUMBER_CDF_PCH_SATA_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_3, > PCI_DEVICE_NUMBER_CDF_PCH_SATA_3, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SMBUS, > PCI_DEVICE_NUMBER_PCH_SMBUS, DEFAULT_PCI_BUS_NUMBER_PCH, > 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SPI, > PCI_DEVICE_NUMBER_PCH_SPI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_TRACE_HUB, > PCI_DEVICE_NUMBER_PCH_TRACE_HUB, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XHCI, > PCI_DEVICE_NUMBER_PCH_XHCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XDCI, > PCI_DEVICE_NUMBER_PCH_XDCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_THERMAL, > PCI_DEVICE_NUMBER_PCH_THERMAL, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > +}; > + > +STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[] =3D { > + // > + // SA Device(s) > + // > + {{{PCI_SVID_OFFSET, SA_MC_FUN, SA_MC_DEV, SA_MC_BUS, = 0, > SA_SEG_NUM, 0}}, {0, 0},0}, > + {{{R_SA_PEG_SS_OFFSET, SA_PEG0_FUN_NUM, SA_PEG0_DEV_NUM, > SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0}, > + {{{R_SA_PEG_SS_OFFSET, SA_PEG1_FUN_NUM, SA_PEG1_DEV_NUM, > SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0}, > + {{{R_SA_PEG_SS_OFFSET, SA_PEG2_FUN_NUM, SA_PEG2_DEV_NUM, > SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, SA_IGD_FUN_0, SA_IGD_DEV, SA_MC_BUS, = 0, > SA_SEG_NUM, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, SA_IPU_FUN_NUM, SA_IPU_DEV_NUM, > SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, SA_GNA_FUN_NUM, SA_GNA_DEV_NUM, > SA_MC_BUS, 0, SA_SEG_NUM, 0}}, {0, 0},0}, > + // > + // PCH Device(s) > + // > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LPC, > PCI_DEVICE_NUMBER_PCH_LPC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_P2SB, > PCI_DEVICE_NUMBER_PCH_P2SB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_PMC, > PCI_DEVICE_NUMBER_PCH_PMC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_HDA, > PCI_DEVICE_NUMBER_PCH_HDA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SATA, > PCI_DEVICE_NUMBER_PCH_SATA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SMBUS, > PCI_DEVICE_NUMBER_PCH_SMBUS, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SPI, > PCI_DEVICE_NUMBER_PCH_SPI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + // > + // Skip PCH LAN controller > + // PCH LAN SVID/SID may be loaded automatically from the NVM Word > 0Ch/0Bh upon power up or reset > + // depending on the "Load Subsystem ID" bit field in NVM word 0Ah > + // > + //{{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LAN, > PCI_DEVICE_NUMBER_PCH_LAN, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_TRACE_HUB, > PCI_DEVICE_NUMBER_PCH_TRACE_HUB, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0, > PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1, > PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0, > PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1, > PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_CNL_SCS_SDCARD, > PCI_DEVICE_NUMBER_PCH_CNL_SCS_SDCARD, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XHCI, > PCI_DEVICE_NUMBER_PCH_XHCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XDCI, > PCI_DEVICE_NUMBER_PCH_XDCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_THERMAL, > PCI_DEVICE_NUMBER_PCH_THERMAL, DEFAULT_PCI_BUS_NUMBER_PCH, > 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_ISH, > PCI_DEVICE_NUMBER_PCH_ISH, DEFAULT_PCI_BUS_NUMBER_PCH, 0, > DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_21, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_22, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_23, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{R_PCH_PCIE_CFG_SVID, > PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_24, > PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0, > PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1, > PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2, > PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3, > PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2, > PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5, > PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4, > PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + // > + // ME Device(s) > + // > + {{{PCI_SVID_OFFSET, HECI_FUNCTION_NUMBER, ME_DEVICE_NUMBER, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, HECI2_FUNCTION_NUMBER, ME_DEVICE_NUMBER, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, IDER_FUNCTION_NUMBER, ME_DEVICE_NUMBER, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, SOL_FUNCTION_NUMBER, ME_DEVICE_NUMBER, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, HECI3_FUNCTION_NUMBER, ME_DEVICE_NUMBER, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0}, > + {{{PCI_SVID_OFFSET, HECI4_FUNCTION_NUMBER, ME_DEVICE_NUMBER, > DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, > 0}}, {0, 0},0} > +}; > + > +/** > + This function performs Silicon PEI Policy initialization. > + > + @param[in] SiPolicy The Silicon Policy PPI instance > + > + @retval EFI_SUCCESS The function completed successfully > +**/ > +EFI_STATUS > +EFIAPI > +UpdatePeiSiPolicy ( > + IN OUT SI_POLICY_PPI *SiPolicy > + ) > +{ > + EFI_STATUS Status; > + SI_CONFIG *SiConfig; > + > + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSiConfigGuid, (VOID *) > &SiConfig); > + ASSERT_EFI_ERROR (Status); > + > + SiConfig->CsmFlag =3D 0; > + > + if (IsCdfPch ()) { > + SiConfig->SsidTablePtr =3D (UINT32*)(UINTN) mCdfSsidTablePtr; > + SiConfig->NumberOfSsidTableEntry =3D (sizeof (mCdfSsidTablePtr) / si= zeof > (SVID_SID_INIT_ENTRY)); > + } else { > + SiConfig->SsidTablePtr =3D (UINT32*)(UINTN) mSsidTablePtr; > + SiConfig->NumberOfSsidTableEntry =3D (sizeof (mSsidTablePtr) / sizeo= f > (SVID_SID_INIT_ENTRY)); > + } > + return EFI_SUCCESS; > +} > + > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra > pperPlatformSecLib/Ia32/PeiCoreEntry.nasm > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/Ia32/PeiCoreEntry.nasm > new file mode 100644 > index 0000000000..5c5b788085 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/Ia32/PeiCoreEntry.nasm > @@ -0,0 +1,130 @@ > +;-----------------------------------------------------------------------= ------- > +; > +; Copyright (c) 2019, Intel Corporation. All rights reserved.
> +; SPDX-License-Identifier: BSD-2-Clause-Patent > +; > +; Module Name: > +; > +; PeiCoreEntry.nasm > +; > +; Abstract: > +; > +; Find and call SecStartup > +; > +;-----------------------------------------------------------------------= ------- > + > +SECTION .text > + > +extern ASM_PFX(SecStartup) > +extern ASM_PFX(PlatformInit) > + > +global ASM_PFX(CallPeiCoreEntryPoint) > +ASM_PFX(CallPeiCoreEntryPoint): > + ; > + ; Obtain the hob list pointer > + ; > + mov eax, [esp+4] > + ; > + ; Obtain the stack information > + ; ECX: start of range > + ; EDX: end of range > + ; > + mov ecx, [esp+8] > + mov edx, [esp+0xC] > + > + ; > + ; Platform init > + ; > + pushad > + push edx > + push ecx > + push eax > + call ASM_PFX(PlatformInit) > + pop eax > + pop eax > + pop eax > + popad > + > + ; > + ; Set stack top pointer > + ; > + mov esp, edx > + > + ; > + ; Push the hob list pointer > + ; > + push eax > + > + ; > + ; Save the value > + ; ECX: start of range > + ; EDX: end of range > + ; > + mov ebp, esp > + push ecx > + push edx > + > + ; > + ; Push processor count to stack first, then BIST status (AP then BSP) > + ; > + mov eax, 1 > + cpuid > + shr ebx, 16 > + and ebx, 0xFF > + cmp bl, 1 > + jae PushProcessorCount > + > + ; > + ; Some processors report 0 logical processors. Effectively 0 =3D 1. > + ; So we fix up the processor count > + ; > + inc ebx > + > +PushProcessorCount: > + push ebx > + > + ; > + ; We need to implement a long-term solution for BIST capture. For now= , we > just copy BSP BIST > + ; for all processor threads > + ; > + xor ecx, ecx > + mov cl, bl > +PushBist: > + movd eax, mm0 > + push eax > + loop PushBist > + > + ; Save Time-Stamp Counter > + movd eax, mm5 > + push eax > + > + movd eax, mm6 > + push eax > + > + ; > + ; Pass entry point of the PEI core > + ; > + mov edi, 0xFFFFFFE0 > + push DWORD [edi] > + > + ; > + ; Pass BFV into the PEI Core > + ; > + mov edi, 0xFFFFFFFC > + push DWORD [edi] > + > + ; > + ; Pass stack size into the PEI Core > + ; > + mov ecx, [ebp - 4] > + mov edx, [ebp - 8] > + push ecx ; RamBase > + > + sub edx, ecx > + push edx ; RamSize > + > + ; > + ; Pass Control into the PEI Core > + ; > + call ASM_PFX(SecStartup) > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra > pperPlatformSecLib/Ia32/SecEntry.nasm > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/Ia32/SecEntry.nasm > new file mode 100644 > index 0000000000..7f6d771e41 > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/Ia32/SecEntry.nasm > @@ -0,0 +1,361 @@ > +;-----------------------------------------------------------------------= ------- > +; > +; Copyright (c) 2019, Intel Corporation. All rights reserved.
> +; SPDX-License-Identifier: BSD-2-Clause-Patent > +; Module Name: > +; > +; SecEntry.nasm > +; > +; Abstract: > +; > +; This is the code that goes from real-mode to protected mode. > +; It consumes the reset vector, calls TempRamInit API from FSP binary. > +; > +;-----------------------------------------------------------------------= ------- > + > +#include "Fsp.h" > + > +SECTION .text > + > +extern ASM_PFX(CallPeiCoreEntryPoint) > +extern ASM_PFX(FsptUpdDataPtr) > +extern ASM_PFX(BoardBeforeTempRamInit) > +; Pcds > +extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize)) > +extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress)) > + > +;-----------------------------------------------------------------------= ----- > +; > +; Procedure: _ModuleEntryPoint > +; > +; Input: None > +; > +; Output: None > +; > +; Destroys: Assume all registers > +; > +; Description: > +; > +; Transition to non-paged flat-model protected mode from a > +; hard-coded GDT that provides exactly two descriptors. > +; This is a bare bones transition to protected mode only > +; used for a while in PEI and possibly DXE. > +; > +; After enabling protected mode, a far jump is executed to > +; transfer to PEI using the newly loaded GDT. > +; > +; Return: None > +; > +; MMX Usage: > +; MM0 =3D BIST State > +; MM5 =3D Save time-stamp counter value high32bit > +; MM6 =3D Save time-stamp counter value low32bit. > +; > +;-----------------------------------------------------------------------= ----- > + > +BITS 16 > +align 4 > +global ASM_PFX(_ModuleEntryPoint) > +ASM_PFX(_ModuleEntryPoint): > + fninit ; clear any pending Floating poi= nt exceptions > + ; > + ; Store the BIST value in mm0 > + ; > + movd mm0, eax > + cli > + > + ; > + ; Check INIT# is asserted by port 0xCF9 > + ; > + mov dx, 0CF9h > + in al, dx > + cmp al, 04h > + jnz NotWarmStart > + > + > + ; > + ; @note Issue warm reset, since if CPU only reset is issued not all MS= Rs are > restored to their defaults > + ; > + mov dx, 0CF9h > + mov al, 06h > + out dx, al > + > +NotWarmStart: > + ; > + ; Save time-stamp counter value > + ; rdtsc load 64bit time-stamp counter to EDX:EAX > + ; > + rdtsc > + movd mm5, edx > + movd mm6, eax > + > + ; > + ; Load the GDT table in GdtDesc > + ; > + mov esi, GdtDesc > + DB 66h > + lgdt [cs:si] > + > + ; > + ; Transition to 16 bit protected mode > + ; > + mov eax, cr0 ; Get control register 0 > + or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit= #1) > + mov cr0, eax ; Activate protected mode > + > + mov eax, cr4 ; Get control register 4 > + or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEX= CPT bit > (bit #10) > + mov cr4, eax > + > + ; > + ; Now we're in 16 bit protected mode > + ; Set up the selectors for 32 bit protected mode entry > + ; > + mov ax, SYS_DATA_SEL > + mov ds, ax > + mov es, ax > + mov fs, ax > + mov gs, ax > + mov ss, ax > + > + ; > + ; Transition to Flat 32 bit protected mode > + ; The jump to a far pointer causes the transition to 32 bit mode > + ; > + mov esi, ProtectedModeEntryLinearAddress > + jmp dword far [cs:si] > + > +;-----------------------------------------------------------------------= ----- > +; > +; Procedure: ProtectedModeEntryPoint > +; > +; Input: None > +; > +; Output: None > +; > +; Destroys: Assume all registers > +; > +; Description: > +; > +; This function handles: > +; Call two basic APIs from FSP binary > +; Initializes stack with some early data (BIST, PEI entry, etc) > +; > +; Return: None > +; > +;-----------------------------------------------------------------------= ----- > + > +BITS 32 > +align 4 > +ProtectedModeEntryPoint: > + ; > + ; Early board hooks > + ; > + mov esp, BoardBeforeTempRamInitRet > + jmp ASM_PFX(BoardBeforeTempRamInit) > + > +BoardBeforeTempRamInitRet: > + > + ; Find the fsp info header > + mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))] > + > + mov eax, dword [edi + FVH_SIGINATURE_OFFSET] > + cmp eax, FVH_SIGINATURE_VALID_VALUE > + jnz FspHeaderNotFound > + > + xor eax, eax > + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET] > + cmp ax, 0 > + jnz FspFvExtHeaderExist > + > + xor eax, eax > + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header > + add edi, eax > + jmp FspCheckFfsHeader > + > +FspFvExtHeaderExist: > + add edi, eax > + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv > Header > + add edi, eax > + > + ; Round up to 8 byte alignment > + mov eax, edi > + and al, 07h > + jz FspCheckFfsHeader > + > + and edi, 0FFFFFFF8h > + add edi, 08h > + > +FspCheckFfsHeader: > + ; Check the ffs guid > + mov eax, dword [edi] > + cmp eax, FSP_HEADER_GUID_DWORD1 > + jnz FspHeaderNotFound > + > + mov eax, dword [edi + 4] > + cmp eax, FSP_HEADER_GUID_DWORD2 > + jnz FspHeaderNotFound > + > + mov eax, dword [edi + 8] > + cmp eax, FSP_HEADER_GUID_DWORD3 > + jnz FspHeaderNotFound > + > + mov eax, dword [edi + 0Ch] > + cmp eax, FSP_HEADER_GUID_DWORD4 > + jnz FspHeaderNotFound > + > + add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header > + > + ; Check the section type as raw section > + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET] > + cmp al, 019h > + jnz FspHeaderNotFound > + > + add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header > + jmp FspHeaderFound > + > +FspHeaderNotFound: > + jmp $ > + > +FspHeaderFound: > + ; Get the fsp TempRamInit Api address > + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] > + add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] > + > + ; Setup the hardcode stack > + mov esp, TempRamInitStack > + > + ; Call the fsp TempRamInit Api > + jmp eax > + > +TempRamInitDone: > + cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code f= or > Microcode Update not found. > + je CallSecFspInit ;If microcode not found, don't hang, but conti= nue. > + > + cmp eax, 0 ;Check if EFI_SUCCESS retuned. > + jnz FspApiFailed > + > + ; ECX: start of range > + ; EDX: end of range > +CallSecFspInit: > + sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; > TemporaryRam for FSP > + xor eax, eax > + mov esp, edx > + > + ; Align the stack at DWORD > + add esp, 3 > + and esp, 0FFFFFFFCh > + > + push edx > + push ecx > + push eax ; zero - no hob list yet > + call ASM_PFX(CallPeiCoreEntryPoint) > + > +FspApiFailed: > + jmp $ > + > +align 10h > +TempRamInitStack: > + DD TempRamInitDone > + DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams > + > +; > +; ROM-based Global-Descriptor Table for the Tiano PEI Phase > +; > +align 16 > +global ASM_PFX(BootGdtTable) > + > +; > +; GDT[0]: 0x00: Null entry, never used. > +; > +NULL_SEL EQU $ - GDT_BASE ; Selector [0] > +GDT_BASE: > +ASM_PFX(BootGdtTable): > + DD 0 > + DD 0 > +; > +; Linear data segment descriptor > +; > +LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8] > + DW 0FFFFh ; limit 0xFFFFF > + DW 0 ; base 0 > + DB 0 > + DB 092h ; present, ring 0, data, expand-= up, writable > + DB 0CFh ; page-granular, 32-bit > + DB 0 > +; > +; Linear code segment descriptor > +; > +LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10] > + DW 0FFFFh ; limit 0xFFFFF > + DW 0 ; base 0 > + DB 0 > + DB 09Bh ; present, ring 0, data, expand-= up, > not-writable > + DB 0CFh ; page-granular, 32-bit > + DB 0 > +; > +; System data segment descriptor > +; > +SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18] > + DW 0FFFFh ; limit 0xFFFFF > + DW 0 ; base 0 > + DB 0 > + DB 093h ; present, ring 0, data, expand-= up, > not-writable > + DB 0CFh ; page-granular, 32-bit > + DB 0 > + > +; > +; System code segment descriptor > +; > +SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20] > + DW 0FFFFh ; limit 0xFFFFF > + DW 0 ; base 0 > + DB 0 > + DB 09Ah ; present, ring 0, data, expand-= up, writable > + DB 0CFh ; page-granular, 32-bit > + DB 0 > +; > +; Spare segment descriptor > +; > +SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28] > + DW 0FFFFh ; limit 0xFFFFF > + DW 0 ; base 0 > + DB 0Eh ; Changed from F000 to E000. > + DB 09Bh ; present, ring 0, code, expand-= up, writable > + DB 00h ; byte-granular, 16-bit > + DB 0 > +; > +; Spare segment descriptor > +; > +SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30] > + DW 0FFFFh ; limit 0xFFFF > + DW 0 ; base 0 > + DB 0 > + DB 093h ; present, ring 0, data, expand-= up, > not-writable > + DB 00h ; byte-granular, 16-bit > + DB 0 > + > +; > +; Spare segment descriptor > +; > +SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38] > + DW 0 ; limit 0 > + DW 0 ; base 0 > + DB 0 > + DB 0 ; present, ring 0, data, expand-= up, writable > + DB 0 ; page-granular, 32-bit > + DB 0 > +GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes > + > +; > +; GDT Descriptor > +; > +GdtDesc: ; GDT descriptor > + DW GDT_SIZE - 1 ; GDT limit > + DD GDT_BASE ; GDT base address > + > + > +ProtectedModeEntryLinearAddress: > +ProtectedModeEntryLinear: > + DD ProtectedModeEntryPoint ; Offset of our 32 bit code > + DW LINEAR_CODE_SEL > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWra > pperPlatformSecLib/Ia32/Stack.nasm > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/Ia32/Stack.nasm > new file mode 100644 > index 0000000000..47db32d64c > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWr > apperPlatformSecLib/Ia32/Stack.nasm > @@ -0,0 +1,72 @@ > +;-----------------------------------------------------------------------= ------- > +; > +; Copyright (c) 2019, Intel Corporation. All rights reserved.
> +; SPDX-License-Identifier: BSD-2-Clause-Patent > +; Abstract: > +; > +; Switch the stack from temporary memory to permanent memory. > +; > +;-----------------------------------------------------------------------= ------- > + > + SECTION .text > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; SecSwitchStack ( > +; UINT32 TemporaryMemoryBase, > +; UINT32 PermanentMemoryBase > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(SecSwitchStack) > +ASM_PFX(SecSwitchStack): > + ; > + ; Save three register: eax, ebx, ecx > + ; > + push eax > + push ebx > + push ecx > + push edx > + > + ; > + ; !!CAUTION!! this function address's is pushed into stack after > + ; migration of whole temporary memory, so need save it to permanent > + ; memory at first! > + ; > + > + mov ebx, [esp + 20] ; Save the first parameter > + mov ecx, [esp + 24] ; Save the second parameter > + > + ; > + ; Save this function's return address into permanent memory at first= . > + ; Then, Fixup the esp point to permanent memory > + ; > + mov eax, esp > + sub eax, ebx > + add eax, ecx > + mov edx, dword [esp] ; copy pushed register's value to per= manent > memory > + mov dword [eax], edx > + mov edx, dword [esp + 4] > + mov dword [eax + 4], edx > + mov edx, dword [esp + 8] > + mov dword [eax + 8], edx > + mov edx, dword [esp + 12] > + mov dword [eax + 12], edx > + mov edx, dword [esp + 16] ; Update this function's return addre= ss into > permanent memory > + mov dword [eax + 16], edx > + mov esp, eax ; From now, esp is pointed to per= manent > memory > + > + ; > + ; Fixup the ebp point to permanent memory > + ; > + mov eax, ebp > + sub eax, ebx > + add eax, ecx > + mov ebp, eax ; From now, ebp is pointed to permanen= t > memory > + > + pop edx > + pop ecx > + pop ebx > + pop eax > + ret > + > diff --git > a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpi > TimerLib.uni > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpi > TimerLib.uni > new file mode 100644 > index 0000000000..33b4be68db > --- /dev/null > +++ > b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpi > TimerLib.uni > @@ -0,0 +1,15 @@ > +/** @file > + Base ACPI Timer Library > + Provides basic timer support using the ACPI timer hardware. The > performance > + counter features are provided by the processors time stamp counter. > + > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#string STR_MODULE_ABSTRACT #language en-US "ACPI Timer > Library" > + > +#string STR_MODULE_DESCRIPTION #language en-US "Provides basic > timer support using the ACPI timer hardware." > + > + > -- > 2.16.2.windows.1