Re: [edk2-platforms][PATCH V1 36/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files

["Chiu, Chasel" <chasel.chiu@intel.com>]

Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>


> -----Original Message-----
> From: Kubacki, Michael A
> Sent: Saturday, August 17, 2019 8:16 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>
> Subject: [edk2-platforms][PATCH V1 36/37]
> WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2083
> 
> Adds the DSC and build files necessary to build the
> WhiskeylakeURvp board instance.
> 
> Key files
> =========
> * build_config.cfg - Board-specific build configuration file.
> * OpenBoardPkg.dsc - The WhiskeylakeURvp board description file.
> * OpenBoardPkgConfig.dsc - Used for feature-related PCD
>   customization.
> * OpenBoardPkgPcd.dsc - Used for other PCD customization.
> * OpenBoardPkg.fdf - The WhiskeylakeURvp board flash file.
> * FlashMapInclude.fdf - The WhiskeylakeURvp board flash map.
> * OpenBoardPkgBuildOption.dsc - Sets build options Based
>   on PCD values.
> 
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
> ---
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> .dsc                | 385 +++++++++++
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> BuildOption.dsc     | 154 +++++
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> Config.dsc          | 128 ++++
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> Pcd.dsc             | 245 +++++++
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/Fla
> shMapInclude.fdf |  49 ++
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg
> .fdf                | 706 ++++++++++++++++++++
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cf
> g                |  33 +
>  7 files changed, 1700 insertions(+)
> 
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> new file mode 100644
> index 0000000000..eea809140c
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.dsc
> @@ -0,0 +1,385 @@
> +## @file
> +#  Platform description.
> +#
> +#
> +#  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> +  #
> +  # Set platform specific package/folder name, same as passed from PREBUILD
> script.
> +  # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as
> package build folder
> +  # DEFINE only takes effect at R9 DSC and FDF.
> +  #
> +  DEFINE      PLATFORM_PACKAGE          = MinPlatformPkg
> +  DEFINE      PLATFORM_SI_PACKAGE       = CoffeelakeSiliconPkg
> +  DEFINE      PLATFORM_SI_BIN_PACKAGE   = CoffeelakeSiliconBinPkg
> +  DEFINE      PLATFORM_FSP_BIN_PACKAGE  = CoffeeLakeFspBinPkg
> +  DEFINE      PLATFORM_BOARD_PACKAGE    = WhiskeylakeOpenBoardPkg
> +  DEFINE      BOARD                     = WhiskeylakeURvp
> +  DEFINE      PROJECT                   =
> $(PLATFORM_BOARD_PACKAGE)/$(BOARD)
> +
> +  #
> +  # Platform On/Off features are defined here
> +  #
> +  !include OpenBoardPkgConfig.dsc
> +
> +###############################################################
> #################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +###############################################################
> #################
> +[Defines]
> +  PLATFORM_NAME                       = $(PLATFORM_PACKAGE)
> +  PLATFORM_GUID                       =
> 84D0F5BD-0EF3-4CC0-9B09-F2D0F2AA5C5E
> +  PLATFORM_VERSION                    = 0.1
> +  DSC_SPECIFICATION                   = 0x00010005
> +  OUTPUT_DIRECTORY                    = Build/$(PROJECT)
> +  SUPPORTED_ARCHITECTURES             = IA32|X64
> +  BUILD_TARGETS                       = DEBUG|RELEASE
> +  SKUID_IDENTIFIER                    = ALL
> +
> +
> +  FLASH_DEFINITION                    = $(PROJECT)/OpenBoardPkg.fdf
> +
> +  FIX_LOAD_TOP_MEMORY_ADDRESS         = 0x0
> +  DEFINE   TOP_MEMORY_ADDRESS         = 0x0
> +
> +  #
> +  # Default value for OpenBoardPkg.fdf use
> +  #
> +  DEFINE BIOS_SIZE_OPTION = SIZE_70
> +
> +###############################################################
> #################
> +#
> +# SKU Identification section - list of all SKU IDs supported by this
> +#                              Platform.
> +#
> +###############################################################
> #################
> +[SkuIds]
> +  0|DEFAULT              # The entry: 0|DEFAULT is reserved and always
> required.
> +  0x60|WhiskeylakeURvp
> +
> +###############################################################
> #################
> +#
> +# Library Class section - list of all Library Classes needed by this Platform.
> +#
> +###############################################################
> #################
> +
> +  !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc
> +  !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc
> +  !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc
> +
> +[LibraryClasses.common]
> +
> +  PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf
> +
> ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/Pe
> iReportFvLib.inf
> +
> +
> PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimpl
> e/PciHostBridgeLibSimple.inf
> +
> PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSi
> mple/PciSegmentInfoLibSimple.inf
> +
> PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformB
> ootManagerLib/DxePlatformBootManagerLib.inf
> +
> I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2c
> AccessLib.inf
> +
> GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpand
> erLib/BaseGpioExpanderLib.inf
> +
> +
> PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHo
> okLib.inf
> +
> +
> FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/Pei
> FspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
> +
> PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFsp
> WrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> +
> +
> FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/Ba
> seFspWrapperApiLib.inf
> +
> FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestL
> ib/PeiFspWrapperApiTestLib.inf
> +
> +
> FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFsp
> WrapperPlatformLib/PeiFspWrapperPlatformLib.inf
> +
> SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library
> /PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> +
> +
> ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/Base
> ConfigBlockLib.inf
> +
> BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/
> BoardInitLibNull.inf
> +
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibN
> ull/TestPointCheckLibNull.inf
> +
> +  # Tbt
> +  !if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
> +
> TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDx
> eSmmTbtCommonLib/TbtCommonLib.inf
> +  !endif
> +
> DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeT
> btPolicyLib/DxeTbtPolicyLib.inf
> +  #
> +  # Silicon Init Package
> +  #
> +  !include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc
> +
> PchHsioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchHsioLib/P
> eiDxeSmmPchHsioLib.inf
> +
> MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDxeS
> mmMmPciLib.inf
> +
> PchPmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPmcLib/Pe
> iDxeSmmPchPmcLib.inf
> +
> +
> TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTim
> erLib.inf
> +
> +[LibraryClasses.IA32]
> +  #
> +  # PEI phase common
> +  #
> +
> SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/Pei
> FspPolicyInitLib/PeiFspPolicyInitLib.inf
> +
> FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFsp
> WrapperPlatformLib/PeiFspWrapperPlatformLib.inf
> +  !if $(TARGET) == DEBUG
> +
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/P
> eiTestPointCheckLib.inf
> +  !endif
> +
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL
> ib.inf
> +
> MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Mult
> iBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf
> +
> BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSu
> pportLib/PeiMultiBoardInitSupportLib.inf
> +
> TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTim
> erLib.inf
> +
> HdaVerbTableLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiHdaVerbTableL
> ib/PeiHdaVerbTableLib.inf
> +
> +  # Tbt
> +  !if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
> +
> PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTb
> tPolicyLib/PeiTbtPolicyLib.inf
> +
> PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private
> /PeiDTbtInitLib/PeiDTbtInitLib.inf
> +  !endif
> +
> +  #
> +  # Silicon Init Package
> +  #
> +  !include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc
> +
> PeiPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyInitL
> ib/PeiPolicyInitLib.inf
> +
> PeiPolicyBoardConfigLib|$(PROJECT)/Library/PeiPolicyBoardConfigLib/PeiPoli
> cyBoardConfigLib.inf
> +
> PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicy
> UpdateLib/PeiPolicyUpdateLib.inf
> +
> PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHo
> oklib.inf
> +  !if $(TARGET) == DEBUG
> +
> GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLib/BaseGp
> ioCheckConflictLib.inf
> +  !else
> +
> GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLibNull/Bas
> eGpioCheckConflictLibNull.inf
> +  !endif
> +
> +[LibraryClasses.IA32.SEC]
> +
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S
> ecTestPointCheckLib.inf
> +
> SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLi
> bNull/SecBoardInitLibNull.inf
> +
> TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTim
> erLib.inf
> +
> +[LibraryClasses.X64]
> +  #
> +  # DXE phase common
> +  #
> +
> FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFs
> pWrapperPlatformLib/DxeFspWrapperPlatformLib.inf
> +  !if $(TARGET) == DEBUG
> +
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/D
> xeTestPointCheckLib.inf
> +  !endif
> +
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPoint
> Lib.inf
> +
> MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Mult
> iBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf
> +
> BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSu
> pportLib/DxeMultiBoardInitSupportLib.inf
> +
> MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoard
> AcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf
> +
> BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSup
> portLib/DxeMultiBoardAcpiSupportLib.inf
> +
> +
> DxePolicyBoardConfigLib|$(PROJECT)/Library/DxePolicyBoardConfigLib/DxeP
> olicyBoardConfigLib.inf
> +
> DxePolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxePolic
> yUpdateLib/DxePolicyUpdateLib.inf
> +  #
> +  # Silicon Init Package
> +  #
> +  !include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i
> nf
> +
> +[LibraryClasses.X64.DXE_SMM_DRIVER]
> +
> SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCo
> mmonLib/SmmSpiFlashCommonLib.inf
> +  !if $(TARGET) == DEBUG
> +
> TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S
> mmTestPointCheckLib.inf
> +  !endif
> +
> TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPoin
> tLib.inf
> +
> MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoard
> AcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
> +
> BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSu
> pportLib/SmmMultiBoardAcpiSupportLib.inf
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i
> nf
> +
> +[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
> +
> ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSy
> stemLib/DxeRuntimeResetSystemLib.inf
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i
> nf
> +  !include OpenBoardPkgPcd.dsc
> +
> +[Components.IA32]
> +  #
> +  # Common
> +  #
> +  !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc
> +
> +  #
> +  # FSP wrapper SEC Core
> +  #
> +  UefiCpuPkg/SecCore/SecCore.inf {
> +    <LibraryClasses>
> +      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> +  }
> +
> +  #
> +  # Silicon
> +  #
> +  !include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc
> +
> +  #
> +  # Platform
> +  #
> +  $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
> +
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.in
> f {
> +    <LibraryClasses>
> +      !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
> +
> BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
> +      !else
> +
> NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
> +      !endif
> +      NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf
> +  }
> +  IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
> +
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe
> m.inf {
> +    <LibraryClasses>
> +
> SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLib
> Null/SiliconPolicyInitLibNull.inf
> +
> SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyUp
> dateLibNull/SiliconPolicyUpdateLibNull.inf
> +  }
> +
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.i
> nf {
> +    <LibraryClasses>
> +      !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
> +
> BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
> +      !else
> +
> NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
> +      !endif
> +  }
> +  IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
> +#to do
> $(PLATFORM_PACKAGE)/FspWrapper/FspWrapperPeim/FspWrapperPeim.inf
> +
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe
> m.inf {
> +    <LibraryClasses>
> +
> SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLib
> Null/SiliconPolicyInitLibNull.inf
> +
> SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyUp
> dateLibNull/SiliconPolicyUpdateLibNull.inf
> +  }
> +
> +  #
> +  # Security
> +  #
> +
> +  !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> +    $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
> +  !endif
> +
> +  IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
> +
> IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSam
> plePei.inf
> +
> +  # Tbt
> +  !if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
> +    $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
> +  !endif
> +
> +[Components.X64]
> +
> +  #
> +  # Common
> +  #
> +  !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc
> +
> +  $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
> +
> +  UefiCpuPkg/CpuDxe/CpuDxe.inf
> +  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> +
> +  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> +  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +
> MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.
> inf
> +  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +
> +  #
> +  # Shell
> +  #
> +  ShellPkg/Application/Shell/Shell.inf {
> +   <PcdsFixedAtBuild>
> +     gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> +   <LibraryClasses>
> +
> NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Comm
> andsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Com
> mandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com
> mandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C
> ommandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C
> ommandsLib.inf
> +
> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComma
> ndLib.inf
> +
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsing
> Lib.inf
> +
> BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgC
> ommandLib.inf
> +
> ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
> +     ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> +  }
> +
> +  #
> +  # Silicon
> +  #
> +  !include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc
> +
> +  # Tbt
> +  !if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
> +    $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
> +    $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
> +    $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
> +  !endif
> +
> +  #
> +  # Platform
> +  #
> +  $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf{
> +    <LibraryClasses>
> +      NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf
> +  }
> +
> +  $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
> {
> +    <LibraryClasses>
> +
> SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLib
> Null/SiliconPolicyInitLibNull.inf
> +
> SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicyUp
> dateLibNull/SiliconPolicyUpdateLibNull.inf
> +  }
> +  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
> +  IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
> +
> +
> $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfi
> g.inf
> +
> +  $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
> +  $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf
> +
> +  #
> +  # OS Boot
> +  #
> +  !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +    $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
> +  $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
> +  $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {
> +    <LibraryClasses>
> +      !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
> +
> BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnabl
> eLib.inf
> +      !else
> +
> NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
> +      !endif
> +  }
> +
> +  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> +
> +  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {
> +    <PcdsPatchableInModule>
> +      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046
> +    <LibraryClasses>
> +      !if $(TARGET) == DEBUG
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i
> nf
> +      !endif
> +  }
> +
> +  !endif
> +
> +  #
> +  # Security
> +  #
> +  $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
> +
> +  !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> +    $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
> +  !endif
> +
> +  IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
> +
> +  #
> +  # Other
> +  #
> +  $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf
> +
> +  !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc
> +  !include OpenBoardPkgBuildOption.dsc
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kgBuildOption.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kgBuildOption.dsc
> new file mode 100644
> index 0000000000..be1d47c719
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kgBuildOption.dsc
> @@ -0,0 +1,154 @@
> +## @file
> +# platform build option configuration file.
> +#
> +#
> +#  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[BuildOptions]
> +# Define Build Options both for EDK and EDKII drivers.
> +
> +
> +  DEFINE DSC_S3_BUILD_OPTIONS =
> +
> +  DEFINE DSC_CSM_BUILD_OPTIONS =
> +
> +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE
> +  DEFINE DSC_ACPI_BUILD_OPTIONS = -DACPI_SUPPORT=1
> +!else
> +  DEFINE DSC_ACPI_BUILD_OPTIONS =
> +!endif
> +
> +  DEFINE BIOS_GUARD_BUILD_OPTIONS =
> +
> +  DEFINE OVERCLOCKING_BUILD_OPTION =
> +
> +  DEFINE FSP_BINARY_BUILD_OPTIONS =
> +
> +  DEFINE FSP_WRAPPER_BUILD_OPTIONS = -DFSP_WRAPPER_FLAG
> +
> +  DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =
> +
> +  DEFINE RESTRICTED_OPTION =
> +
> +
> +  DEFINE SV_BUILD_OPTIONS =
> +
> +  DEFINE TEST_MENU_BUILD_OPTION =
> +
> +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE
> +  DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL-
> +!else
> +  DEFINE OPTIMIZE_DISABLE_OPTIONS =
> +!endif
> +
> +  DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =
> +
> +
> +  DEFINE TPM_BUILD_OPTION =
> +
> +  DEFINE TPM2_BUILD_OPTION =
> +
> +  DEFINE DSC_TBT_BUILD_OPTIONS =
> +
> +  DEFINE DSC_DCTT_BUILD_OPTIONS =
> +
> +  DEFINE EMB_BUILD_OPTIONS =
> +
> +  DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS = -DMEM_DOWN_FLAG=1
> +
> +  DEFINE DSC_KBCEMUL_BUILD_OPTIONS =
> +
> +  DEFINE BOOT_GUARD_BUILD_OPTIONS =
> +
> +  DEFINE SECURE_BOOT_BUILD_OPTIONS =
> +
> +  DEFINE USBTYPEC_BUILD_OPTION =
> +
> +  DEFINE CAPSULE_BUILD_OPTIONS =
> +
> +  DEFINE PERFORMANCE_BUILD_OPTION =
> +
> +  DEFINE DEBUGUSEUSB_BUILD_OPTION =
> +
> +  DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION =
> -DDISABLE_NEW_DEPRECATED_INTERFACES=1
> +
> +  DEFINE SINITBIN_BUILD_OPTION =
> +
> +  DEFINE MINTREE_FLAG_BUILD_OPTION = -DMINTREE_FLAG=1
> +
> +  DEFINE CPUTYPE_BUILD_OPTION = -DCPU_CFL=1
> +
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)  $(OVERCLOCKING_BUILD_OPTION)
> $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_OPTIONS)
> $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS)
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(BOOT_GUARD_BUILD_OPTIONS)
> $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGUSEUSB_BUILD_OPTION)
> $(DSC_S3_BUILD_OPTIONS)
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(FSP_BINARY_BUILD_OPTIONS)
> $(FSP_WRAPPER_BUILD_OPTIONS)
> $(SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS)
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_KBCEMUL_BUILD_OPTIONS)
> $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_BUILD_OPTIONS)
> $(DSC_CSM_BUILD_OPTIONS)
> $(DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION)
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(TPM2_BUILD_OPTION)
> $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS)
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS)
> $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYPEC_BUILD_OPTION)
> $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION)
> +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(CPUTYPE_BUILD_OPTION)
> +[BuildOptions.Common.EDKII]
> +
> +#
> +# For IA32 Global Build Flag
> +#
> +       *_*_IA32_CC_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
> +       *_*_IA32_VFRPP_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +       *_*_IA32_APP_FLAGS     = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +       *_*_IA32_ASLPP_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +       *_*_IA32_ASLCC_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +       *_*_IA32_NASM_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +
> +#
> +# For IA32 Specific Build Flag
> +#
> +GCC:   *_*_IA32_PP_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +MSFT:  *_*_IA32_ASM_FLAGS     =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +MSFT:  *_*_IA32_CC_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
> -DASF_PEI
> +MSFT:  *_*_IA32_VFRPP_FLAGS   =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> +MSFT:  *_*_IA32_APP_FLAGS     = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> $(OPTIMIZE_DISABLE_OPTIONS)
> +MSFT:  *_*_IA32_ASLPP_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> $(OPTIMIZE_DISABLE_OPTIONS)
> +MSFT:  *_*_IA32_ASLCC_FLAGS   =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> +
> +#
> +# For X64 Global Build Flag
> +#
> +       *_*_X64_CC_FLAGS       = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D
> PI_SPECIFICATION_VERSION=0x00010015
> +       *_*_X64_VFRPP_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +       *_*_X64_APP_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +       *_*_X64_ASLPP_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +       *_*_X64_ASLCC_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +       *_*_X64_NASM_FLAGS     = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +
> +
> +#
> +# For X64 Specific Build Flag
> +#
> +GCC:   *_*_X64_PP_FLAGS       = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +MSFT:  *_*_X64_ASM_FLAGS      =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +MSFT:  *_*_X64_CC_FLAGS       = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
> +MSFT:  *_*_X64_VFRPP_FLAGS    =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> +MSFT:  *_*_X64_APP_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> $(OPTIMIZE_DISABLE_OPTIONS)
> +MSFT:  *_*_X64_ASLPP_FLAGS    =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +MSFT:  *_*_X64_ASLCC_FLAGS    =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +
> +
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support page
> level protection
> +[BuildOptions.common.EDKII.DXE_SMM_DRIVER,
> BuildOptions.common.EDKII.SMM_CORE]
> +  MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> +  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support
> MemoryAttribute table
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> +  MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> +  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support NX
> protection
> +[BuildOptions.common.EDKII.DXE_DRIVER,
> BuildOptions.common.EDKII.DXE_CORE,
> BuildOptions.common.EDKII.UEFI_DRIVER,
> BuildOptions.common.EDKII.UEFI_APPLICATION]
> +  #MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> +  #GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kgConfig.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kgConfig.dsc
> new file mode 100644
> index 0000000000..c68fecf50e
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kgConfig.dsc
> @@ -0,0 +1,128 @@
> +## @file
> +#  Platform configuration file.
> +#
> +#
> +#  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[PcdsFixedAtBuild]
> +  #
> +  # Please select BootStage here.
> +  # Stage 1 - enable debug (system deadloop after debug init)
> +  # Stage 2 - mem init (system deadloop after mem init)
> +  # Stage 3 - boot to shell only
> +  # Stage 4 - boot to OS
> +  # Stage 5 - boot to OS with security boot enabled
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
> +
> +[PcdsFeatureFlag]
> +  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
> +  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
> +  gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
> +  gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
> +  gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
> +  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
> +  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
> +  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
> +  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
> +  gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
> +  gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
> +  gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
> +  gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
> +!endif
> +
> +  gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE
> +  #
> +  # More fine granularity control below:
> +  #
> +
> +  gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE
> +
> +#
> +# TRUE is ENABLE. FALSE is DISABLE.
> +#
> +#
> +# BIOS build switches configuration
> +#
> +  gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
> +
> +# CPU
> +  gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
> +
> +# SA
> +  gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
> +
> +# ME
> +  gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
> +
> +  gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE
> +  gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE                       # TRUE -
> HPET / FALSE - 8254 timer is used.
> +  gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
> +
> +  gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE
> +  gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE
> +
> +#
> +# Override some PCDs for specific build requirements.
> +#
> +  #
> +  # Disable USB debug message when Source Level Debug is enabled
> +  # because they cannot be enabled at the same time.
> +  #
> +
> +    gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
> +
> +  !if $(TARGET) == DEBUG
> +    gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
> +  !else
> +    gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
> +  !endif
> +
> +  !if $(TARGET) == DEBUG
> +    gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
> +  !else
> +    gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
> +  !endif
> +
> +    gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kgPcd.dsc
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kgPcd.dsc
> new file mode 100644
> index 0000000000..96d65133ae
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kgPcd.dsc
> @@ -0,0 +1,245 @@
> +## @file
> +#  Platform description.
> +#
> +#
> +#  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +###############################################################
> #################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +###############################################################
> #################
> +[PcdsFeatureFlag.common]
> +
> #gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|T
> RUE
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSection
> First|FALSE
> +!if $(TARGET) == RELEASE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
> +!else
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
> +!endif
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
> +
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> +
> +  gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE
> +
> +[PcdsFixedAtBuild.common]
> +  gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
> +  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
> +!endif
> +
> +  gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
> +  gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
> +  gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
> +
> +  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
> +  gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
> +  gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
> +  gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
> +  gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
> +  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
> +  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
> +
> +  gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize        |
> 0x00026000
> +
> +  gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x40
> 0
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
> +!if $(TARGET) == RELEASE
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
> +  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
> +!else
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALS
> E
> +  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +!endif
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(T
> OP_MEMORY_ADDRESS)
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TR
> UE
> +
> +#
> +# 8MB Default
> +#
> +gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000
> +
> +#
> +# 16MB TSEG in Debug build only.
> +#
> +!if $(TARGET) == DEBUG
> +  gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
> +!endif
> +
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
> +
> +  !if $(TARGET) == RELEASE
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402
> +  !else
> +
> gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188
> B
> +  !endif
> +
> +
> +  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b
> +  !if $(TARGET) == RELEASE
> +  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
> +  !else
> +  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0
> +  !endif
> +
> +  gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEAC000
> +  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFDC0000
> +
> +  ## Specifies the size of the microcode Region.
> +  # @Prompt Microcode Region size.
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
> +
> +  ## Specifies timeout value in microseconds for the BSP to detect all APs for
> the first time.
> +  # @Prompt Timeout for the BSP to detect all APs for the first time.
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
> +
> +  ## Specifies the AP wait loop state during POST phase.
> +  #  The value is defined as below.
> +  #  1: Place AP in the Hlt-Loop state.
> +  #  2: Place AP in the Mwait-Loop state.
> +  #  3: Place AP in the Run-Loop state.
> +  # @Prompt The AP wait loop state.
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
> +
> +
> +  #
> +  # The PCDs are used to control the Windows SMM Security Mitigations Table
> - Protection Flags
> +  #
> +  # BIT0: If set, expresses that for all synchronous SMM entries,SMM will
> validate that input and output buffers lie entirely within the expected fixed
> memory regions.
> +  # BIT1: If set, expresses that for all synchronous SMM entries, SMM will
> validate that input and output pointers embedded within the fixed
> communication buffer only refer to address ranges \
> +  #       that lie entirely within the expected fixed memory regions.
> +  # BIT2: Firmware setting this bit is an indication that it will not allow
> reconfiguration of system resources via non-architectural mechanisms.
> +  # BIT3-31: Reserved
> +  #
> +  gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1
> +  gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2
> +  gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3
> +  gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4
> +  gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00}
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5
> +  gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00}
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
> +  gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03,
> 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00}
> +!endif
> +
> +[PcdsFixedAtBuild.IA32]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
> +  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
> +  gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
> +  gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
> +
> +[PcdsFixedAtBuild.X64]
> +  # Default platform supported RFC 4646 languages: (American) English
> +
> gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-
> US"
> +
> +
> +[PcdsPatchableInModule.common]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> +
> +!if $(TARGET) == DEBUG
> +  gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
> +!endif
> +
> +[PcdsDynamicHii.X64.DEFAULT]
> +
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGloba
> lVariableGuid|0x0|5 # Variable: L"Timeout"
> +
> gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupp
> ort"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
> +
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGloba
> lVariableGuid|0x0|1 # Variable: L"Timeout"
> +!endif
> +
> +[PcdsDynamicDefault]
> +  gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFD50000
> +  # Platform will pre-allocate UPD buffer and pass it to FspWrapper
> +  # Those dummy address will be patched before FspWrapper executing
> +  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0
> +  gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0
> +
> +  ## Specifies max supported number of Logical Processors.
> +  # @Prompt Configure max supported number of Logical Processors
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
> +
> +[PcdsDynamicDefault.common.DEFAULT]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
> +  #
> +  #  Set video to native resolution as Windows 8 WHCK requirement.
> +  #
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0
> +
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
> +
> +  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00
> +
> +[PcdsDynamicDefault.common.DEFAULT]
> +
> +  # Tbt
> +  gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel | 0x1
> +  gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad | 13
> +  gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |
> 0x02010011
> +  gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport | 0x0
> +  gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI | 0x1
> +  gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify | 0x1
> +  gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq| 0x1
> +  gBoardModuleTokenSpaceGuid.PcdDTbtAspm | 0x0
> +  gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch | 0x0
> +
> +  gBoardModuleTokenSpaceGuid.PcdRtd3Tbt | 0x1
> +  gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq | 0x1
> +  gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26
> +  gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100
> +  gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/
> FlashMapInclude.fdf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/
> FlashMapInclude.fdf
> new file mode 100644
> index 0000000000..9209b9e88a
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/
> FlashMapInclude.fdf
> @@ -0,0 +1,49 @@
> +## @file
> +#  FDF file of Platform.
> +#
> +#
> +#  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +#==============================================================
> ===================#
> +# 8 M BIOS - for FSP wrapper
> +#==============================================================
> ===================#
> +DEFINE FLASH_BASE                                                   = 0xFF800000  #
> +DEFINE FLASH_SIZE                                                   = 0x00800000  #
> +DEFINE FLASH_BLOCK_SIZE                                             = 0x00010000  #
> +DEFINE FLASH_NUM_BLOCKS                                             = 0x00000080
> #
> +#==============================================================
> ===================#
> +
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset           =
> 0x00000000  # Flash addr (0xFF800000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize             =
> 0x00040000  #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset   =
> 0x00000000  # Flash addr (0xFF800000)
> +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize    =
> 0x0001E000  #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset
> = 0x0001E000  # Flash addr (0xFF81E000)
> +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> = 0x00002000  #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset   =
> 0x00020000  # Flash addr (0xFF820000)
> +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> = 0x00020000  #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset          =
> 0x00040000  # Flash addr (0xFF840000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize            =
> 0x00060000  #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset          =
> 0x000A0000  # Flash addr (0xFF8A0000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize            =
> 0x00070000  #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset            =
> 0x00110000  # Flash addr (0xFF910000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize              =
> 0x00090000  #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset          =
> 0x001A0000  # Flash addr (0xFF9A0000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize            =
> 0x00190000  #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset        =
> 0x00330000  # Flash addr (0xFFB30000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize          =
> 0x00170000  #
> +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset                  =
> 0x004A0000  # Flash addr (0xFFCA0000)
> +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                    =
> 0x000B0000  #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset              =
> 0x00550000  # Flash addr (0xFFD50000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize                =
> 0x00070000  #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset              =
> 0x005C0000  # Flash addr (0xFFDC0000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize                =
> 0x000EC000  #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset              =
> 0x006AC000  # Flash addr (0xFFEAC000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize                =
> 0x00014000  #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset         =
> 0x006C0000  # Flash addr (0xFFEC0000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize           =
> 0x00140000  #
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.fdf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.fdf
> new file mode 100644
> index 0000000000..611078e4b4
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardP
> kg.fdf
> @@ -0,0 +1,706 @@
> +## @file
> +#  FDF file of Platform.
> +#
> +#
> +#  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> +   !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
> +
> +###############################################################
> #################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into  the Flash Device Image.  Each FD section
> +# defines one flash "device" image.  A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash"  image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +###############################################################
> #################
> +[FD.WhiskeylakeURvp]
> +#
> +# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks,
> cannot be
> +# assigned with PCD values. Instead, it uses the definitions for its variety,
> which
> +# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and
> FLASH_NUM_BLOCKS.
> +#
> +BaseAddress   = $(FLASH_BASE) |
> gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress      #The base address of the
> FLASH Device.
> +Size          = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize
> #The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +BlockSize     = $(FLASH_BLOCK_SIZE)
> +NumBlocks     = $(FLASH_NUM_BLOCKS)
> +
> +DEFINE SIPKG_DXE_SMM_BIN  = INF
> +DEFINE SIPKG_PEI_BIN      = INF
> +
> +# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase,
> because macro expression is not supported.
> +# So, PlatformSecLib uses PcdBiosAreaBaseAddress +
> PcdNemCodeCacheBase to get the real CodeCache base address.
> +SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =
> $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
> +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
> +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
> +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
> +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =
> $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) +
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =
> $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase    =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize    =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset  =
> gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =
> gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
> +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize    =
> gSiPkgTokenSpaceGuid.PcdBiosSize
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress    =
> gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize           =
> gSiPkgTokenSpaceGuid.PcdBiosSize
> +###############################################################
> #################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of
> different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required)
> followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the
> leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +# Fv Size can be adjusted
> +#
> +###############################################################
> #################
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMd
> eModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMd
> eModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +#NV_VARIABLE_STORE
> +DATA = {
> +  ## This is the EFI_FIRMWARE_VOLUME_HEADER
> +  # ZeroVector []
> +  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +  # FileSystemGuid
> +  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> +  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> +  # FvLength: 0x40000
> +  0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
> +  #Signature "_FVH"       #Attributes
> +  0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
> +  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
> +  #
> +  # Be careful on CheckSum field.
> +  #
> +  0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
> +  #Blockmap[0]: 4 Blocks  0x10000 Bytes / Block
> +  0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
> +  #Blockmap[1]: End
> +  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +  ## This is the VARIABLE_STORE_HEADER
> +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
> +  #  Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a,
> { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
> +  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
> +  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
> +!else
> +  #  Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6,
> 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
> +  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
> +  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
> +!endif
> +  #Size: 0x1E000
> (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48
> (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8
> +  # This can speed up the Variable Dispatch a bit.
> +  0xB8, 0xDF, 0x01, 0x00,
> +  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
> +  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfi
> MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEf
> iMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +#NV_FTW_WORKING
> +DATA = {
> +  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =
> gEdkiiWorkingBlockSignatureGuid         =
> +  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b,
> 0x95 }}
> +  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> +  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
> +  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1,
> Reserved
> +  0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
> +  # WriteQueueSize: UINT64
> +  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiM
> deModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiM
> deModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +#NV_FTW_SPARE
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatform
> PkgTokenSpaceGuid.PcdFlashFvAdvancedSize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformP
> kgTokenSpaceGuid.PcdFlashFvAdvancedSize
> +FV = FvAdvanced
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPk
> gTokenSpaceGuid.PcdFlashFvSecuritySize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkg
> TokenSpaceGuid.PcdFlashFvSecuritySize
> +FV = FvSecurity
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPk
> gTokenSpaceGuid.PcdFlashFvOsBootSize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkg
> TokenSpaceGuid.PcdFlashFvOsBootSize
> +FV = FvOsBoot
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformP
> kgTokenSpaceGuid.PcdFlashFvUefiBootSize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPk
> gTokenSpaceGuid.PcdFlashFvUefiBootSize
> +FV = FvUefiBoot
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatfo
> rmPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatfor
> mPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
> +FV = FvPostMemory
> +
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.P
> cdFlashMicrocodeFvSize
> +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.Pc
> dFlashMicrocodeFvSize
> +#Microcode
> +FV = FvMicrocode
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTo
> kenSpaceGuid.PcdFlashFvFspSSize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTok
> enSpaceGuid.PcdFlashFvFspSSize
> +# FSP_S Section
> +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgT
> okenSpaceGuid.PcdFlashFvFspMSize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTo
> kenSpaceGuid.PcdFlashFvFspMSize
> +# FSP_M Section
> +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTo
> kenSpaceGuid.PcdFlashFvFspTSize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTok
> enSpaceGuid.PcdFlashFvFspTSize
> +# FSP_T Section
> +FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
> +
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatfor
> mPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
> +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatfor
> mPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
> +FV = FvPreMemory
> +
> +###############################################################
> #################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed
> within a flash
> +# device file.  This section also defines order the components and modules
> are positioned
> +# within the image.  The [FV] section consists of define statements, set
> statements and
> +# module statements.
> +#
> +###############################################################
> #################
> +[FV.FvMicrocode]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = FALSE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = FALSE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +
> +FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {
> +
> $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/MicrocodeUpd
> ates.bin
> +}
> +
> +[FV.FvPreMemory]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
> +
> +INF  UefiCpuPkg/SecCore/SecCore.inf
> +INF  MdeModulePkg/Core/Pei/PeiMain.inf
> +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
> +
> +INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.in
> f
> +INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe
> m.inf
> +
> +[FV.FvPostMemoryUncompact]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
> +
> +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
> +
> +# Init Board Config PCD
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.i
> nf
> +INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe
> m.inf
> +
> +FILE RAW = C9505BC0-AA3D-4056-9995-870C8DE8594E {
> +
> $(PLATFORM_SI_BIN_PACKAGE)/ChipsetInit/CnlPchLpChipsetInitTable_Dx.bin
> +  }
> +!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
> +FILE FREEFORM
> =PCD(gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid) {
> +  SECTION RAW =
> $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin
> +  SECTION UI  = "Vbt"
> +}
> +FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
> +  SECTION RAW = MdeModulePkg/Logo/Logo.bmp
> +}
> +!endif # PcdPeiDisplayEnable
> +
> +
> +[FV.FvPostMemory]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = 9DFE49DB-8EF0-4D9C-B273-0036144DE917
> +
> +FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
> +      SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> +        SECTION FV_IMAGE = FvPostMemoryUncompact
> +      }
> +}
> +
> +[FV.FvUefiBootUncompact]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = A881D567-6CB0-4eee-8435-2E72D33E45B5
> +
> +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
> +INF  $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeCnl.inf
> +
> +INF  UefiCpuPkg/CpuDxe/CpuDxe.inf
> +INF  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> +
> +INF  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> +INF  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +INF  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +INF
> MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.
> inf
> +INF  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +
> +INF  ShellPkg/Application/Shell/Shell.inf
> +
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
> +INF  $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
> +INF  IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
> +
> +INF  $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
> +
> +
> +[FV.FvUefiBoot]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = 0496D33D-EA79-495C-B65D-ABF607184E3B
> +
> +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> +       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> +         SECTION FV_IMAGE = FvUefiBootUncompact
> +       }
> +     }
> +
> +[FV.FvOsBootUncompact]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
> +
> +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +INF  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
> +INF
> $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> +INF  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +
> +INF  $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
> +INF  $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
> +
> +INF  RuleOverride = DRIVER_ACPITABLE
> $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
> +INF
> $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfi
> g.inf
> +
> +!endif
> +
> +[FV.FvLateSilicon]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
> +$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
> +$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.in
> f
> +$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
> +$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
> +$(SIPKG_DXE_SMM_BIN)
> $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
> +
> +INF  RuleOverride = ACPITABLE
> $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf
> +INF  RuleOverride = ACPITABLE
> $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
> +
> +!endif
> +
> +[FV.FvOsBoot]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = 13BF8810-75FD-4B1A-91E6-E16C4201F80A
> +
> +FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 {
> +       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> +         SECTION FV_IMAGE = FvOsBootUncompact
> +       }
> +     }
> +
> +FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 {
> +       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> +         SECTION FV_IMAGE = FvLateSilicon
> +       }
> +     }
> +
> +[FV.FvSecurityPreMemory]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16         #FV alignment and FV attributes setting.
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
> +
> +!include
> $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
> +
> +INF
> IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSam
> plePei.inf
> +
> +INF  IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
> +
> +[FV.FvSecurityPostMemory]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16         #FV alignment and FV attributes setting.
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = 4199E560-54AE-45E5-91A4-F7BC3804E14A
> +
> +!include
> $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
> +!endif
> +
> +[FV.FvSecurityLate]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = F753FE9A-EEFD-485B-840B-E032D538102C
> +
> +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
> +INF  IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +INF
> $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
> +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
> +INF  $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
> +!endif
> +!endif
> +
> +[FV.FvSecurity]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF
> +
> +FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 {
> +       SECTION FV_IMAGE = FvSecurityPreMemory
> +     }
> +
> +FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B {
> +       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> +         SECTION FV_IMAGE = FvSecurityPostMemory
> +       }
> +     }
> +
> +FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 {
> +       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> +         SECTION FV_IMAGE = FvSecurityLate
> +       }
> +     }
> +
> +[FV.FvAdvancedPreMem]
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = 6053D78A-457E-4490-A237-31D0FBE2F305
> +
> +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
> +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
> +!endif
> +
> +[FV.FvAdvancedPostMem]
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = BE3DF86F-E464-44A3-83F7-0D27E6B88C27
> +
> +[FV.FvAdvancedLate]
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D
> +
> +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable == TRUE
> +INF  $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
> +INF  $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
> +INF
> $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
> +!endif
> +
> +[FV.FvAdvanced]
> +BlockSize          = $(FLASH_BLOCK_SIZE)
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = B23E7388-9953-45C7-9201-0473DDE5487A
> +
> +FILE FV_IMAGE = 35E7406A-5842-4F2B-BC62-19022C12AF74 {
> +       SECTION FV_IMAGE = FvAdvancedPreMem
> +     }
> +
> +FILE FV_IMAGE = F5DCB34F-27EA-48AC-9406-C894F6D587CA {
> +       SECTION FV_IMAGE = FvAdvancedPostMem
> +     }
> +
> +FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
> +       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> +         SECTION FV_IMAGE = FvAdvancedLate
> +       }
> +     }
> +
> +###############################################################
> #################
> +#
> +# Rules are use with the [FV] section's module INF type to define
> +# how an FFS file is created for a given INF file. The following Rule are the
> default
> +# rules for the different module type. User can add the customized rules to
> define the
> +# content of the FFS file.
> +#
> +###############################################################
> #################
> +
> +!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.
> cfg
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.
> cfg
> new file mode 100644
> index 0000000000..1b0619bc1c
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.
> cfg
> @@ -0,0 +1,33 @@
> +# @ build_config.cfg
> +# This is the WhiskeylakeURvp board specific build settings
> +#
> +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +
> +[CONFIG]
> +WORKSPACE_PLATFORM_BIN =
> +EDK_SETUP_OPTION =
> +openssl_path =
> +PLATFORM_BOARD_PACKAGE = WhiskeylakeOpenBoardPkg
> +PROJECT = WhiskeylakeOpenBoardPkg/WhiskeylakeURvp
> +BOARD = WhiskeylakeURvp
> +FLASH_MAP_FDF =
> WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/FlashMapInclude.
> fdf
> +PROJECT_DSC =
> WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc
> +BOARD_PKG_PCD_DSC =
> WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
> +PrepRELEASE = DEBUG
> +SILENT_MODE = FALSE
> +EXT_CONFIG_CLEAR =
> +CapsuleBuild = FALSE
> +EXT_BUILD_FLAGS =
> +CAPSULE_BUILD = 0
> +TARGET = DEBUG
> +TARGET_SHORT = D
> +PERFORMANCE_BUILD = FALSE
> +FSP_WRAPPER_BUILD = TRUE
> +FSP_BIN_PKG = CoffeeLakeFspBinPkg
> +FSP_PKG_NAME = CoffeelakeSiliconPkg
> +FSP_BINARY_BUILD = FALSE
> +FSP_TEST_RELEASE = FALSE
> +SECURE_BOOT_ENABLE = FALSE
> --
> 2.16.2.windows.1