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Mon, 23 Sep 2019 16:36:31 +0800 From: "Chiu, Chasel" To: "devel@edk2.groups.io" , "Kubacki, Michael A" CC: "Desimone, Nathaniel L" , "Sinha, Ankit" , Jeremy Soller Subject: Re: [edk2-devel] [edk2-platforms][PATCH V1 11/12] KabylakeOpenBoardPkg/GalagoPro3: Add build files Thread-Topic: [edk2-devel] [edk2-platforms][PATCH V1 11/12] KabylakeOpenBoardPkg/GalagoPro3: Add build files Thread-Index: AQHVb+MEpCAWonzDaEuzcVrVjY3qI6c49B+g Date: Mon, 23 Sep 2019 08:36:31 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC504DE1C9@PGSMSX112.gar.corp.intel.com> References: <20190920184030.6148-1-michael.a.kubacki@intel.com> <20190920184030.6148-12-michael.a.kubacki@intel.com> In-Reply-To: <20190920184030.6148-12-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMDhkZWEwNmUtN2Y1Yi00NTgwLThiZGItMTVkM2EyMDFhNWYxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiV1wvRjNHUG9TOU5mSzJpS0U3WTBLc3drcExVcXlaOFo3eW9OVlwvU0V4SEtzVndlbmFNTjBsallxSHZZWDFHaWpjIn0= x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.206] MIME-Version: 1.0 Return-Path: chasel.chiu@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Kubacki, > Michael A > Sent: Saturday, September 21, 2019 2:40 AM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Sinha, Ankit ; > Jeremy Soller > Subject: [edk2-devel] [edk2-platforms][PATCH V1 11/12] > KabylakeOpenBoardPkg/GalagoPro3: Add build files >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2207 >=20 > * Adds files required to build the GalagoPro3 board to the board > directory. > * Updates KabylakeOpenBoardPkg/OpenBoardPkg.dec to reference > the new GalagoPro3 board directory. >=20 > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Ankit Sinha > Cc: Jeremy Soller > Signed-off-by: Michael Kubacki > --- > Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > | 4 +- > Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc > | 385 +++++++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgBuildOpti > on.dsc | 151 +++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgConfig.dsc > | 132 ++++ > Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > | 265 ++++++++ >=20 > Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapInc > lude.fdf | 48 ++ > Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf > | 716 ++++++++++++++++++++ > Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg > | 33 + > 8 files changed, 1732 insertions(+), 2 deletions(-) >=20 > diff --git a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > index 383c34537d..bdaf728af1 100644 > --- a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > +++ b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec > @@ -1,5 +1,5 @@ > ## @file > -# Module describe the entire platform configuration. > +# Declaration file for Kaby Lake based boards. > # > # The DEC files are used by the utilities that parse DSC and > # INF files to generate AutoGen.c and AutoGen.h files > @@ -20,6 +20,7 @@ PACKAGE_GUID =3D > 0A8BA6E8-C8AC-4AC1-87AC-52772FA6AE5E >=20 > [Includes] > Include > +GalagoPro3/Include > KabylakeRvp3/Include > Features/Tbt/Include >=20 > @@ -303,7 +304,6 @@ > gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x0 > 00000EC >=20 >=20 > gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013 >=20 > - # gIntelPeiGraphicsVbtGuid =3D {0x4ad46122, 0xffeb, 0x4a52, {0xbf, 0= xb0, > 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}} > gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, > 0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, > 0xb0}|VOID*|0x40000014 >=20 > [PcdsDynamicEx] > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc > new file mode 100644 > index 0000000000..3e7f5c6b8a > --- /dev/null > +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc > @@ -0,0 +1,385 @@ > +## @file > +# System 76 GalagoPro3 board description file. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > +[Defines] > + # > + # Set platform specific package/folder name, same as passed from > PREBUILD script. > + # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well > as package build folder > + # DEFINE only takes effect at R9 DSC and FDF. > + # > + DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg > + DEFINE PLATFORM_SI_PACKAGE =3D > KabylakeSiliconPkg > + DEFINE PLATFORM_SI_BIN_PACKAGE =3D > KabylakeSiliconBinPkg > + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D > KabylakeFspBinPkg > + DEFINE PLATFORM_BOARD_PACKAGE =3D > KabylakeOpenBoardPkg > + DEFINE BOARD =3D GalagoPro3 > + DEFINE PROJECT =3D > $(PLATFORM_BOARD_PACKAGE)/$(BOARD) > + > + # > + # Platform On/Off features are defined here > + # > + !include OpenBoardPkgConfig.dsc > + > +############################################################### > ################# > +# > +# Defines Section - statements that will be processed to create a Makef= ile. > +# > +############################################################### > ################# > +[Defines] > + PLATFORM_NAME =3D $(PLATFORM_PACKAGE) > + PLATFORM_GUID =3D > 7324F33D-4E96-4F8B-A550-544DE6162AB7 > + PLATFORM_VERSION =3D 0.1 > + DSC_SPECIFICATION =3D 0x00010005 > + OUTPUT_DIRECTORY =3D Build/$(PROJECT) > + SUPPORTED_ARCHITECTURES =3D IA32|X64 > + BUILD_TARGETS =3D DEBUG|RELEASE > + SKUID_IDENTIFIER =3D ALL > + > + > + FLASH_DEFINITION =3D > $(PROJECT)/OpenBoardPkg.fdf > + > + FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0 > + DEFINE TOP_MEMORY_ADDRESS =3D 0x0 > + > + # > + # Default value for OpenBoardPkg.fdf use > + # > + DEFINE BIOS_SIZE_OPTION =3D SIZE_60 > + > +############################################################### > ################# > +# > +# SKU Identification section - list of all SKU IDs supported by this > +# Platform. > +# > +############################################################### > ################# > +[SkuIds] > + 0|DEFAULT # The entry: 0|DEFAULT is reserved and > always required. > + 0x60|GalagoPro3 > + > +############################################################### > ################# > +# > +# Library Class section - list of all Library Classes needed by this Pl= atform. > +# > +############################################################### > ################# > + > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc > + > +[LibraryClasses.common] > + > + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf > + > ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/Pei > ReportFvLib.inf > + > + > PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple > /PciHostBridgeLibSimple.inf > + > PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSim > ple/PciSegmentInfoLibSimple.inf > + > PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformB > ootManagerLib/DxePlatformBootManagerLib.inf > + > I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cA > ccessLib.inf > + > GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpande > rLib/BaseGpioExpanderLib.inf > + > + > PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHo > okLib.inf > + > + > FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiF > spWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf > + > PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapper > PlatformSecLib/SecFspWrapperPlatformSecLib.inf > + > + > FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/Bas > eFspWrapperApiLib.inf > + > FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestL > ib/PeiFspWrapperApiTestLib.inf > + > + > FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFsp > WrapperPlatformLib/PeiFspWrapperPlatformLib.inf > + > SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= Lib > Fsp/PeiSiliconPolicyInitLibFsp.inf > + > SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpd= a > teLibFsp/PeiSiliconPolicyUpdateLibFsp.inf > + > + > ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseC > onfigBlockLib.inf > + > SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInit= Lib.i > nf > + > + > BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B > oardInitLibNull.inf > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNu > ll/TestPointCheckLibNull.inf > + > +# Tbt > +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE > + > TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDx > eSmmTbtCommonLib/TbtCommonLib.inf > + > DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTb > tPolicyLib/DxeTbtPolicyLib.inf > +!endif > +# > +# Silicon Init Package > +# > +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc > + > +[LibraryClasses.IA32.SEC] > + > SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .in > f > + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S > ecTestPointCheckLib.inf > + > SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLi > bNull/SecBoardInitLibNull.inf > + > +[LibraryClasses.IA32] > + # > + # PEI phase common > + # > + > SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .in > f > + > DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxe > DebugLibReportStatusCode.inf > + > FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFsp > WrapperPlatformLib/PeiFspWrapperPlatformLib.inf > +!if $(TARGET) =3D=3D DEBUG > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/P > eiTestPointCheckLib.inf > +!endif > + > TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= i > b.inf > + > MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Mult > iBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf > + > BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSup > portLib/PeiMultiBoardInitSupportLib.inf > + > +# Tbt > +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE > + > PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbt > PolicyLib/PeiTbtPolicyLib.inf > + > PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/ > PeiDTbtInitLib/PeiDTbtInitLib.inf > +!endif > +# > +# Silicon Init Package > +# > +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc > + > +[LibraryClasses.X64] > + # > + # DXE phase common > + # > + > FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFsp > WrapperPlatformLib/DxeFspWrapperPlatformLib.inf > +!if $(TARGET) =3D=3D DEBUG > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/D > xeTestPointCheckLib.inf > +!endif > + > TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL > ib.inf > + > MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Mult > iBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf > + > BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSup > portLib/DxeMultiBoardInitSupportLib.inf > + > MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoard > AcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf > + > BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSup > portLib/DxeMultiBoardAcpiSupportLib.inf > + > + > SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/DxeSiliconPolicyInit= Lib > /DxeSiliconPolicyInitLib.inf > + > SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/DxeSiliconPolicyUpdateL= ib/ > DxeSiliconPolicyUpdateLib.inf > + > +# > +# Silicon Init Package > +# > +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc > + > +[LibraryClasses.X64.DXE_SMM_DRIVER] > + > SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCo > mmonLib/SmmSpiFlashCommonLib.inf > +!if $(TARGET) =3D=3D DEBUG > + > TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S > mmTestPointCheckLib.inf > +!endif > + > TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPoin > tLib.inf > + > MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoard > AcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf > + > BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSu > pportLib/SmmMultiBoardAcpiSupportLib.inf > + > +[LibraryClasses.X64.DXE_RUNTIME_DRIVER] > + > ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSys > temLib/DxeRuntimeResetSystemLib.inf > + > +!include OpenBoardPkgPcd.dsc > + > +[Components.IA32] > + > +# > +# Common > +# > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc > + > + # > + # Core > + # > + > MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf > { > + > + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf > + } > + > + # > + # FSP wrapper SEC Core > + # > + UefiCpuPkg/SecCore/SecCore.inf { > + > + #PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf > + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf > + } > + > +# > +# Silicon > +# > +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc > + > +# > +# Platform > +# > + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf > + > $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformI= n > itPei/PlatformInitPreMem.inf { > + > +!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE > + > BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf > +!else > + > NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf > +!endif > + } > + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { > + > + > SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= Lib > Dependency/PeiPreMemSiliconPolicyInitLibDependency.inf > + } > + > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe > m.inf{ > + > + # # > + # Hook a library constructor to update some policy fields when poli= cy > installed. > + # > + > NULL|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemS > iliconPolicyNotifyLib.inf > + } > + > + > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.in > f { > + > +!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE > + > BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.inf > +!else > + > NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf > +!endif > + } > + > + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { > + > + > SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= Lib > Dependency/PeiPostMemSiliconPolicyInitLibDependency.inf > + } > + > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe > m.inf > + > +# > +# Security > +# > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf > +!endif > + > + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf > + > IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSam > plePei.inf > + > +# Tbt > +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE > + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf > +!endif > + > +[Components.X64] > + > +# > +# Common > +# > +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc > + > + UefiCpuPkg/CpuDxe/CpuDxe.inf > + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > + > + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf > + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > + > MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe. > inf > + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf > + > + # > + # Shell > + # > + ShellPkg/Application/Shell/Shell.inf { > + > + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE > + > + > NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma > ndsLib.inf > + > NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma > ndsLib.inf > + > NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma > ndsLib.inf > + > NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Comm > andsLib.inf > + > NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Comm > andsLib.inf > + > NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com > mandsLib.inf > + > NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C > ommandsLib.inf > + > NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C > ommandsLib.inf > + > ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComma > ndLib.inf > + > HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsing= L > ib.inf > + > BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgC > ommandLib.inf > + > ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.in= f > + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf > + } > + > +# > +# Silicon > +# > +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc > + > +# Tbt > +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE > + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf > + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf > + $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf > +!endif > + > +# > +# Platform > +# > + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.in= f > + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf > + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf > + > + > $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig > .inf > + > + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf > + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf > + > +# > +# OS Boot > +# > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { > + > +!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE > + > BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.i > nf > +!else > + > NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf > +!endif > + } > + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { > + > +!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE > + > BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.i > nf > +!else > + > NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf > +!endif > + } > + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { > + > +!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE > + > BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnabl > eLib.inf > +!else > + > NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf > +!endif > + } > + > + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf > + > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf > + > + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { > + > + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 > + > +!if $(TARGET) =3D=3D DEBUG > + > DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i > nf > +!endif > + } > + > +!endif > + > +# > +# Security > +# > + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf > +!endif > + > + IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf > + > +# > +# Other > +# > + $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf > + > +!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc > +!include OpenBoardPkgBuildOption.dsc > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgBuildOp > tion.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgBuildOp > tion.dsc > new file mode 100644 > index 0000000000..8d1539a233 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgBuildOp > tion.dsc > @@ -0,0 +1,151 @@ > +## @file > +# System 76 GalagoPro3 board build option configuration. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[BuildOptions] > +# Define Build Options both for EDK and EDKII drivers. > + > + > + DEFINE DSC_S3_BUILD_OPTIONS =3D > + > + DEFINE DSC_CSM_BUILD_OPTIONS =3D > + > +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE > + DEFINE DSC_ACPI_BUILD_OPTIONS =3D -DACPI_SUPPORT=3D1 > +!else > + DEFINE DSC_ACPI_BUILD_OPTIONS =3D > +!endif > + > + DEFINE BIOS_GUARD_BUILD_OPTIONS =3D > + > + DEFINE OVERCLOCKING_BUILD_OPTION =3D > + > + DEFINE FSP_BINARY_BUILD_OPTIONS =3D > + > + DEFINE FSP_WRAPPER_BUILD_OPTIONS =3D -DFSP_WRAPPER_FLAG > + > + DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =3D > + > + DEFINE RESTRICTED_OPTION =3D > + > + > + DEFINE SV_BUILD_OPTIONS =3D > + > + DEFINE TEST_MENU_BUILD_OPTION =3D > + > +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable =3D=3D FALSE > + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -Od -GL- > +!else > + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D > +!endif > + > + DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =3D > + > + > + DEFINE TPM_BUILD_OPTION =3D > + > + DEFINE TPM2_BUILD_OPTION =3D > + > + DEFINE DSC_TBT_BUILD_OPTIONS =3D > + > + DEFINE DSC_DCTT_BUILD_OPTIONS =3D > + > + DEFINE EMB_BUILD_OPTIONS =3D > + > + DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS =3D -DMEM_DOWN_FLAG=3D1 > + > + DEFINE DSC_KBCEMUL_BUILD_OPTIONS =3D > + > + DEFINE BOOT_GUARD_BUILD_OPTIONS =3D > + > + DEFINE SECURE_BOOT_BUILD_OPTIONS =3D > + > + DEFINE USBTYPEC_BUILD_OPTION =3D > + > + DEFINE CAPSULE_BUILD_OPTIONS =3D > + > + DEFINE PERFORMANCE_BUILD_OPTION =3D > + > + DEFINE DEBUGUSEUSB_BUILD_OPTION =3D > + > + DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION =3D > -DDISABLE_NEW_DEPRECATED_INTERFACES=3D1 > + > + DEFINE SINITBIN_BUILD_OPTION =3D > + > + DEFINE MINTREE_FLAG_BUILD_OPTION =3D -DMINTREE_FLAG=3D1 > + > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OVERCLOCKING_BUILD_OPTION) > $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_OPTIONS) > $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS) > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(BOOT_GUARD_BUILD_OPTIONS) > $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGUSEUSB_BUILD_OPTION) > $(DSC_S3_BUILD_OPTIONS) > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(FSP_BINARY_BUILD_OPTIONS) > $(FSP_WRAPPER_BUILD_OPTIONS) > $(SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS) > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_KBCEMUL_BUILD_OPTIONS) > $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_BUILD_OPTIONS) > $(DSC_CSM_BUILD_OPTIONS) > $(DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION) > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(TPM2_BUILD_OPTION) > $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS) > +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) > $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYPEC_BUILD_OPTION) > $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION) > + > +[BuildOptions.Common.EDKII] > + > +# > +# For IA32 Global Build Flag > +# > + *_*_IA32_CC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D > PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI > + *_*_IA32_VFRPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_IA32_APP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_IA32_ASLPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_IA32_ASLCC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_IA32_NASM_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + > +# > +# For IA32 Specific Build Flag > +# > +GCC: *_*_IA32_PP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +GCC: *_*_IA32_CC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D > PI_SPECIFICATION_VERSION=3D0x00010015 -Wno-unused > -Wl,--allow-multiple-definition > +MSFT: *_*_IA32_ASM_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +MSFT: *_*_IA32_CC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D > PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI > +MSFT: *_*_IA32_VFRPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_IA32_APP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_IA32_ASLPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_IA32_ASLCC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) > + > +# > +# For X64 Global Build Flag > +# > + *_*_X64_CC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D > PI_SPECIFICATION_VERSION=3D0x00010015 > + *_*_X64_VFRPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_X64_APP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_X64_ASLPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_X64_ASLCC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + *_*_X64_NASM_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + > + > +# > +# For X64 Specific Build Flag > +# > +GCC: *_*_X64_PP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +GCC: *_*_X64_CC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D > PI_SPECIFICATION_VERSION=3D0x00010015 -Wno-unused > -Wl,--allow-multiple-definition > +MSFT: *_*_X64_ASM_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +MSFT: *_*_X64_CC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D > PI_SPECIFICATION_VERSION=3D0x00010015 > +MSFT: *_*_X64_VFRPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_X64_APP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) > +MSFT: *_*_X64_ASLPP_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > +MSFT: *_*_X64_ASLCC_FLAGS =3D > $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) > + > + > +# Force PE/COFF sections to be aligned at 4KB boundaries to support pag= e > level protection > +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, > BuildOptions.common.EDKII.SMM_CORE] > + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 > + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 > + > +# Force PE/COFF sections to be aligned at 4KB boundaries to support > MemoryAttribute table > +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] > + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 > + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 > + > +# Force PE/COFF sections to be aligned at 4KB boundaries to support NX > protection > +[BuildOptions.common.EDKII.DXE_DRIVER, > BuildOptions.common.EDKII.DXE_CORE, > BuildOptions.common.EDKII.UEFI_DRIVER, > BuildOptions.common.EDKII.UEFI_APPLICATION] > + #MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 > + #GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 > + > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgConfig.d > sc > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgConfig.d > sc > new file mode 100644 > index 0000000000..3de3f8942c > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgConfig.d > sc > @@ -0,0 +1,132 @@ > +## @file > +# System 76 GalagoPro3 board configuration. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[PcdsFixedAtBuild] > + # > + # Please select BootStage here. > + # Stage 1 - enable debug (system deadloop after debug init) > + # Stage 2 - mem init (system deadloop after mem init) > + # Stage 3 - boot to shell only > + # Stage 4 - boot to OS > + # Stage 5 - boot to OS with security boot enabled > + # > + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 > + > +[PcdsFeatureFlag] > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE > +!endif > + > + gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE > + # > + # More fine granularity control below: > + # > + gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE > + > +# > +# TRUE is ENABLE. FALSE is DISABLE. > +# > + > +# > +# BIOS build switches configuration > +# > + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE > + > +# CPU > + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE > + gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE #Set to FALSE for GCC Build > @todo Convert TXT ASM to NASM > + gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE > + > +# SA > + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE > + > +# ME > + gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE > + > + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE > + gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE > + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE > + gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE > + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE > + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE > + > +# > +# Override some PCDs for specific build requirements. > +# > + # > + # Disable USB debug message when Source Level Debug is enabled > + # because they cannot be enabled at the same time. > + # > + > + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE > + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE > + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE > + > + !if $(TARGET) =3D=3D DEBUG > + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE > + !else > + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE > + !endif > + > + !if $(TARGET) =3D=3D DEBUG > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE > + !else > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE > + !endif > + > + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE > + > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > new file mode 100644 > index 0000000000..2dfdd3b30e > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > @@ -0,0 +1,265 @@ > +## @file > +# System 76 GalagoPro3 board PCD configuration. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +############################################################### > ################# > +# > +# Pcd Section - list of all EDK II PCD Entries defined by this Platform > +# > +############################################################### > ################# > +[PcdsFeatureFlag.common] > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE > + > gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSection > First|FALSE > +!if $(TARGET) =3D=3D RELEASE > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE > +!else > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE > +!endif > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE > + > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE > + > +[PcdsFixedAtBuild.common] > + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE > + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRU= E > + > gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 > +!endif > + > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 > + > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|0x10000000 > + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 > + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 > + > + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | > 0x00026000 > + > + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 > + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 > + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x40 > 0 > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 > +!if $(TARGET) =3D=3D RELEASE > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 > +!else > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F > + > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALS > E > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 > +!endif > + > gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(T > OP_MEMORY_ADDRESS) > + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 > + > + > gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TR > UE > + > + # > + # 8MB Default > + # > + gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 > + > + # > + # 16MB TSEG in Debug build only. > + # > + !if $(TARGET) =3D=3D DEBUG > + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 > + !endif > + > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC > + > + !if $(TARGET) =3D=3D RELEASE > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 > + !else > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188 > B > + !endif > + > + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b > + !if $(TARGET) =3D=3D RELEASE > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 > + !else > + > gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 > + !endif > + > + # > + # FSP Base address PCD will be updated in FDF basing on flash map. > + # > + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 > + > + ## Specifies max supported number of Logical Processors. > + # @Prompt Configure max supported number of Logical Processorss > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12 > + > + ## Specifies the size of the microcode Region. > + # @Prompt Microcode Region size. > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 > + > + ## Specifies timeout value in microseconds for the BSP to detect all = APs > for the first time. > + # @Prompt Timeout for the BSP to detect all APs for the first time. > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 > + > + ## Specifies the AP wait loop state during POST phase. > + # The value is defined as below. > + # 1: Place AP in the Hlt-Loop state. > + # 2: Place AP in the Mwait-Loop state. > + # 3: Place AP in the Run-Loop state. > + # @Prompt The AP wait loop state. > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 > + > + # > + # The PCDs are used to control the Windows SMM Security Mitigations > Table - Protection Flags > + # > + # BIT0: If set, expresses that for all synchronous SMM entries,SMM wi= ll > validate that input and output buffers lie entirely within the expected = fixed > memory regions. > + # BIT1: If set, expresses that for all synchronous SMM entries, SMM w= ill > validate that input and output pointers embedded within the fixed > communication buffer only refer to address ranges \ > + # that lie entirely within the expected fixed memory regions. > + # BIT2: Firmware setting this bit is an indication that it will not a= llow > reconfiguration of system resources via non-architectural mechanisms. > + # BIT3-31: Reserved > + # > + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 > + > + # > + # See HstiFeatureBit.h for the definition > + # > + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 > + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1 > + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, > 0x00, 0x00} > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 2 > + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, > 0x00, 0x00} > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 3 > + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, > 0x00, 0x00} > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 4 > + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, > 0x00, 0x00} > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 5 > + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, > 0x00, 0x00} > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 6 > + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, > 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, = 0x00, > 0x00, 0x00} > +!endif > + > +[PcdsFixedAtBuild.IA32] > + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 > + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 > + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 > + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 > + > +[PcdsFixedAtBuild.X64] > + # Default platform supported RFC 4646 languages: (American) English > + > gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en- > US" > + > +[PcdsPatchableInModule.common] > + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 > + > + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 > + > +!if $(TARGET) =3D=3D DEBUG > + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1 > +!endif > + > +[PcdsDynamicHii.X64.DEFAULT] > + > gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGloba > lVariableGuid|0x0|5 # Variable: L"Timeout" > + > gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupp > ort"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE > + > gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGloba > lVariableGuid|0x0|1 # Variable: L"Timeout" > +!endif > + > +[PcdsDynamicDefault] > + # > + # FSP Base address PCD will be updated in FDF basing on flash map. > + # > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 > + # Platform will pre-allocate UPD buffer and pass it to FspWrapper > + # Those dummy address will be patched before FspWrapper executing > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0xFFFFFFFF > + > +[PcdsDynamicDefault.common.DEFAULT] > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE > + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE > + # > + # Set video to native resolution as Windows 8 WHCK requirement. > + # > + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0 > + > + > gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 > + > +[PcdsDynamicDefault.common.DEFAULT] > + # gEfiTpmDeviceInstanceTpm20DtpmGuid > + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, > 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, = 0x17} > + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0 > + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F > + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 > + > + # Tbt > + gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn | 0x1 > + gBoardModuleTokenSpaceGuid.PcdDTbtControllerType | 0x1 > + gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber | 0x1 > + gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType | 0x2 > + gBoardModuleTokenSpaceGuid.PcdExpander | 0x0 > + gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel | 0x1 > + gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad | 13 > + gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad | > 0x02010011 > + gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature | 0 > + gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting | 0 > + gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode | 0x1 > + #gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter | 0x0 > + gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport | 0x0 > + gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI | 0x1 > + gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify | 0x1 > + gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq| 0x1 > + gBoardModuleTokenSpaceGuid.PcdDTbtAspm | 0x0 > + gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch | 0x0 > + gBoardModuleTokenSpaceGuid.PcdRtd3Tbt | 0x1 > + gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq | 0x1 > + gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support | 0x0 > + gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay | 0x0 > + gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay | 5000 > + gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd | 56 > + gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd | 100 > + gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26 > + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100 > + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28 > + gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe| 0x00000001 > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapI > nclude.fdf > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapI > nclude.fdf > new file mode 100644 > index 0000000000..b33b1e09a9 > --- /dev/null > +++ > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapI > nclude.fdf > @@ -0,0 +1,48 @@ > +## @file > +# Flash map layout file for the System 76 GalagoPro3 board. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D# > +# 6 M BIOS - for FSP wrapper > +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D# > +DEFINE FLASH_BASE > =3D 0xFFA20000 # > +DEFINE FLASH_SIZE > =3D 0x005E0000 # > +DEFINE FLASH_BLOCK_SIZE > =3D 0x00010000 # > +DEFINE FLASH_NUM_BLOCKS > =3D 0x0000005E # > +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D# > + > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset > =3D 0x00000000 # Flash addr (0xFFA20000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize > =3D 0x00040000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D > 0x00000000 # Flash addr (0xFFA20000) > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > =3D 0x0001E000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset > =3D 0x0001E000 # Flash addr (0xFFA3E000) > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > =3D 0x00002000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset > =3D 0x00020000 # Flash addr (0xFFA40000) > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > =3D 0x00020000 # > +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset > =3D 0x00040000 # Flash addr (0xFFA60000) > +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize > =3D 0x00010000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset > =3D 0x00050000 # Flash addr (0xFFA70000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize > =3D 0x00060000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset > =3D 0x000B0000 # Flash addr (0xFFAD0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize > =3D 0x00070000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset > =3D 0x00120000 # Flash addr (0xFFB40000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize > =3D 0x00090000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset > =3D 0x001B0000 # Flash addr (0xFFBD0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize > =3D 0x00140000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset > =3D 0x002F0000 # Flash addr (0xFFD10000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize > =3D 0x000B0000 # > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset > =3D 0x003A0000 # Flash addr (0xFFDC0000) > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > =3D 0x000A0000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset > =3D 0x00440000 # Flash addr (0xFFE60000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize > =3D 0x00060000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset > =3D 0x004A0000 # Flash addr (0xFFEC0000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize > =3D 0x000BC000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset > =3D 0x0055C000 # Flash addr (0xFFF7C000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize > =3D 0x00004000 # > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset > =3D 0x00560000 # Flash addr (0xFFF80000) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize > =3D 0x00080000 # > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf > new file mode 100644 > index 0000000000..56bb0edaad > --- /dev/null > +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf > @@ -0,0 +1,716 @@ > +## @file > +# System 76 GalagoPro3 board flash file. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf > + > +############################################################### > ################# > +# > +# FD Section > +# The [FD] Section is made up of the definition statements and a > +# description of what goes into the Flash Device Image. Each FD secti= on > +# defines one flash "device" image. A flash device image may be one of > +# the following: Removable media bootable image (like a boot floppy > +# image,) an Option ROM image (that would be "flashed" into an add-in > +# card,) a System "Flash" image (that would be burned into a system's > +# flash) or an Update ("Capsule") image that will be used to update and > +# existing system flash. > +# > +############################################################### > ################# > +[FD.GalagoPro3] > +# > +# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks= , > cannot be > +# assigned with PCD values. Instead, it uses the definitions for its va= riety, > which > +# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and > FLASH_NUM_BLOCKS. > +# > +BaseAddress =3D $(FLASH_BASE) | > gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address > of the FLASH Device. > +Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize > #The size in bytes of the FLASH Device > +ErasePolarity =3D 1 > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +NumBlocks =3D $(FLASH_NUM_BLOCKS) > + > +DEFINE SIPKG_DXE_SMM_BIN =3D INF > +DEFINE SIPKG_PEI_BIN =3D INF > + > +# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, > because macro expression is not supported. > +# So, PlatformSecLib uses PcdFlashAreaBaseAddress + > PcdNemCodeCacheBase to get the real CodeCache base address. > +SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset) > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) > +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D > $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D > gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaSize > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset) > +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D > $(gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress) + > $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset) > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAddress > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D > gSiPkgTokenSpaceGuid.PcdFlashAreaSize > +############################################################### > ################# > +# > +# Following are lists of FD Region layout which correspond to the locat= ions > of different > +# images within the flash device. > +# > +# Regions must be defined in ascending order and may not overlap. > +# > +# A Layout Region start with a eight digit hex offset (leading "0x" req= uired) > followed by > +# the pipe "|" character, followed by the size of the region, also in h= ex with > the leading > +# "0x" characters. Like: > +# Offset|Size > +# PcdOffsetCName|PcdSizeCName > +# RegionType > +# Fv Size can be adjusted > +# > +############################################################### > ################# > +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMd > eModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMd > eModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > +#NV_VARIABLE_STORE > +DATA =3D { > + ## This is the EFI_FIRMWARE_VOLUME_HEADER > + # ZeroVector [] > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + # FileSystemGuid > + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, > + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, > + # FvLength: 0x40000 > + 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, > + #Signature "_FVH" #Attributes > + 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00, > + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision > + # > + # Be careful on CheckSum field. > + # > + 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02, > + #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block > + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, > + #Blockmap[1]: End > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + ## This is the VARIABLE_STORE_HEADER > +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE > + # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, > 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} > + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, > + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, > +!else > + # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x= 98, > 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} > + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, > + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, > +!endif > + #Size: 0x1E000 > (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 > (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x1DFB8 > + # This can speed up the Variable Dispatch a bit. > + 0xB8, 0xDF, 0x01, 0x00, > + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: > UINT32 > + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > +} > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfi > MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEf > iMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > +#NV_FTW_WORKING > +DATA =3D { > + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D > gEdkiiWorkingBlockSignatureGuid =3D > + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f= , > 0x1b, 0x95 }} > + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, > + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, > + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, > Reserved > + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, > + # WriteQueueSize: UINT64 > + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > +} > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiM > deModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiM > deModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > +#NV_FTW_SPARE > + > +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gBoardMo > duleTokenSpaceGuid.PcdFlashNvDebugMessageSize > +gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|gBoardMod > uleTokenSpaceGuid.PcdFlashNvDebugMessageSize > +#DEBUG_MESSAGE_AREA > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatform > PkgTokenSpaceGuid.PcdFlashFvAdvancedSize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformP > kgTokenSpaceGuid.PcdFlashFvAdvancedSize > +FV =3D FvAdvanced > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPk > gTokenSpaceGuid.PcdFlashFvSecuritySize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkg > TokenSpaceGuid.PcdFlashFvSecuritySize > +FV =3D FvSecurity > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPk > gTokenSpaceGuid.PcdFlashFvOsBootSize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgT > okenSpaceGuid.PcdFlashFvOsBootSize > +FV =3D FvOsBoot > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformP > kgTokenSpaceGuid.PcdFlashFvUefiBootSize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPk > gTokenSpaceGuid.PcdFlashFvUefiBootSize > +FV =3D FvUefiBoot > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatfo > rmPkgTokenSpaceGuid.PcdFlashFvPostMemorySize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatfor > mPkgTokenSpaceGuid.PcdFlashFvPostMemorySize > +FV =3D FvPostMemory > + > +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.P > cdFlashMicrocodeFvSize > +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.Pc > dFlashMicrocodeFvSize > +#Microcode > +FV =3D FvMicrocode > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTo > kenSpaceGuid.PcdFlashFvFspSSize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTok > enSpaceGuid.PcdFlashFvFspSSize > +# FSP_S Section > +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgT > okenSpaceGuid.PcdFlashFvFspMSize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTo > kenSpaceGuid.PcdFlashFvFspMSize > +# FSP_M Section > +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTo > kenSpaceGuid.PcdFlashFvFspTSize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTok > enSpaceGuid.PcdFlashFvFspTSize > +# FSP_T Section > +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd > + > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatfor > mPkgTokenSpaceGuid.PcdFlashFvPreMemorySize > +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatform > PkgTokenSpaceGuid.PcdFlashFvPreMemorySize > +FV =3D FvPreMemory > + > +############################################################### > ################# > +# > +# FV Section > +# > +# [FV] section is used to define what components or modules are placed > within a flash > +# device file. This section also defines order the components and > modules are positioned > +# within the image. The [FV] section consists of define statements, se= t > statements and > +# module statements. > +# > +############################################################### > ################# > +[FV.FvMicrocode] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D FALSE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D FALSE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > + > +INF RuleOverride =3D MICROCODE > $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf > + > +[FV.FvPreMemory] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D > + > +INF UefiCpuPkg/SecCore/SecCore.inf > +INF MdeModulePkg/Core/Pei/PeiMain.inf > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf > + > +INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf > +INF > $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformI= n > itPei/PlatformInitPreMem.inf > +INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > +INF > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe > m.inf > + > +[FV.FvPostMemoryUncompact] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7 > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf > + > +# Init Board Config PCD > +INF > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.in > f > +INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > +INF > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe > m.inf > + > +!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable =3D=3D TRUE > +FILE FREEFORM =3D 4ad46122-ffeb-4a52-bfb0-518cfca02db0 { > + SECTION RAW =3D GalagoPro3/Gop/Vbt.bin > + SECTION UI =3D "Vbt" > +} > +FILE FREEFORM =3D 7BB28B99-61BB-11D5-9A5D-0090273FC14D { > + SECTION RAW =3D MdeModulePkg/Logo/Logo.bmp > +} > +!endif # PcdPeiDisplayEnable > + > +[FV.FvPostMemory] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 9DFE49DB-8EF0-4D9C-B273-0036144DE917 > + > +FILE FV_IMAGE =3D 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvPostMemoryUncompact > + } > +} > + > +[FV.FvUefiBootUncompact] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D A881D567-6CB0-4eee-8435-2E72D33E45B5 > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf > + > +INF UefiCpuPkg/CpuDxe/CpuDxe.inf > +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > + > +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf > +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > +INF > MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe. > inf > +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf > + > +INF ShellPkg/Application/Shell/Shell.inf > + > +INF > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf > +INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf > + > +INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf > + > +[FV.FvUefiBoot] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 0496D33D-EA79-495C-B65D-ABF607184E3B > + > +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvUefiBootUncompact > + } > + } > + > +[FV.FvOsBootUncompact] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D A0F04529-B715-44C6-BCA4-2DEBDD01EEEC > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf > + > +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > +INF > $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf > +INF > $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf > +INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf > + > +INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf > +INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf > + > +INF RuleOverride =3D DRIVER_ACPITABLE > $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf > + > +INF > $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig > .inf > + > +!endif > + > +[FV.FvLateSilicon] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf > + > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf > + > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf > +$(SIPKG_DXE_SMM_BIN) > $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf > + > +INF RuleOverride =3D ACPITABLE > $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf > +INF RuleOverride =3D ACPITABLE > $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf > + > +!endif > + > +[FV.FvOsBoot] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 13BF8810-75FD-4B1A-91E6-E16C4201F80A > + > +FILE FV_IMAGE =3D B9020753-84A8-4BB6-947C-CE7D41F5CE39 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvOsBootUncompact > + } > + } > + > +FILE FV_IMAGE =3D D4632741-510C-44E3-BE21-C3D6D7881485 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvLateSilicon > + } > + } > + > +[FV.FvSecurityPreMemory] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 #FV alignment and FV attributes > setting. > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B > + > +!include > $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf > + > +INF > IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSam > plePei.inf > + > +INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf > + > +[FV.FvSecurityPostMemory] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 #FV alignment and FV attributes > setting. > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 4199E560-54AE-45E5-91A4-F7BC3804E14A > + > +!include > $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf > +!endif > + > +[FV.FvSecurityLate] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D F753FE9A-EEFD-485B-840B-E032D538102C > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf > + > +INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > + > +INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf > + > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > + > +INF > $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE > +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf > +!endif > + > +!endif > + > +[FV.FvSecurity] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF > + > +FILE FV_IMAGE =3D 757CC075-1428-423D-A73C-22639706C119 { > + SECTION FV_IMAGE =3D FvSecurityPreMemory > + } > + > +FILE FV_IMAGE =3D 80BB8482-44D5-4BEC-82B5-8D87A933830B { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvSecurityPostMemory > + } > + } > + > +FILE FV_IMAGE =3D C83522D9-80A1-4D95-8C25-3F1370497406 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvSecurityLate > + } > + } > + > +[FV.FvAdvancedPreMem] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 6053D78A-457E-4490-A237-31D0FBE2F305 > + > +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE > +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf > +!endif > + > +[FV.FvAdvancedPostMem] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D BE3DF86F-E464-44A3-83F7-0D27E6B88C27 > + > +[FV.FvAdvancedLate] > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D > + > +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE > +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf > +INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf > +INF > $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf > +!endif > + > +[FV.FvAdvanced] > +BlockSize =3D $(FLASH_BLOCK_SIZE) > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D B23E7388-9953-45C7-9201-0473DDE5487A > + > +FILE FV_IMAGE =3D 35E7406A-5842-4F2B-BC62-19022C12AF74 { > + SECTION FV_IMAGE =3D FvAdvancedPreMem > + } > + > +FILE FV_IMAGE =3D F5DCB34F-27EA-48AC-9406-C894F6D587CA { > + SECTION FV_IMAGE =3D FvAdvancedPostMem > + } > + > +FILE FV_IMAGE =3D 5248467B-B87B-4E74-AC02-398AF4BCB712 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvAdvancedLate > + } > + } > + > +############################################################### > ################# > +# > +# Rules are use with the [FV] section's module INF type to define > +# how an FFS file is created for a given INF file. The following Rule a= re the > default > +# rules for the different module type. User can add the customized rule= s to > define the > +# content of the FFS file. > +# > +############################################################### > ################# > + > +!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf > + > diff --git > a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg > b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg > new file mode 100644 > index 0000000000..8c6c51abb4 > --- /dev/null > +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg > @@ -0,0 +1,33 @@ > +# @ build_config.cfg > +# This is the System 76 GalagoPro3 board specific build settings > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > + > + > +[CONFIG] > +WORKSPACE_PLATFORM_BIN =3D > edk2-non-osi/Platform/Intel/KabylakeOpenBoardBinPkg > +EDK_SETUP_OPTION =3D > +openssl_path =3D > +PLATFORM_BOARD_PACKAGE =3D KabylakeOpenBoardPkg > +PROJECT =3D KabylakeOpenBoardPkg/GalagoPro3 > +BOARD =3D GalagoPro3 > +FLASH_MAP_FDF =3D > KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapInclude.fdf > +PROJECT_DSC =3D KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc > +BOARD_PKG_PCD_DSC =3D > KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc > +PrepRELEASE =3D DEBUG > +SILENT_MODE =3D FALSE > +EXT_CONFIG_CLEAR =3D > +CapsuleBuild =3D FALSE > +EXT_BUILD_FLAGS =3D > +CAPSULE_BUILD =3D 0 > +TARGET =3D DEBUG > +TARGET_SHORT =3D D > +PERFORMANCE_BUILD =3D FALSE > +FSP_WRAPPER_BUILD =3D TRUE > +FSP_BIN_PKG =3D KabylakeFspBinPkg > +FSP_PKG_NAME =3D KabylakeFspPkg > +FSP_BINARY_BUILD =3D FALSE > +FSP_TEST_RELEASE =3D FALSE > +SECURE_BOOT_ENABLE =3D FALSE > -- > 2.16.2.windows.1 >=20 >=20 >=20