From: "Chiu, Chasel" <chasel.chiu@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>,
"Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>
Cc: "Kubacki, Michael A" <michael.a.kubacki@intel.com>,
"Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V2] KabylakeSiliconPkg: Logic Error in EISS bit ASSERT
Date: Tue, 8 Oct 2019 04:12:56 +0000 [thread overview]
Message-ID: <3C3EFB470A303B4AB093197B6777CCEC504F1996@PGSMSX112.gar.corp.intel.com> (raw)
In-Reply-To: <20191004201417.5020-1-nathaniel.l.desimone@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Nate
> DeSimone
> Sent: Saturday, October 5, 2019 4:14 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Chaganty, Rangasai V
> <rangasai.v.chaganty@intel.com>
> Subject: [edk2-devel] [edk2-platforms] [PATCH V2] KabylakeSiliconPkg: Logic
> Error in EISS bit ASSERT
>
> Current ASSERT logic checks that the EISS bit is still set after we clear it. This
> is incorrect, it should be checking that that the EISS bit is clear after we clear
> it.
>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> ---
> .../Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c
> index aadc367a9f..c34c378de2 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.c
> @@ -184,7 +184,7 @@ DisableBiosWriteProtect (
> B_PCH_SPI_BC_WPD ); - ASSERT ((PciSegmentRead8
> (SpiBaseAddress + R_PCH_SPI_BC) & B_PCH_SPI_BC_EISS) != 0);+ ASSERT
> ((PciSegmentRead8 (SpiBaseAddress + R_PCH_SPI_BC) & B_PCH_SPI_BC_EISS)
> == 0); return EFI_SUCCESS; }--
> 2.23.0.windows.1
>
>
> -=-=-=-=-=-=
> Groups.io Links: You receive all messages sent to this group.
>
> View/Reply Online (#48489): https://edk2.groups.io/g/devel/message/48489
> Mute This Topic: https://groups.io/mt/34398391/1777047
> Group Owner: devel+owner@edk2.groups.io
> Unsubscribe: https://edk2.groups.io/g/devel/unsub [chasel.chiu@intel.com]
> -=-=-=-=-=-=
prev parent reply other threads:[~2019-10-08 4:12 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-04 20:14 [edk2-platforms] [PATCH V2] KabylakeSiliconPkg: Logic Error in EISS bit ASSERT Nate DeSimone
2019-10-04 21:16 ` Kubacki, Michael A
2019-10-05 0:09 ` Chaganty, Rangasai V
2019-10-08 4:12 ` Chiu, Chasel [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=3C3EFB470A303B4AB093197B6777CCEC504F1996@PGSMSX112.gar.corp.intel.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox