From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.20813.1581335362894424364 for ; Mon, 10 Feb 2020 03:49:23 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: chasel.chiu@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Feb 2020 03:49:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,424,1574150400"; d="scan'208";a="226125647" Received: from kmsmsx153.gar.corp.intel.com ([172.21.73.88]) by orsmga008.jf.intel.com with ESMTP; 10 Feb 2020 03:49:20 -0800 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.4]) by KMSMSX153.gar.corp.intel.com ([169.254.5.66]) with mapi id 14.03.0439.000; Mon, 10 Feb 2020 19:49:19 +0800 From: "Chiu, Chasel" To: "devel@edk2.groups.io" , "philmd@redhat.com" CC: "Ma, Maurice" , "Desimone, Nathaniel L" , "Zeng, Star" Subject: Re: [edk2-devel] [PATCH 1/2] IntelFsp2Pkg/GenCfgOpt.py: Coverity scan flags issues. Thread-Topic: [edk2-devel] [PATCH 1/2] IntelFsp2Pkg/GenCfgOpt.py: Coverity scan flags issues. Thread-Index: AQHV3+0iTnWRZteIXUqxPKqEMZHtv6gUSjaA Date: Mon, 10 Feb 2020 11:49:18 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC5068F483@PGSMSX111.gar.corp.intel.com> References: <20200210035329.19432-1-chasel.chiu@intel.com> <20200210035329.19432-2-chasel.chiu@intel.com> <9e7d3543-112e-2a09-b359-e71dd7e3de7b@redhat.com> In-Reply-To: <9e7d3543-112e-2a09-b359-e71dd7e3de7b@redhat.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjEyNmQyYzYtNzFhMC00ZDE3LWFmNjctNWQ1ZTZjZTJlOGIxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiWWRMNFR1aXpJOEoxdUVqcWV6ZndvaWZHXC85UVwvSHlwSTZOUGR2MlJUUmprUzdcLzM3MExkMkxrdUpObnkyQUI2ciJ9 x-ctpclassification: CTP_NT x-originating-ip: [172.30.20.205] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Philippe, > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Philippe > Mathieu-Daude > Sent: Monday, February 10, 2020 4:36 PM > To: devel@edk2.groups.io; Chiu, Chasel > Cc: Ma, Maurice ; Desimone, Nathaniel L > ; Zeng, Star > Subject: Re: [edk2-devel] [PATCH 1/2] IntelFsp2Pkg/GenCfgOpt.py: Coverit= y > scan flags issues. >=20 > On 2/10/20 4:53 AM, Chiu, Chasel wrote: > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1706 > > > > Issue was: invalid_operation: Invalid operation on null-like value > > "Base". > > Fixed it by initializing Base to 0 before entering while loop. > > > > Test: > > Compared script output before and after this patch and the result is > > identical. > > > > Cc: Maurice Ma > > Cc: Nate DeSimone > > Cc: Star Zeng > > Signed-off-by: Chasel Chiu > > --- > > IntelFsp2Pkg/Tools/GenCfgOpt.py | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py > > b/IntelFsp2Pkg/Tools/GenCfgOpt.py index 2fa7582d85..d1d6901bc3 100644 > > --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py > > +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py > > @@ -1,6 +1,6 @@ > > ## @ GenCfgOpt.py > > # > > -# Copyright (c) 2014 - 2019, Intel Corporation. All rights > > reserved.
> > +# Copyright (c) 2014 - 2020, Intel Corporation. All rights > > +reserved.
> > # SPDX-License-Identifier: BSD-2-Clause-Patent > > # > > ## > > @@ -439,6 +439,7 @@ EndList > > > > MaxAlign =3D 32 #Default align to 32, but if there are 64 = bit > unit, align to 64 > > SizeAlign =3D 0 #record the struct max align > > + Base =3D 0 #Starting offset of sub-structure. >=20 > Are you sure this has to be initialized only once before the while state= ment, > and not within the 'Check VPD/UPD' leaf? >=20 Yes, initializing 'Base' before entering while loop is good enough. This optional feature (auto-assigning UPD element offset) is implemented b= asing on FSP 2.0 spec and offset 0 in the UPD structure is always sub-struc= ture field "FSP_UPD_HEADER. Signature", so 'Base' will be always initialize= d to sub-structure beginning offset before it is actually consumed. Thanks, Chasel Code snippet line#707: if (ConfigDict['embed'].find(':START') !=3D -1): = <=3D=3D offset 0 will always meet this condition and assign Base to ItemOff= set, which is 0 too. Base =3D ItemOffset SubOffset =3D ItemOffset - Base SubRemainder =3D SubOffset % Unit if SubRemainder: Diff =3D Unit - SubRemainder Offset =3D Offset + Diff ItemOffset =3D ItemOffset + Diff > > while len(DscLines): > > DscLine =3D DscLines.pop(0).strip() > > Handle =3D False > > >=20 >=20 >=20