public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
* [edk2-platforms] [PATCH V1 0/2] Add Cometlake U Silicon support and Enable build
@ 2020-02-18 14:53 Kathappan Esakkithevar
  2020-02-18 14:53 ` [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support Kathappan Esakkithevar
  2020-02-18 14:53 ` [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg Kathappan Esakkithevar
  0 siblings, 2 replies; 10+ messages in thread
From: Kathappan Esakkithevar @ 2020-02-18 14:53 UTC (permalink / raw)
  To: devel

V1:
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

CoffeelakeSiliconPkg: Cometlake V1 U specific support is added as below:
* CPU Family Model ID
* System Agent Device ID
* PCH SKU ID
Platform/Intel: 
* Add global configuration to enable build option for CometlakeURvp.
* Also update Cometlake U Rvp details to the Readme.md.

Kathappan Esakkithevar (2):
  CoffeeLakeSiliconPkg: Add Cometlake U Silicon support
  Enable global build for CometlakeOpenBoardPkg and update Readme.md

 Platform/Intel/Readme.md                               | 11 +++++++++++
 Platform/Intel/build.cfg                               |  3 ++-
 .../Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h   |  5 ++++-
 .../PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c       | 18 +++++++++++++++++-
 .../Pch/Include/Register/PchRegsLpcCnl.h               |  3 ++-
 .../Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c    |  5 ++++-
 .../SystemAgent/Include/Register/SaRegsHostBridge.h    |  5 ++++-
 .../MemoryInit/Include/Coffeelake/MrcInterface.h       |  5 +++--
 8 files changed, 47 insertions(+), 8 deletions(-)

-- 
2.16.2.windows.1


^ permalink raw reply	[flat|nested] 10+ messages in thread
* [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support
  2020-02-18 14:53 [edk2-platforms] [PATCH V1 0/2] Add Cometlake U Silicon support and Enable build Kathappan Esakkithevar
@ 2020-02-18 14:53 ` Kathappan Esakkithevar
  2020-02-19  4:06   ` [edk2-devel] " Nate DeSimone
                     ` (2 more replies)
  2020-02-18 14:53 ` [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg Kathappan Esakkithevar
  1 sibling, 3 replies; 10+ messages in thread
From: Kathappan Esakkithevar @ 2020-02-18 14:53 UTC (permalink / raw)
  To: devel
  Cc: Sai Chaganty, Chasel Chiu, Nate DeSimone, Deepika Kethi Reddy,
	Prince Agyeman

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

Adds CPU model, SA Device ID, PCH SKU ID for Cometlake U V1.

Key files
=========
* CpuReg.h - Add CPU Family Model support.
* SaRegsHostBridge.h - Add SA Device ID support.
* MrcInterface.h - Add CPU Family Model support in MRC.
* PchRegsLpcCnl.h - Add PCH SKU ID support.

Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
---
 .../Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h   |  5 ++++-
 .../PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c       | 18 +++++++++++++++++-
 .../Pch/Include/Register/PchRegsLpcCnl.h               |  3 ++-
 .../Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c    |  5 ++++-
 .../SystemAgent/Include/Register/SaRegsHostBridge.h    |  5 ++++-
 .../MemoryInit/Include/Coffeelake/MrcInterface.h       |  5 +++--
 6 files changed, 34 insertions(+), 7 deletions(-)

diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
index 68f2c019e2..4b9ce8d4d3 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
@@ -9,7 +9,7 @@
   - Definitions beginning with "S_" are register sizes
   - Definitions beginning with "N_" are the bit position
 
-  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -181,6 +181,7 @@
 #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX 0x000806E0
 #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO 0x000906E0
 #define CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO 0x00060670
+#define CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT      0x000A0660
 
 #ifndef STALL_ONE_MICRO_SECOND
 #define STALL_ONE_MICRO_SECOND 1
@@ -206,6 +207,7 @@ typedef enum {
   EnumCpuCflUltUlx    = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX,
   EnumCpuCflDtHalo    = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO,
   EnumCpuCnlDtHalo    = CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO,
+  EnumCpuCmlUlt       = CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT,
   EnumCpuMax          = CPUID_FULL_FAMILY_MODEL
 } CPU_FAMILY;
 
@@ -256,6 +258,7 @@ typedef enum {
 ///
 typedef enum {
   EnumCflCpu  = 0,
+  EnumCmlCpu,
   EnumCpuUnknownGeneration = 255
 } CPU_GENERATION;
 #endif
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
index 18f2028fa9..702a10c9d8 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
@@ -1,7 +1,7 @@
 /** @file
   CPU Platform Lib implementation.
 
-  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -80,6 +80,15 @@ GetCpuSku (
   CpuDid = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID));
 
   switch (CpuFamilyModel) {
+    case CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT:
+      switch (CpuDid) {
+        case V_SA_DEVICE_ID_CML_ULT_1:   // CML ULT
+        case V_SA_DEVICE_ID_CML_ULT_2:   // CML ULT
+        case V_SA_DEVICE_ID_CML_ULT_3:   // CML ULT
+          CpuType = EnumCpuUlt;
+          break;
+      }
+      break;
     case CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX:
       switch (CpuDid) {
         case V_SA_DEVICE_ID_KBL_MB_ULT_1:    // KBL ULT OPI
@@ -87,6 +96,9 @@ GetCpuSku (
         case V_SA_DEVICE_ID_CFL_ULT_2:       // CFL ULT
         case V_SA_DEVICE_ID_CFL_ULT_3:       // CFL ULT
         case V_SA_DEVICE_ID_CFL_ULT_4:       // CFL ULT
+        case V_SA_DEVICE_ID_CML_ULT_1:       // CML ULT
+        case V_SA_DEVICE_ID_CML_ULT_2:       // CML ULT
+        case V_SA_DEVICE_ID_CML_ULT_3:       // CML ULT
           CpuType = EnumCpuUlt;
           break;
 
@@ -378,6 +390,10 @@ GetCpuGeneration (
       CpuGeneration = EnumCflCpu;
       break;
 
+    case EnumCpuCmlUlt:
+      CpuGeneration = EnumCmlCpu;
+      break;
+
     default:
       CpuGeneration = EnumCpuUnknownGeneration;
       ASSERT (FALSE);
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
index 74789a87ce..e8a18cac3e 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
@@ -21,7 +21,7 @@
   - Registers / bits of new devices introduced in a PCH generation will be just named
     as "_PCH_" without [generation_name] inserted.
 
-  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -31,6 +31,7 @@
 
 #define V_LPC_CFG_DID_CNL_H                       0xA300
 #define V_LPC_CFG_DID_CNL_LP                      0x9D80
+#define V_LPC_CFG_DID_CML_LP                      0x0280
 
 //
 // PCH-LP Device IDs
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c
index 431b1470c2..da6479f212 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c
@@ -4,7 +4,7 @@
   All function in this library is available for PEI, DXE, and SMM,
   But do not support UEFI RUNTIME environment call.
 
-  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -37,6 +37,9 @@ PchSeriesFromLpcDid (
     case V_LPC_CFG_DID_CNL_LP:
       return PCH_LP;
 
+    case V_LPC_CFG_DID_CML_LP:
+      return PCH_LP;
+
     default:
       return PCH_UNKNOWN_SERIES;
   }
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHostBridge.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHostBridge.h
index 2cc0e5be68..67bbf13d77 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHostBridge.h
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHostBridge.h
@@ -15,7 +15,7 @@
   - Registers / bits of new devices introduced in a SA generation will be just named
     as "_SA_" without [generation_name] inserted.
 
-  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -112,6 +112,9 @@
 #define V_SA_DEVICE_ID_CFL_ULT_4        0x3E35   ///< CoffeeLake Mobile (CFL-U 2+(1 or 2)) SA DID
 #define V_SA_DEVICE_ID_CFL_ULT_6        0x3ECC   ///< CoffeeLake Mobile (CFL-U 2+3e) SA DID
 
+#define V_SA_DEVICE_ID_CML_ULT_1        0x9B51  ///< CometLake (CML-U 6+2) SA DID
+#define V_SA_DEVICE_ID_CML_ULT_2        0x9B61  ///< CometLake (CML-U 4+2) SA DID
+#define V_SA_DEVICE_ID_CML_ULT_3        0x9B71  ///< CometLake (CML-U 2+2) SA DID
 //
 // CoffeeLake CPU Desktop SA Device IDs B0:D0:F0
 //
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeelake/MrcInterface.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeelake/MrcInterface.h
index 635906cc2b..b9b390cc71 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeelake/MrcInterface.h
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeelake/MrcInterface.h
@@ -1,7 +1,7 @@
 /** @file
   This file includes all the data structures that the MRC considers "global data".
 
-  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
@@ -477,7 +477,8 @@ typedef enum {
 ///
 typedef enum {
   cmCFL_ULX_ULT   = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX,  ///< Coffeelake ULT/ULX
-  cmCFL_DT_HALO   = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO   ///< Coffeelake DT/Halo
+  cmCFL_DT_HALO   = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO,  ///< Coffeelake DT/Halo
+  cmCML_ULX_ULT   = CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT        ///< Cometlake ULT/ULX
 } MrcCpuModel;
 
 ///
-- 
2.16.2.windows.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg
  2020-02-18 14:53 [edk2-platforms] [PATCH V1 0/2] Add Cometlake U Silicon support and Enable build Kathappan Esakkithevar
  2020-02-18 14:53 ` [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support Kathappan Esakkithevar
@ 2020-02-18 14:53 ` Kathappan Esakkithevar
  2020-02-19  4:06   ` Nate DeSimone
                     ` (2 more replies)
  1 sibling, 3 replies; 10+ messages in thread
From: Kathappan Esakkithevar @ 2020-02-18 14:53 UTC (permalink / raw)
  To: devel
  Cc: Sai Chaganty, Chasel Chiu, Nate DeSimone, Deepika Kethi Reddy,
	Prince Agyeman

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

This change adds the configuration to enable build for CometlakeURvp.
Also it updates Cometlake U Rvp details to the Readme.md.

Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
---
 Platform/Intel/Readme.md | 11 +++++++++++
 Platform/Intel/build.cfg |  3 ++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md
index 02d9517d19..b5ad8ed5fe 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -56,6 +56,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol
 * The `KabylakeOpenBoardPkg` contains board implementations for Kaby Lake systems.
 * The `SimicsOpenBoardPkg` contains board implementations for the Simics hardware simulator.
 * The `WhiskeylakeOpenBoardPkg` contains board implementations for Whiskey Lake systems.
+* The `CometlakeOpenBoardPkg` contains board implementations for Comet Lake systems.
 
 ### **Supported Hardware**
 
@@ -67,6 +68,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol
 ----------------------------------------|--------------------------------------------|------------------------------|--------------------|
 | RVP 3                                 | Sky Lake, Kaby Lake, Kaby Lake Refresh     | KabylakeOpenBoardPkg         | KabylakeRvp3       |
 | WHL-U DDR4 RVP                        | Whiskey Lake                               | WhiskeylakeOpenBoardPkg      | WhiskeylakeURvp    |
+| CML-U LPDDR3 RVP                      | COmet Lake V1                              | CometlakeOpenBoardPkg        | CometlakeURvp      |
 
 *Note: RVP = Reference and Validation Platform*
 
@@ -237,6 +239,11 @@ return back to the minimum platform caller.
           |       |        |               |---build_config.cfg: WhiskeylakeURvp specific build
           |       |        |                                     settings environment variables.
           |       |        |
+          |       |        |------CometlakeOpenBoardPkg
+          |       |        |       |------CometlakeURvp
+          |       |        |               |---build_config.cfg: CometlakeURvp specific build
+          |       |        |                                     settings environment variables.
+          |       |        |
           |------FSP
   </pre>
 
@@ -257,6 +264,10 @@ return back to the minimum platform caller.
 1. This firmware project has only been tested booting to Microsoft Windows 10 x64 with AHCI mode and Integrated Graphic
    Device.
 
+**CometlakeOpenBoardPkg**
+1. This firmware project has been tested booting to Microsoft Windows 10 x64 with AHCI mode and External Graphic Device.
+2. This firmware project has been also tested booting to Ubuntu 17.10 with AHCI mode and Integrated Graphic Device.
+
 ### **Package Builds**
 
 In some cases, such as BoardModulePkg, a package may provide a set of functionality that is included in other
diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg
index 86a9115021..5bc1dea43c 100644
--- a/Platform/Intel/build.cfg
+++ b/Platform/Intel/build.cfg
@@ -1,7 +1,7 @@
 # @ build.cfg
 # This is the main/default build configuration file
 #
-# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 
@@ -58,3 +58,4 @@ BoardX58Ich10 = SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
 GalagoPro3 = KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg
 KabylakeRvp3 = KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg
 WhiskeylakeURvp = WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg
+CometlakeURvp = CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg
-- 
2.16.2.windows.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread
* Re: [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg
  2020-02-18 14:53 ` [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg Kathappan Esakkithevar
@ 2020-02-19  4:06   ` Nate DeSimone
  2020-02-19  6:43   ` Chiu, Chasel
  2020-02-19  7:49   ` Chaganty, Rangasai V
  2 siblings, 0 replies; 10+ messages in thread
From: Nate DeSimone @ 2020-02-19  4:06 UTC (permalink / raw)
  To: Esakkithevar, Kathappan
  Cc: devel@edk2.groups.io, Chaganty, Rangasai V, Chiu, Chasel,
	Kethi Reddy, Deepika, Agyeman, Prince

Hi Kathappan,

Please see my feedback inline.

Thanks,
Nate

On Tue, Feb 18, 2020 at 02:53:43PM +0000, Esakkithevar, Kathappan wrote:
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280
> 
> This change adds the configuration to enable build for CometlakeURvp.
> Also it updates Cometlake U Rvp details to the Readme.md.
> 
> Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
> Cc: Prince Agyeman <prince.agyeman@intel.com>
> ---
>  Platform/Intel/Readme.md | 11 +++++++++++
>  Platform/Intel/build.cfg |  3 ++-
>  2 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md
> index 02d9517d19..b5ad8ed5fe 100644
> --- a/Platform/Intel/Readme.md
> +++ b/Platform/Intel/Readme.md
> @@ -56,6 +56,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol
>  * The `KabylakeOpenBoardPkg` contains board implementations for Kaby Lake systems.
>  * The `SimicsOpenBoardPkg` contains board implementations for the Simics hardware simulator.
>  * The `WhiskeylakeOpenBoardPkg` contains board implementations for Whiskey Lake systems.
> +* The `CometlakeOpenBoardPkg` contains board implementations for Comet Lake systems.
>  
>  ### **Supported Hardware**
>  
> @@ -67,6 +68,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol
>  ----------------------------------------|--------------------------------------------|------------------------------|--------------------|
>  | RVP 3                                 | Sky Lake, Kaby Lake, Kaby Lake Refresh     | KabylakeOpenBoardPkg         | KabylakeRvp3       |
>  | WHL-U DDR4 RVP                        | Whiskey Lake                               | WhiskeylakeOpenBoardPkg      | WhiskeylakeURvp    |

This should be "Comet Lake V1" not "COmet Lake V1"

> +| CML-U LPDDR3 RVP                      | COmet Lake V1                              | CometlakeOpenBoardPkg        | CometlakeURvp      |
>  
>  *Note: RVP = Reference and Validation Platform*
>  
> @@ -237,6 +239,11 @@ return back to the minimum platform caller.
>            |       |        |               |---build_config.cfg: WhiskeylakeURvp specific build
>            |       |        |                                     settings environment variables.
>            |       |        |
> +          |       |        |------CometlakeOpenBoardPkg
> +          |       |        |       |------CometlakeURvp
> +          |       |        |               |---build_config.cfg: CometlakeURvp specific build
> +          |       |        |                                     settings environment variables.
> +          |       |        |
>            |------FSP
>    </pre>
>  
> @@ -257,6 +264,10 @@ return back to the minimum platform caller.
>  1. This firmware project has only been tested booting to Microsoft Windows 10 x64 with AHCI mode and Integrated Graphic
>     Device.
>  
> +**CometlakeOpenBoardPkg**
> +1. This firmware project has been tested booting to Microsoft Windows 10 x64 with AHCI mode and External Graphic Device.
> +2. This firmware project has been also tested booting to Ubuntu 17.10 with AHCI mode and Integrated Graphic Device.
> +
>  ### **Package Builds**
>  
>  In some cases, such as BoardModulePkg, a package may provide a set of functionality that is included in other
> diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg
> index 86a9115021..5bc1dea43c 100644
> --- a/Platform/Intel/build.cfg
> +++ b/Platform/Intel/build.cfg
> @@ -1,7 +1,7 @@
>  # @ build.cfg
>  # This is the main/default build configuration file
>  #
> -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
>  
> @@ -58,3 +58,4 @@ BoardX58Ich10 = SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
>  GalagoPro3 = KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg
>  KabylakeRvp3 = KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg
>  WhiskeylakeURvp = WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg
> +CometlakeURvp = CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg
> -- 
> 2.16.2.windows.1
> 

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [edk2-devel] [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support
  2020-02-18 14:53 ` [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support Kathappan Esakkithevar
@ 2020-02-19  4:06   ` Nate DeSimone
  2020-02-19  6:42   ` Chiu, Chasel
  2020-02-19  7:40   ` Chaganty, Rangasai V
  2 siblings, 0 replies; 10+ messages in thread
From: Nate DeSimone @ 2020-02-19  4:06 UTC (permalink / raw)
  To: devel@edk2.groups.io, Esakkithevar, Kathappan
  Cc: Chaganty, Rangasai V, Chiu, Chasel, Kethi Reddy, Deepika,
	Agyeman, Prince

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

On Tue, Feb 18, 2020 at 02:53:42PM +0000, Esakkithevar, Kathappan wrote:
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280
> 
> Adds CPU model, SA Device ID, PCH SKU ID for Cometlake U V1.
> 
> Key files
> =========
> * CpuReg.h - Add CPU Family Model support.
> * SaRegsHostBridge.h - Add SA Device ID support.
> * MrcInterface.h - Add CPU Family Model support in MRC.
> * PchRegsLpcCnl.h - Add PCH SKU ID support.
> 
> Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
> Cc: Prince Agyeman <prince.agyeman@intel.com>
> ---
>  .../Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h   |  5 ++++-
>  .../PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c       | 18 +++++++++++++++++-
>  .../Pch/Include/Register/PchRegsLpcCnl.h               |  3 ++-
>  .../Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c    |  5 ++++-
>  .../SystemAgent/Include/Register/SaRegsHostBridge.h    |  5 ++++-
>  .../MemoryInit/Include/Coffeelake/MrcInterface.h       |  5 +++--
>  6 files changed, 34 insertions(+), 7 deletions(-)
> 
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
> index 68f2c019e2..4b9ce8d4d3 100644
> --- a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
> @@ -9,7 +9,7 @@
>    - Definitions beginning with "S_" are register sizes
>    - Definitions beginning with "N_" are the bit position
>
> -  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>  **/
> @@ -181,6 +181,7 @@
>  #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX 0x000806E0
>  #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO 0x000906E0
>  #define CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO 0x00060670
> +#define CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT      0x000A0660
>
>  #ifndef STALL_ONE_MICRO_SECOND
>  #define STALL_ONE_MICRO_SECOND 1
> @@ -206,6 +207,7 @@ typedef enum {
>    EnumCpuCflUltUlx    = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX,
>    EnumCpuCflDtHalo    = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO,
>    EnumCpuCnlDtHalo    = CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO,
> +  EnumCpuCmlUlt       = CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT,
>    EnumCpuMax          = CPUID_FULL_FAMILY_MODEL
>  } CPU_FAMILY;
>
> @@ -256,6 +258,7 @@ typedef enum {
>  ///
>  typedef enum {
>    EnumCflCpu  = 0,
> +  EnumCmlCpu,
>    EnumCpuUnknownGeneration = 255
>  } CPU_GENERATION;
>  #endif
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
> index 18f2028fa9..702a10c9d8 100644
> --- a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
> @@ -1,7 +1,7 @@
>  /** @file
>    CPU Platform Lib implementation.
>
> -  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>  **/
> @@ -80,6 +80,15 @@ GetCpuSku (
>    CpuDid = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID));
>
>    switch (CpuFamilyModel) {
> +    case CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT:
> +      switch (CpuDid) {
> +        case V_SA_DEVICE_ID_CML_ULT_1:   // CML ULT
> +        case V_SA_DEVICE_ID_CML_ULT_2:   // CML ULT
> +        case V_SA_DEVICE_ID_CML_ULT_3:   // CML ULT
> +          CpuType = EnumCpuUlt;
> +          break;
> +      }
> +      break;
>      case CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX:
>        switch (CpuDid) {
>          case V_SA_DEVICE_ID_KBL_MB_ULT_1:    // KBL ULT OPI
> @@ -87,6 +96,9 @@ GetCpuSku (
>          case V_SA_DEVICE_ID_CFL_ULT_2:       // CFL ULT
>          case V_SA_DEVICE_ID_CFL_ULT_3:       // CFL ULT
>          case V_SA_DEVICE_ID_CFL_ULT_4:       // CFL ULT
> +        case V_SA_DEVICE_ID_CML_ULT_1:       // CML ULT
> +        case V_SA_DEVICE_ID_CML_ULT_2:       // CML ULT
> +        case V_SA_DEVICE_ID_CML_ULT_3:       // CML ULT
>            CpuType = EnumCpuUlt;
>            break;
>
> @@ -378,6 +390,10 @@ GetCpuGeneration (
>        CpuGeneration = EnumCflCpu;
>        break;
>
> +    case EnumCpuCmlUlt:
> +      CpuGeneration = EnumCmlCpu;
> +      break;
> +
>      default:
>        CpuGeneration = EnumCpuUnknownGeneration;
>        ASSERT (FALSE);
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> index 74789a87ce..e8a18cac3e 100644
> --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> @@ -21,7 +21,7 @@
>    - Registers / bits of new devices introduced in a PCH generation will be just named
>      as "_PCH_" without [generation_name] inserted.
>
> -  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>  **/
> @@ -31,6 +31,7 @@
>
>  #define V_LPC_CFG_DID_CNL_H                       0xA300
>  #define V_LPC_CFG_DID_CNL_LP                      0x9D80
> +#define V_LPC_CFG_DID_CML_LP                      0x0280
>
>  //
>  // PCH-LP Device IDs
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c
> index 431b1470c2..da6479f212 100644
> --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c
> @@ -4,7 +4,7 @@
>    All function in this library is available for PEI, DXE, and SMM,
>    But do not support UEFI RUNTIME environment call.
>
> -  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>  **/
> @@ -37,6 +37,9 @@ PchSeriesFromLpcDid (
>      case V_LPC_CFG_DID_CNL_LP:
>        return PCH_LP;
>
> +    case V_LPC_CFG_DID_CML_LP:
> +      return PCH_LP;
> +
>      default:
>        return PCH_UNKNOWN_SERIES;
>    }
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHostBridge.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHostBridge.h
> index 2cc0e5be68..67bbf13d77 100644
> --- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHostBridge.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHostBridge.h
> @@ -15,7 +15,7 @@
>    - Registers / bits of new devices introduced in a SA generation will be just named
>      as "_SA_" without [generation_name] inserted.
>
> -  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>  **/
> @@ -112,6 +112,9 @@
>  #define V_SA_DEVICE_ID_CFL_ULT_4        0x3E35   ///< CoffeeLake Mobile (CFL-U 2+(1 or 2)) SA DID
>  #define V_SA_DEVICE_ID_CFL_ULT_6        0x3ECC   ///< CoffeeLake Mobile (CFL-U 2+3e) SA DID
>
> +#define V_SA_DEVICE_ID_CML_ULT_1        0x9B51  ///< CometLake (CML-U 6+2) SA DID
> +#define V_SA_DEVICE_ID_CML_ULT_2        0x9B61  ///< CometLake (CML-U 4+2) SA DID
> +#define V_SA_DEVICE_ID_CML_ULT_3        0x9B71  ///< CometLake (CML-U 2+2) SA DID
>  //
>  // CoffeeLake CPU Desktop SA Device IDs B0:D0:F0
>  //
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeelake/MrcInterface.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeelake/MrcInterface.h
> index 635906cc2b..b9b390cc71 100644
> --- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeelake/MrcInterface.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeelake/MrcInterface.h
> @@ -1,7 +1,7 @@
>  /** @file
>    This file includes all the data structures that the MRC considers "global data".
>
> -  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. <BR>
>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>  **/
> @@ -477,7 +477,8 @@ typedef enum {
>  ///
>  typedef enum {
>    cmCFL_ULX_ULT   = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX,  ///< Coffeelake ULT/ULX
> -  cmCFL_DT_HALO   = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO   ///< Coffeelake DT/Halo
> +  cmCFL_DT_HALO   = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO,  ///< Coffeelake DT/Halo
> +  cmCML_ULX_ULT   = CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT        ///< Cometlake ULT/ULX
>  } MrcCpuModel;
>
>  ///
> -- 
> 2.16.2.windows.1
> 
> 
> 
>

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support
  2020-02-18 14:53 ` [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support Kathappan Esakkithevar
  2020-02-19  4:06   ` [edk2-devel] " Nate DeSimone
@ 2020-02-19  6:42   ` Chiu, Chasel
  2020-02-19  7:40   ` Chaganty, Rangasai V
  2 siblings, 0 replies; 10+ messages in thread
From: Chiu, Chasel @ 2020-02-19  6:42 UTC (permalink / raw)
  To: Esakkithevar, Kathappan, devel@edk2.groups.io
  Cc: Chaganty, Rangasai V, Desimone, Nathaniel L, Kethi Reddy, Deepika,
	Agyeman, Prince


Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

> -----Original Message-----
> From: Esakkithevar, Kathappan <kathappan.esakkithevar@intel.com>
> Sent: Tuesday, February 18, 2020 10:54 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Kethi Reddy, Deepika
> <deepika.kethi.reddy@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>
> Subject: [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add
> Cometlake U Silicon support
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280
> 
> Adds CPU model, SA Device ID, PCH SKU ID for Cometlake U V1.
> 
> Key files
> =========
> * CpuReg.h - Add CPU Family Model support.
> * SaRegsHostBridge.h - Add SA Device ID support.
> * MrcInterface.h - Add CPU Family Model support in MRC.
> * PchRegsLpcCnl.h - Add PCH SKU ID support.
> 
> Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
> Cc: Prince Agyeman <prince.agyeman@intel.com>
> ---
>  .../Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h   |  5 ++++-
>  .../PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c       | 18
> +++++++++++++++++-
>  .../Pch/Include/Register/PchRegsLpcCnl.h               |  3 ++-
>  .../Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c    |  5 ++++-
>  .../SystemAgent/Include/Register/SaRegsHostBridge.h    |  5 ++++-
>  .../MemoryInit/Include/Coffeelake/MrcInterface.h       |  5 +++--
>  6 files changed, 34 insertions(+), 7 deletions(-)
> 
> diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
> index 68f2c019e2..4b9ce8d4d3 100644
> --- a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
> @@ -9,7 +9,7 @@
>    - Definitions beginning with "S_" are register sizes
>    - Definitions beginning with "N_" are the bit position
> 
> -  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
> + <BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent  **/ @@ -181,6 +181,7 @@
> #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX 0x000806E0
> #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO 0x000906E0
> #define CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO 0x00060670
> +#define CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT      0x000A0660
> 
>  #ifndef STALL_ONE_MICRO_SECOND
>  #define STALL_ONE_MICRO_SECOND 1
> @@ -206,6 +207,7 @@ typedef enum {
>    EnumCpuCflUltUlx    =
> CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX,
>    EnumCpuCflDtHalo    =
> CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO,
>    EnumCpuCnlDtHalo    =
> CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO,
> +  EnumCpuCmlUlt       =
> CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT,
>    EnumCpuMax          = CPUID_FULL_FAMILY_MODEL
>  } CPU_FAMILY;
> 
> @@ -256,6 +258,7 @@ typedef enum {
>  ///
>  typedef enum {
>    EnumCflCpu  = 0,
> +  EnumCmlCpu,
>    EnumCpuUnknownGeneration = 255
>  } CPU_GENERATION;
>  #endif
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/C
> puPlatformLibrary.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/
> CpuPlatformLibrary.c
> index 18f2028fa9..702a10c9d8 100644
> ---
> a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/C
> puPlatformLibrary.c
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatfor
> +++ mLib/CpuPlatformLibrary.c
> @@ -1,7 +1,7 @@
>  /** @file
>    CPU Platform Lib implementation.
> 
> -  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
> + <BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent  **/ @@ -80,6 +80,15 @@
> GetCpuSku (
>    CpuDid = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM,
> SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID));
> 
>    switch (CpuFamilyModel) {
> +    case CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT:
> +      switch (CpuDid) {
> +        case V_SA_DEVICE_ID_CML_ULT_1:   // CML ULT
> +        case V_SA_DEVICE_ID_CML_ULT_2:   // CML ULT
> +        case V_SA_DEVICE_ID_CML_ULT_3:   // CML ULT
> +          CpuType = EnumCpuUlt;
> +          break;
> +      }
> +      break;
>      case CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX:
>        switch (CpuDid) {
>          case V_SA_DEVICE_ID_KBL_MB_ULT_1:    // KBL ULT OPI
> @@ -87,6 +96,9 @@ GetCpuSku (
>          case V_SA_DEVICE_ID_CFL_ULT_2:       // CFL ULT
>          case V_SA_DEVICE_ID_CFL_ULT_3:       // CFL ULT
>          case V_SA_DEVICE_ID_CFL_ULT_4:       // CFL ULT
> +        case V_SA_DEVICE_ID_CML_ULT_1:       // CML ULT
> +        case V_SA_DEVICE_ID_CML_ULT_2:       // CML ULT
> +        case V_SA_DEVICE_ID_CML_ULT_3:       // CML ULT
>            CpuType = EnumCpuUlt;
>            break;
> 
> @@ -378,6 +390,10 @@ GetCpuGeneration (
>        CpuGeneration = EnumCflCpu;
>        break;
> 
> +    case EnumCpuCmlUlt:
> +      CpuGeneration = EnumCmlCpu;
> +      break;
> +
>      default:
>        CpuGeneration = EnumCpuUnknownGeneration;
>        ASSERT (FALSE);
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> index 74789a87ce..e8a18cac3e 100644
> --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpc
> +++ Cnl.h
> @@ -21,7 +21,7 @@
>    - Registers / bits of new devices introduced in a PCH generation will be just
> named
>      as "_PCH_" without [generation_name] inserted.
> 
> -  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
> + <BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent  **/ @@ -31,6 +31,7 @@
> 
>  #define V_LPC_CFG_DID_CNL_H                       0xA300
>  #define V_LPC_CFG_DID_CNL_LP                      0x9D80
> +#define V_LPC_CFG_DID_CML_LP                      0x0280
> 
>  //
>  // PCH-LP Device IDs
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInf
> oLibCnl.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInf
> oLibCnl.c
> index 431b1470c2..da6479f212 100644
> ---
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInf
> oLibCnl.c
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib
> +++ /PchInfoLibCnl.c
> @@ -4,7 +4,7 @@
>    All function in this library is available for PEI, DXE, and SMM,
>    But do not support UEFI RUNTIME environment call.
> 
> -  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
> + <BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent  **/ @@ -37,6 +37,9 @@
> PchSeriesFromLpcDid (
>      case V_LPC_CFG_DID_CNL_LP:
>        return PCH_LP;
> 
> +    case V_LPC_CFG_DID_CML_LP:
> +      return PCH_LP;
> +
>      default:
>        return PCH_UNKNOWN_SERIES;
>    }
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHos
> tBridge.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHos
> tBridge.h
> index 2cc0e5be68..67bbf13d77 100644
> ---
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHos
> tBridge.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/Sa
> +++ RegsHostBridge.h
> @@ -15,7 +15,7 @@
>    - Registers / bits of new devices introduced in a SA generation will be just
> named
>      as "_SA_" without [generation_name] inserted.
> 
> -  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
> + <BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent  **/ @@ -112,6 +112,9 @@
>  #define V_SA_DEVICE_ID_CFL_ULT_4        0x3E35   ///< CoffeeLake
> Mobile (CFL-U 2+(1 or 2)) SA DID
>  #define V_SA_DEVICE_ID_CFL_ULT_6        0x3ECC   ///< CoffeeLake
> Mobile (CFL-U 2+3e) SA DID
> 
> +#define V_SA_DEVICE_ID_CML_ULT_1        0x9B51  ///< CometLake
> (CML-U 6+2) SA DID
> +#define V_SA_DEVICE_ID_CML_ULT_2        0x9B61  ///< CometLake
> (CML-U 4+2) SA DID
> +#define V_SA_DEVICE_ID_CML_ULT_3        0x9B71  ///< CometLake
> (CML-U 2+2) SA DID
>  //
>  // CoffeeLake CPU Desktop SA Device IDs B0:D0:F0  // diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeel
> ake/MrcInterface.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeel
> ake/MrcInterface.h
> index 635906cc2b..b9b390cc71 100644
> ---
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeel
> ake/MrcInterface.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/
> +++ Coffeelake/MrcInterface.h
> @@ -1,7 +1,7 @@
>  /** @file
>    This file includes all the data structures that the MRC considers "global
> data".
> 
> -  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.
> + <BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent  **/ @@ -477,7 +477,8 @@
> typedef enum {  ///  typedef enum {
>    cmCFL_ULX_ULT   =
> CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX,  ///< Coffeelake
> ULT/ULX
> -  cmCFL_DT_HALO   =
> CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO   ///< Coffeelake
> DT/Halo
> +  cmCFL_DT_HALO   =
> CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO,  ///< Coffeelake
> DT/Halo
> +  cmCML_ULX_ULT   = CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT
> ///< Cometlake ULT/ULX
>  } MrcCpuModel;
> 
>  ///
> --
> 2.16.2.windows.1


^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg
  2020-02-18 14:53 ` [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg Kathappan Esakkithevar
  2020-02-19  4:06   ` Nate DeSimone
@ 2020-02-19  6:43   ` Chiu, Chasel
  2020-02-19  7:49   ` Chaganty, Rangasai V
  2 siblings, 0 replies; 10+ messages in thread
From: Chiu, Chasel @ 2020-02-19  6:43 UTC (permalink / raw)
  To: Esakkithevar, Kathappan, devel@edk2.groups.io
  Cc: Chaganty, Rangasai V, Desimone, Nathaniel L, Kethi Reddy, Deepika,
	Agyeman, Prince


Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

> -----Original Message-----
> From: Esakkithevar, Kathappan <kathappan.esakkithevar@intel.com>
> Sent: Tuesday, February 18, 2020 10:54 PM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Kethi Reddy, Deepika
> <deepika.kethi.reddy@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>
> Subject: [edk2-platforms] [PATCH V1 2/2] Enable build for
> CometlakeOpenBoardPkg
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280
> 
> This change adds the configuration to enable build for CometlakeURvp.
> Also it updates Cometlake U Rvp details to the Readme.md.
> 
> Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
> Cc: Prince Agyeman <prince.agyeman@intel.com>
> ---
>  Platform/Intel/Readme.md | 11 +++++++++++  Platform/Intel/build.cfg |  3
> ++-
>  2 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index
> 02d9517d19..b5ad8ed5fe 100644
> --- a/Platform/Intel/Readme.md
> +++ b/Platform/Intel/Readme.md
> @@ -56,6 +56,7 @@ A UEFI firmware implementation using MinPlatformPkg
> is constructed using the fol
>  * The `KabylakeOpenBoardPkg` contains board implementations for Kaby
> Lake systems.
>  * The `SimicsOpenBoardPkg` contains board implementations for the Simics
> hardware simulator.
>  * The `WhiskeylakeOpenBoardPkg` contains board implementations for
> Whiskey Lake systems.
> +* The `CometlakeOpenBoardPkg` contains board implementations for Comet
> Lake systems.
> 
>  ### **Supported Hardware**
> 
> @@ -67,6 +68,7 @@ A UEFI firmware implementation using MinPlatformPkg
> is constructed using the fol
> ----------------------------------------|--------------------------------------------|-------------
> -----------------|--------------------|
>  | RVP 3                                 | Sky Lake, Kaby Lake, Kaby
> Lake Refresh     | KabylakeOpenBoardPkg         | KabylakeRvp3
> |
>  | WHL-U DDR4 RVP                        | Whiskey Lake
> | WhiskeylakeOpenBoardPkg      | WhiskeylakeURvp    |
> +| CML-U LPDDR3 RVP                      | COmet Lake V1
> | CometlakeOpenBoardPkg        | CometlakeURvp      |
> 
>  *Note: RVP = Reference and Validation Platform*
> 
> @@ -237,6 +239,11 @@ return back to the minimum platform caller.
>            |       |        |               |---build_config.cfg:
> WhiskeylakeURvp specific build
>            |       |        |
> settings environment variables.
>            |       |        |
> +          |       |        |------CometlakeOpenBoardPkg
> +          |       |        |       |------CometlakeURvp
> +          |       |        |               |---build_config.cfg:
> CometlakeURvp specific build
> +          |       |        |
> settings environment variables.
> +          |       |        |
>            |------FSP
>    </pre>
> 
> @@ -257,6 +264,10 @@ return back to the minimum platform caller.
>  1. This firmware project has only been tested booting to Microsoft Windows
> 10 x64 with AHCI mode and Integrated Graphic
>     Device.
> 
> +**CometlakeOpenBoardPkg**
> +1. This firmware project has been tested booting to Microsoft Windows 10
> x64 with AHCI mode and External Graphic Device.
> +2. This firmware project has been also tested booting to Ubuntu 17.10 with
> AHCI mode and Integrated Graphic Device.
> +
>  ### **Package Builds**
> 
>  In some cases, such as BoardModulePkg, a package may provide a set of
> functionality that is included in other diff --git a/Platform/Intel/build.cfg
> b/Platform/Intel/build.cfg index 86a9115021..5bc1dea43c 100644
> --- a/Platform/Intel/build.cfg
> +++ b/Platform/Intel/build.cfg
> @@ -1,7 +1,7 @@
>  # @ build.cfg
>  # This is the main/default build configuration file  # -# Copyright (c) 2019,
> Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  #
> 
> @@ -58,3 +58,4 @@ BoardX58Ich10 =
> SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
>  GalagoPro3 = KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg
>  KabylakeRvp3 = KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg
>  WhiskeylakeURvp =
> WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg
> +CometlakeURvp =
> CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg
> --
> 2.16.2.windows.1


^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support
  2020-02-18 14:53 ` [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support Kathappan Esakkithevar
  2020-02-19  4:06   ` [edk2-devel] " Nate DeSimone
  2020-02-19  6:42   ` Chiu, Chasel
@ 2020-02-19  7:40   ` Chaganty, Rangasai V
  2 siblings, 0 replies; 10+ messages in thread
From: Chaganty, Rangasai V @ 2020-02-19  7:40 UTC (permalink / raw)
  To: Esakkithevar, Kathappan, devel@edk2.groups.io
  Cc: Chiu, Chasel, Desimone, Nathaniel L, Kethi Reddy, Deepika,
	Agyeman, Prince

Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>

-----Original Message-----
From: Esakkithevar, Kathappan <kathappan.esakkithevar@intel.com> 
Sent: Tuesday, February 18, 2020 6:54 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Kethi Reddy, Deepika <deepika.kethi.reddy@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>
Subject: [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

Adds CPU model, SA Device ID, PCH SKU ID for Cometlake U V1.

Key files
=========
* CpuReg.h - Add CPU Family Model support.
* SaRegsHostBridge.h - Add SA Device ID support.
* MrcInterface.h - Add CPU Family Model support in MRC.
* PchRegsLpcCnl.h - Add PCH SKU ID support.

Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
---
 .../Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h   |  5 ++++-
 .../PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c       | 18 +++++++++++++++++-
 .../Pch/Include/Register/PchRegsLpcCnl.h               |  3 ++-
 .../Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c    |  5 ++++-
 .../SystemAgent/Include/Register/SaRegsHostBridge.h    |  5 ++++-
 .../MemoryInit/Include/Coffeelake/MrcInterface.h       |  5 +++--
 6 files changed, 34 insertions(+), 7 deletions(-)

diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
index 68f2c019e2..4b9ce8d4d3 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h
@@ -9,7 +9,7 @@
   - Definitions beginning with "S_" are register sizes
   - Definitions beginning with "N_" are the bit position
 
-  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. 
+ <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent  **/ @@ -181,6 +181,7 @@  #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX 0x000806E0  #define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO 0x000906E0  #define CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO 0x00060670
+#define CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT      0x000A0660
 
 #ifndef STALL_ONE_MICRO_SECOND
 #define STALL_ONE_MICRO_SECOND 1
@@ -206,6 +207,7 @@ typedef enum {
   EnumCpuCflUltUlx    = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX,
   EnumCpuCflDtHalo    = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO,
   EnumCpuCnlDtHalo    = CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO,
+  EnumCpuCmlUlt       = CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT,
   EnumCpuMax          = CPUID_FULL_FAMILY_MODEL
 } CPU_FAMILY;
 
@@ -256,6 +258,7 @@ typedef enum {
 ///
 typedef enum {
   EnumCflCpu  = 0,
+  EnumCmlCpu,
   EnumCpuUnknownGeneration = 255
 } CPU_GENERATION;
 #endif
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
index 18f2028fa9..702a10c9d8 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatfor
+++ mLib/CpuPlatformLibrary.c
@@ -1,7 +1,7 @@
 /** @file
   CPU Platform Lib implementation.
 
-  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. 
+ <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent  **/ @@ -80,6 +80,15 @@ GetCpuSku (
   CpuDid = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID));
 
   switch (CpuFamilyModel) {
+    case CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT:
+      switch (CpuDid) {
+        case V_SA_DEVICE_ID_CML_ULT_1:   // CML ULT
+        case V_SA_DEVICE_ID_CML_ULT_2:   // CML ULT
+        case V_SA_DEVICE_ID_CML_ULT_3:   // CML ULT
+          CpuType = EnumCpuUlt;
+          break;
+      }
+      break;
     case CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX:
       switch (CpuDid) {
         case V_SA_DEVICE_ID_KBL_MB_ULT_1:    // KBL ULT OPI
@@ -87,6 +96,9 @@ GetCpuSku (
         case V_SA_DEVICE_ID_CFL_ULT_2:       // CFL ULT
         case V_SA_DEVICE_ID_CFL_ULT_3:       // CFL ULT
         case V_SA_DEVICE_ID_CFL_ULT_4:       // CFL ULT
+        case V_SA_DEVICE_ID_CML_ULT_1:       // CML ULT
+        case V_SA_DEVICE_ID_CML_ULT_2:       // CML ULT
+        case V_SA_DEVICE_ID_CML_ULT_3:       // CML ULT
           CpuType = EnumCpuUlt;
           break;
 
@@ -378,6 +390,10 @@ GetCpuGeneration (
       CpuGeneration = EnumCflCpu;
       break;
 
+    case EnumCpuCmlUlt:
+      CpuGeneration = EnumCmlCpu;
+      break;
+
     default:
       CpuGeneration = EnumCpuUnknownGeneration;
       ASSERT (FALSE);
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
index 74789a87ce..e8a18cac3e 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpc
+++ Cnl.h
@@ -21,7 +21,7 @@
   - Registers / bits of new devices introduced in a PCH generation will be just named
     as "_PCH_" without [generation_name] inserted.
 
-  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. 
+ <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent  **/ @@ -31,6 +31,7 @@
 
 #define V_LPC_CFG_DID_CNL_H                       0xA300
 #define V_LPC_CFG_DID_CNL_LP                      0x9D80
+#define V_LPC_CFG_DID_CML_LP                      0x0280
 
 //
 // PCH-LP Device IDs
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c
index 431b1470c2..da6479f212 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLibCnl.c
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib
+++ /PchInfoLibCnl.c
@@ -4,7 +4,7 @@
   All function in this library is available for PEI, DXE, and SMM,
   But do not support UEFI RUNTIME environment call.
 
-  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. 
+ <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent  **/ @@ -37,6 +37,9 @@ PchSeriesFromLpcDid (
     case V_LPC_CFG_DID_CNL_LP:
       return PCH_LP;
 
+    case V_LPC_CFG_DID_CML_LP:
+      return PCH_LP;
+
     default:
       return PCH_UNKNOWN_SERIES;
   }
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHostBridge.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHostBridge.h
index 2cc0e5be68..67bbf13d77 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHostBridge.h
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/Sa
+++ RegsHostBridge.h
@@ -15,7 +15,7 @@
   - Registers / bits of new devices introduced in a SA generation will be just named
     as "_SA_" without [generation_name] inserted.
 
-  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. 
+ <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent  **/ @@ -112,6 +112,9 @@
 #define V_SA_DEVICE_ID_CFL_ULT_4        0x3E35   ///< CoffeeLake Mobile (CFL-U 2+(1 or 2)) SA DID
 #define V_SA_DEVICE_ID_CFL_ULT_6        0x3ECC   ///< CoffeeLake Mobile (CFL-U 2+3e) SA DID
 
+#define V_SA_DEVICE_ID_CML_ULT_1        0x9B51  ///< CometLake (CML-U 6+2) SA DID
+#define V_SA_DEVICE_ID_CML_ULT_2        0x9B61  ///< CometLake (CML-U 4+2) SA DID
+#define V_SA_DEVICE_ID_CML_ULT_3        0x9B71  ///< CometLake (CML-U 2+2) SA DID
 //
 // CoffeeLake CPU Desktop SA Device IDs B0:D0:F0  // diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeelake/MrcInterface.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeelake/MrcInterface.h
index 635906cc2b..b9b390cc71 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeelake/MrcInterface.h
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/
+++ Coffeelake/MrcInterface.h
@@ -1,7 +1,7 @@
 /** @file
   This file includes all the data structures that the MRC considers "global data".
 
-  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
+  Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. 
+ <BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent  **/ @@ -477,7 +477,8 @@ typedef enum {  ///  typedef enum {
   cmCFL_ULX_ULT   = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX,  ///< Coffeelake ULT/ULX
-  cmCFL_DT_HALO   = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO   ///< Coffeelake DT/Halo
+  cmCFL_DT_HALO   = CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO,  ///< Coffeelake DT/Halo
+  cmCML_ULX_ULT   = CPUID_FULL_FAMILY_MODEL_COMETLAKE_ULT        ///< Cometlake ULT/ULX
 } MrcCpuModel;
 
 ///
--
2.16.2.windows.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread
* Re: [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg
  2020-02-18 14:53 ` [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg Kathappan Esakkithevar
  2020-02-19  4:06   ` Nate DeSimone
  2020-02-19  6:43   ` Chiu, Chasel
@ 2020-02-19  7:49   ` Chaganty, Rangasai V
  2020-02-19 12:11     ` Kathappan Esakkithevar
  2 siblings, 1 reply; 10+ messages in thread
From: Chaganty, Rangasai V @ 2020-02-19  7:49 UTC (permalink / raw)
  To: Esakkithevar, Kathappan, devel@edk2.groups.io
  Cc: Chiu, Chasel, Desimone, Nathaniel L, Kethi Reddy, Deepika,
	Agyeman, Prince

Minor comments - Please see inline

Thanks,
Sai

-----Original Message-----
From: Esakkithevar, Kathappan <kathappan.esakkithevar@intel.com> 
Sent: Tuesday, February 18, 2020 6:54 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Kethi Reddy, Deepika <deepika.kethi.reddy@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>
Subject: [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280

This change adds the configuration to enable build for CometlakeURvp.
Also it updates Cometlake U Rvp details to the Readme.md.

Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
---
 Platform/Intel/Readme.md | 11 +++++++++++  Platform/Intel/build.cfg |  3 ++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 02d9517d19..b5ad8ed5fe 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -56,6 +56,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol
[Sai]: typo - it should be "following"
 * The `KabylakeOpenBoardPkg` contains board implementations for Kaby Lake systems.
 * The `SimicsOpenBoardPkg` contains board implementations for the Simics hardware simulator.
 * The `WhiskeylakeOpenBoardPkg` contains board implementations for Whiskey Lake systems.
+* The `CometlakeOpenBoardPkg` contains board implementations for Comet Lake systems.
  [Sai]: The systems names should be one word - e.g. CometLake
 ### **Supported Hardware**
 
@@ -67,6 +68,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol  ----------------------------------------|--------------------------------------------|------------------------------|--------------------|
 | RVP 3                                 | Sky Lake, Kaby Lake, Kaby Lake Refresh     | KabylakeOpenBoardPkg         | KabylakeRvp3       |
 | WHL-U DDR4 RVP                        | Whiskey Lake                               | WhiskeylakeOpenBoardPkg      | WhiskeylakeURvp    |
+| CML-U LPDDR3 RVP                      | COmet Lake V1                              | CometlakeOpenBoardPkg        | CometlakeURvp      |
 
 *Note: RVP = Reference and Validation Platform*
 
@@ -237,6 +239,11 @@ return back to the minimum platform caller.
           |       |        |               |---build_config.cfg: WhiskeylakeURvp specific build
           |       |        |                                     settings environment variables.
           |       |        |
+          |       |        |------CometlakeOpenBoardPkg
+          |       |        |       |------CometlakeURvp
+          |       |        |               |---build_config.cfg: CometlakeURvp specific build
+          |       |        |                                     settings environment variables.
+          |       |        |
           |------FSP
   </pre>
 
@@ -257,6 +264,10 @@ return back to the minimum platform caller.
 1. This firmware project has only been tested booting to Microsoft Windows 10 x64 with AHCI mode and Integrated Graphic
    Device.
 
+**CometlakeOpenBoardPkg**
+1. This firmware project has been tested booting to Microsoft Windows 10 x64 with AHCI mode and External Graphic Device.
+2. This firmware project has been also tested booting to Ubuntu 17.10 with AHCI mode and Integrated Graphic Device.
+
 ### **Package Builds**
 
 In some cases, such as BoardModulePkg, a package may provide a set of functionality that is included in other diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index 86a9115021..5bc1dea43c 100644
--- a/Platform/Intel/build.cfg
+++ b/Platform/Intel/build.cfg
@@ -1,7 +1,7 @@
 # @ build.cfg
 # This is the main/default build configuration file  # -# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent  #
 
@@ -58,3 +58,4 @@ BoardX58Ich10 = SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
 GalagoPro3 = KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg
 KabylakeRvp3 = KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg
 WhiskeylakeURvp = WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg
+CometlakeURvp = CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg
--
2.16.2.windows.1


^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg
  2020-02-19  7:49   ` Chaganty, Rangasai V
@ 2020-02-19 12:11     ` Kathappan Esakkithevar
  0 siblings, 0 replies; 10+ messages in thread
From: Kathappan Esakkithevar @ 2020-02-19 12:11 UTC (permalink / raw)
  To: Chaganty, Rangasai V, devel@edk2.groups.io
  Cc: Chiu, Chasel, Desimone, Nathaniel L, Kethi Reddy, Deepika,
	Agyeman, Prince

Hi Sai, 

I have updated the feedback comments and please help to review at [edk2-devel] [edk2-platforms] [PATCH V2 2/2] Enable build for CometlakeOpenBoardPkg

For comment : > [Sai]: typo - it should be "following" 

I saw the Readme.md , below statement is correct as below at line 45. 

"A UEFI firmware implementation using MinPlatformPkg is constructed using the following pieces."

Not sure why we are seeing below trimmed lines at patches. 

"@@ -53,9 +53,10 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol"
"@@ -237,6 +239,11 @@ return back to the minimum platform caller."

> -----Original Message-----
> From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
> Sent: Wednesday, February 19, 2020 1:20 PM
> To: Esakkithevar, Kathappan <kathappan.esakkithevar@intel.com>;
> devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Kethi Reddy, Deepika
> <deepika.kethi.reddy@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>
> Subject: RE: [edk2-platforms] [PATCH V1 2/2] Enable build for
> CometlakeOpenBoardPkg
> 
> Minor comments - Please see inline
> 
> Thanks,
> Sai
> 
> -----Original Message-----
> From: Esakkithevar, Kathappan <kathappan.esakkithevar@intel.com>
> Sent: Tuesday, February 18, 2020 6:54 AM
> To: devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel
> <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Kethi Reddy, Deepika
> <deepika.kethi.reddy@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>
> Subject: [edk2-platforms] [PATCH V1 2/2] Enable build for
> CometlakeOpenBoardPkg
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2280
> 
> This change adds the configuration to enable build for CometlakeURvp.
> Also it updates Cometlake U Rvp details to the Readme.md.
> 
> Signed-off-by: Kathappan Esakkithevar <kathappan.esakkithevar@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Deepika Kethi Reddy <deepika.kethi.reddy@intel.com>
> Cc: Prince Agyeman <prince.agyeman@intel.com>
> ---
>  Platform/Intel/Readme.md | 11 +++++++++++  Platform/Intel/build.cfg |  3 ++-
>  2 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index
> 02d9517d19..b5ad8ed5fe 100644
> --- a/Platform/Intel/Readme.md
> +++ b/Platform/Intel/Readme.md
> @@ -56,6 +56,7 @@ A UEFI firmware implementation using MinPlatformPkg is
> constructed using the fol
> [Sai]: typo - it should be "following"
>  * The `KabylakeOpenBoardPkg` contains board implementations for Kaby Lake
> systems.
>  * The `SimicsOpenBoardPkg` contains board implementations for the Simics
> hardware simulator.
>  * The `WhiskeylakeOpenBoardPkg` contains board implementations for
> Whiskey Lake systems.
> +* The `CometlakeOpenBoardPkg` contains board implementations for Comet
> Lake systems.
>   [Sai]: The systems names should be one word - e.g. CometLake  ###
> **Supported Hardware**
> 
> @@ -67,6 +68,7 @@ A UEFI firmware implementation using MinPlatformPkg is
> constructed using the fol  ----------------------------------------|-----------------------------
> ---------------|------------------------------|--------------------|
>  | RVP 3                                 | Sky Lake, Kaby Lake, Kaby Lake Refresh     |
> KabylakeOpenBoardPkg         | KabylakeRvp3       |
>  | WHL-U DDR4 RVP                        | Whiskey Lake                               |
> WhiskeylakeOpenBoardPkg      | WhiskeylakeURvp    |
> +| CML-U LPDDR3 RVP                      | COmet Lake V1                              |
> CometlakeOpenBoardPkg        | CometlakeURvp      |
> 
>  *Note: RVP = Reference and Validation Platform*
> 
> @@ -237,6 +239,11 @@ return back to the minimum platform caller.
>            |       |        |               |---build_config.cfg: WhiskeylakeURvp specific build
>            |       |        |                                     settings environment variables.
>            |       |        |
> +          |       |        |------CometlakeOpenBoardPkg
> +          |       |        |       |------CometlakeURvp
> +          |       |        |               |---build_config.cfg: CometlakeURvp specific build
> +          |       |        |                                     settings environment variables.
> +          |       |        |
>            |------FSP
>    </pre>
> 
> @@ -257,6 +264,10 @@ return back to the minimum platform caller.
>  1. This firmware project has only been tested booting to Microsoft Windows
> 10 x64 with AHCI mode and Integrated Graphic
>     Device.
> 
> +**CometlakeOpenBoardPkg**
> +1. This firmware project has been tested booting to Microsoft Windows 10
> x64 with AHCI mode and External Graphic Device.
> +2. This firmware project has been also tested booting to Ubuntu 17.10 with
> AHCI mode and Integrated Graphic Device.
> +
>  ### **Package Builds**
> 
>  In some cases, such as BoardModulePkg, a package may provide a set of
> functionality that is included in other diff --git a/Platform/Intel/build.cfg
> b/Platform/Intel/build.cfg index 86a9115021..5bc1dea43c 100644
> --- a/Platform/Intel/build.cfg
> +++ b/Platform/Intel/build.cfg
> @@ -1,7 +1,7 @@
>  # @ build.cfg
>  # This is the main/default build configuration file  # -# Copyright (c) 2019, Intel
> Corporation. All rights reserved.<BR>
> +# Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.<BR>
>  # SPDX-License-Identifier: BSD-2-Clause-Patent  #
> 
> @@ -58,3 +58,4 @@ BoardX58Ich10 =
> SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
>  GalagoPro3 = KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg
>  KabylakeRvp3 = KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg
>  WhiskeylakeURvp =
> WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg
> +CometlakeURvp = CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg
> --
> 2.16.2.windows.1
> 


^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-02-19 12:13 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-02-18 14:53 [edk2-platforms] [PATCH V1 0/2] Add Cometlake U Silicon support and Enable build Kathappan Esakkithevar
2020-02-18 14:53 ` [edk2-platforms] [PATCH V1 1/2] CoffeeLakeSiliconPkg: Add Cometlake U Silicon support Kathappan Esakkithevar
2020-02-19  4:06   ` [edk2-devel] " Nate DeSimone
2020-02-19  6:42   ` Chiu, Chasel
2020-02-19  7:40   ` Chaganty, Rangasai V
2020-02-18 14:53 ` [edk2-platforms] [PATCH V1 2/2] Enable build for CometlakeOpenBoardPkg Kathappan Esakkithevar
2020-02-19  4:06   ` Nate DeSimone
2020-02-19  6:43   ` Chiu, Chasel
2020-02-19  7:49   ` Chaganty, Rangasai V
2020-02-19 12:11     ` Kathappan Esakkithevar

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox