From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web12.1675.1584403710212829162 for ; Mon, 16 Mar 2020 17:08:30 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: chasel.chiu@intel.com) IronPort-SDR: sxUnw3bCXEPDqhl3/vHCEcWUyJBPnKD0v0Tt1dBjhDYZBPXL/nsV6uDeIYbaj3wtbo2V0YkIsm pvWuRutz+oBA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2020 17:08:29 -0700 IronPort-SDR: aPfSb16DpL/DXaxOczHYUhYSTLYKbvyMyAOKNsVZ98rRk3txx75iXJ0PHAafoqHzShuBnaSw4m MSZtowY6oeHQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,562,1574150400"; d="scan'208";a="443550782" Received: from pgsmsx101.gar.corp.intel.com ([10.221.44.78]) by fmsmga005.fm.intel.com with ESMTP; 16 Mar 2020 17:08:28 -0700 Received: from pgsmsx111.gar.corp.intel.com ([169.254.2.178]) by PGSMSX101.gar.corp.intel.com ([169.254.1.189]) with mapi id 14.03.0439.000; Tue, 17 Mar 2020 08:08:27 +0800 From: "Chiu, Chasel" To: "Chen, TinaX Y" , "devel@edk2.groups.io" CC: "Ni, Ray" , "Chaganty, Rangasai V" , "Tsao, Ethan" Subject: Re: [PATCH] IntelSiliconPkg/Include/Library:Add ConfigBlockLib.h Thread-Topic: [PATCH] IntelSiliconPkg/Include/Library:Add ConfigBlockLib.h Thread-Index: AQHV+6EETzSQ6zqjTkCKMW2cmGsgoqhL6KzQ Date: Tue, 17 Mar 2020 00:08:26 +0000 Message-ID: <3C3EFB470A303B4AB093197B6777CCEC506D7A49@PGSMSX111.gar.corp.intel.com> References: <20200316144123.9372-1-tinax.y.chen@intel.com> In-Reply-To: <20200316144123.9372-1-tinax.y.chen@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [172.30.20.205] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Chasel Chiu > -----Original Message----- > From: Chen, TinaX Y > Sent: Monday, March 16, 2020 10:41 PM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Chaganty, Rangasai V > ; Chiu, Chasel ; > Tsao, Ethan > Subject: [PATCH] IntelSiliconPkg/Include/Library:Add ConfigBlockLib.h >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2318 >=20 > Change reference path of ConfigBlockLib to IntelSiliconPkg for Coffeelake= . >=20 > Change-Id: I433e0a7a00c0cc15a0986050c203c7ca8aef02a2 > Signed-off-by: TinaX Y Chen > cc: Ray Ni > cc: Rangasai V Chaganty > cc: Chasel Chiu > cc: Ethan Tsao > --- > Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc > b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc > index 37c77d8f..2f25bdb3 100644 > --- a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc > +++ b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc > @@ -1,7 +1,7 @@ > ## @file > # Component description file for the Coffee Lake silicon package DSC fi= le. > # > -# Copyright (c) 2019 Intel Corporation. All rights reserved.
> +# Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved. > +
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -147,7 +147,7 @@ > gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 > # Silicon Init Common Library > # > !include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc > -ConfigBlockLib|ClientSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBl > -ConfigBlockLib|ockLib.inf > +ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlo > +ConfigBlockLib|ckLib.inf >=20 > PchTraceHubInitLib|ClientSiliconPkg/Library/BasePchTraceHubInitLib/BasePc= h > TraceHubInitLib.inf >=20 > [LibraryClasses.IA32] > -- > 2.16.2.windows.1