From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: zhichao.gao@intel.com) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by groups.io with SMTP; Fri, 24 May 2019 00:47:56 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 May 2019 00:47:55 -0700 X-ExtLoop1: 1 Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga001.jf.intel.com with ESMTP; 24 May 2019 00:47:55 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 24 May 2019 00:47:55 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.129]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.33]) with mapi id 14.03.0415.000; Fri, 24 May 2019 15:47:51 +0800 From: "Gao, Zhichao" To: "Ni, Ray" , "devel@edk2.groups.io" CC: "Wang, Jian J" , "Wu, Hao A" , "Zeng, Star" , "Gao, Liming" , Sean Brogan , Michael Turner , Bret Barkelew , "Kinney, Michael D" , "Dong, Eric" , Laszlo Ersek Subject: Re: [PATCH 0/6] Fix race condition and add event protocol Thread-Topic: [PATCH 0/6] Fix race condition and add event protocol Thread-Index: AQHVEe41BKZdEtNJB0+TtHHLcqx0waZ5u6YggAADdWA= Date: Fri, 24 May 2019 07:47:50 +0000 Message-ID: <3CE959C139B4C44DBEA1810E3AA6F9000B7D4F48@SHSMSX101.ccr.corp.intel.com> References: <20190524050437.38616-1-zhichao.gao@intel.com> <734D49CCEBEEF84792F5B80ED585239D5C15E506@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <734D49CCEBEEF84792F5B80ED585239D5C15E506@SHSMSX104.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: zhichao.gao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Sorry I didn't add the BZ link. https://bugzilla.tianocore.org/show_bug.cgi?id=3D1400=20 "If an interrupt happens between CheckEvent and gIdleLoopEvent, there would= be a event pending during cpu sleep." Here is the wait for event flow: Result =3D CheckEvent (interrupt happens here, and set the gEventPending) Result =3D=3D FALSE Ilde event (put cpu to sleep)(there are events in pending list and they sho= uld be handle, but the cpu is hlt and cannot handle it) Solution is here: Result =3D CheckEvent (interrupt happens) Disable interrupt PendingResult =3D Check gEventPending If gEventPending =3D=3D TRUE { Enable interrupt and goto CheckEvent to handle } else { Enable interrupt and hlt (this should be 'atomic' so that no race conditi= on would happen) } Thanks, Zhichao > -----Original Message----- > From: Ni, Ray > Sent: Friday, May 24, 2019 1:18 PM > To: Gao, Zhichao ; devel@edk2.groups.io > Cc: Wang, Jian J ; Wu, Hao A ; > Zeng, Star ; Gao, Liming ; > Sean Brogan ; Michael Turner > ; Bret Barkelew > ; Kinney, Michael D > ; Dong, Eric ; Laszlo > Ersek > Subject: RE: [PATCH 0/6] Fix race condition and add event protocol >=20 > Zhichao, > Did your detailed patch commit message describe the consequence of the > race condition? (I haven't checked.) If no, could you please describe in = detail > about the consequence? >=20 > Thanks, > Ray >=20 > > -----Original Message----- > > From: Gao, Zhichao > > Sent: Friday, May 24, 2019 1:05 PM > > To: devel@edk2.groups.io > > Cc: Wang, Jian J ; Wu, Hao A > > ; Ni, Ray ; Zeng, Star > > ; Gao, Liming ; Sean Brogan > > ; Michael Turner > > ; Bret Barkelew > > ; Kinney, Michael D > > ; Dong, Eric ; Laszlo > > Ersek > > Subject: [PATCH 0/6] Fix race condition and add event protocol > > > > There is a race condition in CoreWaitForEvent function: > > If an interrupt happens between CheckEvent and gIdleLoopEvent, there > > would be a event pending during cpu sleep. > > So it is required to check the gEventPending with the interrupt disable= d. > > Implement a gEfiCpu2ProtocolGuid to fix that. The protocol include one > > interface to enable interrupt and put the cpu to sleep. > > > > Add a event protocol gEdkiiCommonEventProtocolGuid to support all TPL > > event. It is require for PI drivers that use HW interrput. > > > > Cc: Jian J Wang > > Cc: Hao A Wu > > cc: Ray Ni > > Cc: Star Zeng > > Cc: Liming gao > > Cc: Sean Brogan > > Cc: Michael Turner > > Cc: Bret Barkelew > > Cc: Michael D Kinney > > Cc: Eric Dong > > Cc: Laszlo Ersek > > > > Sean Brogan (5): > > MdeModulePkg: Add gEdkiiCommonEventProtocolGuid for event > > MdePkg/BaseLib.h: Add EnableInterruptsAndSleep function declare > > MdePkg/BaseLib: Implement EnableInterruptsAndSleep > > MdePkg: Add gEfiCpu2ProtocolGuid and header file > > MdeModulePkg/DxeMain: Implement common event protocol > > > > Zhichao Gao (1): > > UefiCpuPkg/CpuDxe: Implement Cpu2 protocol > > > > MdeModulePkg/Core/Dxe/DxeMain.h | 64 ++++++++++- > > MdeModulePkg/Core/Dxe/DxeMain.inf | 1 + > > MdeModulePkg/Core/Dxe/DxeMain/DxeMain.c | 22 ++++ > > .../Core/Dxe/DxeMain/DxeProtocolNotify.c | 1 + > > MdeModulePkg/Core/Dxe/Event/Event.c | 102 ++++++++++++++++- > - > > MdeModulePkg/Core/Dxe/Event/Event.h | 2 +- > > MdeModulePkg/Include/Protocol/CommonEvent.h | 18 ++++ > > MdeModulePkg/MdeModulePkg.dec | 3 + > > MdePkg/Include/Library/BaseLib.h | 11 ++ > > MdePkg/Include/Protocol/Cpu2.h | 43 ++++++++ > > .../Library/BaseLib/Ia32/EnableInterrupts.c | 18 +++- > > .../BaseLib/Ia32/EnableInterrupts.nasm | 15 ++- > > .../Library/BaseLib/X64/EnableInterrupts.nasm | 15 ++- > > MdePkg/MdePkg.dec | 3 + > > UefiCpuPkg/CpuDxe/CpuDxe.c | 40 ++++++- > > UefiCpuPkg/CpuDxe/CpuDxe.h | 15 +++ > > UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 +- > > 17 files changed, 358 insertions(+), 18 deletions(-) create mode > > 100644 MdeModulePkg/Include/Protocol/CommonEvent.h > > create mode 100644 MdePkg/Include/Protocol/Cpu2.h > > > > -- > > 2.21.0.windows.1