From: "Rebecca Cran" <rebecca@bsdio.com>
To: devel@edk2.groups.io, abner.chang@hpe.com
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>,
Sean Brogan <sean.brogan@microsoft.com>,
Bob Feng <bob.c.feng@intel.com>,
Leif Lindholm <leif@nuviainc.com>,
Michael D Kinney <michael.d.kinney@intel.com>,
Liming Gao <liming.gao@intel.com>,
Gilbert Chen <gilbert.chen@hpe.com>,
Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
Subject: Re: [edk2-devel] [edk2/master PATCH RISC-V CI v2 3/5] BaseTools: Enable RISC-V architecture for RISC-V EDK2 CI.
Date: Fri, 20 Mar 2020 18:32:33 -0600 [thread overview]
Message-ID: <3a585769-cede-f3fb-86a2-6d00c6cde3c4@bsdio.com> (raw)
In-Reply-To: <20200309095318.7331-4-abner.chang@hpe.com>
On 2020-03-09 03:53, Abner Chang wrote:
> @@ -83,3 +90,27 @@ class LinuxGcc5ToolChain(IUefiBuildPlugin):
> return -2
>
> return 0
> +
> + def _check_riscv64(self):
> + # check to see if full path already configured
> + if shell_environment.GetEnvironment().get_shell_var("GCC5_RISCV64_PREFIX") is not None:
> + self.Logger.info("GCC5_RISCV64_PREFIX is already set.")
Just a nit: I think the normal Python style is to have two lines between
functions, not one. You can check with pyflakes.
--
Rebecca Cran
next prev parent reply other threads:[~2020-03-21 0:32 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-09 9:53 [edk2/master PATCH RISC-V CI v2 0/5] RISC-V EDK2 CI configuration files Abner Chang
2020-03-09 9:53 ` [edk2/master PATCH RISC-V CI v2 1/5] RiscVPlatformPkg: Add RiscVPlatformPkg yaml file for EDK2 CI Abner Chang
2020-03-20 0:51 ` [edk2-devel] " Michael D Kinney
2020-03-09 9:53 ` [edk2/master PATCH RISC-V CI v2 2/5] RiscVPkg: Add RiscVPkg " Abner Chang
2020-03-20 0:51 ` [edk2-devel] " Michael D Kinney
2020-03-22 3:12 ` Abner Chang
2020-03-09 9:53 ` [edk2/master PATCH RISC-V CI v2 3/5] BaseTools: Enable RISC-V architecture for RISC-V " Abner Chang
2020-03-21 0:32 ` Rebecca Cran [this message]
2020-03-09 9:53 ` [edk2/master PATCH RISC-V CI v2 4/5] .azurepipelines: Add RISC-V architecture on " Abner Chang
2020-03-09 9:53 ` [edk2/master PATCH RISC-V CI v2 5/5] .pytool: " Abner Chang
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