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Tue, 13 Jul 2021 09:27:36 +0000 Received: from DF4PR8401MB0444.NAMPRD84.PROD.OUTLOOK.COM ([fe80::c804:b24:831b:272a]) by DF4PR8401MB0444.NAMPRD84.PROD.OUTLOOK.COM ([fe80::c804:b24:831b:272a%5]) with mapi id 15.20.4308.027; Tue, 13 Jul 2021 09:27:36 +0000 Subject: Re: [PATCH] BaseTools GenFw: Add support for R_RISCV_PCREL_LO12_S relocation To: Sunil V L , CC: , Liming Gao , Bob Feng , Yuwei Chen , Pete Batard , Abner Chang References: <20210710063114.4278-1-sunilvl@ventanamicro.com> From: "Daniel Schaefer" Message-ID: <3a9012d4-512b-e545-5541-39986d5a7b50@hpe.com> Date: Tue, 13 Jul 2021 17:27:30 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 In-Reply-To: <20210710063114.4278-1-sunilvl@ventanamicro.com> X-ClientProxiedBy: SA0PR11CA0104.namprd11.prod.outlook.com (2603:10b6:806:d1::19) To DF4PR8401MB0444.NAMPRD84.PROD.OUTLOOK.COM (2a01:111:e400:760d::23) X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [192.168.42.127] (123.193.59.220) by SA0PR11CA0104.namprd11.prod.outlook.com (2603:10b6:806:d1::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; 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charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Looks good. I compared it with existing R_RISCV_PCREL_LO12_I and looked at the differences. This one doesn't do use mRiscVPass1GotFixup. I assume this is an optimization that's not possible here? Haven't tested that it works but since it works for Pete: Reviewed-by: Daniel Schaefer Thanks! On 7/10/21 2:31 PM, Sunil V L wrote: > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3459 > > This patch adds support for R_RISCV_PCREL_LO12_S relocation type. > The logic is same as existing R_RISCV_PCREL_LO12_I relocation > except the difference between load vs store instruction formats. > > Signed-off-by: Sunil V L > > Cc: Liming Gao > Cc: Bob Feng > Cc: Yuwei Chen > Cc: Pete Batard > Cc: Abner Chang > Cc: Daniel Schaefer > --- > BaseTools/Source/C/GenFw/Elf64Convert.c | 55 +++++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c > index 3d7e20aaff..0bb3ead228 100644 > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > @@ -557,6 +557,60 @@ WriteSectionRiscV64 ( > Value = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); > break; > > + case R_RISCV_PCREL_LO12_S: > + if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) { > + int i; > + Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); > + > + Value = ((UINT32)(RV_X(*(UINT32 *)Targ, 25, 7)) << 5); > + Value = (Value | (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5))); > + > + if(Value & (RISCV_IMM_REACH/2)) { > + Value |= ~(RISCV_IMM_REACH-1); > + } > + Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex]; > + > + if(-2048 > (INT32)Value) { > + i = (((INT32)Value * -1) / 4096); > + Value2 -= i; > + Value += 4096 * i; > + if(-2048 > (INT32)Value) { > + Value2 -= 1; > + Value += 4096; > + } > + } > + else if( 2047 < (INT32)Value) { > + i = (Value / 4096); > + Value2 += i; > + Value -= 4096 * i; > + if(2047 < (INT32)Value) { > + Value2 += 1; > + Value -= 4096; > + } > + } > + > + // Update the IMM of SD instruction > + // > + // |31 25|24 20|19 15|14 12 |11 7|6 0| > + // |-------------------------------------------|-------| > + // |imm[11:5] | rs2 | rs1 | funct3 |imm[4:0] | opcode| > + // --------------------------------------------------- > + > + // First Zero out current IMM > + *(UINT32 *)Targ &= ~0xfe000f80; > + > + // Update with new IMM > + *(UINT32 *)Targ |= (RV_X(Value, 5, 7) << 25); > + *(UINT32 *)Targ |= (RV_X(Value, 0, 5) << 7); > + > + // Update previous instruction > + *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12)); > + } > + mRiscVPass1Sym = NULL; > + mRiscVPass1Targ = NULL; > + mRiscVPass1SymSecIndex = 0; > + break; > + > case R_RISCV_PCREL_LO12_I: > if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) { > int i; > @@ -1587,6 +1641,7 @@ WriteRelocations64 ( > case R_RISCV_PCREL_HI20: > case R_RISCV_GOT_HI20: > case R_RISCV_PCREL_LO12_I: > + case R_RISCV_PCREL_LO12_S: > break; > > default: >