From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A1ED7223648BD for ; Tue, 30 Jan 2018 21:06:56 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Jan 2018 21:12:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,438,1511856000"; d="scan'208";a="13883046" Received: from ray-dev.ccr.corp.intel.com (HELO [10.239.9.19]) ([10.239.9.19]) by orsmga007.jf.intel.com with ESMTP; 30 Jan 2018 21:12:30 -0800 To: Laszlo Ersek , edk2-devel-01 Cc: Eric Dong , Jian J Wang , Jiewen Yao , Paolo Bonzini References: <20180130153348.31992-1-lersek@redhat.com> <20180130153348.31992-4-lersek@redhat.com> From: "Ni, Ruiyu" Message-ID: <3af56420-bcd9-c870-efea-e0203e1aa2fe@Intel.com> Date: Wed, 31 Jan 2018 13:12:30 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <20180130153348.31992-4-lersek@redhat.com> Subject: Re: [PATCH 3/3] UefiCpuPkg/PiSmmCpuDxeSmm: eliminate conditional jump in IA32 SmmStartup() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 31 Jan 2018 05:06:57 -0000 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit On 1/30/2018 11:33 PM, Laszlo Ersek wrote: > SMM emulation under KVM crashes the guest when the "jz" branch, added in > commit d4d87596c11d ("UefiCpuPkg/PiSmmCpuDxeSmm: Enable NXE if it's > supported", 2018-01-18), is taken. > > Rework the propagation of CPUID.80000001H:EDX.NX [bit 20] to IA32_EFER.NXE > [bit 11] so that no code is executed conditionally. > > Cc: Eric Dong > Cc: Jian J Wang > Cc: Jiewen Yao > Cc: Paolo Bonzini > Cc: Ruiyu Ni > Ref: http://mid.mail-archive.com/d6fff558-6c4f-9ca6-74a7-e7cd9d007276@redhat.com > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Laszlo Ersek > --- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm > index 9231aa5b3ded..102e0bdbabc8 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm > @@ -44,26 +44,25 @@ global ASM_PFX(SmmStartup) > > BITS 16 > ASM_PFX(SmmStartup): > mov eax, 0x80000001 ; read capability > cpuid > mov ebx, edx ; rdmsr will change edx. keep it in ebx. > + and ebx, BIT20 ; extract XD capability bit Per CPUID_EXTENDED_CPU_SIG_EDX definition in UefiCpuPkg/Include/Register/CpuId.h, the BIT name is NX. > + shr ebx, 9 ; shift bit to IA32_EFER NXE position How about changing above comments to: ; shift bit to IA32_EFER.NXE[BIT11] position? > DB 0x66, 0xb8 ; mov eax, imm32 > ASM_PFX(gSmmCr3): DD 0 > mov cr3, eax > o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))] > DB 0x66, 0xb8 ; mov eax, imm32 > ASM_PFX(gSmmCr4): DD 0 > mov cr4, eax > mov ecx, 0xc0000080 ; IA32_EFER MSR > rdmsr > - test ebx, BIT20 ; check NXE capability > - jz .1 > - or ah, BIT3 ; set NXE bit > + or eax, ebx ; set NXE bit if XD is available ; Bit name is NX. > wrmsr > -.1: > DB 0x66, 0xb8 ; mov eax, imm32 > ASM_PFX(gSmmCr0): DD 0 > mov di, PROTECT_MODE_DS > mov cr0, eax > DB 0x66, 0xea ; jmp far [ptr48] > ASM_PFX(gSmmJmpAddr): > Very clever solution to remove jz. With the minor comments update, Reviewed-by: Ruiyu Ni -- Thanks, Ray