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Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [edk2-devel] [edk2-platforms][PATCH 1/1] AmpereAltraPkg: Update ArmPlatformLib to work with changed ARM_CORE_INFO To: Rebecca Cran , devel@edk2.groups.io, ardb@kernel.org, Rebecca Cran CC: nhi@os.amperecomputing.com, patches@amperecomputing.com, quic_llindhol@quicinc.com, ardb+tianocore@kernel.org, Tinh Nguyen , harb@amperecomputing.com References: <20230113042126.3107135-1-nhi@os.amperecomputing.com> <7d401f29-56d9-d754-88a6-684ce329a727@quicinc.com> <25ee195f-85ee-d783-7e5c-f0da8b9972b4@quicinc.com> <923d3222-775c-f0e8-b4c1-4c10f122ad0a@bsdio.com> From: "Nhi Pham" In-Reply-To: <923d3222-775c-f0e8-b4c1-4c10f122ad0a@bsdio.com> X-ClientProxiedBy: SG2PR02CA0115.apcprd02.prod.outlook.com (2603:1096:4:92::31) To PH0PR01MB7287.prod.exchangelabs.com (2603:10b6:510:10a::21) Return-Path: nhi@os.amperecomputing.com MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH0PR01MB7287:EE_|CH0PR01MB7172:EE_ X-MS-Office365-Filtering-Correlation-Id: 7ee75400-0e64-40f1-ef73-08db03556b7b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Hi Rebecca, ++ Harb who can give more insights on this. FYI, the original concern is=20 https://edk2.groups.io/g/devel/message/98482 On 1/18/2023 1:21 AM, Rebecca Cran wrote: > On 1/17/23 09:40, Ard Biesheuvel wrote: >> On Tue, 17 Jan 2023 at 13:55, Rebecca Cran wrote: >>> I was under the impression that this is becoming a more standard format= ? >>> >> If this is not defined in an ARM spec somewhere, we shouldn't add it >> to ArmPkg at this point. > > From what I've found, the ARM specs such as the Arm Architecture=20 > Reference Manual for A-profile architecture don't define the meaning=20 > of the affinity fields? That appears to be left up to the individual=20 > Arm core TRMs. > I think so. This might be silicon specific implementation. Per Arm Armv8-A Architecture Registers=20 (https://developer.arm.com/documentation/ddi0595/2021-12/AArch64-Registers/= MPIDR-EL1--Multiprocessor-Affinity-Register),=20 if I interpret correctly, the AFF0 will give core ID or thread ID based=20 on the MT bit in the MPIDR register. I think we should remove the following definitions particularly for=20 getting core id and cluster in ArmPkg/Include/Library/ArmLib.h to avoid=20 the confusion to others #define ARM_CORE_MASK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ARM_C= ORE_AFF0 #define ARM_CLUSTER_MASK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ARM_CORE_AFF1 #define GET_CORE_ID(MpId)=C2=A0=C2=A0=C2=A0=C2=A0 ((MpId) & ARM_CORE_MASK) #define GET_CLUSTER_ID(MpId)=C2=A0 (((MpId) & ARM_CLUSTER_MASK) >> 8) #define GET_MPID(ClusterId, CoreId)=C2=A0=C2=A0 (((ClusterId) << 8) | (Core= Id)) #define PRIMARY_CORE_ID=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (PcdGet32(PcdAr= mPrimaryCore) & ARM_CORE_MASK) And, should support GET_AFFx like #define ARM_MPIDR_GET_AFF0(Mpid) ((Mpid) & ARM_CORE_AFF0) For silicon specific usage, it can abstract them to proper IDs like #define XXX_GET_CORE_ID(Mpid) ARM_MPIDR_GET_AFF0(Mpid) Thanks, Nhi > For example, the Cortex-X2 TRM says: > > Affinity level 0. This is the affinity level that is most significant=20 > for determining PE behavior. Higher affinity > levels are increasingly less significant in determining PE behavior.=20 > The assigned value of the MPIDR.{Aff2, > Aff1, Aff0} or AArch64-MPIDR_EL1.{Aff3, Aff2, Aff1, Aff0} set of=20 > fields of each PE must be unique within the > system as a whole. > 0b00000000 > Only one thread. > > > Affinity level 1. See the description of Aff0 for more information. > Value read from the CPUID configuration pins. Identification number=20 > for each CPU in an cluster counting from > zero. > > > Affinity level 2. See the description of Aff0 for more information. > The value will be determined by the CLUSTERIDAFF2 configuration pins. > > > Affinity level 3. See the description of Aff0 for more information. > The value will be determined by the CLUSTERIDAFF3 configuration pins. >