From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=209.132.183.28; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4C1E42118FF23 for ; Thu, 15 Nov 2018 04:44:16 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C153E750D0; Thu, 15 Nov 2018 12:44:15 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-130.rdu2.redhat.com [10.10.120.130]) by smtp.corp.redhat.com (Postfix) with ESMTP id E2DE7604A1; Thu, 15 Nov 2018 12:44:14 +0000 (UTC) To: Ard Biesheuvel Cc: Leif Lindholm , "edk2-devel@lists.01.org" References: <20181114192724.27068-1-ard.biesheuvel@linaro.org> <20181114200036.o5nv5qnkwlmbkwxu@bivouac.eciton.net> From: Laszlo Ersek Message-ID: <3b59c20c-c24d-9ca3-be42-0540bec25c3c@redhat.com> Date: Thu, 15 Nov 2018 13:44:13 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Thu, 15 Nov 2018 12:44:15 +0000 (UTC) Subject: Re: [PATCH] ArmPkg/ArmGicDxe ARM: fix encoding for GICv3 interrupt acknowledge X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Nov 2018 12:44:16 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 11/15/18 13:37, Ard Biesheuvel wrote: > On Wed, 14 Nov 2018 at 14:11, Laszlo Ersek wrote: >> >> On 11/14/18 21:00, Leif Lindholm wrote: >>> On Wed, Nov 14, 2018 at 11:27:24AM -0800, Ard Biesheuvel wrote: >>>> Fix a typo in the 32-bit ARM version of the GICv3 driver, which uses >>>> the wrong system register encoding to access ICC_IAR1, and attempted >>>> to access ICC_IAR0 instead. This results in boot time hangs both >>>> under QEMU emulation and on real hardware. >>>> >>>> Contributed-under: TianoCore Contribution Agreement 1.1 >>>> Signed-off-by: Ard Biesheuvel >>> >>> Reviewed-by: Leif Lindholm >>> >>> I would say given how long we've gone without finding this, >> >> Right, that makes me curious -- what has changed now? What exposed this bug? >> > > I was regression testing a EFI workaround I put in the kernel for > GICv3, which was apparently the first time anyone tried running > EDK2/ARM on a GICv3 system (which is one of the reasons I wanted to > get you one of the Socionext SynQuacer boards: it has a GICv3 with > GICv2 compatibility and support for 32-bit guests, but sadly, we still > don't have any with fixed silicon) > Thanks! Laszlo