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Thu, 1 Sep 2022 15:43:12 +0000 Message-ID: <3be210d1-6e81-106e-6551-70d138c97aa6@arm.com> Date: Thu, 1 Sep 2022 16:43:11 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH v2 1/2] CloudHv/arm: add PeiMemInfoLib To: Jianyong Wu , devel@edk2.groups.io CC: ardb+tianocore@kernel.org, justin.he@arm.com, "nd@arm.com" References: <20220819080911.188127-1-jianyong.wu@arm.com> <20220819080911.188127-2-jianyong.wu@arm.com> From: "Sami Mujawar" In-Reply-To: <20220819080911.188127-2-jianyong.wu@arm.com> X-ClientProxiedBy: LO4P123CA0256.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:194::9) To AS8PR08MB6806.eurprd08.prod.outlook.com (2603:10a6:20b:39b::12) MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 2891712b-96a4-4046-94da-08da8c30b317 X-MS-TrafficTypeDiagnostic: AM7PR08MB5526:EE_|VE1EUR03FT063:EE_|DU0PR08MB7637:EE_ x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2022 15:43:21.5770 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2891712b-96a4-4046-94da-08da8c30b317 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT063.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB7637 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Hi Jianyong, Thank you for the updated patch. I have one comment marked inline as [SAMI]. Other than that this patch=20 looks good to me. With that fixed. Reviewed-by: Sami Mujawar Regards, Sami Mujawar On 19/08/2022 09:09 am, Jianyong Wu wrote: > Memory layout in CLoud Hypervisor for arm is changed and is different > with Qemu, thus we should build its own PeiMemInfoLib. > The main change in the memory layout is that normal ram may not contiguou= s > under 4G. The top 64M under 4G is reserved for 32bit device. > > What this patch does: > 1. get all of the memory node from DT; > 2. Add all of the memory nodes to Hob; > 3. Init page table for each memory node; > > Signed-off-by: Jianyong Wu > --- > .../CloudHvVirtMemInfoLib.c | 230 ++++++++++++++++++ > .../CloudHvVirtMemInfoLib.h | 42 ++++ > .../CloudHvVirtMemInfoPeiLib.inf | 46 ++++ > 3 files changed, 318 insertions(+) > create mode 100644 ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirt= MemInfoLib.c > create mode 100644 ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirt= MemInfoLib.h > create mode 100644 ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirt= MemInfoPeiLib.inf > > diff --git a/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoL= ib.c b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoLib.c > new file mode 100644 > index 0000000000..d9c434754e > --- /dev/null > +++ b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoLib.c > @@ -0,0 +1,230 @@ > +/** @file > + > + Copyright (c) 2022, Arm Limited. All rights reserved. > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include "CloudHvVirtMemInfoLib.h" > + > +CLOUDHV_MEM_NODE_INFO CloudHvMemNode[CLOUDHV_MAX_MEM_NODE_NUM]; > + > +RETURN_STATUS > +EFIAPI > +CloudHvVirtMemInfoPeiLibConstructor ( > + VOID > + ) > +{ > + VOID *DeviceTreeBase; > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > + INT32 Node, Prev; > + UINT64 FirMemNodeBase, FirMemNodeSize; > + UINT64 CurBase, MemBase; > + UINT64 CurSize; > + CONST CHAR8 *Type; > + INT32 Len; > + CONST UINT64 *RegProp; > + RETURN_STATUS PcdStatus; > + UINT8 Index; > + > + ZeroMem (CloudHvMemNode, sizeof(CloudHvMemNode)); > + > + FirMemNodeBase =3D 0; > + FirMemNodeSize =3D 0; > + Index =3D 0; > + MemBase =3D FixedPcdGet64 (PcdSystemMemoryBase); > + ResourceAttributes =3D ( > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED > + ); > + DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeInitialBaseAd= dress); > + if (DeviceTreeBase =3D=3D NULL) { > + return EFI_NOT_FOUND; > + } > + > + // > + // Make sure we have a valid device tree blob > + // > + if (fdt_check_header (DeviceTreeBase) !=3D 0) { > + return EFI_NOT_FOUND; > + } > + > + // > + // Look for the lowest memory node > + // > + for (Prev =3D 0; ; Prev =3D Node) { > + Node =3D fdt_next_node (DeviceTreeBase, Prev, NULL); > + if (Node < 0) { > + break; > + } > + > + // > + // Check for memory node > + // > + Type =3D fdt_getprop (DeviceTreeBase, Node, "device_type", &Len); > + if (Type && (AsciiStrnCmp (Type, "memory", Len) =3D=3D 0)) { [SAMI] Apologies I missed this in my earlier review. The above check=20 should be =C2=A0+ if ((Type !=3D0) && (AsciiStrnCmp (Type, "memory", Len) =3D=3D 0))= { as Type is not boolean. [/SAMI] > + // > + // Get the 'reg' property of this node. For now, we will assume > + // two 8 byte quantities for base and size, respectively. > + // > + RegProp =3D fdt_getprop (DeviceTreeBase, Node, "reg", &Len); > + if ((RegProp !=3D 0) && (Len =3D=3D (2 * sizeof (UINT64)))) { > + CurBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); > + CurSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); > + > + DEBUG (( > + DEBUG_INFO, > + "%a: System RAM @ 0x%lx - 0x%lx\n", > + __FUNCTION__, > + CurBase, > + CurBase + CurSize - 1 > + )); > + > + // We should build Hob seperately for the memory node except the= first one > + if (CurBase !=3D MemBase) { > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + CurBase, > + CurSize > + ); > + } else { > + FirMemNodeBase =3D CurBase; > + FirMemNodeSize =3D CurSize; > + } > + > + CloudHvMemNode[Index].Base =3D CurBase; > + CloudHvMemNode[Index].Size =3D CurSize; > + Index++; > + > + if (Index >=3D CLOUDHV_MAX_MEM_NODE_NUM) { > + DEBUG (( > + DEBUG_WARN, > + "%a: memory node larger than %d will not be included into Me= mory System\n", > + __FUNCTION__, > + CLOUDHV_MAX_MEM_NODE_NUM > + )); > + break; > + } > + } else { > + DEBUG (( > + DEBUG_ERROR, > + "%a: Failed to parse FDT memory node\n", > + __FUNCTION__ > + )); > + } > + } > + } > + > + // > + // Make sure the start of DRAM matches our expectation > + // > + if (FixedPcdGet64 (PcdSystemMemoryBase) !=3D FirMemNodeBase) { > + return EFI_NOT_FOUND; > + } > + PcdStatus =3D PcdSet64S (PcdSystemMemorySize, FirMemNodeSize); > + ASSERT_RETURN_ERROR (PcdStatus); > + ASSERT ( > + (((UINT64)PcdGet64 (PcdFdBaseAddress) + > + (UINT64)PcdGet32 (PcdFdSize)) <=3D FirMemNodeBase) || > + ((UINT64)PcdGet64 (PcdFdBaseAddress) >=3D (FirMemNodeBase + FirMemNo= deSize)) > + ); > + > + return RETURN_SUCCESS; > +} > + > +/** > + Return the Virtual Memory Map of your platform > + > + This Virtual Memory Map is used by MemoryInitPei Module to initialize = the MMU > + on your platform. > + > + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTO= R > + describing a Physical-to-Virtual Mem= ory > + mapping. This array must be ended by= a > + zero-filled entry. The allocated mem= ory > + will not be freed. > + > +**/ > +VOID > +ArmVirtGetMemoryMap ( > + OUT ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap > + ) > +{ > + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > + UINT8 Index =3D 0, MemNodeIndex =3D 0; > + > + ASSERT (VirtualMemoryMap !=3D NULL); > + > + VirtualMemoryTable =3D AllocatePool ( > + sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * > + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS > + ); > + > + if (VirtualMemoryTable =3D=3D NULL) { > + DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTIO= N__)); > + return; > + } > + // System DRAM > + while ((MemNodeIndex < CLOUDHV_MAX_MEM_NODE_NUM) && (CloudHvMemNode[Me= mNodeIndex].Size !=3D 0)) { > + VirtualMemoryTable[Index].PhysicalBase =3D CloudHvMemNode[MemNodeInd= ex].Base; > + VirtualMemoryTable[Index].VirtualBase =3D CloudHvMemNode[MemNodeInd= ex].Base; > + VirtualMemoryTable[Index].Length =3D CloudHvMemNode[MemNodeInd= ex].Size; > + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBU= TE_WRITE_BACK; > + > + DEBUG (( > + DEBUG_INFO, > + "%a: Dumping System DRAM Memory Node%d Map:\n" > + "\tPhysicalBase: 0x%lX\n" > + "\tVirtualBase: 0x%lX\n" > + "\tLength: 0x%lX\n", > + __FUNCTION__, > + MemNodeIndex, > + VirtualMemoryTable[Index].PhysicalBase, > + VirtualMemoryTable[Index].VirtualBase, > + VirtualMemoryTable[Index].Length > + )); > + Index++; > + MemNodeIndex++; > + } > + // Memory mapped peripherals (UART, RTC, GIC, virtio-mmio, etc) > + VirtualMemoryTable[Index].PhysicalBase =3D MACH_VIRT_PERIPH_BASE; > + VirtualMemoryTable[Index].VirtualBase =3D MACH_VIRT_PERIPH_BASE; > + VirtualMemoryTable[Index].Length =3D MACH_VIRT_PERIPH_SIZE; > + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; > + Index++; > + > + // Map the FV region as normal executable memory > + VirtualMemoryTable[Index].PhysicalBase =3D PcdGet64 (PcdFvBaseAddress)= ; > + VirtualMemoryTable[Index].VirtualBase =3D VirtualMemoryTable[Index].P= hysicalBase; > + VirtualMemoryTable[Index].Length =3D FixedPcdGet32 (PcdFvSize); > + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _WRITE_BACK; > + Index++; > + > + // Memory mapped for 32bit device (like TPM) > + VirtualMemoryTable[Index].PhysicalBase =3D TOP_32BIT_DEVICE_BASE; > + VirtualMemoryTable[Index].VirtualBase =3D TOP_32BIT_DEVICE_BASE; > + VirtualMemoryTable[Index].Length =3D TOP_32BIT_DEVICE_SIZE; > + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE= _DEVICE; > + Index++; > + > + // End of Table > + ZeroMem (&VirtualMemoryTable[Index], sizeof (ARM_MEMORY_REGION_DESCRIP= TOR)); > + > + *VirtualMemoryMap =3D VirtualMemoryTable; > +} > diff --git a/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoL= ib.h b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoLib.h > new file mode 100644 > index 0000000000..e624373472 > --- /dev/null > +++ b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoLib.h > @@ -0,0 +1,42 @@ > +/** @file > + > + Copyright (c) 2022, Arm Limited. All rights reserved. > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _CLOUDHV_VIRT_MEM_INFO_LIB_H_ > +#define _CLOUDHV_VIRT_MEM_INFO_LIB_H_ > + > +// > +// Cloud Hypervisor may have more than one memory nodes. Even there is n= o limit for that, > +// I think 10 is enough in general. > +// > +#define CLOUDHV_MAX_MEM_NODE_NUM 10 > + > +// Record memory node info (base address and size) > +typedef struct { > + UINT64 Base; > + UINT64 Size; > +} CLOUDHV_MEM_NODE_INFO; > + > +// Number of Virtual Memory Map Descriptors > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (4 + CLOUDHV_MAX_MEM_NODE_NU= M) > + > +// > +// Core peripherals such as the UART, the GIC and the RTC are > +// all mapped in the 'miscellaneous device I/O' region, which we just ma= p > +// in its entirety rather than device by device. Note that it does not > +// cover any of the NOR flash banks or PCI resource windows. > +// > +#define MACH_VIRT_PERIPH_BASE 0x00400000 > +#define MACH_VIRT_PERIPH_SIZE 0x0FC00000 > + > +// > +// The top of the 64M memory region under 4GB reserved for device > +// > +#define TOP_32BIT_DEVICE_BASE 0xFC000000 > +#define TOP_32BIT_DEVICE_SIZE 0x04000000 > + > +#endif // _CLOUDHV_VIRT_MEM_INFO_LIB_H_ > diff --git a/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoP= eiLib.inf b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiL= ib.inf > new file mode 100644 > index 0000000000..30626776ae > --- /dev/null > +++ b/ArmVirtPkg/Library/CloudHvVirtMemInfoLib/CloudHvVirtMemInfoPeiLib.i= nf > @@ -0,0 +1,46 @@ > +/** @file > + > + Copyright (c) 2022, Arm Limited. All rights reserved. > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +[Defines] > + INF_VERSION =3D 0x0001001B > + BASE_NAME =3D CloudHvVirtMemInfoPeiLib > + FILE_GUID =3D c7ada233-d35b-49c3-aa51-e2b5cd80c91= 0 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D ArmVirtMemInfoLib|PEIM > + CONSTRUCTOR =3D CloudHvVirtMemInfoPeiLibConstructor > + > +[Sources] > + CloudHvVirtMemInfoLib.c > + CloudHvVirtMemInfoLib.h > + > +[Packages] > + ArmPkg/ArmPkg.dec > + ArmVirtPkg/ArmVirtPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + > +[LibraryClasses] > + ArmLib > + BaseMemoryLib > + DebugLib > + FdtLib > + MemoryAllocationLib > + PcdLib > + > +[Pcd] > + gArmTokenSpaceGuid.PcdFdBaseAddress > + gArmTokenSpaceGuid.PcdFvBaseAddress > + gArmTokenSpaceGuid.PcdSystemMemoryBase > + gArmTokenSpaceGuid.PcdSystemMemorySize > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdFdSize > + gArmTokenSpaceGuid.PcdFvSize > + gArmVirtTokenSpaceGuid.PcdDeviceTreeInitialBaseAddress