From: "Laszlo Ersek" <lersek@redhat.com>
To: devel@edk2.groups.io, ray.ni@intel.com
Cc: "Dong, Eric" <eric.dong@intel.com>
Subject: Re: [edk2-devel] [PATCH 3/3] UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports
Date: Tue, 2 Jul 2019 17:20:12 +0200 [thread overview]
Message-ID: <3c51b8a8-7517-6377-51c8-9e33c0c2af2d@redhat.com> (raw)
In-Reply-To: <1a147a74-9986-1287-5334-5876eebe7682@redhat.com>
On 07/02/19 17:18, Laszlo Ersek wrote:
> On 07/02/19 16:44, Ni, Ray wrote:
>> Laszlo,
>> I agree with your changes.
>> Will include your changes in V2.
>
> Thanks, Ray -- currently waiting for suitable hardware (with 5-level
> paging support) to become available internally @RH for my testing.
>
> On host hardware that does not support 5-level paging, there seem to be
> no adverse effects.
>
> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Forgot to mention that this applies with the PatchInstructionX86()
update in place.
Thanks
Laszlo
next prev parent reply other threads:[~2019-07-02 15:20 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-28 6:46 [PATCH 0/3] Enable 5 level paging when CPU supports Ni, Ray
2019-06-28 6:46 ` [PATCH 1/3] UefiCpuPkg/PiSmmCpu: Change variable names and comments to follow SDM Ni, Ray
2019-06-28 6:46 ` [PATCH 2/3] MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging Ni, Ray
2019-06-28 6:47 ` [PATCH 3/3] UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports Ni, Ray
2019-06-28 7:18 ` [edk2-devel] " Yao, Jiewen
2019-06-28 7:27 ` Ni, Ray
2019-06-28 15:32 ` Laszlo Ersek
2019-06-28 15:36 ` Laszlo Ersek
2019-07-01 12:44 ` Laszlo Ersek
2019-07-02 14:44 ` Ni, Ray
2019-07-02 15:18 ` Laszlo Ersek
2019-07-02 15:20 ` Laszlo Ersek [this message]
2019-07-03 10:08 ` Laszlo Ersek
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