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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C X-Received: from SATLEXMB03.amd.com (165.204.84.17) by SA2PEPF00001505.mail.protection.outlook.com (10.167.242.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7611.14 via Frontend Transport; Mon, 20 May 2024 09:44:41 +0000 X-Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 20 May 2024 04:44:40 -0500 X-Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Mon, 20 May 2024 04:44:39 -0500 From: "Abdul Lateef Attar via groups.io" To: CC: Abdul Lateef Attar , Abner Chang , Paul Grimes Subject: [edk2-devel] [edk2-platforms PATCH v2 3/5] AmdMinBoardPkg: Implement BoardInitLib for PEI phase Date: Mon, 20 May 2024 15:14:27 +0530 Message-ID: <3c60c5e1d40d970698e72d06a83c1d786891f31f.1716197957.git.AbdulLateef.Attar@amd.com> In-Reply-To: References: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: AbdulLateef.Attar@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001505:EE_|MN2PR12MB4240:EE_ X-MS-Office365-Filtering-Correlation-Id: d61fa550-83ab-4527-93a3-08dc78b178c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?hGNH9iSVeut19mXKtERBCYR7S90I/pErCB0WfS2j0f5EDbcAdMIwnn69xiQK?= =?us-ascii?Q?xv0+uxF7eM2MQtLmpr1Qd3USLerBvHbVggFNoEpmo5PT7AUGiQs2qZABCyXR?= =?us-ascii?Q?74vmUVeggQzZglLDmwzg0p7c3zv49zxMUnCnbK++nXw2bIAUQY35LBP8Qkac?= =?us-ascii?Q?vzMe9yMcUXSmUtYaeZnN9BG+9+X9SYjbH2L8inqE/+YcOjC6CJv/+FFBPhIs?= =?us-ascii?Q?VeY9X+uPAT+VdWdQC/uz+FZ3nz63uuJjQsj8tRMOUFCyKE4JT1x4lh2mSDnL?= =?us-ascii?Q?Bkvx3DfnKKELKGyVEv9rhQPfej19GxiDCLPX5YQ4qn/+VldEWTirQ9rlYp+A?= =?us-ascii?Q?b1q7XU3XWYZWj+ZcMHANvyVvnJZyI4bNclyt/BDXeml0UMyi3X536AHKYvjc?= =?us-ascii?Q?xhVMeOUDI8ymhM5I+P7HcFs3V59ehzvC25UnGjU5yF8cbBKSqj+QASh9rbaq?= =?us-ascii?Q?6WHySvhwoKUORmZ3cM1yvz7Z9KT0pWWhzhjD/4wZ2OD1eXbUO3fpdVgHs8dZ?= =?us-ascii?Q?n0ouP/oQsQWLV0tMZFAlA8ZVmhhqHhrhPjIfBOSHEBMKvFBV09NyuZp5CvGR?= =?us-ascii?Q?PP0Pvcj1U7PNGdWmoj/P3rRpetAKJCp6R6ujFHc1qDPqXGOC0fII50hQiEY3?= =?us-ascii?Q?A3I5dslUBXPzme2Khjc7IUD7RIytsVCqAtgVgOK7CzUdBppdztJZXFzYAzIO?= =?us-ascii?Q?O3h+39ZhhJGVfP1ikDvYZL2Exp4gqOKTe7tga8FJGn9vWf4tSGGucmS/WDMi?= =?us-ascii?Q?H1BzOVHFjPh8bPJvgpod5iz4C1nxLcMO7D7L8xvtn1YRgFJ6fBVNZbOlujFJ?= =?us-ascii?Q?Q03FggmczWDz78uw/nQ34z08YG1wJZaB3zKVwxPiuF3KXJchGlQhoTzQWGPP?= =?us-ascii?Q?HKEpgO16PCWTLA5IyXSvf4mB8YNCeF7LkaRj5f3wH2+imBwUeF03bf1g1Gaz?= =?us-ascii?Q?kr4Mchq2CgIzH+FLvJmL5mfoROOzrrf79LnfTGSdyt+Vmkuz5hcbOPFxNQqk?= =?us-ascii?Q?r585GzRKP5FH9glF1fRPg1VZd1TDMnyVXIbMIcM4uKtRuBuRJkxicBeA0aIT?= =?us-ascii?Q?tMn02jseGYQDj0+05bpmDlLC10Vm8rUhwSDJq1yjqwxdrpRYeasV6gP92FYO?= =?us-ascii?Q?sw/VKRnX1WeD5QlX+0oJgyEPq8UeZOkF1goY+k1J8zuo+iSdbaaK7BkqTtsv?= =?us-ascii?Q?ep5RIhD7AVkBOzgRUjDV6xZ3Jw7WRgf3l2fY3aw4CVZQGKwk5UamTRmeN45w?= =?us-ascii?Q?vRJ0VVCMp3s8znSMY7sVRo190mKG96eiSRd2FSPQUX94pFrR8UmFYJ7ImphX?= =?us-ascii?Q?SKqvb/85uDWQIAIsjvg+AkJqJrV8oxYPB5QW9ZxDAVcuR+xItlLH79ow+B2z?= =?us-ascii?Q?AzP7s6Q=3D?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2024 09:44:41.0123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d61fa550-83ab-4527-93a3-08dc78b178c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001505.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4240 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Mon, 20 May 2024 02:44:46 -0700 Resent-From: AbdulLateef.Attar@amd.com Reply-To: devel@edk2.groups.io,AbdulLateef.Attar@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: w58gawzFBaehSn2JFQT5jcHCx7686176AA= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=kJNyyj5L; dmarc=pass (policy=none) header.from=groups.io; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io PeiBoardInitPreMemLib library provides board-specific initialization functions for the PEI phase. Cc: Abner Chang Cc: Paul Grimes Signed-off-by: Abdul Lateef Attar --- .../AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec | 8 + .../AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc | 5 + .../PeiBoardInitPreMemLib/AmdMemoryInfoHob.h | 50 ++++ .../PeiBoardInitPreMemLib.c | 229 ++++++++++++++++++ .../PeiBoardInitPreMemLib.inf | 45 ++++ .../PeiBoardInitPreMemLib/PeiMemoryInit.c | 198 +++++++++++++++ .../PeiBoardInitPreMemLib/PeiMemoryInit.h | 50 ++++ 7 files changed, 585 insertions(+) create mode 100644 Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemL= ib/AmdMemoryInfoHob.h create mode 100644 Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemL= ib/PeiBoardInitPreMemLib.c create mode 100644 Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemL= ib/PeiBoardInitPreMemLib.inf create mode 100644 Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemL= ib/PeiMemoryInit.c create mode 100644 Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemL= ib/PeiMemoryInit.h diff --git a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec b/Platform/AMD/= AmdMinBoardPkg/AmdMinBoardPkg.dec index 03d1d77c34..98768af210 100644 --- a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec +++ b/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dec @@ -19,6 +19,10 @@ =20 [Guids] gAmdMinBoardPkgTokenSpaceGuid =3D {0xd4d23d79, 0x73bf, 0x460a, {0xa1, 0= xc7, 0x85, 0xa3, 0xca, 0x71, 0xb9, 0x4c}} + gAmdMemoryInfoHobGuid =3D { 0x1bce3d14, 0xa5fe, 0x4a0b, { 0x9a,= 0x8d, 0x69, 0xca, 0x5d, 0x98, 0x38, 0xd3}} + +[Ppis] + gAmdMemoryInfoHobPpiGuid =3D { 0xba16e587, 0x1d66, 0x41b7, { 0x9b,= 0x52, 0xca, 0x4f, 0x2c, 0xad, 0x0d, 0xc8}} =20 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] # @@ -41,3 +45,7 @@ gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize |0x00= 000000|UINT32|0x10000008 gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset |0x00= 000000|UINT32|0x10000009 =20 + # SMRAM size + # Holds the SMRAM area size, which is reserved for SMRAM operation + # default value 128MB + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdSmramAreaSize |0x08= 000000|UINT64|0x20000100 diff --git a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc b/Platform/AMD/= AmdMinBoardPkg/AmdMinBoardPkg.dsc index be33089a45..7e356a2a67 100644 --- a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc +++ b/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc @@ -22,6 +22,9 @@ MinPlatformPkg/MinPlatformPkg.dec UefiCpuPkg/UefiCpuPkg.dec =20 +[PcdsDynamicDefault] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x10000000 + [LibraryClasses] SpcrDeviceLib|AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf ReportFvLib|AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf @@ -38,6 +41,7 @@ =20 [LibraryClasses.common.PEIM] SetCacheMtrrLib|AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.i= nf + BoardInitLib|AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPr= eMemLib.inf =20 [Components] AmdMinBoardPkg/Library/SpcrDeviceLib/SpcrDeviceLib.inf @@ -45,6 +49,7 @@ [Components.IA32] AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf AmdMinBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf + AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardInitPreMemLib.inf =20 [Components.X64] AmdMinBoardPkg/PciHotPlug/PciHotPlugInit.inf diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/AmdM= emoryInfoHob.h b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/= AmdMemoryInfoHob.h new file mode 100644 index 0000000000..b596b3bdf3 --- /dev/null +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/AmdMemoryIn= foHob.h @@ -0,0 +1,50 @@ +/** @file + Defines AMD memory info hob. + + Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserv= ed. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef AMD_MEMORY_INFO_HOB_H_ +#define AMD_MEMORY_INFO_HOB_H_ + +#pragma pack (push, 1) + +/// Memory descriptor structure for each memory range +typedef struct { + UINT64 Base; ///< Base address of memory ra= ng + UINT64 Size; ///< Size of memory rang + UINT32 Attribute; ///< Attribute of memory rang + UINT32 Reserved; ///< For alignment purpose +} AMD_MEMORY_RANGE_DESCRIPTOR; + +/// Memory info HOB structure +typedef struct { + UINT32 Version; ///< Version of HO= B structure + BOOLEAN Reserved1; + UINT16 Reserved2; + BOOLEAN Reserved3; + UINT8 Reserved4; + BOOLEAN Reserved5; + UINT32 Reserved6; + UINT32 Reserved7; + UINT32 NumberOfDescriptor; ///< Number of mem= ory range descriptor + AMD_MEMORY_RANGE_DESCRIPTOR Ranges[1]; ///< Memory ranges= array +} AMD_MEMORY_INFO_HOB; + +#pragma pack (pop) + +/// Memory attribute in the memory range descriptor =3D AVAILABLE +#define AMD_MEMORY_ATTRIBUTE_AVAILABLE 0x1 + +/// Memory attribute in the memory range descriptor =3D UMA +#define AMD_MEMORY_ATTRIBUTE_UMA 0x2 + +/// Memory attribute in the memory range descriptor =3D MMIO +#define AMD_MEMORY_ATTRIBUTE_MMIO 0x3 + +/// Memory attribute in the memory range descriptor =3D RESERVED +#define AMD_MEMORY_ATTRIBUTE_RESERVED 0x4 + +#endif diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiB= oardInitPreMemLib.c b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMe= mLib/PeiBoardInitPreMemLib.c new file mode 100644 index 0000000000..01e73efa12 --- /dev/null +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardIni= tPreMemLib.c @@ -0,0 +1,229 @@ +/** @file + BoardInitLib library implementation for pre-mem PEI phase. + +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include "PeiMemoryInit.h" + +EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_DISPATCH | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gAmdMemoryInfoHobPpiGuid, + EndofAmdMemoryInfoHobPpiGuidCallBack +}; + +/** + Get Pcie base address from MSR and set PcdPciExpressBaseSize + + @retval EFI_SUCCESS PcdPciExpressBaseSize value set successfully. +**/ +EFI_STATUS +EFIAPI +SetPcieBaseSize ( + VOID + ) +{ + EFI_STATUS Status; + UINT64 PcieBaseSize; + UINT8 BusRange; + + Status =3D EFI_SUCCESS; + + // Gather the value of PcdPciExpressBaseSize from MSR + BusRange =3D RShiftU64 (AsmReadMsr64 (0xC0010058), 2) & 0xF; + PcieBaseSize =3D MultU64x64 (LShiftU64 (1, BusRange), SIZE_1MB); + PcdSet64S (PcdPciExpressBaseSize, (UINT64)PcieBaseSize); + return Status; +} + +/** + This board service detects the board type. + + @retval EFI_SUCCESS The board was detected successfully. + @retval EFI_NOT_FOUND The board could not be detected. +**/ +EFI_STATUS +EFIAPI +BoardDetect ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + This board service initializes board-specific debug devices. + + @retval EFI_SUCCESS Board-specific debug initialization was successful= . + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardDebugInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + This board service detects the boot mode. + + @retval EFI_BOOT_MODE The boot mode. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_BOOT_MODE +EFIAPI +BoardBootModeDetect ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + A hook for board-specific initialization prior to memory initialization. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitBeforeMemoryInit ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D PeiServicesNotifyPpi (&mNotifyList); + ASSERT_EFI_ERROR (Status); + Status =3D SetPcieBaseSize (); + ASSERT_EFI_ERROR (Status); + return (Status); +} + +/** + A hook for board-specific initialization after memory initialization. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitAfterMemoryInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + A hook for board-specific initialization prior to disabling temporary RA= M. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitBeforeTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + A hook for board-specific initialization after disabling temporary RAM. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitAfterTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + A hook for board-specific initialization prior to silicon initialization= . + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitBeforeSiliconInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + A hook for board-specific initialization after silicon initialization. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitAfterSiliconInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + A hook for board-specific initialization after PCI enumeration. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitAfterPciEnumeration ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + A hook for board-specific functionality for the ReadyToBoot event. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitReadyToBoot ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + A hook for board-specific functionality for the ExitBootServices event. + + @retval EFI_SUCCESS The board initialization was successful. + @retval EFI_NOT_READY The board has not been detected yet. +**/ +EFI_STATUS +EFIAPI +BoardInitEndOfFirmware ( + VOID + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiB= oardInitPreMemLib.inf b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPre= MemLib/PeiBoardInitPreMemLib.inf new file mode 100644 index 0000000000..5bc19e6834 --- /dev/null +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiBoardIni= tPreMemLib.inf @@ -0,0 +1,45 @@ +## @file +# Board Init Library for AMD Platforms. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D PeiBoardInitPreMemLib + FILE_GUID =3D A394D6BE-4433-4564-8FEB-2C90DD9ECE5B + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + HobLib + PcdLib + +[Packages] + AmdMinBoardPkg/AmdMinBoardPkg.dec + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[Sources] + AmdMemoryInfoHob.h + PeiMemoryInit.h + PeiBoardInitPreMemLib.c + PeiMemoryInit.c + +[Guids] + gAmdMemoryInfoHobGuid + gEfiSmmSmramMemoryGuid + +[Ppis] + gAmdMemoryInfoHobPpiGuid ## CON= SUMES + gPeiPlatformMemorySizePpiGuid ## CON= SUMES + +[Pcd] + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdSmramAreaSize + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CON= SUMES diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiM= emoryInit.c b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/Pei= MemoryInit.c new file mode 100644 index 0000000000..03f08214e2 --- /dev/null +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiMemoryIn= it.c @@ -0,0 +1,198 @@ +/** @file + +Copyright (C) 2023 - 2024 Advanced Micro Devices, Inc. All rights reserved +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiMemoryInit.h" +#include "AmdMemoryInfoHob.h" + +/** + A Callback routine only AmdMemoryInfoHob is ready. + + @param[in] PeiServices General purpose services available to ever= y PEIM. + @param[in] NotifyDescriptor The descriptor for the notification event. + @param[in] Ppi The context of the notification. + + @retval EFI_SUCCESS Platform Pre Memory initialization is successful. + EFI_STATUS Various failure from underlying routine calls. +**/ +EFI_STATUS +EFIAPI +EndofAmdMemoryInfoHobPpiGuidCallBack ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + PEI_PLATFORM_MEMORY_SIZE_PPI *PlatformMemorySizePpi; + EFI_STATUS Status; + UINT64 MemorySize; + AMD_MEMORY_INFO_HOB *AmdMemoryInfoHob; + AMD_MEMORY_RANGE_DESCRIPTOR *AmdMemoryInfoRange; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PEI_HOB_POINTERS Hob; + UINTN Index; + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; + EFI_PHYSICAL_ADDRESS SmramBaseAddress; + UINT8 SmramRanges; + UINTN DataSize; + + SmramBaseAddress =3D 0; + SmramRanges =3D 0; + + // Locate AMD_MEMORY_INFO_HOB Guided HOB and retrieve data + AmdMemoryInfoHob =3D NULL; + GuidHob =3D GetFirstGuidHob (&gAmdMemoryInfoHobGuid); + if (GuidHob !=3D NULL) { + AmdMemoryInfoHob =3D GET_GUID_HOB_DATA (GuidHob); + } + + if (AmdMemoryInfoHob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Error: Could not locate AMD_MEMORY_INFO_HOB.\n")= ); + return EFI_OUT_OF_RESOURCES; + } + + DEBUG ((DEBUG_INFO, "AMD_MEMORY_INFO_HOB at 0x%X\n", AmdMemoryInfoHob)); + DEBUG ((DEBUG_INFO, " Version: 0x%X\n", AmdMemoryInfoHob->Version)); + DEBUG ((DEBUG_INFO, " NumberOfDescriptor: 0x%X\n", AmdMemoryInfoHob->Nu= mberOfDescriptor)); + + // + // Build Descriptors + // + DEBUG ((DEBUG_INFO, "\nAMD HOB Descriptors:")); + for (Index =3D 0; Index < AmdMemoryInfoHob->NumberOfDescriptor; Index++)= { + AmdMemoryInfoRange =3D (AMD_MEMORY_RANGE_DESCRIPTOR *)&(AmdMemoryInfoH= ob->Ranges[Index]); + + DEBUG ((DEBUG_INFO, "\n Index: %d\n", Index)); + DEBUG ((DEBUG_INFO, " Base: 0x%lX\n", AmdMemoryInfoRange->Base)); + DEBUG ((DEBUG_INFO, " Size: 0x%lX\n", AmdMemoryInfoRange->Size)); + DEBUG ((DEBUG_INFO, " Attribute: 0x%X\n", AmdMemoryInfoRange->Attrib= ute)); + + switch (AmdMemoryInfoRange->Attribute) { + case AMD_MEMORY_ATTRIBUTE_AVAILABLE: + if (AmdMemoryInfoRange->Base < SIZE_4GB) { + SmramRanges =3D 1u; + // Set SMRAM base at heighest range below 4GB + SmramBaseAddress =3D AmdMemoryInfoRange->Base + AmdMemoryInfoRan= ge->Size - FixedPcdGet32 (PcdAmdSmramAreaSize); + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + (EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | EFI_RESOURCE_AT= TRIBUTE_UNCACHEABLE), + SmramBaseAddress, + FixedPcdGet32 (PcdAmdSmramAreaSize) + ); + DEBUG (( + DEBUG_INFO, + "SMRAM RESERVED_MEMORY: Base =3D 0x%lX, Size =3D 0x%lX\n", + SmramBaseAddress, + FixedPcdGet32 (PcdAmdSmramAreaSize) + )); + + AmdMemoryInfoRange->Size -=3D FixedPcdGet32 (PcdAmdSmramAreaSize= ); + } + + if (AmdMemoryInfoRange->Size) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + SYSTEM_MEMORY_ATTRIBUTES, + AmdMemoryInfoRange->Base, + AmdMemoryInfoRange->Size + ); + + DEBUG (( + DEBUG_INFO, + "SYSTEM_MEMORY: Base =3D 0x%lX, Size =3D 0x%lX\n", + AmdMemoryInfoRange->Base, + AmdMemoryInfoRange->Size + )); + } + + break; + + case AMD_MEMORY_ATTRIBUTE_MMIO: + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + MEMORY_MAPPED_IO_ATTRIBUTES, + AmdMemoryInfoRange->Base, + AmdMemoryInfoRange->Size + ); + + DEBUG (( + DEBUG_INFO, + "MMIO: Base =3D 0x%lX, Size =3D 0x%lX\n", + AmdMemoryInfoRange->Base, + AmdMemoryInfoRange->Size + )); + break; + + case AMD_MEMORY_ATTRIBUTE_RESERVED: + case AMD_MEMORY_ATTRIBUTE_UMA: + default: + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + 0, + AmdMemoryInfoRange->Base, + AmdMemoryInfoRange->Size + ); + + DEBUG (( + DEBUG_INFO, + "RESERVED_MEMORY: Base =3D 0x%lX, Size =3D 0x%lX\n", + AmdMemoryInfoRange->Base, + AmdMemoryInfoRange->Size + )); + break; + } + } + + ASSERT (SmramRanges > 0); + DataSize =3D sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK); + DataSize +=3D ((SmramRanges - 1) * sizeof (EFI_SMRAM_DESCRIPTOR)); + + Hob.Raw =3D BuildGuidHob ( + &gEfiSmmSmramMemoryGuid, + DataSize + ); + ASSERT (Hob.Raw); + + SmramHobDescriptorBlock =3D (EFI_SMRAM_HOB_= DESCRIPTOR_BLOCK *)(Hob.Raw); + SmramHobDescriptorBlock->NumberOfSmmReservedRegions =3D SmramRanges; + SmramHobDescriptorBlock->Descriptor[0].PhysicalStart =3D SmramBaseAddres= s; + SmramHobDescriptorBlock->Descriptor[0].CpuStart =3D SmramBaseAddres= s; + SmramHobDescriptorBlock->Descriptor[0].PhysicalSize =3D FixedPcdGet32 (= PcdAmdSmramAreaSize); + SmramHobDescriptorBlock->Descriptor[0].RegionState =3D EFI_SMRAM_CLOSE= D | EFI_CACHEABLE; + + Status =3D PeiServicesLocatePpi ( + &gPeiPlatformMemorySizePpiGuid, + 0, + NULL, + (VOID **)&PlatformMemorySizePpi + ); + ASSERT_EFI_ERROR (Status); + + Status =3D PlatformMemorySizePpi->GetPlatformMemorySize ( + PeiServices, + PlatformMemorySizePpi, + &MemorySize + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: Error(%r) in getting Platform Memory size.\n", + __func__, + Status + )); + return Status; + } + + DEBUG (( + DEBUG_INFO, + "Installing PeiMemory, BaseAddress =3D 0x%x, Size =3D 0x%x\n", + 0, + MemorySize + )); + Status =3D PeiServicesInstallPeiMemory (0, MemorySize); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiM= emoryInit.h b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/Pei= MemoryInit.h new file mode 100644 index 0000000000..726db25543 --- /dev/null +++ b/Platform/AMD/AmdMinBoardPkg/Library/PeiBoardInitPreMemLib/PeiMemoryIn= it.h @@ -0,0 +1,50 @@ +/** @file + This file contains definitions required for memory initialization in PEI= phase. + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef PEI_MEMORY_INIT_PEI_H_ +#define PEI_MEMORY_INIT_PEI_H_ + +#include +#include +#include +#include +#include +#include +#include + +#define SYSTEM_MEMORY_ATTRIBUTES ( \ + EFI_RESOURCE_ATTRIBUTE_PRESENT | \ + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \ + EFI_RESOURCE_ATTRIBUTE_TESTED | \ + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | \ + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | \ + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | \ + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE \ + ) + +#define MEMORY_MAPPED_IO_ATTRIBUTES ( \ + EFI_RESOURCE_ATTRIBUTE_PRESENT | \ + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \ + EFI_RESOURCE_ATTRIBUTE_TESTED | \ + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \ + ) + +/** + A Callback routine only AmdMemoryInfoHob is ready. + + @retval EFI_SUCCESS Platform Pre Memory initialization is successfull. + EFI_STATUS Various failure from underlying routine calls. +**/ +EFI_STATUS +EFIAPI +EndofAmdMemoryInfoHobPpiGuidCallBack ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +#endif // PEI_MEMORY_INIT_PEI_H_ --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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