* [PATCH 0/5] RPi4: Enable ACPI PCIe conduit
@ 2021-08-05 16:35 Jeremy Linton
2021-08-05 16:35 ` [PATCH 1/5] Platform/RaspberryPi: Add XHCI/PCI selection menu Jeremy Linton
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Jeremy Linton @ 2021-08-05 16:35 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton
A new Arm standard DEN0115A specifies how
platforms that don't have standard ECAM can
use the firmware to handle config read/write
operations. This is mostly implemented in TFA
but UEFI needs to assure that there is a
description of the root complex in the ACPI
namespace.
This set adds that description based on
a new menu item which toggles between XHCI
platform description and PCIe via a BDS
menu selection on the RPi4. The CM4 is really
the platform that needs this as it has a PCIe
slot. On that platform PCIe is enabled by default.
Jeremy Linton (5):
Platform/RaspberryPi: Add XHCI/PCI selection menu
Platform/RaspberryPi: break XHCI into its own SSDT
Platform/RaspberryPi: Add PCIe SSDT
Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
Platform/RaspberryPi: Enable NVMe boot on cm4
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 4 +
Platform/RaspberryPi/AcpiTables/Dsdt.asl | 3 -
Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++++++++
Platform/RaspberryPi/AcpiTables/Xhci.asl | 35 +--
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 56 +++++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 1 +
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 +
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 17 ++
Platform/RaspberryPi/Include/ConfigVars.h | 4 +
Platform/RaspberryPi/RPi3/RPi3.dsc | 6 +
Platform/RaspberryPi/RPi4/RPi4.dsc | 13 ++
Platform/RaspberryPi/RPi4/RPi4.fdf | 5 +
Platform/RaspberryPi/RaspberryPi.dec | 1 +
.../Bcm2711PciHostBridgeLibConstructor.c | 5 -
.../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 ++-
15 files changed, 388 insertions(+), 28 deletions(-)
create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl
--
2.13.7
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/5] Platform/RaspberryPi: Add XHCI/PCI selection menu
2021-08-05 16:35 [PATCH 0/5] RPi4: Enable ACPI PCIe conduit Jeremy Linton
@ 2021-08-05 16:35 ` Jeremy Linton
2021-08-05 16:35 ` [PATCH 2/5] Platform/RaspberryPi: break XHCI into its own SSDT Jeremy Linton
` (3 subsequent siblings)
4 siblings, 0 replies; 16+ messages in thread
From: Jeremy Linton @ 2021-08-05 16:35 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton
Arm has standardized a PCI SMC conduit that can be used
to access the PCI config space in a standardized way. This
functionality doesn't yet exist in many OS/Distro's. Lets
add another advanced config item that allows the user
to toggle between presenting the XHCI on the base RPi4
as a platform device, or presenting this newer PCIe
conduit. The CM4 doesn't have an attached XHCI controller
soldered to the PCIe, so we hide the menu and only allow
PCIe mode.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 42 ++++++++++++++++++++++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 1 +
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 +++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 17 +++++++++
Platform/RaspberryPi/Include/ConfigVars.h | 4 +++
Platform/RaspberryPi/RPi3/RPi3.dsc | 6 ++++
Platform/RaspberryPi/RPi4/RPi4.dsc | 8 +++++
Platform/RaspberryPi/RaspberryPi.dec | 1 +
8 files changed, 84 insertions(+)
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 9e78cb47ad..87f6b4e7bb 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -43,6 +43,7 @@ extern UINT8 ConfigDxeStrings[];
STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol;
STATIC UINT32 mModelFamily = 0;
STATIC UINT32 mModelInstalledMB = 0;
+STATIC UINT32 mModelRevision = 0;
STATIC EFI_MAC_ADDRESS mMacAddress;
@@ -271,6 +272,40 @@ SetupVariables (
ASSERT_EFI_ERROR (Status);
}
+ if (mModelFamily >= 4) {
+ if (((mModelRevision >> 4) & 0xFF) == 0x14) {
+ /*
+ * Enable PCIe by default on CM4
+ */
+ Status = PcdSet32S (PcdXhciPci, 2);
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ Size = sizeof (UINT32);
+ Status = gRT->GetVariable (L"XhciPci",
+ &gConfigDxeFormSetGuid,
+ NULL, &Size, &Var32);
+ if (EFI_ERROR (Status) || (Var32 == 0)) {
+ /*
+ * Enable XHCI by default
+ */
+ Status = PcdSet32S (PcdXhciPci, 0);
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ /*
+ * Enable PCIe
+ */
+ Status = PcdSet32S (PcdXhciPci, 1);
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ } else {
+ /*
+ * Disable PCIe and XHCI
+ */
+ Status = PcdSet32S (PcdXhciPci, 0);
+ ASSERT_EFI_ERROR (Status);
+ }
+
Size = sizeof (AssetTagVar);
Status = gRT->GetVariable (L"AssetTag",
&gConfigDxeFormSetGuid,
@@ -888,6 +923,13 @@ ConfigInitialize (
DEBUG ((DEBUG_INFO, "Current Raspberry Pi installed RAM size is %d MB\n", mModelInstalledMB));
}
+ Status = mFwProtocol->GetModelRevision (&mModelRevision);
+ if (Status != EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR, "Couldn't get the Raspberry Pi revision: %r\n", Status));
+ } else {
+ DEBUG ((DEBUG_INFO, "Current Raspberry Pi revision %x\n", mModelRevision));
+ }
+
Status = SetupVariables ();
if (Status != EFI_SUCCESS) {
DEBUG ((DEBUG_ERROR, "Couldn't not setup NV vars: %r\n", Status));
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
index 4bb2d08550..e6e22ad82e 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
@@ -94,6 +94,7 @@
gRaspberryPiTokenSpaceGuid.PcdFanOnGpio
gRaspberryPiTokenSpaceGuid.PcdFanTemp
gRaspberryPiTokenSpaceGuid.PcdUartInUse
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci
[Depex]
gPcdProtocolGuid AND gRaspberryPiFirmwareProtocolGuid
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
index 466fa852cb..5ec17072c3 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
@@ -57,6 +57,11 @@
#string STR_ADVANCED_FANTEMP_PROMPT #language en-US "ACPI fan temperature"
#string STR_ADVANCED_FANTEMP_HELP #language en-US "Cycle a fan at C"
+#string STR_ADVANCED_XHCIPCI_PROMPT #language en-US "ACPI XHCI/PCIe"
+#string STR_ADVANCED_XHCIPCI_HELP #language en-US "OS sees XHCI USB platform device or PCIe bridge"
+#string STR_ADVANCED_XHCIPCI_XHCI #language en-US "XHCI"
+#string STR_ADVANCED_XHCIPCI_PCIE #language en-US "PCIe"
+
#string STR_ADVANCED_ASSET_TAG_PROMPT #language en-US "Asset Tag"
#string STR_ADVANCED_ASSET_TAG_HELP #language en-US "Set the system Asset Tag"
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
index fa34eab809..18b3ec726e 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
@@ -56,6 +56,11 @@ formset
name = FanTemp,
guid = CONFIGDXE_FORM_SET_GUID;
+ efivarstore ADVANCED_XHCIPCI_VARSTORE_DATA,
+ attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ name = XhciPci,
+ guid = CONFIGDXE_FORM_SET_GUID;
+
efivarstore SYSTEM_TABLE_MODE_VARSTORE_DATA,
attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
name = SystemTableMode,
@@ -212,6 +217,18 @@ formset
default = 60,
endnumeric;
endif;
+
+ suppressif ideqval XhciPci.Value == 2;
+ grayoutif NOT ideqval SystemTableMode.Mode == SYSTEM_TABLE_MODE_ACPI;
+ oneof varid = XhciPci.Value,
+ prompt = STRING_TOKEN(STR_ADVANCED_XHCIPCI_PROMPT),
+ help = STRING_TOKEN(STR_ADVANCED_XHCIPCI_HELP),
+ flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED,
+ option text = STRING_TOKEN(STR_ADVANCED_XHCIPCI_XHCI), value = 0, flags = DEFAULT;
+ option text = STRING_TOKEN(STR_ADVANCED_XHCIPCI_PCIE), value = 1, flags = 0;
+ endoneof;
+ endif;
+ endif;
#endif
string varid = AssetTag.AssetTag,
prompt = STRING_TOKEN(STR_ADVANCED_ASSET_TAG_PROMPT),
diff --git a/Platform/RaspberryPi/Include/ConfigVars.h b/Platform/RaspberryPi/Include/ConfigVars.h
index 142317985a..a5b32b5284 100644
--- a/Platform/RaspberryPi/Include/ConfigVars.h
+++ b/Platform/RaspberryPi/Include/ConfigVars.h
@@ -77,6 +77,10 @@ typedef struct {
} ADVANCED_FANTEMP_VARSTORE_DATA;
typedef struct {
+ UINT32 Value;
+} ADVANCED_XHCIPCI_VARSTORE_DATA;
+
+typedef struct {
#define SYSTEM_TABLE_MODE_ACPI 0
#define SYSTEM_TABLE_MODE_BOTH 1
#define SYSTEM_TABLE_MODE_DT 2
diff --git a/Platform/RaspberryPi/RPi3/RPi3.dsc b/Platform/RaspberryPi/RPi3/RPi3.dsc
index 1c8a5408e7..6ab5d1ae6d 100644
--- a/Platform/RaspberryPi/RPi3/RPi3.dsc
+++ b/Platform/RaspberryPi/RPi3/RPi3.dsc
@@ -520,6 +520,12 @@
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberryPiTokenSpaceGuid|0x0|0
+ # Select XHCI/PCIe mode (not valid on rpi3)
+ #
+ # 0 - DISABLED
+ #
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4/RPi4.dsc
index dcf9bb5f11..babcbb2f41 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -536,6 +536,14 @@
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberryPiTokenSpaceGuid|0x0|0
+ # Select XHCI/PCIe mode
+ #
+ # 0 - XHCI Enabled (default on !cm4)
+ # 1 - PCIe Enabled
+ # 2 - PCIe Enabled (default on cm4)
+ #
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RaspberryPi.dec b/Platform/RaspberryPi/RaspberryPi.dec
index 2ca25ff9e6..797be59274 100644
--- a/Platform/RaspberryPi/RaspberryPi.dec
+++ b/Platform/RaspberryPi/RaspberryPi.dec
@@ -71,3 +71,4 @@
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|0|UINT32|0x0000001E
gRaspberryPiTokenSpaceGuid.PcdMmcEnableDma|0|UINT32|0x0000001F
gRaspberryPiTokenSpaceGuid.PcdUartInUse|1|UINT32|0x00000021
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|0|UINT32|0x00000022
--
2.13.7
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/5] Platform/RaspberryPi: break XHCI into its own SSDT
2021-08-05 16:35 [PATCH 0/5] RPi4: Enable ACPI PCIe conduit Jeremy Linton
2021-08-05 16:35 ` [PATCH 1/5] Platform/RaspberryPi: Add XHCI/PCI selection menu Jeremy Linton
@ 2021-08-05 16:35 ` Jeremy Linton
2021-08-06 15:50 ` [edk2-devel] " Andrei Warkentin
2021-08-05 16:35 ` [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT Jeremy Linton
` (2 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Jeremy Linton @ 2021-08-05 16:35 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton
Lets prepare to switch between XHCI and PCI by moving
the XHCI definition into its own SSDT. That way we can
select it based on the menu settings.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 +
Platform/RaspberryPi/AcpiTables/Dsdt.asl | 3 --
Platform/RaspberryPi/AcpiTables/Xhci.asl | 35 ++++++++++++++--------
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 8 +++++
4 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index 1ddc9ca5fe..f3e8d950c1 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -38,6 +38,7 @@
SpcrPl011.aslc
Pptt.aslc
SsdtThermal.asl
+ Xhci.asl
[Packages]
ArmPkg/ArmPkg.dec
diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
index 1ee6379f46..b594d50bdf 100644
--- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl
+++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
@@ -64,9 +64,6 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
Scope (\_SB_)
{
include ("Pep.asl")
-#if (RPI_MODEL == 4)
- include ("Xhci.asl")
-#endif
Device (CPU0)
{
diff --git a/Platform/RaspberryPi/AcpiTables/Xhci.asl b/Platform/RaspberryPi/AcpiTables/Xhci.asl
index bc3fea60f9..9b37277956 100644
--- a/Platform/RaspberryPi/AcpiTables/Xhci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Xhci.asl
@@ -9,6 +9,8 @@
#include <IndustryStandard/Bcm2711.h>
+#include "AcpiTables.h"
+
/*
* The following can be used to remove parenthesis from
* defined macros that the compiler complains about.
@@ -24,12 +26,17 @@
*/
#define XHCI_REG_LENGTH 0x1000
-Device (SCB0) {
- Name (_HID, "ACPI0004")
- Name (_UID, 0x0)
- Name (_CCA, 0x0)
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
- Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+ Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
/*
* Container devices with _DMA must have _CRS, meaning SCB0
* to provide all resources that XHC0 consumes (except
@@ -57,15 +64,15 @@ Device (SCB0) {
Add (MMBE, XHCI_REG_LENGTH - 1, MMBE)
Add (MMLE, XHCI_REG_LENGTH - 1, MMLE)
Return (RBUF)
- }
+ }
- Name (_DMA, ResourceTemplate() {
+ Name (_DMA, ResourceTemplate() {
/*
* XHC0 is limited to DMA to first 3GB. Note this
* only applies to PCIe, not GENET or other devices
* next to the A72.
*/
- QWordMemory (ResourceConsumer,
+ QWordMemory (ResourceProducer,
,
MinFixed,
MaxFixed,
@@ -79,10 +86,10 @@ Device (SCB0) {
,
,
)
- })
+ })
- Device (XHC0)
- {
+ Device (XHC0)
+ {
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x0) // _UID: Unique ID
Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute
@@ -131,5 +138,7 @@ Device (SCB0) {
Debug = "xHCI enable"
Store (0x6, CMND)
}
- }
-}
+ } // end XHC0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 87f6b4e7bb..7c5786303d 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -814,6 +814,14 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
PcdToken(PcdSdIsArasan),
SsdtEmmcNameOpReplace
},
+#if (RPI_MODEL == 4)
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'X', 'H', 'C', 'I'),
+ 0,
+ PcdToken(PcdXhciPci),
+ NULL
+ },
+#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
0,
--
2.13.7
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT
2021-08-05 16:35 [PATCH 0/5] RPi4: Enable ACPI PCIe conduit Jeremy Linton
2021-08-05 16:35 ` [PATCH 1/5] Platform/RaspberryPi: Add XHCI/PCI selection menu Jeremy Linton
2021-08-05 16:35 ` [PATCH 2/5] Platform/RaspberryPi: break XHCI into its own SSDT Jeremy Linton
@ 2021-08-05 16:35 ` Jeremy Linton
2021-08-06 13:42 ` Ard Biesheuvel
2021-08-06 15:37 ` Andrei Warkentin
2021-08-05 16:35 ` [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4 Jeremy Linton
2021-08-05 16:35 ` [PATCH 5/5] Platform/RaspberryPi: Enable NVMe boot on cm4 Jeremy Linton
4 siblings, 2 replies; 16+ messages in thread
From: Jeremy Linton @ 2021-08-05 16:35 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton
Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port, on a machine without
a MADT it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +
Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++++++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +
3 files changed, 246 insertions(+)
create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
Pptt.aslc
SsdtThermal.asl
Xhci.asl
+ Pci.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
new file mode 100644
index 0000000000..34474f13ef
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,237 @@
+/** @file
+ *
+ * Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ * Copyright (c) 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Bcm2711.h>
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...) __VA_ARGS__
+#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
+
+/*
+ * According to UEFI boot log for the VLI device on Pi 4.
+ */
+#define RT_REG_LENGTH 0x1000
+
+// copy paste job from juno
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
+ Link, /* Interrupt allocated via Link device. */ \
+ Zero /* global system interrupt number (no used) */ \
+ }
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link)
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Method (_CRS, 0, Serialized) {
+ // Container devices with _DMA must have _CRS,
+ // meaning SCB0 to provide all resources that
+ // PCI0 consumes (except interrupts).
+ Name (RBUF, ResourceTemplate () {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX
+ 0x0,
+ 0x1, // LEN
+ ,
+ ,
+ MMIO
+ )
+ })
+ CreateQwordField (RBUF, MMIO._MAX, MMBE)
+ CreateQwordField (RBUF, MMIO._LEN, MMLE)
+ Add (MMBE, RT_REG_LENGTH - 1, MMBE)
+ Add (MMLE, RT_REG_LENGTH - 1, MMLE)
+ Return (RBUF)
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ // PCIe can only DMA to first 3GB with early SOC's
+ // But we keep the restriction on the later ones
+ // To avoid DMA translation problems.
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ //
+ // PCI Root Complex
+ //
+ LNK_DEVICE(1, LNKA, 175)
+ LNK_DEVICE(2, LNKB, 176)
+ LNK_DEVICE(3, LNKC, 177)
+ LNK_DEVICE(4, LNKD, 178)
+
+ Device(PCI0)
+ {
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 0) // Mark the PCI noncoherent
+
+ // Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ QWordMemory (ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKA), // INTA
+ ROOT_PRT_ENTRY(1, LNKB), // INTB
+ ROOT_PRT_ENTRY(2, LNKC), // INTC
+ ROOT_PRT_ENTRY(3, LNKD), // INTD
+ })
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ QWordMemory ( // 32-bit BAR Windows in 64-bit addr
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, //cacheable? is that right?
+ 0x00000000, // Granularity
+ 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
+ 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
+ 2 // SANITIZED_PCIE_MMIO_LEN + 1
+ ,,,MMI1,,TypeTranslation
+ )
+ }) // end Name(RBUF)
+
+ // Work around ASL's inability to add in a resource definition
+ // or for that matter compute the min,max,len properly
+ CreateQwordField (RBUF, MMI1._MIN, MMIB)
+ CreateQwordField (RBUF, MMI1._MAX, MMIE)
+ CreateQwordField (RBUF, MMI1._TRA, MMIT)
+ CreateQwordField (RBUF, MMI1._LEN, MMIL)
+ Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
+ Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
+ Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
+ Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
+
+ Return (RBUF)
+ } // end Method(_CRS)
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ // See [1] 6.2.10, [2] 4.5
+ Method(_OSC,4) {
+ // Note, This code is very similar to the code in the PCIe firmware
+ // specification which can be used as a reference
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+ // Mask out Native HotPlug
+ And(CTRL,0x1E,CTRL)
+ // Always allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+ } // PCI0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 7c5786303d..4c40820858 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
PcdToken(PcdXhciPci),
NULL
},
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
+ PcdToken(PcdXhciPci),
+ 0,
+ NULL
+ },
#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
--
2.13.7
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
2021-08-05 16:35 [PATCH 0/5] RPi4: Enable ACPI PCIe conduit Jeremy Linton
` (2 preceding siblings ...)
2021-08-05 16:35 ` [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT Jeremy Linton
@ 2021-08-05 16:35 ` Jeremy Linton
2021-08-06 13:42 ` Ard Biesheuvel
2021-08-06 16:02 ` [edk2-devel] " Andrei Warkentin
2021-08-05 16:35 ` [PATCH 5/5] Platform/RaspberryPi: Enable NVMe boot on cm4 Jeremy Linton
4 siblings, 2 replies; 16+ messages in thread
From: Jeremy Linton @ 2021-08-05 16:35 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton, René Treffer
The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.
Suggested-by: René Treffer <treffer+groups.io@measite.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
.../Bcm2711PciHostBridgeLibConstructor.c | 5 -----
.../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++-------
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
} while (((Data & 0x30) != 0x030) && (Timeout));
DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
- if ((Data & 0x30) != 0x30) {
- DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
- return EFI_DEVICE_ERROR;
- }
-
if ((Data & 0x80) != 0x80) {
DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
UINT64 Base;
UINT64 Offset;
UINT32 Dev;
+ UINT32 Bus;
+ UINT32 Data;
Base = PCIE_REG_BASE;
Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
Base += PCIE_EXT_CFG_DATA;
if (mPciSegmentLastAccess != Address) {
Dev = EFI_PCI_ADDR_DEV (Address);
+ Bus = EFI_PCI_ADDR_BUS (Address);
+
/*
- * Scan things out directly rather than translating the "bus" to a device, etc..
- * only we need to limit each bus to a single device.
+ * There can only be a single device on bus 1 (downstream of root).
+ * Subsequent busses (behind a PCIe switch) can have more.
*/
- if (Dev < 1) {
- MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
- mPciSegmentLastAccess = Address;
- } else {
- mPciSegmentLastAccess = 0;
+ if (Dev > 0 && (Bus < 2)) {
return 0xFFFFFFFF;
}
+
+ /* Don't probe slots if the link is down */
+ Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+ if ((Data & 0x30) != 0x30) {
+ DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+ return 0xFFFFFFFF;
+ }
+
+ MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+ mPciSegmentLastAccess = Address;
}
}
return Base + Offset;
--
2.13.7
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 5/5] Platform/RaspberryPi: Enable NVMe boot on cm4
2021-08-05 16:35 [PATCH 0/5] RPi4: Enable ACPI PCIe conduit Jeremy Linton
` (3 preceding siblings ...)
2021-08-05 16:35 ` [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4 Jeremy Linton
@ 2021-08-05 16:35 ` Jeremy Linton
4 siblings, 0 replies; 16+ messages in thread
From: Jeremy Linton @ 2021-08-05 16:35 UTC (permalink / raw)
To: devel
Cc: pete, ardb+tianocore, awarkentin, Sunny.Wang,
samer.el-haj-mahmoud, Jeremy Linton
The CM4 has a number of carrier boards with PCIe
slots. With the PCIe changes in place its quite
possible to setup a NVMe root device. Lets allow
people to boot from it.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/RPi4/RPi4.dsc | 5 +++++
Platform/RaspberryPi/RPi4/RPi4.fdf | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4/RPi4.dsc
index babcbb2f41..25c29a0fbf 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -754,6 +754,11 @@
}
#
+ # NVMe boot devices
+ #
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
# UEFI application (Shell Embedded Boot Loader)
#
ShellPkg/Application/Shell/Shell.inf {
diff --git a/Platform/RaspberryPi/RPi4/RPi4.fdf b/Platform/RaspberryPi/RPi4/RPi4.fdf
index 3534cd3dc3..0c782d2f35 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.fdf
+++ b/Platform/RaspberryPi/RPi4/RPi4.fdf
@@ -283,6 +283,11 @@ READ_LOCK_STATUS = TRUE
INF EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf
#
+ # NVMe boot devices
+ #
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
# SCSI Bus and Disk Driver
#
INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
--
2.13.7
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT
2021-08-05 16:35 ` [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT Jeremy Linton
@ 2021-08-06 13:42 ` Ard Biesheuvel
2021-08-06 21:35 ` [edk2-devel] " Jeremy Linton
2021-08-06 15:37 ` Andrei Warkentin
1 sibling, 1 reply; 16+ messages in thread
From: Ard Biesheuvel @ 2021-08-06 13:42 UTC (permalink / raw)
To: Jeremy Linton
Cc: edk2-devel-groups-io, Peter Batard, Ard Biesheuvel,
Andrei Warkentin, Sunny Wang, Samer El-Haj-Mahmoud
On Thu, 5 Aug 2021 at 18:36, Jeremy Linton <jeremy.linton@arm.com> wrote:
>
> Since we plan on toggling between XHCI and PCI the PCI
> root needs to be in its own SSDT. This is all thats needed
> of UEFI. The SMC conduit is provided directly to the running
> OS. When the OS detects this PCIe port, on a machine without
> a MADT it attempts to connect to the SMC conduit. The RPi
> definition doesn't have any power mgmt, and only provides
> a description of the root port.
>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
> ---
> Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +
> Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++++++++
> Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +
> 3 files changed, 246 insertions(+)
> create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl
>
> diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
> index f3e8d950c1..da2a6db85f 100644
> --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
> +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
> @@ -39,6 +39,7 @@
> Pptt.aslc
> SsdtThermal.asl
> Xhci.asl
> + Pci.asl
>
> [Packages]
> ArmPkg/ArmPkg.dec
> @@ -59,6 +60,8 @@
> gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
> gArmTokenSpaceGuid.PcdGicDistributorBase
> gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
> + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
> + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
> gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
> gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
> gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
> diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
> new file mode 100644
> index 0000000000..34474f13ef
> --- /dev/null
> +++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
> @@ -0,0 +1,237 @@
> +/** @file
> + *
> + * Copyright (c) 2019 Linaro, Limited. All rights reserved.
> + * Copyright (c) 2021 Arm
> + *
> + * SPDX-License-Identifier: BSD-2-Clause-Patent
> + *
> + **/
> +
> +#include <IndustryStandard/Bcm2711.h>
> +
> +#include "AcpiTables.h"
> +
> +/*
> + * The following can be used to remove parenthesis from
> + * defined macros that the compiler complains about.
> + */
> +#define ISOLATE_ARGS(...) __VA_ARGS__
> +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
> +
> +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
> +#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
> +#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
> +
> +/*
> + * According to UEFI boot log for the VLI device on Pi 4.
> + */
> +#define RT_REG_LENGTH 0x1000
> +
> +// copy paste job from juno
> +#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
> + Device(Link_Name) { \
> + Name(_HID, EISAID("PNP0C0F")) \
> + Name(_UID, Unique_Id) \
> + Name(_PRS, ResourceTemplate() { \
> + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
> + }) \
> + Method (_CRS, 0) { Return (_PRS) } \
> + Method (_SRS, 1) { } \
> + Method (_DIS) { } \
> + }
> +
> +#define PRT_ENTRY(Address, Pin, Link) \
> + Package (4) { \
> + Address, /* uses the same format as _ADR */ \
> + Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
> + Link, /* Interrupt allocated via Link device. */ \
> + Zero /* global system interrupt number (no used) */ \
> + }
> +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link)
> +
This can be done in a much simpler way - SynQuacer uses this, for instance
Name (_PRT, Package () {
Package () { 0xFFFF, 0, Zero, 222 }, // INTA
Package () { 0xFFFF, 1, Zero, 222 }, // INTB
Package () { 0xFFFF, 2, Zero, 222 }, // INTC
Package () { 0xFFFF, 3, Zero, 222 }, // INTD
})
> +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
> +{
> + Scope (\_SB_)
> + {
> +
> + Device (SCB0) {
> + Name (_HID, "ACPI0004")
> + Name (_UID, 0x0)
Even if this file and the xhci one should never be exposed to the OS
at the same time, can we please use unique UIDs?
> + Name (_CCA, 0x0)
> +
> + Method (_CRS, 0, Serialized) {
> + // Container devices with _DMA must have _CRS,
> + // meaning SCB0 to provide all resources that
> + // PCI0 consumes (except interrupts).
> + Name (RBUF, ResourceTemplate () {
> + QWordMemory (ResourceProducer,
> + ,
> + MinFixed,
> + MaxFixed,
> + NonCacheable,
> + ReadWrite,
> + 0x0,
> + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN
> + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX
> + 0x0,
> + 0x1, // LEN
> + ,
> + ,
> + MMIO
> + )
> + })
> + CreateQwordField (RBUF, MMIO._MAX, MMBE)
> + CreateQwordField (RBUF, MMIO._LEN, MMLE)
> + Add (MMBE, RT_REG_LENGTH - 1, MMBE)
> + Add (MMLE, RT_REG_LENGTH - 1, MMLE)
> + Return (RBUF)
> + }
> +
> + Name (_DMA, ResourceTemplate() {
> + // PCIe can only DMA to first 3GB with early SOC's
> + // But we keep the restriction on the later ones
> + // To avoid DMA translation problems.
> + QWordMemory (ResourceProducer,
> + ,
> + MinFixed,
> + MaxFixed,
> + NonCacheable,
> + ReadWrite,
> + 0x0,
> + 0x0, // MIN
> + 0xbfffffff, // MAX
> + 0x0, // TRA
> + 0xc0000000, // LEN
> + ,
> + ,
> + )
> + })
> +
> + //
> + // PCI Root Complex
> + //
> + LNK_DEVICE(1, LNKA, 175)
> + LNK_DEVICE(2, LNKB, 176)
> + LNK_DEVICE(3, LNKC, 177)
> + LNK_DEVICE(4, LNKD, 178)
> +
> + Device(PCI0)
> + {
> + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> + Name(_SEG, Zero) // PCI Segment Group number
> + Name(_BBN, Zero) // PCI Base Bus Number
> + Name(_CCA, 0) // Mark the PCI noncoherent
> +
> + // Root Complex 0
> + Device (RP0) {
> + Name(_ADR, 0xF0000000) // Dev 0, Func 0
> + }
> +
Can we just drop this?
> + Name (_DMA, ResourceTemplate() {
> + QWordMemory (ResourceConsumer,
> + ,
> + MinFixed,
> + MaxFixed,
> + NonCacheable,
> + ReadWrite,
> + 0x0,
> + 0x0, // MIN
> + 0xbfffffff, // MAX
> + 0x0, // TRA
> + 0xc0000000, // LEN
> + ,
> + ,
> + )
> + })
> +
Do we need this method on the host bridge device as well as on the container?
> + // PCI Routing Table
> + Name(_PRT, Package() {
> + ROOT_PRT_ENTRY(0, LNKA), // INTA
> + ROOT_PRT_ENTRY(1, LNKB), // INTB
> + ROOT_PRT_ENTRY(2, LNKC), // INTC
> + ROOT_PRT_ENTRY(3, LNKD), // INTD
> + })
> + // Root complex resources
> + Method (_CRS, 0, Serialized) {
> + Name (RBUF, ResourceTemplate () {
> + WordBusNumber ( // Bus numbers assigned to this root
> + ResourceProducer,
> + MinFixed, MaxFixed, PosDecode,
> + 0, // AddressGranularity
> + 0, // AddressMinimum - Minimum Bus Number
> + 255, // AddressMaximum - Maximum Bus Number
> + 0, // AddressTranslation - Set to 0
> + 256 // RangeLength - Number of Busses
> + )
> +
> + QWordMemory ( // 32-bit BAR Windows in 64-bit addr
> + ResourceProducer, PosDecode,
> + MinFixed, MaxFixed,
> + NonCacheable, ReadWrite, //cacheable? is that right?
> + 0x00000000, // Granularity
> + 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
> + 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
> + SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
> + 2 // SANITIZED_PCIE_MMIO_LEN + 1
> + ,,,MMI1,,TypeTranslation
> + )
> + }) // end Name(RBUF)
> +
> + // Work around ASL's inability to add in a resource definition
> + // or for that matter compute the min,max,len properly
> + CreateQwordField (RBUF, MMI1._MIN, MMIB)
> + CreateQwordField (RBUF, MMI1._MAX, MMIE)
> + CreateQwordField (RBUF, MMI1._TRA, MMIT)
> + CreateQwordField (RBUF, MMI1._LEN, MMIL)
> + Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
> + Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
> + Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
> + Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
> +
> + Return (RBUF)
> + } // end Method(_CRS)
> + //
> + // OS Control Handoff
> + //
> + Name(SUPP, Zero) // PCI _OSC Support Field value
> + Name(CTRL, Zero) // PCI _OSC Control Field value
> +
> + // See [1] 6.2.10, [2] 4.5
> + Method(_OSC,4) {
> + // Note, This code is very similar to the code in the PCIe firmware
> + // specification which can be used as a reference
> + // Check for proper UUID
> + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> + // Create DWord-adressable fields from the Capabilities Buffer
> + CreateDWordField(Arg3,0,CDW1)
> + CreateDWordField(Arg3,4,CDW2)
> + CreateDWordField(Arg3,8,CDW3)
> + // Save Capabilities DWord2 & 3
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> + // Mask out Native HotPlug
> + And(CTRL,0x1E,CTRL)
> + // Always allow native PME, AER (no dependencies)
> + // Never allow SHPC (no SHPC controller in this system)
> + And(CTRL,0x1D,CTRL)
> +
> + If(LNotEqual(Arg1,One)) { // Unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> +
> + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
> + Or(CDW1,0x10,CDW1)
> + }
> + // Update DWORD3 in the buffer
> + Store(CTRL,CDW3)
> + Return(Arg3)
> + } Else {
> + Or(CDW1,4,CDW1) // Unrecognized UUID
> + Return(Arg3)
> + }
> + } // End _OSC
> + } // PCI0
> + } //end SCB0
> + } //end scope sb
> +} //end definition block
> diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
> index 7c5786303d..4c40820858 100644
> --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
> +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
> @@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
> PcdToken(PcdXhciPci),
> NULL
> },
> + {
> + SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
> + PcdToken(PcdXhciPci),
> + 0,
> + NULL
> + },
> #endif
> { // DSDT
> SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
> --
> 2.13.7
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
2021-08-05 16:35 ` [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4 Jeremy Linton
@ 2021-08-06 13:42 ` Ard Biesheuvel
2021-08-06 14:06 ` Jeremy Linton
2021-08-06 16:02 ` [edk2-devel] " Andrei Warkentin
1 sibling, 1 reply; 16+ messages in thread
From: Ard Biesheuvel @ 2021-08-06 13:42 UTC (permalink / raw)
To: Jeremy Linton
Cc: edk2-devel-groups-io, Peter Batard, Ard Biesheuvel,
Andrei Warkentin, Sunny Wang, Samer El-Haj-Mahmoud,
René Treffer
On Thu, 5 Aug 2021 at 18:36, Jeremy Linton <jeremy.linton@arm.com> wrote:
>
> The CM4 has an actual pcie slot, so we need to move the linkup
> check to the configuration probe logic. Further the device
> restriction logic needs to be relaxed to support downstream
> PCIe switches.
>
> Suggested-by: René Treffer <treffer+groups.io@measite.de>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Please split this into two patches.
> ---
> .../Bcm2711PciHostBridgeLibConstructor.c | 5 -----
> .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++-------
> 2 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> index 8587d2d36d..4d4c584726 100644
> --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
> } while (((Data & 0x30) != 0x030) && (Timeout));
> DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
>
> - if ((Data & 0x30) != 0x30) {
> - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
> - return EFI_DEVICE_ERROR;
> - }
> -
> if ((Data & 0x80) != 0x80) {
> DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
> return EFI_UNSUPPORTED;
> diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> index 44ce3b4b99..3ccc131eab 100644
> --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> @@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
> UINT64 Base;
> UINT64 Offset;
> UINT32 Dev;
> + UINT32 Bus;
> + UINT32 Data;
>
> Base = PCIE_REG_BASE;
> Offset = Address & 0xFFF; /* Pick off the 4k register offset */
> @@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
> Base += PCIE_EXT_CFG_DATA;
> if (mPciSegmentLastAccess != Address) {
> Dev = EFI_PCI_ADDR_DEV (Address);
> + Bus = EFI_PCI_ADDR_BUS (Address);
> +
> /*
> - * Scan things out directly rather than translating the "bus" to a device, etc..
> - * only we need to limit each bus to a single device.
> + * There can only be a single device on bus 1 (downstream of root).
> + * Subsequent busses (behind a PCIe switch) can have more.
> */
> - if (Dev < 1) {
> - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
> - mPciSegmentLastAccess = Address;
> - } else {
> - mPciSegmentLastAccess = 0;
> + if (Dev > 0 && (Bus < 2)) {
> return 0xFFFFFFFF;
> }
> +
> + /* Don't probe slots if the link is down */
> + Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
> + if ((Data & 0x30) != 0x30) {
> + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
> + return 0xFFFFFFFF;
> + }
> +
> + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
> + mPciSegmentLastAccess = Address;
> }
> }
> return Base + Offset;
> --
> 2.13.7
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
2021-08-06 13:42 ` Ard Biesheuvel
@ 2021-08-06 14:06 ` Jeremy Linton
0 siblings, 0 replies; 16+ messages in thread
From: Jeremy Linton @ 2021-08-06 14:06 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel-groups-io, Peter Batard, Ard Biesheuvel,
Andrei Warkentin, Sunny Wang, Samer El-Haj-Mahmoud,
René Treffer
Hi,
On 8/6/21 8:42 AM, Ard Biesheuvel wrote:
> On Thu, 5 Aug 2021 at 18:36, Jeremy Linton <jeremy.linton@arm.com> wrote:
>>
>> The CM4 has an actual pcie slot, so we need to move the linkup
>> check to the configuration probe logic. Further the device
>> restriction logic needs to be relaxed to support downstream
>> PCIe switches.
>>
>> Suggested-by: René Treffer <treffer+groups.io@measite.de>
>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>
> Please split this into two patches.
Your talking about the linkup move, vs expanding the dev<0 check?
Ok.
>
>> ---
>> .../Bcm2711PciHostBridgeLibConstructor.c | 5 -----
>> .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++-------
>> 2 files changed, 17 insertions(+), 12 deletions(-)
>>
>> diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
>> index 8587d2d36d..4d4c584726 100644
>> --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
>> +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
>> @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
>> } while (((Data & 0x30) != 0x030) && (Timeout));
>> DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
>>
>> - if ((Data & 0x30) != 0x30) {
>> - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
>> - return EFI_DEVICE_ERROR;
>> - }
>> -
>> if ((Data & 0x80) != 0x80) {
>> DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
>> return EFI_UNSUPPORTED;
>> diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
>> index 44ce3b4b99..3ccc131eab 100644
>> --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
>> +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
>> @@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
>> UINT64 Base;
>> UINT64 Offset;
>> UINT32 Dev;
>> + UINT32 Bus;
>> + UINT32 Data;
>>
>> Base = PCIE_REG_BASE;
>> Offset = Address & 0xFFF; /* Pick off the 4k register offset */
>> @@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
>> Base += PCIE_EXT_CFG_DATA;
>> if (mPciSegmentLastAccess != Address) {
>> Dev = EFI_PCI_ADDR_DEV (Address);
>> + Bus = EFI_PCI_ADDR_BUS (Address);
>> +
>> /*
>> - * Scan things out directly rather than translating the "bus" to a device, etc..
>> - * only we need to limit each bus to a single device.
>> + * There can only be a single device on bus 1 (downstream of root).
>> + * Subsequent busses (behind a PCIe switch) can have more.
>> */
>> - if (Dev < 1) {
>> - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
>> - mPciSegmentLastAccess = Address;
>> - } else {
>> - mPciSegmentLastAccess = 0;
>> + if (Dev > 0 && (Bus < 2)) {
>> return 0xFFFFFFFF;
>> }
>> +
>> + /* Don't probe slots if the link is down */
>> + Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
>> + if ((Data & 0x30) != 0x30) {
>> + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
>> + return 0xFFFFFFFF;
>> + }
>> +
>> + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
>> + mPciSegmentLastAccess = Address;
>> }
>> }
>> return Base + Offset;
>> --
>> 2.13.7
>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT
2021-08-05 16:35 ` [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT Jeremy Linton
2021-08-06 13:42 ` Ard Biesheuvel
@ 2021-08-06 15:37 ` Andrei Warkentin
2021-08-06 21:31 ` Jeremy Linton
1 sibling, 1 reply; 16+ messages in thread
From: Andrei Warkentin @ 2021-08-06 15:37 UTC (permalink / raw)
To: devel@edk2.groups.io, jeremy.linton@arm.com
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com
[-- Attachment #1: Type: text/plain, Size: 13812 bytes --]
Hi Jeremy,
MADT -> MCFG (and in other patches as well, where you refer to MADT)
The other feedback that Ard provided makes sense to me as well.
A
--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware
________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton=arm.com@groups.io>
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
Subject: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT
Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port, on a machine without
a MADT it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +
Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++++++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +
3 files changed, 246 insertions(+)
create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
Pptt.aslc
SsdtThermal.asl
Xhci.asl
+ Pci.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
new file mode 100644
index 0000000000..34474f13ef
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,237 @@
+/** @file
+ *
+ * Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ * Copyright (c) 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Bcm2711.h>
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...) __VA_ARGS__
+#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
+
+/*
+ * According to UEFI boot log for the VLI device on Pi 4.
+ */
+#define RT_REG_LENGTH 0x1000
+
+// copy paste job from juno
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
+ Link, /* Interrupt allocated via Link device. */ \
+ Zero /* global system interrupt number (no used) */ \
+ }
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link)
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Method (_CRS, 0, Serialized) {
+ // Container devices with _DMA must have _CRS,
+ // meaning SCB0 to provide all resources that
+ // PCI0 consumes (except interrupts).
+ Name (RBUF, ResourceTemplate () {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX
+ 0x0,
+ 0x1, // LEN
+ ,
+ ,
+ MMIO
+ )
+ })
+ CreateQwordField (RBUF, MMIO._MAX, MMBE)
+ CreateQwordField (RBUF, MMIO._LEN, MMLE)
+ Add (MMBE, RT_REG_LENGTH - 1, MMBE)
+ Add (MMLE, RT_REG_LENGTH - 1, MMLE)
+ Return (RBUF)
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ // PCIe can only DMA to first 3GB with early SOC's
+ // But we keep the restriction on the later ones
+ // To avoid DMA translation problems.
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ //
+ // PCI Root Complex
+ //
+ LNK_DEVICE(1, LNKA, 175)
+ LNK_DEVICE(2, LNKB, 176)
+ LNK_DEVICE(3, LNKC, 177)
+ LNK_DEVICE(4, LNKD, 178)
+
+ Device(PCI0)
+ {
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 0) // Mark the PCI noncoherent
+
+ // Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ QWordMemory (ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKA), // INTA
+ ROOT_PRT_ENTRY(1, LNKB), // INTB
+ ROOT_PRT_ENTRY(2, LNKC), // INTC
+ ROOT_PRT_ENTRY(3, LNKD), // INTD
+ })
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ QWordMemory ( // 32-bit BAR Windows in 64-bit addr
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, //cacheable? is that right?
+ 0x00000000, // Granularity
+ 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
+ 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
+ 2 // SANITIZED_PCIE_MMIO_LEN + 1
+ ,,,MMI1,,TypeTranslation
+ )
+ }) // end Name(RBUF)
+
+ // Work around ASL's inability to add in a resource definition
+ // or for that matter compute the min,max,len properly
+ CreateQwordField (RBUF, MMI1._MIN, MMIB)
+ CreateQwordField (RBUF, MMI1._MAX, MMIE)
+ CreateQwordField (RBUF, MMI1._TRA, MMIT)
+ CreateQwordField (RBUF, MMI1._LEN, MMIL)
+ Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
+ Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
+ Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
+ Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
+
+ Return (RBUF)
+ } // end Method(_CRS)
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ // See [1] 6.2.10, [2] 4.5
+ Method(_OSC,4) {
+ // Note, This code is very similar to the code in the PCIe firmware
+ // specification which can be used as a reference
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+ // Mask out Native HotPlug
+ And(CTRL,0x1E,CTRL)
+ // Always allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+ } // PCI0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 7c5786303d..4c40820858 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
PcdToken(PcdXhciPci),
NULL
},
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
+ PcdToken(PcdXhciPci),
+ 0,
+ NULL
+ },
#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
--
2.13.7
-=-=-=-=-=-=
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* Re: [edk2-devel] [PATCH 2/5] Platform/RaspberryPi: break XHCI into its own SSDT
2021-08-05 16:35 ` [PATCH 2/5] Platform/RaspberryPi: break XHCI into its own SSDT Jeremy Linton
@ 2021-08-06 15:50 ` Andrei Warkentin
0 siblings, 0 replies; 16+ messages in thread
From: Andrei Warkentin @ 2021-08-06 15:50 UTC (permalink / raw)
To: devel@edk2.groups.io, jeremy.linton@arm.com
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com
[-- Attachment #1: Type: text/plain, Size: 6504 bytes --]
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware
________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton=arm.com@groups.io>
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
Subject: [edk2-devel] [PATCH 2/5] Platform/RaspberryPi: break XHCI into its own SSDT
Lets prepare to switch between XHCI and PCI by moving
the XHCI definition into its own SSDT. That way we can
select it based on the menu settings.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 +
Platform/RaspberryPi/AcpiTables/Dsdt.asl | 3 --
Platform/RaspberryPi/AcpiTables/Xhci.asl | 35 ++++++++++++++--------
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 8 +++++
4 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index 1ddc9ca5fe..f3e8d950c1 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -38,6 +38,7 @@
SpcrPl011.aslc
Pptt.aslc
SsdtThermal.asl
+ Xhci.asl
[Packages]
ArmPkg/ArmPkg.dec
diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
index 1ee6379f46..b594d50bdf 100644
--- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl
+++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
@@ -64,9 +64,6 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
Scope (\_SB_)
{
include ("Pep.asl")
-#if (RPI_MODEL == 4)
- include ("Xhci.asl")
-#endif
Device (CPU0)
{
diff --git a/Platform/RaspberryPi/AcpiTables/Xhci.asl b/Platform/RaspberryPi/AcpiTables/Xhci.asl
index bc3fea60f9..9b37277956 100644
--- a/Platform/RaspberryPi/AcpiTables/Xhci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Xhci.asl
@@ -9,6 +9,8 @@
#include <IndustryStandard/Bcm2711.h>
+#include "AcpiTables.h"
+
/*
* The following can be used to remove parenthesis from
* defined macros that the compiler complains about.
@@ -24,12 +26,17 @@
*/
#define XHCI_REG_LENGTH 0x1000
-Device (SCB0) {
- Name (_HID, "ACPI0004")
- Name (_UID, 0x0)
- Name (_CCA, 0x0)
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
- Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+ Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
/*
* Container devices with _DMA must have _CRS, meaning SCB0
* to provide all resources that XHC0 consumes (except
@@ -57,15 +64,15 @@ Device (SCB0) {
Add (MMBE, XHCI_REG_LENGTH - 1, MMBE)
Add (MMLE, XHCI_REG_LENGTH - 1, MMLE)
Return (RBUF)
- }
+ }
- Name (_DMA, ResourceTemplate() {
+ Name (_DMA, ResourceTemplate() {
/*
* XHC0 is limited to DMA to first 3GB. Note this
* only applies to PCIe, not GENET or other devices
* next to the A72.
*/
- QWordMemory (ResourceConsumer,
+ QWordMemory (ResourceProducer,
,
MinFixed,
MaxFixed,
@@ -79,10 +86,10 @@ Device (SCB0) {
,
,
)
- })
+ })
- Device (XHC0)
- {
+ Device (XHC0)
+ {
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x0) // _UID: Unique ID
Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute
@@ -131,5 +138,7 @@ Device (SCB0) {
Debug = "xHCI enable"
Store (0x6, CMND)
}
- }
-}
+ } // end XHC0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 87f6b4e7bb..7c5786303d 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -814,6 +814,14 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
PcdToken(PcdSdIsArasan),
SsdtEmmcNameOpReplace
},
+#if (RPI_MODEL == 4)
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'X', 'H', 'C', 'I'),
+ 0,
+ PcdToken(PcdXhciPci),
+ NULL
+ },
+#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
0,
--
2.13.7
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
2021-08-05 16:35 ` [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4 Jeremy Linton
2021-08-06 13:42 ` Ard Biesheuvel
@ 2021-08-06 16:02 ` Andrei Warkentin
2021-08-06 16:04 ` Andrei Warkentin
1 sibling, 1 reply; 16+ messages in thread
From: Andrei Warkentin @ 2021-08-06 16:02 UTC (permalink / raw)
To: devel@edk2.groups.io, jeremy.linton@arm.com
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com, René Treffer
[-- Attachment #1: Type: text/plain, Size: 4272 bytes --]
Hi Jeremy,
Is any of this still conceptually necessary if we adopt the SMCCC interface within UEFI?
Instead of assuming the first downstream bus is bus 1, could you read the secondary BN from the RP?
--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware
________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton=arm.com@groups.io>
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>; René Treffer <treffer+groups.io@measite.de>
Subject: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.
Suggested-by: René Treffer <treffer+groups.io@measite.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
.../Bcm2711PciHostBridgeLibConstructor.c | 5 -----
.../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++-------
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
} while (((Data & 0x30) != 0x030) && (Timeout));
DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
- if ((Data & 0x30) != 0x30) {
- DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
- return EFI_DEVICE_ERROR;
- }
-
if ((Data & 0x80) != 0x80) {
DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
UINT64 Base;
UINT64 Offset;
UINT32 Dev;
+ UINT32 Bus;
+ UINT32 Data;
Base = PCIE_REG_BASE;
Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
Base += PCIE_EXT_CFG_DATA;
if (mPciSegmentLastAccess != Address) {
Dev = EFI_PCI_ADDR_DEV (Address);
+ Bus = EFI_PCI_ADDR_BUS (Address);
+
/*
- * Scan things out directly rather than translating the "bus" to a device, etc..
- * only we need to limit each bus to a single device.
+ * There can only be a single device on bus 1 (downstream of root).
+ * Subsequent busses (behind a PCIe switch) can have more.
*/
- if (Dev < 1) {
- MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
- mPciSegmentLastAccess = Address;
- } else {
- mPciSegmentLastAccess = 0;
+ if (Dev > 0 && (Bus < 2)) {
return 0xFFFFFFFF;
}
+
+ /* Don't probe slots if the link is down */
+ Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+ if ((Data & 0x30) != 0x30) {
+ DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+ return 0xFFFFFFFF;
+ }
+
+ MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+ mPciSegmentLastAccess = Address;
}
}
return Base + Offset;
--
2.13.7
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
2021-08-06 16:02 ` [edk2-devel] " Andrei Warkentin
@ 2021-08-06 16:04 ` Andrei Warkentin
2021-08-06 21:52 ` Jeremy Linton
0 siblings, 1 reply; 16+ messages in thread
From: Andrei Warkentin @ 2021-08-06 16:04 UTC (permalink / raw)
To: devel@edk2.groups.io, jeremy.linton@arm.com
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com, René Treffer
[-- Attachment #1: Type: text/plain, Size: 5259 bytes --]
Ok, I misunderstood the patch set (I thought the PciHostBridgeLib itself would eventually move to DEN0115).
I still think that (in general) would be a good idea - if not for the benefit of the Pi, then for the next upstreamed platform where you could avoid implementing custom config access code...
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware
________________________________
From: Andrei Warkentin <awarkentin@vmware.com>
Sent: Friday, August 6, 2021 7:02 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>; jeremy.linton@arm.com <jeremy.linton@arm.com>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; René Treffer <treffer+groups.io@measite.de>
Subject: Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
Hi Jeremy,
Is any of this still conceptually necessary if we adopt the SMCCC interface within UEFI?
Instead of assuming the first downstream bus is bus 1, could you read the secondary BN from the RP?
--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware
________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton=arm.com@groups.io>
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>; René Treffer <treffer+groups.io@measite.de>
Subject: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.
Suggested-by: René Treffer <treffer+groups.io@measite.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
.../Bcm2711PciHostBridgeLibConstructor.c | 5 -----
.../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++-------
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
} while (((Data & 0x30) != 0x030) && (Timeout));
DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
- if ((Data & 0x30) != 0x30) {
- DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
- return EFI_DEVICE_ERROR;
- }
-
if ((Data & 0x80) != 0x80) {
DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
UINT64 Base;
UINT64 Offset;
UINT32 Dev;
+ UINT32 Bus;
+ UINT32 Data;
Base = PCIE_REG_BASE;
Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
Base += PCIE_EXT_CFG_DATA;
if (mPciSegmentLastAccess != Address) {
Dev = EFI_PCI_ADDR_DEV (Address);
+ Bus = EFI_PCI_ADDR_BUS (Address);
+
/*
- * Scan things out directly rather than translating the "bus" to a device, etc..
- * only we need to limit each bus to a single device.
+ * There can only be a single device on bus 1 (downstream of root).
+ * Subsequent busses (behind a PCIe switch) can have more.
*/
- if (Dev < 1) {
- MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
- mPciSegmentLastAccess = Address;
- } else {
- mPciSegmentLastAccess = 0;
+ if (Dev > 0 && (Bus < 2)) {
return 0xFFFFFFFF;
}
+
+ /* Don't probe slots if the link is down */
+ Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+ if ((Data & 0x30) != 0x30) {
+ DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+ return 0xFFFFFFFF;
+ }
+
+ MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+ mPciSegmentLastAccess = Address;
}
}
return Base + Offset;
--
2.13.7
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT
2021-08-06 15:37 ` Andrei Warkentin
@ 2021-08-06 21:31 ` Jeremy Linton
0 siblings, 0 replies; 16+ messages in thread
From: Jeremy Linton @ 2021-08-06 21:31 UTC (permalink / raw)
To: Andrei Warkentin, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com
Hi,
On 8/6/21 10:37 AM, Andrei Warkentin wrote:
> Hi Jeremy,
>
> MADT -> MCFG (and in other patches as well, where you refer to MADT)
I will take 4 letter acronyms that start with an M... <chuckle>
Thanks,
> The other feedback that Ard provided makes sense to me as well.
>
> A
>
> --
> Andrei Warkentin,
> Arm Enablement Architect,
> Cloud Platform Business Unit, VMware
> ________________________________
> From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton=arm.com@groups.io>
> Sent: Thursday, August 5, 2021 7:35 PM
> To: devel@edk2.groups.io <devel@edk2.groups.io>
> Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
> Subject: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT
>
> Since we plan on toggling between XHCI and PCI the PCI
> root needs to be in its own SSDT. This is all thats needed
> of UEFI. The SMC conduit is provided directly to the running
> OS. When the OS detects this PCIe port, on a machine without
> a MADT it attempts to connect to the SMC conduit. The RPi
> definition doesn't have any power mgmt, and only provides
> a description of the root port.
>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
> ---
> Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +
> Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++++++++
> Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +
> 3 files changed, 246 insertions(+)
> create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl
>
> diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
> index f3e8d950c1..da2a6db85f 100644
> --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
> +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
> @@ -39,6 +39,7 @@
> Pptt.aslc
> SsdtThermal.asl
> Xhci.asl
> + Pci.asl
>
> [Packages]
> ArmPkg/ArmPkg.dec
> @@ -59,6 +60,8 @@
> gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
> gArmTokenSpaceGuid.PcdGicDistributorBase
> gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
> + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
> + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
> gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
> gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
> gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
> diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
> new file mode 100644
> index 0000000000..34474f13ef
> --- /dev/null
> +++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
> @@ -0,0 +1,237 @@
> +/** @file
> + *
> + * Copyright (c) 2019 Linaro, Limited. All rights reserved.
> + * Copyright (c) 2021 Arm
> + *
> + * SPDX-License-Identifier: BSD-2-Clause-Patent
> + *
> + **/
> +
> +#include <IndustryStandard/Bcm2711.h>
> +
> +#include "AcpiTables.h"
> +
> +/*
> + * The following can be used to remove parenthesis from
> + * defined macros that the compiler complains about.
> + */
> +#define ISOLATE_ARGS(...) __VA_ARGS__
> +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
> +
> +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
> +#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
> +#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
> +
> +/*
> + * According to UEFI boot log for the VLI device on Pi 4.
> + */
> +#define RT_REG_LENGTH 0x1000
> +
> +// copy paste job from juno
> +#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
> + Device(Link_Name) { \
> + Name(_HID, EISAID("PNP0C0F")) \
> + Name(_UID, Unique_Id) \
> + Name(_PRS, ResourceTemplate() { \
> + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
> + }) \
> + Method (_CRS, 0) { Return (_PRS) } \
> + Method (_SRS, 1) { } \
> + Method (_DIS) { } \
> + }
> +
> +#define PRT_ENTRY(Address, Pin, Link) \
> + Package (4) { \
> + Address, /* uses the same format as _ADR */ \
> + Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
> + Link, /* Interrupt allocated via Link device. */ \
> + Zero /* global system interrupt number (no used) */ \
> + }
> +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link)
> +
> +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
> +{
> + Scope (\_SB_)
> + {
> +
> + Device (SCB0) {
> + Name (_HID, "ACPI0004")
> + Name (_UID, 0x0)
> + Name (_CCA, 0x0)
> +
> + Method (_CRS, 0, Serialized) {
> + // Container devices with _DMA must have _CRS,
> + // meaning SCB0 to provide all resources that
> + // PCI0 consumes (except interrupts).
> + Name (RBUF, ResourceTemplate () {
> + QWordMemory (ResourceProducer,
> + ,
> + MinFixed,
> + MaxFixed,
> + NonCacheable,
> + ReadWrite,
> + 0x0,
> + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN
> + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX
> + 0x0,
> + 0x1, // LEN
> + ,
> + ,
> + MMIO
> + )
> + })
> + CreateQwordField (RBUF, MMIO._MAX, MMBE)
> + CreateQwordField (RBUF, MMIO._LEN, MMLE)
> + Add (MMBE, RT_REG_LENGTH - 1, MMBE)
> + Add (MMLE, RT_REG_LENGTH - 1, MMLE)
> + Return (RBUF)
> + }
> +
> + Name (_DMA, ResourceTemplate() {
> + // PCIe can only DMA to first 3GB with early SOC's
> + // But we keep the restriction on the later ones
> + // To avoid DMA translation problems.
> + QWordMemory (ResourceProducer,
> + ,
> + MinFixed,
> + MaxFixed,
> + NonCacheable,
> + ReadWrite,
> + 0x0,
> + 0x0, // MIN
> + 0xbfffffff, // MAX
> + 0x0, // TRA
> + 0xc0000000, // LEN
> + ,
> + ,
> + )
> + })
> +
> + //
> + // PCI Root Complex
> + //
> + LNK_DEVICE(1, LNKA, 175)
> + LNK_DEVICE(2, LNKB, 176)
> + LNK_DEVICE(3, LNKC, 177)
> + LNK_DEVICE(4, LNKD, 178)
> +
> + Device(PCI0)
> + {
> + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
> + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
> + Name(_SEG, Zero) // PCI Segment Group number
> + Name(_BBN, Zero) // PCI Base Bus Number
> + Name(_CCA, 0) // Mark the PCI noncoherent
> +
> + // Root Complex 0
> + Device (RP0) {
> + Name(_ADR, 0xF0000000) // Dev 0, Func 0
> + }
> +
> + Name (_DMA, ResourceTemplate() {
> + QWordMemory (ResourceConsumer,
> + ,
> + MinFixed,
> + MaxFixed,
> + NonCacheable,
> + ReadWrite,
> + 0x0,
> + 0x0, // MIN
> + 0xbfffffff, // MAX
> + 0x0, // TRA
> + 0xc0000000, // LEN
> + ,
> + ,
> + )
> + })
> +
> + // PCI Routing Table
> + Name(_PRT, Package() {
> + ROOT_PRT_ENTRY(0, LNKA), // INTA
> + ROOT_PRT_ENTRY(1, LNKB), // INTB
> + ROOT_PRT_ENTRY(2, LNKC), // INTC
> + ROOT_PRT_ENTRY(3, LNKD), // INTD
> + })
> + // Root complex resources
> + Method (_CRS, 0, Serialized) {
> + Name (RBUF, ResourceTemplate () {
> + WordBusNumber ( // Bus numbers assigned to this root
> + ResourceProducer,
> + MinFixed, MaxFixed, PosDecode,
> + 0, // AddressGranularity
> + 0, // AddressMinimum - Minimum Bus Number
> + 255, // AddressMaximum - Maximum Bus Number
> + 0, // AddressTranslation - Set to 0
> + 256 // RangeLength - Number of Busses
> + )
> +
> + QWordMemory ( // 32-bit BAR Windows in 64-bit addr
> + ResourceProducer, PosDecode,
> + MinFixed, MaxFixed,
> + NonCacheable, ReadWrite, //cacheable? is that right?
> + 0x00000000, // Granularity
> + 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
> + 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
> + SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
> + 2 // SANITIZED_PCIE_MMIO_LEN + 1
> + ,,,MMI1,,TypeTranslation
> + )
> + }) // end Name(RBUF)
> +
> + // Work around ASL's inability to add in a resource definition
> + // or for that matter compute the min,max,len properly
> + CreateQwordField (RBUF, MMI1._MIN, MMIB)
> + CreateQwordField (RBUF, MMI1._MAX, MMIE)
> + CreateQwordField (RBUF, MMI1._TRA, MMIT)
> + CreateQwordField (RBUF, MMI1._LEN, MMIL)
> + Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
> + Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
> + Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
> + Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
> +
> + Return (RBUF)
> + } // end Method(_CRS)
> + //
> + // OS Control Handoff
> + //
> + Name(SUPP, Zero) // PCI _OSC Support Field value
> + Name(CTRL, Zero) // PCI _OSC Control Field value
> +
> + // See [1] 6.2.10, [2] 4.5
> + Method(_OSC,4) {
> + // Note, This code is very similar to the code in the PCIe firmware
> + // specification which can be used as a reference
> + // Check for proper UUID
> + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
> + // Create DWord-adressable fields from the Capabilities Buffer
> + CreateDWordField(Arg3,0,CDW1)
> + CreateDWordField(Arg3,4,CDW2)
> + CreateDWordField(Arg3,8,CDW3)
> + // Save Capabilities DWord2 & 3
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> + // Mask out Native HotPlug
> + And(CTRL,0x1E,CTRL)
> + // Always allow native PME, AER (no dependencies)
> + // Never allow SHPC (no SHPC controller in this system)
> + And(CTRL,0x1D,CTRL)
> +
> + If(LNotEqual(Arg1,One)) { // Unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> +
> + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
> + Or(CDW1,0x10,CDW1)
> + }
> + // Update DWORD3 in the buffer
> + Store(CTRL,CDW3)
> + Return(Arg3)
> + } Else {
> + Or(CDW1,4,CDW1) // Unrecognized UUID
> + Return(Arg3)
> + }
> + } // End _OSC
> + } // PCI0
> + } //end SCB0
> + } //end scope sb
> +} //end definition block
> diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
> index 7c5786303d..4c40820858 100644
> --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
> +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
> @@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
> PcdToken(PcdXhciPci),
> NULL
> },
> + {
> + SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
> + PcdToken(PcdXhciPci),
> + 0,
> + NULL
> + },
> #endif
> { // DSDT
> SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
> --
> 2.13.7
>
>
>
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT
2021-08-06 13:42 ` Ard Biesheuvel
@ 2021-08-06 21:35 ` Jeremy Linton
0 siblings, 0 replies; 16+ messages in thread
From: Jeremy Linton @ 2021-08-06 21:35 UTC (permalink / raw)
To: devel, ardb
Cc: Peter Batard, Ard Biesheuvel, Andrei Warkentin, Sunny Wang,
Samer El-Haj-Mahmoud
Hi,
So I've tested with all the comments below and everything seems to be
working fine, so no issues there. I will re-post RSN.
Thanks,
On 8/6/21 8:42 AM, Ard Biesheuvel via groups.io wrote:
> On Thu, 5 Aug 2021 at 18:36, Jeremy Linton <jeremy.linton@arm.com> wrote:
>>
>> Since we plan on toggling between XHCI and PCI the PCI
>> root needs to be in its own SSDT. This is all thats needed
>> of UEFI. The SMC conduit is provided directly to the running
>> OS. When the OS detects this PCIe port, on a machine without
>> a MADT it attempts to connect to the SMC conduit. The RPi
>> definition doesn't have any power mgmt, and only provides
>> a description of the root port.
>>
>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>> ---
>> Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +
>> Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++++++++
>> Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +
>> 3 files changed, 246 insertions(+)
>> create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl
>>
>> diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
>> index f3e8d950c1..da2a6db85f 100644
>> --- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
>> +++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
>> @@ -39,6 +39,7 @@
>> Pptt.aslc
>> SsdtThermal.asl
>> Xhci.asl
>> + Pci.asl
>>
>> [Packages]
>> ArmPkg/ArmPkg.dec
>> @@ -59,6 +60,8 @@
>> gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
>> gArmTokenSpaceGuid.PcdGicDistributorBase
>> gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
>> + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
>> + gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
>> gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
>> gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
>> gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
>> diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
>> new file mode 100644
>> index 0000000000..34474f13ef
>> --- /dev/null
>> +++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
>> @@ -0,0 +1,237 @@
>> +/** @file
>> + *
>> + * Copyright (c) 2019 Linaro, Limited. All rights reserved.
>> + * Copyright (c) 2021 Arm
>> + *
>> + * SPDX-License-Identifier: BSD-2-Clause-Patent
>> + *
>> + **/
>> +
>> +#include <IndustryStandard/Bcm2711.h>
>> +
>> +#include "AcpiTables.h"
>> +
>> +/*
>> + * The following can be used to remove parenthesis from
>> + * defined macros that the compiler complains about.
>> + */
>> +#define ISOLATE_ARGS(...) __VA_ARGS__
>> +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
>> +
>> +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
>> +#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
>> +#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
>> +
>> +/*
>> + * According to UEFI boot log for the VLI device on Pi 4.
>> + */
>> +#define RT_REG_LENGTH 0x1000
>> +
>> +// copy paste job from juno
>> +#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
>> + Device(Link_Name) { \
>> + Name(_HID, EISAID("PNP0C0F")) \
>> + Name(_UID, Unique_Id) \
>> + Name(_PRS, ResourceTemplate() { \
>> + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
>> + }) \
>> + Method (_CRS, 0) { Return (_PRS) } \
>> + Method (_SRS, 1) { } \
>> + Method (_DIS) { } \
>> + }
>> +
>> +#define PRT_ENTRY(Address, Pin, Link) \
>> + Package (4) { \
>> + Address, /* uses the same format as _ADR */ \
>> + Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
>> + Link, /* Interrupt allocated via Link device. */ \
>> + Zero /* global system interrupt number (no used) */ \
>> + }
>> +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link)
>> +
>
> This can be done in a much simpler way - SynQuacer uses this, for instance
>
> Name (_PRT, Package () {
> Package () { 0xFFFF, 0, Zero, 222 }, // INTA
> Package () { 0xFFFF, 1, Zero, 222 }, // INTB
> Package () { 0xFFFF, 2, Zero, 222 }, // INTC
> Package () { 0xFFFF, 3, Zero, 222 }, // INTD
> })
>
>> +DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
>> +{
>> + Scope (\_SB_)
>> + {
>> +
>> + Device (SCB0) {
>> + Name (_HID, "ACPI0004")
>> + Name (_UID, 0x0)
>
> Even if this file and the xhci one should never be exposed to the OS
> at the same time, can we please use unique UIDs?
>
>
>> + Name (_CCA, 0x0)
>> +
>> + Method (_CRS, 0, Serialized) {
>> + // Container devices with _DMA must have _CRS,
>> + // meaning SCB0 to provide all resources that
>> + // PCI0 consumes (except interrupts).
>> + Name (RBUF, ResourceTemplate () {
>> + QWordMemory (ResourceProducer,
>> + ,
>> + MinFixed,
>> + MaxFixed,
>> + NonCacheable,
>> + ReadWrite,
>> + 0x0,
>> + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN
>> + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX
>> + 0x0,
>> + 0x1, // LEN
>> + ,
>> + ,
>> + MMIO
>> + )
>> + })
>> + CreateQwordField (RBUF, MMIO._MAX, MMBE)
>> + CreateQwordField (RBUF, MMIO._LEN, MMLE)
>> + Add (MMBE, RT_REG_LENGTH - 1, MMBE)
>> + Add (MMLE, RT_REG_LENGTH - 1, MMLE)
>> + Return (RBUF)
>> + }
>> +
>> + Name (_DMA, ResourceTemplate() {
>> + // PCIe can only DMA to first 3GB with early SOC's
>> + // But we keep the restriction on the later ones
>> + // To avoid DMA translation problems.
>> + QWordMemory (ResourceProducer,
>> + ,
>> + MinFixed,
>> + MaxFixed,
>> + NonCacheable,
>> + ReadWrite,
>> + 0x0,
>> + 0x0, // MIN
>> + 0xbfffffff, // MAX
>> + 0x0, // TRA
>> + 0xc0000000, // LEN
>> + ,
>> + ,
>> + )
>> + })
>> +
>> + //
>> + // PCI Root Complex
>> + //
>> + LNK_DEVICE(1, LNKA, 175)
>> + LNK_DEVICE(2, LNKB, 176)
>> + LNK_DEVICE(3, LNKC, 177)
>> + LNK_DEVICE(4, LNKD, 178)
>> +
>> + Device(PCI0)
>> + {
>> + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
>> + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
>> + Name(_SEG, Zero) // PCI Segment Group number
>> + Name(_BBN, Zero) // PCI Base Bus Number
>> + Name(_CCA, 0) // Mark the PCI noncoherent
>> +
>> + // Root Complex 0
>> + Device (RP0) {
>> + Name(_ADR, 0xF0000000) // Dev 0, Func 0
>> + }
>> +
>
> Can we just drop this?
>
>> + Name (_DMA, ResourceTemplate() {
>> + QWordMemory (ResourceConsumer,
>> + ,
>> + MinFixed,
>> + MaxFixed,
>> + NonCacheable,
>> + ReadWrite,
>> + 0x0,
>> + 0x0, // MIN
>> + 0xbfffffff, // MAX
>> + 0x0, // TRA
>> + 0xc0000000, // LEN
>> + ,
>> + ,
>> + )
>> + })
>> +
>
> Do we need this method on the host bridge device as well as on the container?
>
>> + // PCI Routing Table
>> + Name(_PRT, Package() {
>> + ROOT_PRT_ENTRY(0, LNKA), // INTA
>> + ROOT_PRT_ENTRY(1, LNKB), // INTB
>> + ROOT_PRT_ENTRY(2, LNKC), // INTC
>> + ROOT_PRT_ENTRY(3, LNKD), // INTD
>> + })
>> + // Root complex resources
>> + Method (_CRS, 0, Serialized) {
>> + Name (RBUF, ResourceTemplate () {
>> + WordBusNumber ( // Bus numbers assigned to this root
>> + ResourceProducer,
>> + MinFixed, MaxFixed, PosDecode,
>> + 0, // AddressGranularity
>> + 0, // AddressMinimum - Minimum Bus Number
>> + 255, // AddressMaximum - Maximum Bus Number
>> + 0, // AddressTranslation - Set to 0
>> + 256 // RangeLength - Number of Busses
>> + )
>> +
>> + QWordMemory ( // 32-bit BAR Windows in 64-bit addr
>> + ResourceProducer, PosDecode,
>> + MinFixed, MaxFixed,
>> + NonCacheable, ReadWrite, //cacheable? is that right?
>> + 0x00000000, // Granularity
>> + 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
>> + 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
>> + SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
>> + 2 // SANITIZED_PCIE_MMIO_LEN + 1
>> + ,,,MMI1,,TypeTranslation
>> + )
>> + }) // end Name(RBUF)
>> +
>> + // Work around ASL's inability to add in a resource definition
>> + // or for that matter compute the min,max,len properly
>> + CreateQwordField (RBUF, MMI1._MIN, MMIB)
>> + CreateQwordField (RBUF, MMI1._MAX, MMIE)
>> + CreateQwordField (RBUF, MMI1._TRA, MMIT)
>> + CreateQwordField (RBUF, MMI1._LEN, MMIL)
>> + Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
>> + Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
>> + Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
>> + Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
>> +
>> + Return (RBUF)
>> + } // end Method(_CRS)
>> + //
>> + // OS Control Handoff
>> + //
>> + Name(SUPP, Zero) // PCI _OSC Support Field value
>> + Name(CTRL, Zero) // PCI _OSC Control Field value
>> +
>> + // See [1] 6.2.10, [2] 4.5
>> + Method(_OSC,4) {
>> + // Note, This code is very similar to the code in the PCIe firmware
>> + // specification which can be used as a reference
>> + // Check for proper UUID
>> + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
>> + // Create DWord-adressable fields from the Capabilities Buffer
>> + CreateDWordField(Arg3,0,CDW1)
>> + CreateDWordField(Arg3,4,CDW2)
>> + CreateDWordField(Arg3,8,CDW3)
>> + // Save Capabilities DWord2 & 3
>> + Store(CDW2,SUPP)
>> + Store(CDW3,CTRL)
>> + // Mask out Native HotPlug
>> + And(CTRL,0x1E,CTRL)
>> + // Always allow native PME, AER (no dependencies)
>> + // Never allow SHPC (no SHPC controller in this system)
>> + And(CTRL,0x1D,CTRL)
>> +
>> + If(LNotEqual(Arg1,One)) { // Unknown revision
>> + Or(CDW1,0x08,CDW1)
>> + }
>> +
>> + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
>> + Or(CDW1,0x10,CDW1)
>> + }
>> + // Update DWORD3 in the buffer
>> + Store(CTRL,CDW3)
>> + Return(Arg3)
>> + } Else {
>> + Or(CDW1,4,CDW1) // Unrecognized UUID
>> + Return(Arg3)
>> + }
>> + } // End _OSC
>> + } // PCI0
>> + } //end SCB0
>> + } //end scope sb
>> +} //end definition block
>> diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
>> index 7c5786303d..4c40820858 100644
>> --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
>> +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
>> @@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {Yah, I will fix that.
>> PcdToken(PcdXhciPci),
>> NULL
>> },
>> + {
>> + SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
>> + PcdToken(PcdXhciPci),
>> + 0,
>> + NULL
>> + },
>> #endif
>> { // DSDT
>> SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
>> --
>> 2.13.7
>>
>
>
>
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
2021-08-06 16:04 ` Andrei Warkentin
@ 2021-08-06 21:52 ` Jeremy Linton
0 siblings, 0 replies; 16+ messages in thread
From: Jeremy Linton @ 2021-08-06 21:52 UTC (permalink / raw)
To: Andrei Warkentin, devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, Sunny.Wang@arm.com,
samer.el-haj-mahmoud@arm.com, René Treffer
Hi,
On 8/6/21 11:04 AM, Andrei Warkentin wrote:
> Ok, I misunderstood the patch set (I thought the PciHostBridgeLib itself would eventually move to DEN0115).
>
> I still think that (in general) would be a good idea - if not for the benefit of the Pi, then for the next upstreamed platform where you could avoid implementing custom config access code...
Right, the only bit that goes away is the PciSegmentLibGetConfigBase()
code to be replaced by the SMC call. Which I will do, but I think its
better to fix to this one and make that a separate patch-set ideally
with another platform in parallel.
>
> Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
>
> --
> Andrei Warkentin,
> Arm Enablement Architect,
> Cloud Platform Business Unit, VMware
> ________________________________
> From: Andrei Warkentin <awarkentin@vmware.com>
> Sent: Friday, August 6, 2021 7:02 PM
> To: devel@edk2.groups.io <devel@edk2.groups.io>; jeremy.linton@arm.com <jeremy.linton@arm.com>
> Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; René Treffer <treffer+groups.io@measite.de>
> Subject: Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
>
> Hi Jeremy,
>
> Is any of this still conceptually necessary if we adopt the SMCCC interface within UEFI?
>
> Instead of assuming the first downstream bus is bus 1, could you read the secondary BN from the RP?
>
> --
> Andrei Warkentin,
> Arm Enablement Architect,
> Cloud Platform Business Unit, VMware
> ________________________________
> From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton=arm.com@groups.io>
> Sent: Thursday, August 5, 2021 7:35 PM
> To: devel@edk2.groups.io <devel@edk2.groups.io>
> Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>; René Treffer <treffer+groups.io@measite.de>
> Subject: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
>
> The CM4 has an actual pcie slot, so we need to move the linkup
> check to the configuration probe logic. Further the device
> restriction logic needs to be relaxed to support downstream
> PCIe switches.
>
> Suggested-by: René Treffer <treffer+groups.io@measite.de>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
> ---
> .../Bcm2711PciHostBridgeLibConstructor.c | 5 -----
> .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++-------
> 2 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> index 8587d2d36d..4d4c584726 100644
> --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
> @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
> } while (((Data & 0x30) != 0x030) && (Timeout));
> DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
>
> - if ((Data & 0x30) != 0x30) {
> - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
> - return EFI_DEVICE_ERROR;
> - }
> -
> if ((Data & 0x80) != 0x80) {
> DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
> return EFI_UNSUPPORTED;
> diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> index 44ce3b4b99..3ccc131eab 100644
> --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
> @@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
> UINT64 Base;
> UINT64 Offset;
> UINT32 Dev;
> + UINT32 Bus;
> + UINT32 Data;
>
> Base = PCIE_REG_BASE;
> Offset = Address & 0xFFF; /* Pick off the 4k register offset */
> @@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
> Base += PCIE_EXT_CFG_DATA;
> if (mPciSegmentLastAccess != Address) {
> Dev = EFI_PCI_ADDR_DEV (Address);
> + Bus = EFI_PCI_ADDR_BUS (Address);
> +
> /*
> - * Scan things out directly rather than translating the "bus" to a device, etc..
> - * only we need to limit each bus to a single device.
> + * There can only be a single device on bus 1 (downstream of root).
> + * Subsequent busses (behind a PCIe switch) can have more.
> */
> - if (Dev < 1) {
> - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
> - mPciSegmentLastAccess = Address;
> - } else {
> - mPciSegmentLastAccess = 0;
> + if (Dev > 0 && (Bus < 2)) {
> return 0xFFFFFFFF;
> }
> +
> + /* Don't probe slots if the link is down */
> + Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
> + if ((Data & 0x30) != 0x30) {
> + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
> + return 0xFFFFFFFF;
> + }
> +
> + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
> + mPciSegmentLastAccess = Address;
> }
> }
> return Base + Offset;
> --
> 2.13.7
>
>
>
>
>
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2021-08-06 21:53 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-08-05 16:35 [PATCH 0/5] RPi4: Enable ACPI PCIe conduit Jeremy Linton
2021-08-05 16:35 ` [PATCH 1/5] Platform/RaspberryPi: Add XHCI/PCI selection menu Jeremy Linton
2021-08-05 16:35 ` [PATCH 2/5] Platform/RaspberryPi: break XHCI into its own SSDT Jeremy Linton
2021-08-06 15:50 ` [edk2-devel] " Andrei Warkentin
2021-08-05 16:35 ` [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT Jeremy Linton
2021-08-06 13:42 ` Ard Biesheuvel
2021-08-06 21:35 ` [edk2-devel] " Jeremy Linton
2021-08-06 15:37 ` Andrei Warkentin
2021-08-06 21:31 ` Jeremy Linton
2021-08-05 16:35 ` [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4 Jeremy Linton
2021-08-06 13:42 ` Ard Biesheuvel
2021-08-06 14:06 ` Jeremy Linton
2021-08-06 16:02 ` [edk2-devel] " Andrei Warkentin
2021-08-06 16:04 ` Andrei Warkentin
2021-08-06 21:52 ` Jeremy Linton
2021-08-05 16:35 ` [PATCH 5/5] Platform/RaspberryPi: Enable NVMe boot on cm4 Jeremy Linton
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