From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: prince.agyeman@intel.com) Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Wed, 11 Sep 2019 09:40:51 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Sep 2019 09:40:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,494,1559545200"; d="scan'208";a="209724121" Received: from paagyema-desk2.amr.corp.intel.com ([10.24.15.58]) by fmsmga004.fm.intel.com with ESMTP; 11 Sep 2019 09:40:11 -0700 From: "Agyeman, Prince" To: devel@edk2.groups.io Cc: philmd@redhat.com, "Agyeman, Prince" , David Wei , Liming Gao , Ankit Sinha , Kubacki Michael A , Nate DeSimone Subject: [edk2-devel] [PATCH v2 3/3] SimicsIch10Pkg: Fix GCC build issues Date: Wed, 11 Sep 2019 09:40:10 -0700 Message-Id: <3d85dd4ce503ef01b66ab4be55bfcf921c7e7012.1568219401.git.prince.agyeman@intel.com> X-Mailer: git-send-email 2.19.1.windows.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: "Agyeman, Prince" Removed Status variable as the SmmClear function always returns EFI_SUCCESS. Refer to the Smmclear function for details Removed SpiBaseAddress variable as this address was never used in the SendSpiCmd function. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2162 Cc: David Wei Cc: Liming Gao Cc: Ankit Sinha Cc: Agyeman Prince Cc: Kubacki Michael A Cc: Nate DeSimone Signed-off-by: Prince Agyeman --- .../LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c | 3 --- .../SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c | 7 ++----- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c index bd08b2453b..3e7dffedfb 100644 --- a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c +++ b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c @@ -637,7 +637,6 @@ SendSpiCmd ( EFI_STATUS Status; UINT32 Index; SPI_INSTANCE *SpiInstance; - UINTN SpiBaseAddress; UINTN PchSpiBar0; UINT32 HardwareSpiAddr; UINT32 FlashRegionSize; @@ -648,9 +647,7 @@ SendSpiCmd ( Status = EFI_SUCCESS; SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This); - SpiBaseAddress = SpiInstance->PchSpiBase; PchSpiBar0 = AcquireSpiBar0 (SpiInstance); - SpiBaseAddress = SpiInstance->PchSpiBase; ABase = SpiInstance->PchAcpiBase; // diff --git a/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c b/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c index 268b04d25a..cc2d00b785 100644 --- a/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c +++ b/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c @@ -131,7 +131,6 @@ SmmControl2DxeTrigger ( IN UINTN ActivationInterval OPTIONAL ) { - EFI_STATUS Status; // // No support for queued or periodic activation. // @@ -141,7 +140,7 @@ SmmControl2DxeTrigger ( /// /// Clear any pending the APM SMI /// - Status = SmmClear(); + SmmClear(); // // The so-called "Advanced Power Management Status Port Register" is in fact // a generic data passing register, between the caller and the SMI @@ -181,8 +180,6 @@ SmmControl2DxeClear ( IN BOOLEAN Periodic OPTIONAL ) { - EFI_STATUS Status; - if (Periodic) { return EFI_INVALID_PARAMETER; } @@ -201,7 +198,7 @@ SmmControl2DxeClear ( // // So, nothing to do here. // - Status = SmmClear(); + SmmClear(); return EFI_SUCCESS; } -- 2.19.1.windows.1