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Wed, 22 Apr 2020 17:42:27 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: cabf90a3-5f75-4cb0-d021-08d7e6e48669 X-MS-TrafficTypeDiagnostic: DM6PR12MB3449:|DM6PR12MB3449: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-Forefront-PRVS: 03818C953D X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM6PR12MB3163.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(10009020)(4636009)(136003)(346002)(376002)(39860400002)(366004)(396003)(66556008)(16526019)(66476007)(186003)(5660300002)(4326008)(30864003)(86362001)(54906003)(8936002)(81156014)(966005)(6486002)(66946007)(316002)(19627235002)(52116002)(7696005)(956004)(36756003)(6916009)(2906002)(2616005)(8676002)(478600001)(26005)(136400200001);DIR:OUT;SFP:1101; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ah0n7pTchdIjUh50fKRI2ObPLn65UfT66CbY46bA1DY8YTLjhFn+UmfvhzO2RTB32Wc3VC7NHQwMcojiYa9Axfnm74MMsw9ya2gzrlLTwYsFPMSgiYTATGNZ1lR5WuoJoxdwIvhD+YvNrP0KI7H4jEOteJfymOBKzWuxgNzU0f9YMvIsBRfEvN/sXEpaLcO2gg3DE/haS7jBoTT+pukszjeoVNrTENHpvEYtrZlaNlBcFzo+UfEGiQmi9KBh8RHJmT68oF6ucUHWKPezNlZgEp+UKe7TRdR6g7f/rU+nw09QseUTytOu1FkMFWTbLeVnPdspKVzgCKQX9F6Z4t76RlY6nyzpkKSFZyH34tcnV2RENPhQY43pw2/TMKkQ2DXbcOw8ZFQ5XCtYo2D2pYOhDuGaOZfVu+WGcVNaHKSYSm7rG5e3MqvRUhiueFeHCxUV1vdUOWx4O5VOhTWE249UhDSL2B1td1KBPhPC6oDNoe9cxIO0aIiY/WpvmBYaLY+MaF7v1LX3CBda2LZwIoiCCT5C7/4oMIzAfW4BEJsFkYmDvXTYmyNQAbDkFP+8kCB7N7N2VBeYt1A1E2bJj3R9yg== X-MS-Exchange-AntiSpam-MessageData: BUH7NuJ5JUm9AuEre7y3Tf5ZeVMUy46ahVM4nWdjxt6R41lbxijgfFX2w1ozbAZi60qTsPEMC+IysbbRSVv1Z+TCRhmclbWa8kCXOBtEcGe5XoZAAOeBavNujXFFS/0nOga+7Aei5sGvBSyxsDzr4Q== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: cabf90a3-5f75-4cb0-d021-08d7e6e48669 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2020 17:42:27.9737 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Gp/GCoPrNO25NZAPK/sfnc+tQKM2RVtrZEhBhWmCTFzZUXrATrpiBsEamuAEkNb6LLs5aMaUkqovMiuLs04aaA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3449 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Under SEV-ES, a IOIO_PROT intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support a IOIO_PROT NAE event. Parse the instruction that generated the #VC exception, setting the required register values in the GHCB and creating the proper SW_EXITINFO1 value in the GHCB. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 599 +++++++++++++++++- 1 file changed, 585 insertions(+), 14 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index c0a0eee319bf..588f2af572e1 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -11,6 +11,567 @@ #include #include "AMDSevVcCommon.h" +// +// Instruction execution mode definition +// +typedef enum { + LongMode64Bit = 0, + LongModeCompat32Bit, + LongModeCompat16Bit, +} SEV_ES_INSTRUCTION_MODE; + +// +// Instruction size definition (for operand and address) +// +typedef enum { + Size8Bits = 0, + Size16Bits, + Size32Bits, + Size64Bits, +} SEV_ES_INSTRUCTION_SIZE; + +// +// Intruction segment definition +// +typedef enum { + SegmentEs = 0, + SegmentCs, + SegmentSs, + SegmentDs, + SegmentFs, + SegmentGs, +} SEV_ES_INSTRUCTION_SEGMENT; + +// +// Instruction rep function definition +// +typedef enum { + RepNone = 0, + RepZ, + RepNZ, +} SEV_ES_INSTRUCTION_REP; + +// +// Instruction REX prefix definition +// +typedef union { + struct { + UINT8 BitB:1; + UINT8 BitX:1; + UINT8 BitR:1; + UINT8 BitW:1; + UINT8 Rex:4; + } Bits; + + UINT8 Uint8; +} SEV_ES_INSTRUCTION_REX_PREFIX; + +// +// Instruction ModRM definition +// +typedef union { + struct { + UINT8 Rm:3; + UINT8 Reg:3; + UINT8 Mod:2; + } Bits; + + UINT8 Uint8; +} SEV_ES_INSTRUCTION_MODRM; + +typedef struct { + UINT8 Rm; + UINT8 Reg; + UINT8 Mod; +} SEV_ES_INSTRUCTION_MODRM_EXT; + +// +// Instruction SIB definition +// +typedef union { + struct { + UINT8 Base:3; + UINT8 Index:3; + UINT8 Scale:2; + } Bits; + + UINT8 Uint8; +} SEV_ES_INSTRUCTION_SIB; + +typedef struct { + UINT8 Base; + UINT8 Index; + UINT8 Scale; +} SEV_ES_INSTRUCTION_SIB_EXT; + +// +// Instruction opcode definition +// +typedef struct { + SEV_ES_INSTRUCTION_MODRM_EXT ModRm; + + SEV_ES_INSTRUCTION_SIB_EXT Sib; + + UINTN RegData; + UINTN RmData; +} SEV_ES_INSTRUCTION_OPCODE_EXT; + +// +// Instruction parsing context definition +// +typedef struct { + GHCB *Ghcb; + + SEV_ES_INSTRUCTION_MODE Mode; + SEV_ES_INSTRUCTION_SIZE DataSize; + SEV_ES_INSTRUCTION_SIZE AddrSize; + BOOLEAN SegmentSpecified; + SEV_ES_INSTRUCTION_SEGMENT Segment; + SEV_ES_INSTRUCTION_REP RepMode; + + UINT8 *Begin; + UINT8 *End; + + UINT8 *Prefixes; + UINT8 *OpCodes; + UINT8 *Displacement; + UINT8 *Immediate; + + SEV_ES_INSTRUCTION_REX_PREFIX RexPrefix; + + BOOLEAN ModRmPresent; + SEV_ES_INSTRUCTION_MODRM ModRm; + + BOOLEAN SibPresent; + SEV_ES_INSTRUCTION_SIB Sib; + + UINT8 PrefixSize; + UINT8 OpCodeSize; + UINT8 DisplacementSize; + UINT8 ImmediateSize; + + SEV_ES_INSTRUCTION_OPCODE_EXT Ext; +} SEV_ES_INSTRUCTION_DATA; + +// +// Non-automatic Exit function prototype +// +typedef +UINT64 +(*NAE_EXIT) ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ); + + +/** + Checks the GHCB to determine if the specified register has been marked valid. + + The ValidBitmap area represents the areas of the GHCB that have been marked + valid. Return an indication of whether the area of the GHCB that holds the + specified register has been marked valid. + + @param[in] Ghcb Pointer to the Guest-Hypervisor Communication Block + @param[in] Reg Offset in the GHCB of the register to check + + @retval TRUE Register has been marked vald in the GHCB + @retval FALSE Register has not been marked valid in the GHCB + +**/ +STATIC +BOOLEAN +GhcbIsRegValid ( + IN GHCB *Ghcb, + IN GHCB_REGISTER Reg + ) +{ + UINT32 RegIndex; + UINT32 RegBit; + + RegIndex = Reg / 8; + RegBit = Reg & 0x07; + + return (Ghcb->SaveArea.ValidBitmap[RegIndex] & (1 << RegBit)); +} + +/** + Marks a register as valid in the GHCB. + + The ValidBitmap area represents the areas of the GHCB that have been marked + valid. Set the area of the GHCB that holds the specified register as valid. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communication Block + @param[in] Reg Offset in the GHCB of the register to mark valid + +**/ +STATIC +VOID +GhcbSetRegValid ( + IN OUT GHCB *Ghcb, + IN GHCB_REGISTER Reg + ) +{ + UINT32 RegIndex; + UINT32 RegBit; + + RegIndex = Reg / 8; + RegBit = Reg & 0x07; + + Ghcb->SaveArea.ValidBitmap[RegIndex] |= (1 << RegBit); +} + +/** + Decode instruction prefixes. + + Parse the instruction data to track the instruction prefixes that have + been used. + + @param[in] Regs x64 processor context + @param[in, out] InstructionData Instruction parsing context + +**/ +STATIC +VOID +DecodePrefixes ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN OUT SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_MODE Mode; + SEV_ES_INSTRUCTION_SIZE ModeDataSize; + SEV_ES_INSTRUCTION_SIZE ModeAddrSize; + UINT8 *Byte; + + /*TODO: Determine current mode - 64-bit for now */ + Mode = LongMode64Bit; + ModeDataSize = Size32Bits; + ModeAddrSize = Size64Bits; + + InstructionData->Mode = Mode; + InstructionData->DataSize = ModeDataSize; + InstructionData->AddrSize = ModeAddrSize; + + InstructionData->Prefixes = InstructionData->Begin; + + Byte = InstructionData->Prefixes; + for ( ; ; Byte++, InstructionData->PrefixSize++) { + switch (*Byte) { + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if (Mode != LongMode64Bit) { + InstructionData->SegmentSpecified = TRUE; + InstructionData->Segment = (*Byte >> 3) & 3; + } + break; + + case 0x40 ... 0x4F: + InstructionData->RexPrefix.Uint8 = *Byte; + if (*Byte & 0x08) + InstructionData->DataSize = Size64Bits; + break; + + case 0x64: + InstructionData->SegmentSpecified = TRUE; + InstructionData->Segment = *Byte & 7; + break; + + case 0x66: + if (!InstructionData->RexPrefix.Uint8) { + InstructionData->DataSize = + (Mode == LongMode64Bit) ? Size16Bits : + (Mode == LongModeCompat32Bit) ? Size16Bits : + (Mode == LongModeCompat16Bit) ? Size32Bits : 0; + } + break; + + case 0x67: + InstructionData->AddrSize = + (Mode == LongMode64Bit) ? Size32Bits : + (Mode == LongModeCompat32Bit) ? Size16Bits : + (Mode == LongModeCompat16Bit) ? Size32Bits : 0; + break; + + case 0xF0: + break; + + case 0xF2: + InstructionData->RepMode = RepZ; + break; + + case 0xF3: + InstructionData->RepMode = RepNZ; + break; + + default: + InstructionData->OpCodes = Byte; + InstructionData->OpCodeSize = (*Byte == 0x0F) ? 2 : 1; + + InstructionData->End = Byte + InstructionData->OpCodeSize; + InstructionData->Displacement = InstructionData->End; + InstructionData->Immediate = InstructionData->End; + return; + } + } +} + +/** + Determine instruction length + + Return the total length of the parsed instruction. + + @param[in] InstructionData Instruction parsing context + + @retval Length of parsed instruction + +**/ +STATIC +UINT64 +InstructionLength ( + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + return (UINT64) (InstructionData->End - InstructionData->Begin); +} + +/** + Initialize the instruction parsing context. + + Initialize the instruction parsing context, which includes decoding the + instruction prefixes. + + @param[in, out] InstructionData Instruction parsing context + @param[in] Ghcb Pointer to the Guest-Hypervisor Communication + Block + @param[in] Regs x64 processor context + +**/ +STATIC +VOID +InitInstructionData ( + IN OUT SEV_ES_INSTRUCTION_DATA *InstructionData, + IN GHCB *Ghcb, + IN EFI_SYSTEM_CONTEXT_X64 *Regs + ) +{ + SetMem (InstructionData, sizeof (*InstructionData), 0); + InstructionData->Ghcb = Ghcb; + InstructionData->Begin = (UINT8 *) Regs->Rip; + InstructionData->End = (UINT8 *) Regs->Rip; + + DecodePrefixes (Regs, InstructionData); +} + +/** + Report an unsupported event to the hypervisor + + Use the VMGEXIT support to report an unsupported event to the hypervisor. + + @param[in] Ghcb Pointer to the Guest-Hypervisor Communication + Block + @param[in] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval New exception value to propagate + +**/ +STATIC +UINT64 +UnsupportedExit ( + IN GHCB *Ghcb, + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Status = VmgExit (Ghcb, SvmExitUnsupported, Regs->ExceptionData, 0); + if (Status == 0) { + GHCB_EVENT_INJECTION Event; + + Event.Uint64 = 0; + Event.Elements.Vector = GP_EXCEPTION; + Event.Elements.Type = GHCB_EVENT_INJECTION_TYPE_EXCEPTION; + Event.Elements.Valid = 1; + + Status = Event.Uint64; + } + + return Status; +} + +#define IOIO_TYPE_STR (1 << 2) +#define IOIO_TYPE_IN 1 +#define IOIO_TYPE_INS (IOIO_TYPE_IN | IOIO_TYPE_STR) +#define IOIO_TYPE_OUT 0 +#define IOIO_TYPE_OUTS (IOIO_TYPE_OUT | IOIO_TYPE_STR) + +#define IOIO_REP (1 << 3) + +#define IOIO_ADDR_64 (1 << 9) +#define IOIO_ADDR_32 (1 << 8) +#define IOIO_ADDR_16 (1 << 7) + +#define IOIO_DATA_32 (1 << 6) +#define IOIO_DATA_16 (1 << 5) +#define IOIO_DATA_8 (1 << 4) +#define IOIO_DATA_BYTES(x) (((x) & 0x70) >> 4) + +#define IOIO_SEG_ES (0 << 10) +#define IOIO_SEG_DS (3 << 10) + +/** + Build the IOIO event information. + + The IOIO event information identifies the type of IO operation to be performed + by the hypervisor. Build this information based on the instruction data. + + @param[in] Regs x64 processor context + @param[in, out] InstructionData Instruction parsing context + + @retval Others IOIO event information value + +**/ +STATIC +UINT64 +IoioExitInfo ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN OUT SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo; + + ExitInfo = 0; + + switch (*(InstructionData->OpCodes)) { + // IN immediate opcodes + case 0xE4: + case 0xE5: + InstructionData->ImmediateSize = 1; + InstructionData->End++; + ExitInfo |= IOIO_TYPE_IN; + ExitInfo |= ((*(InstructionData->OpCodes + 1)) << 16); + break; + + // OUT immediate opcodes + case 0xE6: + case 0xE7: + InstructionData->ImmediateSize = 1; + InstructionData->End++; + ExitInfo |= IOIO_TYPE_OUT; + ExitInfo |= ((*(InstructionData->OpCodes + 1)) << 16) | IOIO_TYPE_OUT; + break; + + // IN register opcodes + case 0xEC: + case 0xED: + ExitInfo |= IOIO_TYPE_IN; + ExitInfo |= ((Regs->Rdx & 0xffff) << 16); + break; + + // OUT register opcodes + case 0xEE: + case 0xEF: + ExitInfo |= IOIO_TYPE_OUT; + ExitInfo |= ((Regs->Rdx & 0xffff) << 16); + break; + + default: + return 0; + } + + switch (*(InstructionData->OpCodes)) { + case 0xE4: + case 0xE6: + case 0xEC: + case 0xEE: + // Single-byte opcodes + ExitInfo |= IOIO_DATA_8; + break; + + default: + // Length determined by instruction parsing + ExitInfo |= (InstructionData->DataSize == Size16Bits) ? IOIO_DATA_16 + : IOIO_DATA_32; + } + + switch (InstructionData->AddrSize) { + case Size16Bits: + ExitInfo |= IOIO_ADDR_16; + break; + + case Size32Bits: + ExitInfo |= IOIO_ADDR_32; + break; + + case Size64Bits: + ExitInfo |= IOIO_ADDR_64; + break; + + default: + break; + } + + if (InstructionData->RepMode) { + ExitInfo |= IOIO_REP; + } + + return ExitInfo; +} + +/** + Handle an IOIO event. + + Use the VMGEXIT instruction to handle an IOIO event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communication + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @retval Others New exception value to propagate + +**/ +STATIC +UINT64 +IoioExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo1, Status; + + ExitInfo1 = IoioExitInfo (Regs, InstructionData); + if (!ExitInfo1) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + if (ExitInfo1 & IOIO_TYPE_IN) { + Ghcb->SaveArea.Rax = 0; + } else { + CopyMem (&Ghcb->SaveArea.Rax, &Regs->Rax, IOIO_DATA_BYTES (ExitInfo1)); + } + GhcbSetRegValid (Ghcb, GhcbRax); + + Status = VmgExit (Ghcb, SvmExitIoioProt, ExitInfo1, 0); + if (Status) { + return Status; + } + + if (ExitInfo1 & IOIO_TYPE_IN) { + if (!GhcbIsRegValid (Ghcb, GhcbRax)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + CopyMem (&Regs->Rax, &Ghcb->SaveArea.Rax, IOIO_DATA_BYTES (ExitInfo1)); + } + + return 0; +} + /** Common #VC exception handling routine. @@ -30,6 +591,8 @@ DoVcCommon ( ) { EFI_SYSTEM_CONTEXT_X64 *Regs; + SEV_ES_INSTRUCTION_DATA InstructionData; + NAE_EXIT NaeExit; UINT64 Status; UINTN ExitCode, VcRet; @@ -39,23 +602,31 @@ DoVcCommon ( ExitCode = Regs->ExceptionData; switch (ExitCode) { + case SvmExitIoioProt: + NaeExit = IoioExit; + break; + default: - Status = VmgExit (Ghcb, SvmExitUnsupported, ExitCode, 0); - if (Status == 0) { - Regs->ExceptionData = 0; - VcRet = GP_EXCEPTION; + NaeExit = UnsupportedExit; + } + + InitInstructionData (&InstructionData, Ghcb, Regs); + + Status = NaeExit (Ghcb, Regs, &InstructionData); + if (Status == 0) { + Regs->Rip += InstructionLength (&InstructionData); + VcRet = 0; + } else { + GHCB_EVENT_INJECTION Event; + + Event.Uint64 = Status; + if (Event.Elements.ErrorCodeValid) { + Regs->ExceptionData = Event.Elements.ErrorCode; } else { - GHCB_EVENT_INJECTION Event; - - Event.Uint64 = Status; - if (Event.Elements.ErrorCodeValid) { - Regs->ExceptionData = Event.Elements.ErrorCode; - } else { - Regs->ExceptionData = 0; - } - - VcRet = Event.Elements.Vector; + Regs->ExceptionData = 0; } + + VcRet = Event.Elements.Vector; } VmgDone (Ghcb); -- 2.17.1