From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by mx.groups.io with SMTP id smtpd.web11.33103.1601899647336050598 for ; Mon, 05 Oct 2020 05:07:27 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@akeo-ie.20150623.gappssmtp.com header.s=20150623 header.b=Plz0n7MT; spf=pass (domain: akeo.ie, ip: 209.85.128.67, mailfrom: pete@akeo.ie) Received: by mail-wm1-f67.google.com with SMTP id y15so8524497wmi.0 for ; Mon, 05 Oct 2020 05:07:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=S47QjvbJb7dTzjWub8nuEJjdCcWJKxGILwXUxgsd2Co=; b=Plz0n7MT6q3/fGpx/EN3Mxbd+QX18TgUUuUYdPw/JpqR7FbILuq2xzVsiVgDiOKhvc jPEKFHxPx47+On52YTARehU6ueeW7lco2THdnOov8xJEKLFRr3wYnDXpeyWmjbjGKTe3 R9bRQB6nWd9sNrwXSflTB1/58b1b57NP11kqQQsRqWg9MkvOq0h1yZcpkGRPyynW0LKi WLx44rSQmj4X/HvQr9FIc7RnKfaayxzdSIVNzKwuWgxh/shLFXO230H5O0SziycjUBE3 UA+5LXWgqN4gE7UFzrUF7J6p+qm12plQSGGr5NXjKd0kSwa7tJ75CleUjw/s6+NLBXaA F2+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=S47QjvbJb7dTzjWub8nuEJjdCcWJKxGILwXUxgsd2Co=; b=FplXdDUG60VPnRKIXFzBycgCojsfnQGwuSzXPFYoumuUHCgleLQjZcm1uYt7jQJLCu Z2ajWOkYTB1gFfhAd+ye7tkveIlDQxNQ6AHX9y5yIXIrGrvsXwodXHP/diWWsXD0fEmz TWneae99eKWTU/+ifc9bxJFjlLwTUEXgJLmlLSFp+G974NTNcqOyko+zc91GsBcWZJpY mXuUHXJRrk3v/Lc5R2swn/TBpt8Z9Xiy55h3CJzZA4B2/PT9eCXKBL362TU6qxRki4v4 kJcA0896H0Eqf4LQqS6Wi7D60Mbz3BvLjUQqZEefj2hSnkFumuRnx5hxcrTtCxGhC1rg t1CQ== X-Gm-Message-State: AOAM532G+yU1dg7/NZCOQFi/ehJpAP7avUyMe/i2Nnf9V0G7I+qPtTAP 67/zXLZXGn2cbEGvWkxLIOBBJQ== X-Google-Smtp-Source: ABdhPJwSePvw8Lr+Am1Dg1rRnJRiRKcoj3w+Ri07SSyM7646gBUOZyFX+OM5ExidI5twThjVXweT3Q== X-Received: by 2002:a7b:c10c:: with SMTP id w12mr161834wmi.175.1601899645620; Mon, 05 Oct 2020 05:07:25 -0700 (PDT) Return-Path: Received: from [10.0.0.122] ([84.203.75.189]) by smtp.googlemail.com with ESMTPSA id s11sm12697369wrt.43.2020.10.05.05.07.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Oct 2020 05:07:24 -0700 (PDT) Subject: Re: [edk2-devel] [PATCH v1 1/1] Platform/RaspberryPi/ConfigDxe: Fix JTAG Pinout for Pi3/4 To: Samer El-Haj-Mahmoud , "devel@edk2.groups.io" , "Andrei Warkentin (awarkentin@vmware.com)" , Jeff Booher-Kaeding Cc: Ard Biesheuvel , Leif Lindholm References: <20200914213230.78282-1-jeff.booher-kaeding@arm.com> From: "Pete Batard" Message-ID: <3e9fb07b-a330-6a3a-0e0e-2221819c5483@akeo.ie> Date: Mon, 5 Oct 2020 13:07:23 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.12.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 8bit With Andrei's reply, that's an RB for me: On 2020.09.29 15:01, Samer El-Haj-Mahmoud wrote: > Thanks Pete and Andrei. Should we count these as RB or AB for the patch? > > Reviewed-by: Samer El-Haj-Mahmoud > > *From:* devel@edk2.groups.io *On Behalf Of > *Andrei Warkentin via groups.io > *Sent:* Monday, September 21, 2020 4:01 PM > *To:* Pete Batard ; Jeff Booher-Kaeding > ; devel@edk2.groups.io > *Cc:* Ard Biesheuvel ; Leif Lindholm > > *Subject:* Re: [edk2-devel] [PATCH v1 1/1] > Platform/RaspberryPi/ConfigDxe: Fix JTAG Pinout for Pi3/4 > > Hi folks, > > No objection at all. IIRC the original pin selection was driven by an > article I read about using OpenOCD with Pi 3. > > A > > ------------------------------------------------------------------------ > > *From:*Pete Batard > > *Sent:* Tuesday, September 15, 2020 7:26 AM > *To:* Jeff Booher-Kaeding >; devel@edk2.groups.io > > > *Cc:* Ard Biesheuvel >; Leif Lindholm >; Andrei Warkentin > > *Subject:* Re: [PATCH v1 1/1] Platform/RaspberryPi/ConfigDxe: Fix JTAG > Pinout for Pi3/4 > > Copying Andrei on this, as the existing JTAG pinout is not technically > incorrect, since GPIO pin 4 can be used for TDI in ALT5 mode, and we are > using the relevant ALT mode in the existing code. See > https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsysprogs.com%2FVisualKernel%2Ftutorials%2Fraspberry%2Fjtagsetup%2F&data=02%7C01%7Cawarkentin%40vmware.com%7C1c1badf5e6f1433b44b508d859728a32%7Cb39138ca3cee4b4aa4d6cd83d9dd62f0%7C0%7C0%7C637357695767996220&sdata=rGIzM4Io36gFJrAK%2F4xZs0fm0DpXVvamhOYYXfc09ek%3D&reserved=0 > > As far as I'm concerned, I think it makes sense to use the same ALT mode > and have all the JTAG pins grouped, but I'd like to confirm whether we > deliberately chose not to use GPIO 26 in order to leave it available for > some other purpose, before I approve this patch. > > If Andrei says he's okay with it, then I see no objection to this change. > > Regards, > > /Pete > > On 2020.09.14 22:32, Jeff Booher-Kaeding wrote: > > Updated the pinout to match the Pi4 datasheet, tested with the RPi4, > Pi3 Datasheet has same pinout. > > > > Signed-off-by: Jeff Booher-Kaeding > > > > > Cc: Ard Biesheuvel > > > Cc: Leif Lindholm > > > Cc: Pete Batard > > > --- > >   Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +++--- > >   1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c > b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c > > index ac1004fe1836..6e793efb8227 100644 > > --- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c > > +++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c > > @@ -502,7 +502,7 @@ ApplyVariables ( > >      * 1           VREF        N/A               1 > > > >      * 3           nTRST       GPIO22    ALT4    15 > > > >      * 4           GND         N/A               9 > > > > -   * 5           TDI         GPIO4     ALT5    7 > > > > +   * 5           TDI         GPIO26    ALT4    37 > > > >      * 7           TMS         GPIO27    ALT4    13 > > > >      * 9           TCK         GPIO25    ALT4    22 > > > >      * 11          RTCK        GPIO23    ALT4    16 > > > > @@ -510,14 +510,14 @@ ApplyVariables ( > >      */ > > > >     if (PcdGet32 (PcdDebugEnableJTAG)) { > > > >       GpioPinFuncSet (22, GPIO_FSEL_ALT4); > > > > -    GpioPinFuncSet (4, GPIO_FSEL_ALT5); > > > > +    GpioPinFuncSet (26, GPIO_FSEL_ALT4); > > > >       GpioPinFuncSet (27, GPIO_FSEL_ALT4); > > > >       GpioPinFuncSet (25, GPIO_FSEL_ALT4); > > > >       GpioPinFuncSet (23, GPIO_FSEL_ALT4); > > > >       GpioPinFuncSet (24, GPIO_FSEL_ALT4); > > > >     } else { > > > >       GpioPinFuncSet (22, GPIO_FSEL_INPUT); > > > > -    GpioPinFuncSet (4, GPIO_FSEL_INPUT); > > > > +    GpioPinFuncSet (26, GPIO_FSEL_INPUT); > > > >       GpioPinFuncSet (27, GPIO_FSEL_INPUT); > > > >       GpioPinFuncSet (25, GPIO_FSEL_INPUT); > > > >       GpioPinFuncSet (23, GPIO_FSEL_INPUT); > > Reviewed-by: Pete Batard