From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id A679BD806DA for ; Tue, 26 Sep 2023 08:25:05 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=NR8Vkmm5YdWFltQdJY8/vXmMeJ1lmpCQDzIyxaliqSs=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1695716704; v=1; b=MIuViKR6DlKneQ2oCDnTKhxWKP2KG7e54N5WzcWJ05Q/zseQqqpVMLi+G1nM8DAZK0JIXV1f rZR7ynbHufTU1AmWHcx5HxcUwi3bn3j1i03mRwhF5ROmyi1lzexmulET+C0KVACj8/J1E6NGTB6 yhAAUSDFPTPVgiFdb9dZlRUY= X-Received: by 127.0.0.2 with SMTP id 1greYY7687511xSNSx4HWLQL; Tue, 26 Sep 2023 01:25:04 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web10.14331.1695716703204759610 for ; Tue, 26 Sep 2023 01:25:03 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="360895014" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="360895014" X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2023 01:25:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="748738543" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="748738543" X-Received: from gaocheng-desk.ccr.corp.intel.com ([10.239.154.170]) by orsmga002.jf.intel.com with ESMTP; 26 Sep 2023 01:24:59 -0700 From: "Gao" To: devel@edk2.groups.io Cc: Gao Cheng , Hao A Wu , Ray Ni , Jian J Wang , Liming Gao Subject: [edk2-devel] [PATCH v2] MdeModulePkg/Xhci: Skip size round up for TRB during address translation Date: Tue, 26 Sep 2023 16:24:49 +0800 Message-ID: <3f126940d742db17c161127670de2f933ae62789.1695716554.git.gao.cheng@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gao.cheng@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: yjp66V7khH12yOnDLJNDrpo3x7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=MIuViKR6; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none) REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4560=0D =0D TRB Template is 16 bytes. When boundary checking is 64 bytes for xHCI=0D device/host memory address, it may exceed xHCI host memory pool and=0D cause unwanted DXE_ASSERT. Introduce a new input parameter to indicate=0D whether to enforce 64byte size alignment and round up. For TRB case,=0D should set it to FALSE to skip the size round up.=0D =0D Signed-off-by: Gao Cheng =0D Cc: Hao A Wu =0D Cc: Ray Ni =0D Cc: Jian J Wang =0D Cc: Liming Gao =0D ---=0D MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c | 24 ++++++++---=0D MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h | 8 +++-=0D MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 54 +++++++++++++-----------=0D MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c | 24 ++++++++---=0D MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h | 8 +++-=0D MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 48 +++++++++++----------=0D 6 files changed, 103 insertions(+), 63 deletions(-)=0D =0D diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c b/MdeModulePkg/Bus/Pci= /XhciDxe/UsbHcMem.c=0D index d0ad1582e4..b54187ec22 100644=0D --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c=0D +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c=0D @@ -226,6 +226,7 @@ UsbHcAllocMemFromBlock (=0D @param Pool The memory pool of the host controller.=0D @param Mem The pointer to host memory.=0D @param Size The size of the memory region.=0D + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes.=0D =0D @return The pci memory address=0D =0D @@ -234,7 +235,8 @@ EFI_PHYSICAL_ADDRESS=0D UsbHcGetPciAddrForHostAddr (=0D IN USBHC_MEM_POOL *Pool,=0D IN VOID *Mem,=0D - IN UINTN Size=0D + IN UINTN Size,=0D + IN BOOLEAN Alignment=0D )=0D {=0D USBHC_MEM_BLOCK *Head;=0D @@ -243,8 +245,12 @@ UsbHcGetPciAddrForHostAddr (=0D EFI_PHYSICAL_ADDRESS PhyAddr;=0D UINTN Offset;=0D =0D - Head =3D Pool->Head;=0D - AllocSize =3D USBHC_MEM_ROUND (Size);=0D + Head =3D Pool->Head;=0D + if (Alignment) {=0D + AllocSize =3D USBHC_MEM_ROUND (Size);=0D + } else {=0D + AllocSize =3D Size;=0D + }=0D =0D if (Mem =3D=3D NULL) {=0D return 0;=0D @@ -275,6 +281,7 @@ UsbHcGetPciAddrForHostAddr (=0D @param Pool The memory pool of the host controller.=0D @param Mem The pointer to pci memory.=0D @param Size The size of the memory region.=0D + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes.=0D =0D @return The host memory address=0D =0D @@ -283,7 +290,8 @@ EFI_PHYSICAL_ADDRESS=0D UsbHcGetHostAddrForPciAddr (=0D IN USBHC_MEM_POOL *Pool,=0D IN VOID *Mem,=0D - IN UINTN Size=0D + IN UINTN Size,=0D + IN BOOLEAN Alignment=0D )=0D {=0D USBHC_MEM_BLOCK *Head;=0D @@ -292,8 +300,12 @@ UsbHcGetHostAddrForPciAddr (=0D EFI_PHYSICAL_ADDRESS HostAddr;=0D UINTN Offset;=0D =0D - Head =3D Pool->Head;=0D - AllocSize =3D USBHC_MEM_ROUND (Size);=0D + Head =3D Pool->Head;=0D + if (Alignment) {=0D + AllocSize =3D USBHC_MEM_ROUND (Size);=0D + } else {=0D + AllocSize =3D Size;=0D + }=0D =0D if (Mem =3D=3D NULL) {=0D return 0;=0D diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h b/MdeModulePkg/Bus/Pci= /XhciDxe/UsbHcMem.h=0D index c85b0b919f..b21bf9da3e 100644=0D --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h=0D +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h=0D @@ -129,6 +129,7 @@ UsbHcFreeMem (=0D @param Pool The memory pool of the host controller.=0D @param Mem The pointer to host memory.=0D @param Size The size of the memory region.=0D + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes.=0D =0D @return The pci memory address=0D =0D @@ -137,7 +138,8 @@ EFI_PHYSICAL_ADDRESS=0D UsbHcGetPciAddrForHostAddr (=0D IN USBHC_MEM_POOL *Pool,=0D IN VOID *Mem,=0D - IN UINTN Size=0D + IN UINTN Size,=0D + IN BOOLEAN Alignment=0D );=0D =0D /**=0D @@ -146,6 +148,7 @@ UsbHcGetPciAddrForHostAddr (=0D @param Pool The memory pool of the host controller.=0D @param Mem The pointer to pci memory.=0D @param Size The size of the memory region.=0D + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes.=0D =0D @return The host memory address=0D =0D @@ -154,7 +157,8 @@ EFI_PHYSICAL_ADDRESS=0D UsbHcGetHostAddrForPciAddr (=0D IN USBHC_MEM_POOL *Pool,=0D IN VOID *Mem,=0D - IN UINTN Size=0D + IN UINTN Size,=0D + IN BOOLEAN Alignment=0D );=0D =0D /**=0D diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pc= i/XhciDxe/XhciSched.c=0D index 53421e64a8..c2be171780 100644=0D --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c=0D +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c=0D @@ -588,7 +588,7 @@ XhcInitSched (=0D // Some 3rd party XHCI external cards don't support single 64-bytes widt= h register access,=0D // So divide it to two 32-bytes width register access.=0D //=0D - DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries);= =0D + DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries, T= RUE);=0D XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy));=0D XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy));=0D =0D @@ -607,7 +607,7 @@ XhcInitSched (=0D // So we set RCS as inverted PCS init value to let Command Ring empty=0D //=0D CmdRing =3D (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;=0D - CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)= CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);=0D + CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID *)(UINTN)= CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER, TRUE);=0D ASSERT ((CmdRingPhy & 0x3F) =3D=3D 0);=0D CmdRingPhy |=3D XHC_CRCR_RCS;=0D //=0D @@ -809,7 +809,7 @@ CreateEventRing (=0D EventRing->EventRingDequeue =3D (TRB_TEMPLATE *)EventRing->EventRingSeg0= ;=0D EventRing->EventRingEnqueue =3D (TRB_TEMPLATE *)EventRing->EventRingSeg0= ;=0D =0D - DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);=0D + DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, TRUE= );=0D =0D //=0D // Software maintains an Event Ring Consumer Cycle State (CCS) bit, init= ializing it to '1'=0D @@ -829,7 +829,7 @@ CreateEventRing (=0D ERSTBase->PtrHi =3D XHC_HIGH_32BIT (DequeuePhy);=0D ERSTBase->RingTrbSize =3D EVENT_RING_TRB_NUMBER;=0D =0D - ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size);=0D + ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size, TR= UE);=0D =0D //=0D // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) regist= er (5.5.2.3.1)=0D @@ -913,7 +913,7 @@ CreateTransferRing (=0D //=0D EndTrb =3D (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (Trb= Num - 1));=0D EndTrb->Type =3D TRB_TYPE_LINK;=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof = (TRB_TEMPLATE) * TrbNum);=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof = (TRB_TEMPLATE) * TrbNum, TRUE);=0D EndTrb->PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D EndTrb->PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D //=0D @@ -1045,7 +1045,7 @@ IsTransferRingTrb (=0D if (CheckedTrb->Type =3D=3D TRB_TYPE_LINK) {=0D LinkTrb =3D (LINK_TRB *)CheckedTrb;=0D PhyAddr =3D (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((U= INT64)LinkTrb->PtrHi, 32));=0D - CheckedTrb =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xh= c->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));=0D + CheckedTrb =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xh= c->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE);=0D ASSERT (CheckedTrb =3D=3D Urb->Ring->RingSeg0);=0D }=0D }=0D @@ -1154,7 +1154,7 @@ XhcCheckUrbResult (=0D // Need convert pci device address to host address=0D //=0D PhyAddr =3D (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT= 64)EvtTrb->TRBPtrHi, 32));=0D - TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->Me= mPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));=0D + TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->Me= mPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE);=0D =0D //=0D // Update the status of URB including the pending URB, the URB that is= currently checked,=0D @@ -1259,7 +1259,7 @@ EXIT:=0D High =3D XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);=0D XhcDequeue =3D (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);=0D =0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.Eve= ntRingDequeue, sizeof (TRB_TEMPLATE));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.Eve= ntRingDequeue, sizeof (TRB_TEMPLATE), FALSE);=0D =0D if ((XhcDequeue & (~0x0F)) !=3D (PhyAddr & (~0x0F))) {=0D //=0D @@ -2280,7 +2280,8 @@ XhcInitializeDeviceSlot (=0D PhyAddr =3D UsbHcGetPciAddrForHostAddr (=0D Xhc->MemPool,=0D ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endpoint= TransferRing[0])->RingSeg0,=0D - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER=0D + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER,=0D + TRUE=0D );=0D InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0;=0D InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D @@ -2298,7 +2299,7 @@ XhcInitializeDeviceSlot (=0D // 7) Load the appropriate (Device Slot ID) entry in the Device Context = Base Address Array (5.4.6) with=0D // a pointer to the Output Device Context data structure (6.2.1).=0D //=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT), TRUE);=0D //=0D // Fill DCBAA with PCI device address=0D //=0D @@ -2313,7 +2314,7 @@ XhcInitializeDeviceSlot (=0D //=0D gBS->Stall (XHC_RESET_RECOVERY_DELAY);=0D ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT), TRUE);=0D CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbAddr.CycleBit =3D 1;=0D @@ -2496,7 +2497,8 @@ XhcInitializeDeviceSlot64 (=0D PhyAddr =3D UsbHcGetPciAddrForHostAddr (=0D Xhc->MemPool,=0D ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endpoint= TransferRing[0])->RingSeg0,=0D - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER=0D + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER,=0D + TRUE=0D );=0D InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0;=0D InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D @@ -2514,7 +2516,7 @@ XhcInitializeDeviceSlot64 (=0D // 7) Load the appropriate (Device Slot ID) entry in the Device Context = Base Address Array (5.4.6) with=0D // a pointer to the Output Device Context data structure (6.2.1).=0D //=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT_64));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT_64), TRUE);=0D //=0D // Fill DCBAA with PCI device address=0D //=0D @@ -2529,7 +2531,7 @@ XhcInitializeDeviceSlot64 (=0D //=0D gBS->Stall (XHC_RESET_RECOVERY_DELAY);=0D ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64), TRUE);=0D CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbAddr.CycleBit =3D 1;=0D @@ -2964,7 +2966,8 @@ XhcInitializeEndpointContext (=0D PhyAddr =3D UsbHcGetPciAddrForHostAddr (=0D Xhc->MemPool,=0D ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endpoi= ntTransferRing[Dci-1])->RingSeg0,=0D - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER=0D + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER,=0D + TRUE=0D );=0D PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F);=0D PhyAddr |=3D (EFI_PHYSICAL_ADDRESS)((TRANSFER_RIN= G *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS= ;=0D @@ -3166,7 +3169,8 @@ XhcInitializeEndpointContext64 (=0D PhyAddr =3D UsbHcGetPciAddrForHostAddr (=0D Xhc->MemPool,=0D ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endpoi= ntTransferRing[Dci-1])->RingSeg0,=0D - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER=0D + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER,=0D + TRUE=0D );=0D PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F);=0D PhyAddr |=3D (EFI_PHYSICAL_ADDRESS)((TRANSFER_RIN= G *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS= ;=0D @@ -3248,7 +3252,7 @@ XhcSetConfigCmd (=0D // configure endpoint=0D //=0D ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT), TRUE);=0D CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbCfgEP.CycleBit =3D 1;=0D @@ -3339,7 +3343,7 @@ XhcSetConfigCmd64 (=0D // configure endpoint=0D //=0D ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64), TRUE);=0D CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbCfgEP.CycleBit =3D 1;=0D @@ -3513,7 +3517,7 @@ XhcSetTrDequeuePointer (=0D // Send stop endpoint command to transit Endpoint from running to stop s= tate=0D //=0D ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->= Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->= Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE);=0D CmdSetTRDeq.PtrLo =3D XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;=0D CmdSetTRDeq.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdSetTRDeq.CycleBit =3D 1;=0D @@ -3713,7 +3717,7 @@ XhcSetInterface (=0D // 5) Issue and successfully complete a Configure Endpoint Command.=0D //=0D ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Inp= utContext, sizeof (INPUT_CONTEXT));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Inp= utContext, sizeof (INPUT_CONTEXT), TRUE);=0D CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbCfgEP.CycleBit =3D 1;=0D @@ -3919,7 +3923,7 @@ XhcSetInterface64 (=0D // 5) Issue and successfully complete a Configure Endpoint Command.=0D //=0D ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Inp= utContext, sizeof (INPUT_CONTEXT_64));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Inp= utContext, sizeof (INPUT_CONTEXT_64), TRUE);=0D CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbCfgEP.CycleBit =3D 1;=0D @@ -3986,7 +3990,7 @@ XhcEvaluateContext (=0D InputContext->EP[0].EPState =3D 0;=0D =0D ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT), TRUE);=0D CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbEvalu.CycleBit =3D 1;=0D @@ -4047,7 +4051,7 @@ XhcEvaluateContext64 (=0D InputContext->EP[0].EPState =3D 0;=0D =0D ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64), TRUE);=0D CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbEvalu.CycleBit =3D 1;=0D @@ -4116,7 +4120,7 @@ XhcConfigHubContext (=0D InputContext->Slot.MTT =3D MTT;=0D =0D ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT), TRUE);=0D CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbCfgEP.CycleBit =3D 1;=0D @@ -4185,7 +4189,7 @@ XhcConfigHubContext64 (=0D InputContext->Slot.MTT =3D MTT;=0D =0D ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64), TRUE);=0D CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbCfgEP.CycleBit =3D 1;=0D diff --git a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c b/MdeModulePkg/Bus/Pci= /XhciPei/UsbHcMem.c=0D index e779a31138..88db5fe46e 100644=0D --- a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c=0D +++ b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c=0D @@ -190,6 +190,7 @@ UsbHcAllocMemFromBlock (=0D @param Pool The memory pool of the host controller.=0D @param Mem The pointer to host memory.=0D @param Size The size of the memory region.=0D + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes.=0D =0D @return The pci memory address=0D =0D @@ -198,7 +199,8 @@ EFI_PHYSICAL_ADDRESS=0D UsbHcGetPciAddrForHostAddr (=0D IN USBHC_MEM_POOL *Pool,=0D IN VOID *Mem,=0D - IN UINTN Size=0D + IN UINTN Size,=0D + IN BOOLEAN Alignment=0D )=0D {=0D USBHC_MEM_BLOCK *Head;=0D @@ -207,8 +209,12 @@ UsbHcGetPciAddrForHostAddr (=0D EFI_PHYSICAL_ADDRESS PhyAddr;=0D UINTN Offset;=0D =0D - Head =3D Pool->Head;=0D - AllocSize =3D USBHC_MEM_ROUND (Size);=0D + Head =3D Pool->Head;=0D + if (Alignment) {=0D + AllocSize =3D USBHC_MEM_ROUND (Size);=0D + } else {=0D + AllocSize =3D Size;=0D + }=0D =0D if (Mem =3D=3D NULL) {=0D return 0;=0D @@ -239,6 +245,7 @@ UsbHcGetPciAddrForHostAddr (=0D @param Pool The memory pool of the host controller.=0D @param Mem The pointer to pci memory.=0D @param Size The size of the memory region.=0D + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes.=0D =0D @return The host memory address=0D =0D @@ -247,7 +254,8 @@ EFI_PHYSICAL_ADDRESS=0D UsbHcGetHostAddrForPciAddr (=0D IN USBHC_MEM_POOL *Pool,=0D IN VOID *Mem,=0D - IN UINTN Size=0D + IN UINTN Size,=0D + IN BOOLEAN Alignment=0D )=0D {=0D USBHC_MEM_BLOCK *Head;=0D @@ -256,8 +264,12 @@ UsbHcGetHostAddrForPciAddr (=0D EFI_PHYSICAL_ADDRESS HostAddr;=0D UINTN Offset;=0D =0D - Head =3D Pool->Head;=0D - AllocSize =3D USBHC_MEM_ROUND (Size);=0D + Head =3D Pool->Head;=0D + if (Alignment) {=0D + AllocSize =3D USBHC_MEM_ROUND (Size);=0D + } else {=0D + AllocSize =3D Size;=0D + }=0D =0D if (Mem =3D=3D NULL) {=0D return 0;=0D diff --git a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h b/MdeModulePkg/Bus/Pci= /XhciPei/UsbHcMem.h=0D index 2b4c8b19fc..8f760e084e 100644=0D --- a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h=0D +++ b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h=0D @@ -68,6 +68,7 @@ typedef struct _USBHC_MEM_POOL {=0D @param Pool The memory pool of the host controller.=0D @param Mem The pointer to host memory.=0D @param Size The size of the memory region.=0D + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes.=0D =0D @return The pci memory address=0D =0D @@ -76,7 +77,8 @@ EFI_PHYSICAL_ADDRESS=0D UsbHcGetPciAddrForHostAddr (=0D IN USBHC_MEM_POOL *Pool,=0D IN VOID *Mem,=0D - IN UINTN Size=0D + IN UINTN Size,=0D + IN BOOLEAN Alignment=0D );=0D =0D /**=0D @@ -85,6 +87,7 @@ UsbHcGetPciAddrForHostAddr (=0D @param Pool The memory pool of the host controller.=0D @param Mem The pointer to pci memory.=0D @param Size The size of the memory region.=0D + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes.=0D =0D @return The host memory address=0D =0D @@ -93,7 +96,8 @@ EFI_PHYSICAL_ADDRESS=0D UsbHcGetHostAddrForPciAddr (=0D IN USBHC_MEM_POOL *Pool,=0D IN VOID *Mem,=0D - IN UINTN Size=0D + IN UINTN Size,=0D + IN BOOLEAN Alignment=0D );=0D =0D /**=0D diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pc= i/XhciPei/XhciSched.c=0D index 8400c90f7a..53272f62dd 100644=0D --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c=0D +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c=0D @@ -675,7 +675,7 @@ XhcPeiCheckUrbResult (=0D // Need convert pci device address to host address=0D //=0D PhyAddr =3D (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT= 64)EvtTrb->TRBPtrHi, 32));=0D - TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->Me= mPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE));=0D + TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc->Me= mPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE);=0D =0D //=0D // Update the status of Urb according to the finished event regardless= of whether=0D @@ -766,7 +766,7 @@ EXIT:=0D High =3D XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);=0D XhcDequeue =3D (UINT64)(LShiftU64 ((UINT64)High, 32) | Low);=0D =0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.Eve= ntRingDequeue, sizeof (TRB_TEMPLATE));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->EventRing.Eve= ntRingDequeue, sizeof (TRB_TEMPLATE), FALSE);=0D =0D if ((XhcDequeue & (~0x0F)) !=3D (PhyAddr & (~0x0F))) {=0D //=0D @@ -1213,7 +1213,8 @@ XhcPeiInitializeDeviceSlot (=0D PhyAddr =3D UsbHcGetPciAddrForHostAddr (=0D Xhc->MemPool,=0D ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endpoint= TransferRing[0])->RingSeg0,=0D - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER=0D + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER,=0D + TRUE=0D );=0D InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0;=0D InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D @@ -1231,7 +1232,7 @@ XhcPeiInitializeDeviceSlot (=0D // 7) Load the appropriate (Device Slot ID) entry in the Device Context = Base Address Array (5.4.6) with=0D // a pointer to the Output Device Context data structure (6.2.1).=0D //=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT), TRUE);=0D //=0D // Fill DCBAA with PCI device address=0D //=0D @@ -1246,7 +1247,7 @@ XhcPeiInitializeDeviceSlot (=0D //=0D MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);=0D ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT), TRUE);=0D CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbAddr.CycleBit =3D 1;=0D @@ -1427,7 +1428,8 @@ XhcPeiInitializeDeviceSlot64 (=0D PhyAddr =3D UsbHcGetPciAddrForHostAddr (=0D Xhc->MemPool,=0D ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endpoint= TransferRing[0])->RingSeg0,=0D - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER=0D + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER,=0D + TRUE=0D );=0D InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0;=0D InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D @@ -1445,7 +1447,7 @@ XhcPeiInitializeDeviceSlot64 (=0D // 7) Load the appropriate (Device Slot ID) entry in the Device Context = Base Address Array (5.4.6) with=0D // a pointer to the Output Device Context data structure (6.2.1).=0D //=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT_64));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, siz= eof (DEVICE_CONTEXT_64), TRUE);=0D //=0D // Fill DCBAA with PCI device address=0D //=0D @@ -1460,7 +1462,7 @@ XhcPeiInitializeDeviceSlot64 (=0D //=0D MicroSecondDelay (XHC_RESET_RECOVERY_DELAY);=0D ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->U= sbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64), TRUE);=0D CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbAddr.CycleBit =3D 1;=0D @@ -1882,7 +1884,8 @@ XhcPeiSetConfigCmd (=0D PhyAddr =3D UsbHcGetPciAddrForHostAddr (=0D Xhc->MemPool,=0D ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endp= ointTransferRing[Dci-1])->RingSeg0,=0D - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER=0D + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER,=0D + TRUE=0D );=0D PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F);=0D PhyAddr |=3D (EFI_PHYSICAL_ADDRESS)((TRANSFER_R= ING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingP= CS;=0D @@ -1901,7 +1904,7 @@ XhcPeiSetConfigCmd (=0D // configure endpoint=0D //=0D ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT), TRUE);=0D CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbCfgEP.CycleBit =3D 1;=0D @@ -2108,7 +2111,8 @@ XhcPeiSetConfigCmd64 (=0D PhyAddr =3D UsbHcGetPciAddrForHostAddr (=0D Xhc->MemPool,=0D ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].Endp= ointTransferRing[Dci-1])->RingSeg0,=0D - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER=0D + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER,=0D + TRUE=0D );=0D =0D PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F);=0D @@ -2129,7 +2133,7 @@ XhcPeiSetConfigCmd64 (=0D // configure endpoint=0D //=0D ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64), TRUE);=0D CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbCfgEP.CycleBit =3D 1;=0D @@ -2184,7 +2188,7 @@ XhcPeiEvaluateContext (=0D InputContext->EP[0].MaxPacketSize =3D MaxPacketSize;=0D =0D ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT), TRUE);=0D CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbEvalu.CycleBit =3D 1;=0D @@ -2239,7 +2243,7 @@ XhcPeiEvaluateContext64 (=0D InputContext->EP[0].MaxPacketSize =3D MaxPacketSize;=0D =0D ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64), TRUE);=0D CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbEvalu.CycleBit =3D 1;=0D @@ -2308,7 +2312,7 @@ XhcPeiConfigHubContext (=0D InputContext->Slot.MTT =3D MTT;=0D =0D ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT), TRUE);=0D CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbCfgEP.CycleBit =3D 1;=0D @@ -2377,7 +2381,7 @@ XhcPeiConfigHubContext64 (=0D InputContext->Slot.MTT =3D MTT;=0D =0D ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Input= Context, sizeof (INPUT_CONTEXT_64), TRUE);=0D CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdTrbCfgEP.CycleBit =3D 1;=0D @@ -2522,7 +2526,7 @@ XhcPeiSetTrDequeuePointer (=0D // Send stop endpoint command to transit Endpoint from running to stop s= tate=0D //=0D ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->= Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->= Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE);=0D CmdSetTRDeq.PtrLo =3D XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;=0D CmdSetTRDeq.PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D CmdSetTRDeq.CycleBit =3D 1;=0D @@ -2682,7 +2686,7 @@ XhcPeiCreateEventRing (=0D ASSERT (((UINTN)Buf & 0x3F) =3D=3D 0);=0D ZeroMem (Buf, Size);=0D =0D - DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);=0D + DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, TRUE= );=0D =0D EventRing->EventRingSeg0 =3D Buf;=0D EventRing->TrbNumber =3D EVENT_RING_TRB_NUMBER;=0D @@ -2707,7 +2711,7 @@ XhcPeiCreateEventRing (=0D ERSTBase->PtrHi =3D XHC_HIGH_32BIT (DequeuePhy);=0D ERSTBase->RingTrbSize =3D EVENT_RING_TRB_NUMBER;=0D =0D - ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size);=0D + ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, TRUE);= =0D =0D //=0D // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) regist= er (5.5.2.3.1)=0D @@ -2855,7 +2859,7 @@ XhcPeiCreateTransferRing (=0D //=0D EndTrb =3D (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (Trb= Num - 1));=0D EndTrb->Type =3D TRB_TYPE_LINK;=0D - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof = (TRB_TEMPLATE) * TrbNum);=0D + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeof = (TRB_TEMPLATE) * TrbNum, TRUE);=0D EndTrb->PtrLo =3D XHC_LOW_32BIT (PhyAddr);=0D EndTrb->PtrHi =3D XHC_HIGH_32BIT (PhyAddr);=0D //=0D @@ -2988,7 +2992,7 @@ XhcPeiInitSched (=0D // Some 3rd party XHCI external cards don't support single 64-bytes widt= h register access,=0D // So divide it to two 32-bytes width register access.=0D //=0D - DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Size);=0D + DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Size, TRUE= );=0D XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy));=0D XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (DcbaaPhy))= ;=0D =0D @@ -3006,7 +3010,7 @@ XhcPeiInitSched (=0D // Transfer Ring it checks for a Cycle bit transition. If a transition d= etected, the ring is empty.=0D // So we set RCS as inverted PCS init value to let Command Ring empty=0D //=0D - CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->CmdRing.Ri= ngSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER);=0D + CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->CmdRing.Ri= ngSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER, TRUE);=0D ASSERT ((CmdRingPhy & 0x3F) =3D=3D 0);=0D CmdRingPhy |=3D XHC_CRCR_RCS;=0D //=0D -- =0D 2.42.0.windows.2=0D =0D -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109065): https://edk2.groups.io/g/devel/message/109065 Mute This Topic: https://groups.io/mt/101591675/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-