From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (EUR04-VI1-obe.outbound.protection.outlook.com [40.107.8.49]) by mx.groups.io with SMTP id smtpd.web10.25608.1669301547292415951 for ; Thu, 24 Nov 2022 06:52:27 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=7J7ikV7+; spf=pass (domain: arm.com, ip: 40.107.8.49, mailfrom: sami.mujawar@arm.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=oAio/LxtxeAJC+nXzBUiPMDuFmyJ1m89MTieZXrWycY=; b=7J7ikV7+oAz0ZzybEE3RJB4KHoMZSc/Rowf38HDmtr5WS0mRwW3QRrFhYjUOgtU0n99fi5F+CWHNALxaoMbgX58nxYDD7/BO83VN6Bt8uK79m5IUdBKXawPi0PUkjeE33z752MONMjUL8G4M5rPTOXVolnn416D7fk/v+2UK2VM= Received: from AS9PR07CA0022.eurprd07.prod.outlook.com (2603:10a6:20b:46c::34) by PA4PR08MB6272.eurprd08.prod.outlook.com (2603:10a6:102:ef::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.19; Thu, 24 Nov 2022 14:52:18 +0000 Received: from VI1EUR03FT042.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:46c:cafe::5c) by AS9PR07CA0022.outlook.office365.com (2603:10a6:20b:46c::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.19 via Frontend Transport; Thu, 24 Nov 2022 14:52:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by VI1EUR03FT042.mail.protection.outlook.com (100.127.144.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.19 via Frontend Transport; Thu, 24 Nov 2022 14:52:18 +0000 Received: ("Tessian outbound 2ff13c8f2c05:v130"); Thu, 24 Nov 2022 14:52:17 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: e0bf8fbdbf49fa1c X-CR-MTA-TID: 64aa7808 Received: from 1b2db320ea61.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 5F8AEA37-3F73-40A5-B7A4-DB0DDDA709ED.1; Thu, 24 Nov 2022 14:52:05 +0000 Received: from EUR05-DB8-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 1b2db320ea61.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 24 Nov 2022 14:52:05 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Rc5VSBN1xJJZxZp9ZjhpemR10fENmAjmNhZNKwrYRoYfuE2PVbWLWCx6Ec3IMRC/90Kc6nhTEZvcyBIJ9k6vHBN8kbwCHLWT5y2hAfK9TEoRp/0BR89G+hRi6lOIhTyhT6Qn/OQz7jmxqYUxzsSjGOJwt1Zi3E37fqH78q3xK6o5/ck4el2VVkjujeDrRw7XncHqTZS7maEiBFzLQU6c+hs+NmuJ+RflPhxFu3r9U0wzvKSXCqb1JHWZBIL57EqOBGLwDElxqXIlbwl3IELoJJ+yU3prsQTzzJosZeY4XGFJTATOjug1MZeMDqVoa0mm/JlEzyVr29cA3EZFiA2tPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=oAio/LxtxeAJC+nXzBUiPMDuFmyJ1m89MTieZXrWycY=; b=azsKeictU1ZKx3anWYDQzVhUm/5sHuN4p/ZSB6/PWQgyUpBqnWTPsLYqaCeA5mL9ZcAek5XFzNTXuFLRM5RlGG2IugNd2GnGmCAFGbVjkQQom7YonJkpU8ZveYVVqO81PfYX2OlwBbCcRD5FbyLjjAcsnVd4cm2PaMvd1e1xcXt2wX7R1YU40EIdQ0ySXeJs7QXJTWsrbX2YqGSZD0UIwWvJU96w+wT0Ma+QhPj/R7J5WN54p8BBI0bwV3vfv8VskfOJ6QUxURUtj1awF33FZ74yrD/rLItVa7vs9IRDp+GjMfFMgkxvIb+UO3qY93oWQxHKRyhE4n2t3mFZlDDoNg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=oAio/LxtxeAJC+nXzBUiPMDuFmyJ1m89MTieZXrWycY=; b=7J7ikV7+oAz0ZzybEE3RJB4KHoMZSc/Rowf38HDmtr5WS0mRwW3QRrFhYjUOgtU0n99fi5F+CWHNALxaoMbgX58nxYDD7/BO83VN6Bt8uK79m5IUdBKXawPi0PUkjeE33z752MONMjUL8G4M5rPTOXVolnn416D7fk/v+2UK2VM= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from AS8PR08MB6806.eurprd08.prod.outlook.com (2603:10a6:20b:39b::12) by AM0PR08MB5475.eurprd08.prod.outlook.com (2603:10a6:208:188::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.19; Thu, 24 Nov 2022 14:52:03 +0000 Received: from AS8PR08MB6806.eurprd08.prod.outlook.com ([fe80::eca2:349c:4dbf:7f10]) by AS8PR08MB6806.eurprd08.prod.outlook.com ([fe80::eca2:349c:4dbf:7f10%8]) with mapi id 15.20.5857.019; Thu, 24 Nov 2022 14:52:03 +0000 Message-ID: <40e22f09-d7de-bd40-dd1f-9e0d9e29238c@arm.com> Date: Thu, 24 Nov 2022 14:52:02 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [edk2-devel] [PATCH 1/1] ArmPlatformPkg: Remove AP support from PrePi/PrePeiCore To: Rebecca Cran , Leif Lindholm , Ard Biesheuvel , Thomas Abraham CC: devel@edk2.groups.io, quic_rcran@quicinc.com, Ard Biesheuvel , "nd@arm.com" References: <20221027173121.754041-1-rebecca@quicinc.com> <1a0045d6-d826-ab1d-4297-cac91ca7cac9@quicinc.com> From: "Sami Mujawar" In-Reply-To: <1a0045d6-d826-ab1d-4297-cac91ca7cac9@quicinc.com> X-ClientProxiedBy: LO4P123CA0458.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1aa::13) To AS8PR08MB6806.eurprd08.prod.outlook.com (2603:10a6:20b:39b::12) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: AS8PR08MB6806:EE_|AM0PR08MB5475:EE_|VI1EUR03FT042:EE_|PA4PR08MB6272:EE_ X-MS-Office365-Filtering-Correlation-Id: f25c289e-4efc-4be2-e7ad-08dace2b7bc4 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: Wj2+tQfFENy/wA1BzqMMl8G5IJJIhVvTQLFZqWdCizaJJ5WBk6YYzTHzXIbsJaxGSiqvLxwu3HKL4Yra8TkhgVW97GXr/NsKy+rnWyN+IMHlCcrW+Zu214YxSm/FOA6zoC8KjHHVRLymLJjg/tLeYi4jtyMk7sV2bhqEuJBTwAQTTXEaI8RLWxc0PbN9Eky48BkulAtSRcnO2vttj2Au4FLOxS40g8UQSNg8a87YByUi0nckP8b6fILsT01cZ94y5swHxsJ6Y2BEq7YWNOkw6pk+e/TtFK6jefBTqwjG1zUBWYyxZMNEikphlrw095ZqFmvwJJXMdccxSBExNvkoyzm8z2cQyTprsBJjUCGlEma9twWZBCFgmVeuXa6uSdyhZlOHSGgqqX57w3ZgIRsj2eHkYfTXFsO0qkjF7j6khM7lbQROD3gzrz9Y50QTOLmDdLCBToAFOnLZlQjVMtw1kDRk7SRVXzeFP5l7BHcpcF1MCXBRVcO75pvF0+zdCwLNnBWVVHU98QXoju66kxbgyasf4Kw6/9LQJLKhUkbquyXG+rpqUg09Pn74k2DTRMBcCc/bhjjvns425Ythf6vkrd8sJfYRQ4+YMSOUjgoobpFsPHhS51IgasNVRCiOxXDEegCUdZuojygcohU0wTQ3KW4BQoHLPBHXVvwY7Fmluowf0ozwpCYoc5RAH8VOoN5dB+IGqpFWNnDdPWppmioO6lWs3KN3L21TmJv/Bpq8EsGi7pyPvLGV298PbmqtQdT86CFOlIyPfSOUFxJUe03Ty7sKC2gWwtVUzS9/YLBKXso= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AS8PR08MB6806.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(396003)(136003)(376002)(366004)(451199015)(4326008)(8676002)(66946007)(66476007)(66556008)(8936002)(44832011)(30864003)(5660300002)(83380400001)(41300700001)(36756003)(31696002)(86362001)(26005)(6512007)(6506007)(478600001)(6486002)(53546011)(966005)(186003)(2616005)(6636002)(316002)(110136005)(2906002)(54906003)(31686004)(66899015)(38100700002)(45980500001)(43740500002);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB5475 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Return-Path: Sami.Mujawar@arm.com X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: VI1EUR03FT042.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 85a3c743-db0f-43ac-900e-08dace2b7316 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ow2mwm5JZjby3aXYtIPsZUCygIKpB+gbORgABkdgIusN5BgRJvN3Na9xBVwLbqJv1DLSr9C02Lsk4u40x0y7N/uKEJ4Fnjdp+Gv+rJzHK9iDhYJuO6yg9yLR0ucWZ8WWI3ne50ryM92IZYTEaeb1BP2ER6SfJuC6A3LZTwe5+BYzcvMCMLwn2Y9ONDm8bNlAVz/YoZYDmKKtCRAhCNOPt7CFjB1j9sD++YggiWWL25/KQpgmn0a1OPxZmJiBI1PdxpIkqbHG6m25Xalir9CF5O6zlFGGcjCzRMDGMPHrJaFzg9xs0cSB49132fmfTVo5Jyx91lrHiz5gRQSlFk79q1kjGcLzPM8Q6M+oOvik4nlTgMDn3yru+X6YVmK3gV9+P27PttckBlhA+o0YkufxcqbrPz4gO/EcF9VoK8HZ2FqW05KuMWL2JNXvIZ/LmXdkR/MtNiQOytColuDDR62cMmG0aAcpYko+pD41VB5ednXa9OBke7PGI30i6Gau9W1Ew3hJfia2znIw5T9frMJfyv6zd4C7oob/9tdq/gwHuG2EskaOI+POfJLmDcKdpM31z0u1+WmW0Ro5SMxjmu/hKysfFZGSmPdbfezZaNNDZoQerCtJdtdjPgHA+8GUFs2BLssGN//4BgYMhStBYk5nLhbXn6wA8U0HwvnbIyYQIdfupjwM8S1BDTsdIgAHdUxqPzLTvU6cc3MxGjMhF6xoywVk3VysPKT1sMoZuQE1FL65PKAnW8gq0yDq7X5ibFBhmkTZdUx1IOt0kJFA4KX2N1ZCfGnDFUqHRlaGuGjvWhg= X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(396003)(376002)(136003)(451199015)(46966006)(36840700001)(40470700004)(186003)(336012)(47076005)(2616005)(6512007)(30864003)(44832011)(53546011)(6506007)(82310400005)(5660300002)(41300700001)(36756003)(26005)(8936002)(31696002)(86362001)(316002)(54906003)(110136005)(6636002)(8676002)(6486002)(4326008)(40460700003)(966005)(478600001)(70586007)(70206006)(36860700001)(66899015)(2906002)(31686004)(356005)(40480700001)(81166007)(83380400001)(82740400003)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2022 14:52:18.0201 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f25c289e-4efc-4be2-e7ad-08dace2b7bc4 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR03FT042.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB6272 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Hi Leif, Rebecca, Apologies for the delay in getting back. We can drop the TC2 support in edk2-platforms. Regards, Sami Mujawar On 18/11/2022 02:09 pm, Rebecca Cran wrote: > Hi Sami, > > I was wondering if you could answer Leif's question? > > Thanks. > Rebecca Cran > > On 10/28/22 03:17, Leif Lindholm wrote: >> On Thu, Oct 27, 2022 at 20:10:33 +0200, Ard Biesheuvel wrote: >>> On Thu, 27 Oct 2022 at 19:31, Rebecca Cran =20 >>> wrote: >>>> >>>> Modern platforms use TF-A, so there's no need for support of >>>> secondary cores in EDK2 since TF-A will keep them in a holding >>>> pen until the PSCI_CPU_ON SMC call is received. >>>> >>>> Therefore, remove the code that handles secondary CPUs from >>>> PrePeiCore and PrePi and add ASSERTs if a secondary core >>>> reaches the functions. >>>> >>>> Signed-off-by: Rebecca Cran >>> >>> No objections to this patch, but this change will break the old SMP >>> 32-bit ARM platforms in edk2-platforms so you will need to propose a >>> solution for those as well. >> >> I think TC2 is the last one of those standing. And I don't see much >> value in keeping all of this around for such a niche (and old) >> platform. If someone ports TF-A to it, we could always add it back in >> later. >> >> Single-core non-PSCI platforms (i.e. beagleboard) aren't affected. >> >> Sami: would you be OK with deleting the TC2 support in edk2-platforms? >> >> / >> =C2=A0=C2=A0=C2=A0=C2=A0 Leif >> >>>> --- >>>> =C2=A0 ArmPlatformPkg/PrePeiCore/MainMPCore.c=C2=A0 | 92 -------------= ------- >>>> =C2=A0 ArmPlatformPkg/PrePeiCore/MainUniCore.c |=C2=A0 9 -- >>>> =C2=A0 ArmPlatformPkg/PrePeiCore/PrePeiCore.c=C2=A0 | 37 ++++---- >>>> =C2=A0 ArmPlatformPkg/PrePi/MainMPCore.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 | 69 --------------- >>>> =C2=A0 ArmPlatformPkg/PrePi/MainUniCore.c=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 |=C2=A0 9 -- >>>> =C2=A0 ArmPlatformPkg/PrePi/PrePi.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 36 ++++---- >>>> =C2=A0 6 files changed, 34 insertions(+), 218 deletions(-) >>>> >>>> diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c=20 >>>> b/ArmPlatformPkg/PrePeiCore/MainMPCore.c >>>> index b5d0d3a6442f..44850a4f3946 100644 >>>> --- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c >>>> +++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c >>>> @@ -12,98 +12,6 @@ >>>> >>>> =C2=A0 #include "PrePeiCore.h" >>>> >>>> -/* >>>> - * This is the main function for secondary cores. They loop around=20 >>>> until a non Null value is written to >>>> - * SYS_FLAGS register.The SYS_FLAGS register is platform specific. >>>> - * Note:The secondary cores, while executing secondary_main,=20 >>>> assumes that: >>>> - *=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : SGI 0 is configured as Non-secure = interrupt >>>> - *=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : Priority Mask is configured to all= ow SGI 0 >>>> - *=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : Interrupt Distributor and CPU inte= rfaces are enabled >>>> - * >>>> - */ >>>> -VOID >>>> -EFIAPI >>>> -SecondaryMain ( >>>> -=C2=A0 IN UINTN=C2=A0 MpId >>>> -=C2=A0 ) >>>> -{ >>>> -=C2=A0 EFI_STATUS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 Status; >>>> -=C2=A0 UINTN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 PpiListSize; >>>> -=C2=A0 UINTN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 PpiListCount; >>>> -=C2=A0 EFI_PEI_PPI_DESCRIPTOR=C2=A0 *PpiList; >>>> -=C2=A0 ARM_MP_CORE_INFO_PPI=C2=A0=C2=A0=C2=A0 *ArmMpCoreInfoPpi; >>>> -=C2=A0 UINTN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Index; >>>> -=C2=A0 UINTN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmCoreCount; >>>> -=C2=A0 ARM_CORE_INFO=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 *ArmCoreInfoTable; >>>> -=C2=A0 UINT32=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ClusterId; >>>> -=C2=A0 UINT32=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CoreId; >>>> - >>>> -=C2=A0 VOID=C2=A0 (*SecondaryStart)( >>>> -=C2=A0=C2=A0=C2=A0 VOID >>>> -=C2=A0=C2=A0=C2=A0 ); >>>> -=C2=A0 UINTN=C2=A0 SecondaryEntryAddr; >>>> -=C2=A0 UINTN=C2=A0 AcknowledgeInterrupt; >>>> -=C2=A0 UINTN=C2=A0 InterruptId; >>>> - >>>> -=C2=A0 ClusterId =3D GET_CLUSTER_ID (MpId); >>>> -=C2=A0 CoreId=C2=A0=C2=A0=C2=A0 =3D GET_CORE_ID (MpId); >>>> - >>>> -=C2=A0 // Get the gArmMpCoreInfoPpiGuid >>>> -=C2=A0 PpiListSize =3D 0; >>>> -=C2=A0 ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList); >>>> -=C2=A0 PpiListCount =3D PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR)= ; >>>> -=C2=A0 for (Index =3D 0; Index < PpiListCount; Index++, PpiList++) { >>>> -=C2=A0=C2=A0=C2=A0 if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpi= Guid) =3D=3D=20 >>>> TRUE) { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break; >>>> -=C2=A0=C2=A0=C2=A0 } >>>> -=C2=A0 } >>>> - >>>> -=C2=A0 // On MP Core Platform we must implement the ARM MP Core Info = PPI >>>> -=C2=A0 ASSERT (Index !=3D PpiListCount); >>>> - >>>> -=C2=A0 ArmMpCoreInfoPpi =3D PpiList->Ppi; >>>> -=C2=A0 ArmCoreCount=C2=A0=C2=A0=C2=A0=C2=A0 =3D 0; >>>> -=C2=A0 Status=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 =3D ArmMpCoreInfoPpi->GetMpCoreInfo=20 >>>> (&ArmCoreCount, &ArmCoreInfoTable); >>>> -=C2=A0 ASSERT_EFI_ERROR (Status); >>>> - >>>> -=C2=A0 // Find the core in the ArmCoreTable >>>> -=C2=A0 for (Index =3D 0; Index < ArmCoreCount; Index++) { >>>> -=C2=A0=C2=A0=C2=A0 if ((GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr= ) =3D=3D=20 >>>> ClusterId) && >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (GET_MPIDR_AFF0 (ArmCoreIn= foTable[Index].Mpidr) =3D=3D CoreId)) >>>> -=C2=A0=C2=A0=C2=A0 { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break; >>>> -=C2=A0=C2=A0=C2=A0 } >>>> -=C2=A0 } >>>> - >>>> -=C2=A0 // The ARM Core Info Table must define every core >>>> -=C2=A0 ASSERT (Index !=3D ArmCoreCount); >>>> - >>>> -=C2=A0 // Clear Secondary cores MailBox >>>> -=C2=A0 MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress,=20 >>>> ArmCoreInfoTable[Index].MailboxClearValue); >>>> - >>>> -=C2=A0 do { >>>> -=C2=A0=C2=A0=C2=A0 ArmCallWFI (); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Read the Mailbox >>>> -=C2=A0=C2=A0=C2=A0 SecondaryEntryAddr =3D MmioRead32=20 >>>> (ArmCoreInfoTable[Index].MailboxGetAddress); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Acknowledge the interrupt and send End of Inter= rupt signal. >>>> -=C2=A0=C2=A0=C2=A0 AcknowledgeInterrupt =3D ArmGicAcknowledgeInterrup= t (PcdGet64=20 >>>> (PcdGicInterruptInterfaceBase), &InterruptId); >>>> -=C2=A0=C2=A0=C2=A0 // Check if it is a valid interrupt ID >>>> -=C2=A0=C2=A0=C2=A0 if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGe= t64=20 >>>> (PcdGicDistributorBase))) { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Got a valid SGI number hence signal= End of Interrupt >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmGicEndOfInterrupt (PcdGet64=20 >>>> (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt); >>>> -=C2=A0=C2=A0=C2=A0 } >>>> -=C2=A0 } while (SecondaryEntryAddr =3D=3D 0); >>>> - >>>> -=C2=A0 // Jump to secondary core entry point. >>>> -=C2=A0 SecondaryStart =3D (VOID (*)()) SecondaryEntryAddr; >>>> -=C2=A0 SecondaryStart (); >>>> - >>>> -=C2=A0 // The secondaries shouldn't reach here >>>> -=C2=A0 ASSERT (FALSE); >>>> -} >>>> - >>>> =C2=A0 VOID >>>> =C2=A0 EFIAPI >>>> =C2=A0 PrimaryMain ( >>>> diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c=20 >>>> b/ArmPlatformPkg/PrePeiCore/MainUniCore.c >>>> index 1c2580eb923b..3d3c6caaa32a 100644 >>>> --- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c >>>> +++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c >>>> @@ -8,15 +8,6 @@ >>>> >>>> =C2=A0 #include "PrePeiCore.h" >>>> >>>> -VOID >>>> -EFIAPI >>>> -SecondaryMain ( >>>> -=C2=A0 IN UINTN=C2=A0 MpId >>>> -=C2=A0 ) >>>> -{ >>>> -=C2=A0 ASSERT (FALSE); >>>> -} >>>> - >>>> =C2=A0 VOID >>>> =C2=A0 EFIAPI >>>> =C2=A0 PrimaryMain ( >>>> diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c=20 >>>> b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c >>>> index 42a7ccc9c6a0..64d1ef601ea3 100644 >>>> --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c >>>> +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c >>>> @@ -117,27 +117,26 @@ CEntryPoint ( >>>> >>>> =C2=A0=C2=A0=C2=A0 // Note: The MMU will be enabled by MemoryPeim. Onl= y the=20 >>>> primary core will have the MMU on. >>>> >>>> -=C2=A0 // If not primary Jump to Secondary Main >>>> -=C2=A0 if (ArmPlatformIsPrimaryCore (MpId)) { >>>> -=C2=A0=C2=A0=C2=A0 // Invoke "ProcessLibraryConstructorList" to have = all library=20 >>>> constructors >>>> -=C2=A0=C2=A0=C2=A0 // called. >>>> -=C2=A0=C2=A0=C2=A0 ProcessLibraryConstructorList (); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 PrintFirmwareVersion (); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Initialize the Debug Agent for Source Level Deb= ugging >>>> -=C2=A0=C2=A0=C2=A0 InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC= , NULL, NULL); >>>> -=C2=A0=C2=A0=C2=A0 SaveAndSetDebugTimerInterrupt (TRUE); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Initialize the platform specific controllers >>>> -=C2=A0=C2=A0=C2=A0 ArmPlatformInitialize (MpId); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Goto primary Main. >>>> -=C2=A0=C2=A0=C2=A0 PrimaryMain (PeiCoreEntryPoint); >>>> -=C2=A0 } else { >>>> -=C2=A0=C2=A0=C2=A0 SecondaryMain (MpId); >>>> +=C2=A0 if (!ArmPlatformIsPrimaryCore (MpId)) { >>>> +=C2=A0=C2=A0=C2=A0 ASSERT (FALSE); >>>> =C2=A0=C2=A0=C2=A0 } >>>> >>>> +=C2=A0 // Invoke "ProcessLibraryConstructorList" to have all library= =20 >>>> constructors >>>> +=C2=A0 // called. >>>> +=C2=A0 ProcessLibraryConstructorList (); >>>> + >>>> +=C2=A0 PrintFirmwareVersion (); >>>> + >>>> +=C2=A0 // Initialize the Debug Agent for Source Level Debugging >>>> +=C2=A0 InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL= ); >>>> +=C2=A0 SaveAndSetDebugTimerInterrupt (TRUE); >>>> + >>>> +=C2=A0 // Initialize the platform specific controllers >>>> +=C2=A0 ArmPlatformInitialize (MpId); >>>> + >>>> +=C2=A0 // Goto primary Main. >>>> +=C2=A0 PrimaryMain (PeiCoreEntryPoint); >>>> + >>>> =C2=A0=C2=A0=C2=A0 // PEI Core should always load and never return >>>> =C2=A0=C2=A0=C2=A0 ASSERT (FALSE); >>>> =C2=A0 } >>>> diff --git a/ArmPlatformPkg/PrePi/MainMPCore.c=20 >>>> b/ArmPlatformPkg/PrePi/MainMPCore.c >>>> index 68a7c13298d0..ce7058a2846f 100644 >>>> --- a/ArmPlatformPkg/PrePi/MainMPCore.c >>>> +++ b/ArmPlatformPkg/PrePi/MainMPCore.c >>>> @@ -33,72 +33,3 @@ PrimaryMain ( >>>> =C2=A0=C2=A0=C2=A0 // We must never return >>>> =C2=A0=C2=A0=C2=A0 ASSERT (FALSE); >>>> =C2=A0 } >>>> - >>>> -VOID >>>> -SecondaryMain ( >>>> -=C2=A0 IN=C2=A0 UINTN=C2=A0 MpId >>>> -=C2=A0 ) >>>> -{ >>>> -=C2=A0 EFI_STATUS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 Status; >>>> -=C2=A0 ARM_MP_CORE_INFO_PPI=C2=A0 *ArmMpCoreInfoPpi; >>>> -=C2=A0 UINTN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Index; >>>> -=C2=A0 UINTN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmCoreCount; >>>> -=C2=A0 ARM_CORE_INFO=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = *ArmCoreInfoTable; >>>> -=C2=A0 UINT32=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ClusterId; >>>> -=C2=A0 UINT32=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CoreId; >>>> - >>>> -=C2=A0 VOID=C2=A0 (*SecondaryStart)( >>>> -=C2=A0=C2=A0=C2=A0 VOID >>>> -=C2=A0=C2=A0=C2=A0 ); >>>> -=C2=A0 UINTN=C2=A0 SecondaryEntryAddr; >>>> -=C2=A0 UINTN=C2=A0 AcknowledgeInterrupt; >>>> -=C2=A0 UINTN=C2=A0 InterruptId; >>>> - >>>> -=C2=A0 ClusterId =3D GET_CLUSTER_ID (MpId); >>>> -=C2=A0 CoreId=C2=A0=C2=A0=C2=A0 =3D GET_CORE_ID (MpId); >>>> - >>>> -=C2=A0 // On MP Core Platform we must implement the ARM MP Core Info= =20 >>>> PPI (gArmMpCoreInfoPpiGuid) >>>> -=C2=A0 Status =3D GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID=20 >>>> **)&ArmMpCoreInfoPpi); >>>> -=C2=A0 ASSERT_EFI_ERROR (Status); >>>> - >>>> -=C2=A0 ArmCoreCount =3D 0; >>>> -=C2=A0 Status=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D ArmMpCoreInfoPp= i->GetMpCoreInfo (&ArmCoreCount,=20 >>>> &ArmCoreInfoTable); >>>> -=C2=A0 ASSERT_EFI_ERROR (Status); >>>> - >>>> -=C2=A0 // Find the core in the ArmCoreTable >>>> -=C2=A0 for (Index =3D 0; Index < ArmCoreCount; Index++) { >>>> -=C2=A0=C2=A0=C2=A0 if ((GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr= ) =3D=3D=20 >>>> ClusterId) && >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (GET_MPIDR_AFF0 (ArmCoreIn= foTable[Index].Mpidr) =3D=3D CoreId)) >>>> -=C2=A0=C2=A0=C2=A0 { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break; >>>> -=C2=A0=C2=A0=C2=A0 } >>>> -=C2=A0 } >>>> - >>>> -=C2=A0 // The ARM Core Info Table must define every core >>>> -=C2=A0 ASSERT (Index !=3D ArmCoreCount); >>>> - >>>> -=C2=A0 // Clear Secondary cores MailBox >>>> -=C2=A0 MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress,=20 >>>> ArmCoreInfoTable[Index].MailboxClearValue); >>>> - >>>> -=C2=A0 do { >>>> -=C2=A0=C2=A0=C2=A0 ArmCallWFI (); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Read the Mailbox >>>> -=C2=A0=C2=A0=C2=A0 SecondaryEntryAddr =3D MmioRead32=20 >>>> (ArmCoreInfoTable[Index].MailboxGetAddress); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Acknowledge the interrupt and send End of Inter= rupt signal. >>>> -=C2=A0=C2=A0=C2=A0 AcknowledgeInterrupt =3D ArmGicAcknowledgeInterrup= t (PcdGet64=20 >>>> (PcdGicInterruptInterfaceBase), &InterruptId); >>>> -=C2=A0=C2=A0=C2=A0 // Check if it is a valid interrupt ID >>>> -=C2=A0=C2=A0=C2=A0 if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGe= t64=20 >>>> (PcdGicDistributorBase))) { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Got a valid SGI number hence signal= End of Interrupt >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmGicEndOfInterrupt (PcdGet64=20 >>>> (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt); >>>> -=C2=A0=C2=A0=C2=A0 } >>>> -=C2=A0 } while (SecondaryEntryAddr =3D=3D 0); >>>> - >>>> -=C2=A0 // Jump to secondary core entry point. >>>> -=C2=A0 SecondaryStart =3D (VOID (*)()) SecondaryEntryAddr; >>>> -=C2=A0 SecondaryStart (); >>>> - >>>> -=C2=A0 // The secondaries shouldn't reach here >>>> -=C2=A0 ASSERT (FALSE); >>>> -} >>>> diff --git a/ArmPlatformPkg/PrePi/MainUniCore.c=20 >>>> b/ArmPlatformPkg/PrePi/MainUniCore.c >>>> index 6162d1241f84..7449facacd51 100644 >>>> --- a/ArmPlatformPkg/PrePi/MainUniCore.c >>>> +++ b/ArmPlatformPkg/PrePi/MainUniCore.c >>>> @@ -20,12 +20,3 @@ PrimaryMain ( >>>> =C2=A0=C2=A0=C2=A0 // We must never return >>>> =C2=A0=C2=A0=C2=A0 ASSERT (FALSE); >>>> =C2=A0 } >>>> - >>>> -VOID >>>> -SecondaryMain ( >>>> -=C2=A0 IN=C2=A0 UINTN=C2=A0 MpId >>>> -=C2=A0 ) >>>> -{ >>>> -=C2=A0 // We must never get into this function on UniCore system >>>> -=C2=A0 ASSERT (FALSE); >>>> -} >>>> diff --git a/ArmPlatformPkg/PrePi/PrePi.c=20 >>>> b/ArmPlatformPkg/PrePi/PrePi.c >>>> index 9b127b94a67c..60061b8b6963 100644 >>>> --- a/ArmPlatformPkg/PrePi/PrePi.c >>>> +++ b/ArmPlatformPkg/PrePi/PrePi.c >>>> @@ -177,7 +177,11 @@ CEntryPoint ( >>>> =C2=A0=C2=A0=C2=A0 // Initialize the platform specific controllers >>>> =C2=A0=C2=A0=C2=A0 ArmPlatformInitialize (MpId); >>>> >>>> -=C2=A0 if (ArmPlatformIsPrimaryCore (MpId) &&=20 >>>> PerformanceMeasurementEnabled ()) { >>>> +=C2=A0 if (!ArmPlatformIsPrimaryCore (MpId)) { >>>> +=C2=A0=C2=A0=C2=A0 ASSERT (FALSE); >>>> +=C2=A0 } >>>> + >>>> +=C2=A0 if (PerformanceMeasurementEnabled ()) { >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Initialize the Timer Library to setu= p the Timer HW controller >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 TimerConstructor (); >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // We cannot call yet the PerformanceLi= b because the HOB List=20 >>>> has not been initialized >>>> @@ -195,29 +199,21 @@ CEntryPoint ( >>>> >>>> =C2=A0=C2=A0=C2=A0 // Define the Global Variable region when we are no= t running in=20 >>>> XIP >>>> =C2=A0=C2=A0=C2=A0 if (!IS_XIP ()) { >>>> -=C2=A0=C2=A0=C2=A0 if (ArmPlatformIsPrimaryCore (MpId)) { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (ArmIsMpCore ()) { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Signal the Global Varia= ble Region is defined (event:=20 >>>> ARM_CPU_EVENT_DEFAULT) >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmCallSEV (); >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >>>> -=C2=A0=C2=A0=C2=A0 } else { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Wait the Primary core has defined t= he address of the=20 >>>> Global Variable region (event: ARM_CPU_EVENT_DEFAULT) >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmCallWFE (); >>>> +=C2=A0=C2=A0=C2=A0 if (ArmIsMpCore ()) { >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Signal the Global Variable Region i= s defined (event:=20 >>>> ARM_CPU_EVENT_DEFAULT) >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmCallSEV (); >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >>>> =C2=A0=C2=A0=C2=A0 } >>>> >>>> -=C2=A0 // If not primary Jump to Secondary Main >>>> -=C2=A0 if (ArmPlatformIsPrimaryCore (MpId)) { >>>> -=C2=A0=C2=A0=C2=A0 InvalidateDataCacheRange ( >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (VOID *)UefiMemoryBase, >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 FixedPcdGet32 (PcdSystemMemoryUefiRegi= onSize) >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ); >>>> +=C2=A0 InvalidateDataCacheRange ( >>>> +=C2=A0=C2=A0=C2=A0 (VOID *)UefiMemoryBase, >>>> +=C2=A0=C2=A0=C2=A0 FixedPcdGet32 (PcdSystemMemoryUefiRegionSize) >>>> +=C2=A0=C2=A0=C2=A0 ); >>>> >>>> -=C2=A0=C2=A0=C2=A0 // Goto primary Main. >>>> -=C2=A0=C2=A0=C2=A0 PrimaryMain (UefiMemoryBase, StacksBase, StartTime= Stamp); >>>> -=C2=A0 } else { >>>> -=C2=A0=C2=A0=C2=A0 SecondaryMain (MpId); >>>> -=C2=A0 } >>>> +=C2=A0 PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp); >>>> + >>>> +=C2=A0 // We must never return >>>> +=C2=A0 ASSERT (FALSE); >>>> >>>> =C2=A0=C2=A0=C2=A0 // DXE Core should always load and never return >>>> =C2=A0=C2=A0=C2=A0 ASSERT (FALSE); >>>> --=20 >>>> 2.30.2 >>>> >>>> >>>> >>>>=20 >>>> >>>>