From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AAC5781D2D for ; Fri, 20 Jan 2017 09:43:34 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx16.intmail.prod.int.phx2.redhat.com [10.5.11.28]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2DF2480469; Fri, 20 Jan 2017 17:43:35 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-71.phx2.redhat.com [10.3.116.71]) by smtp.corp.redhat.com (Postfix) with ESMTP id AE3992112CA; Fri, 20 Jan 2017 17:43:33 +0000 (UTC) To: Ard Biesheuvel , edk2-devel@ml01.01.org References: <1484931946-11648-1-git-send-email-ard.biesheuvel@linaro.org> Cc: leif.lindholm@linaro.org, heyi.guo@linaro.org, ashedel@microsoft.com From: Laszlo Ersek Message-ID: <41af2323-60d6-e494-553e-270fae030c0e@redhat.com> Date: Fri, 20 Jan 2017 18:43:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.6.0 MIME-Version: 1.0 In-Reply-To: <1484931946-11648-1-git-send-email-ard.biesheuvel@linaro.org> X-Scanned-By: MIMEDefang 2.74 on 10.5.11.28 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Fri, 20 Jan 2017 17:43:35 +0000 (UTC) Subject: Re: [PATCH] ArmPkg/ArmMmuLib: Revert "use a pool allocation for the root table" X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2017 17:43:34 -0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit On 01/20/17 18:05, Ard Biesheuvel wrote: > This reverts commit d32702d2c2aa23e828363a7f88829b78ce36c3af. > > Using a pool allocation for the root translation table seemed like > a good idea at the time, but as it turns out, such allocations are > handled in a way that makes them unsuitable for this purpose: they > are backed by HOBs that don't remain in the same place during the > various PI phase changes, which means the address programmed into > the TTBR register is no longer valid, and may refer to memory that > is reported as available to the OS. > > So switch back to using a page based allocation. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 29 ++++---------------- > 1 file changed, 6 insertions(+), 23 deletions(-) Acked-by: Laszlo Ersek > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > index c78297084207..540069a59b2e 100644 > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > @@ -553,12 +553,10 @@ ArmConfigureMmu ( > ) > { > VOID* TranslationTable; > - VOID* TranslationTableBuffer; > UINT32 TranslationTableAttribute; > UINT64 MaxAddress; > UINTN T0SZ; > UINTN RootTableEntryCount; > - UINTN RootTableEntrySize; > UINT64 TCR; > RETURN_STATUS Status; > > @@ -643,19 +641,8 @@ ArmConfigureMmu ( > // Set TCR > ArmSetTCR (TCR); > > - // Allocate pages for translation table. Pool allocations are 8 byte aligned, > - // but we may require a higher alignment based on the size of the root table. > - RootTableEntrySize = RootTableEntryCount * sizeof(UINT64); > - if (RootTableEntrySize < EFI_PAGE_SIZE / 2) { > - TranslationTableBuffer = AllocatePool (2 * RootTableEntrySize - 8); > - // > - // Naturally align the root table. Preserves possible NULL value > - // > - TranslationTable = (VOID *)((UINTN)(TranslationTableBuffer - 1) | (RootTableEntrySize - 1)) + 1; > - } else { > - TranslationTable = AllocatePages (1); > - TranslationTableBuffer = NULL; > - } > + // Allocate pages for translation table > + TranslationTable = AllocatePages (1); > if (TranslationTable == NULL) { > return RETURN_OUT_OF_RESOURCES; > } > @@ -669,10 +656,10 @@ ArmConfigureMmu ( > } > > if (TranslationTableSize != NULL) { > - *TranslationTableSize = RootTableEntrySize; > + *TranslationTableSize = RootTableEntryCount * sizeof(UINT64); > } > > - ZeroMem (TranslationTable, RootTableEntrySize); > + ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); > > // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs > ArmDisableMmu (); > @@ -689,7 +676,7 @@ ArmConfigureMmu ( > DEBUG_CODE_BEGIN (); > // Find the memory attribute for the Translation Table > if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase && > - (UINTN)TranslationTable + RootTableEntrySize <= MemoryTable->PhysicalBase + > + (UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase + > MemoryTable->Length) { > TranslationTableAttribute = MemoryTable->Attributes; > } > @@ -718,11 +705,7 @@ ArmConfigureMmu ( > return RETURN_SUCCESS; > > FREE_TRANSLATION_TABLE: > - if (TranslationTableBuffer != NULL) { > - FreePool (TranslationTableBuffer); > - } else { > - FreePages (TranslationTable, 1); > - } > + FreePages (TranslationTable, 1); > return Status; > } > >