* [edk2-devel] [PATCH v2] ArmPkg/ProcessorSubClassDxe: Limit counts to 0xFF
@ 2024-02-06 15:24 Jeff Brasen via groups.io
2024-02-06 17:24 ` Sami Mujawar
0 siblings, 1 reply; 2+ messages in thread
From: Jeff Brasen via groups.io @ 2024-02-06 15:24 UTC (permalink / raw)
To: devel; +Cc: ardb+tianocore, quic_llindhol, sami.mujawar, Jeff Brasen
The CoreCount, EnabledCore and ThreadCount counts should be set to 0xFF
if value is greater than 255 per the SMBIOS specification.
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
---
.../ProcessorSubClassDxe/ProcessorSubClass.c | 42 +++++++++++++------
1 file changed, 30 insertions(+), 12 deletions(-)
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
index 9050588500..abb4c726de 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
@@ -702,19 +702,37 @@ AddSmbiosProcessorTypeTable (
LegacyVoltage = (UINT8 *)&Type4Record->Voltage;
- *LegacyVoltage = MiscProcessorData.Voltage;
- Type4Record->CurrentSpeed = MiscProcessorData.CurrentSpeed;
- Type4Record->MaxSpeed = MiscProcessorData.MaxSpeed;
- Type4Record->Status = ProcessorStatus.Data;
- Type4Record->L1CacheHandle = L1CacheHandle;
- Type4Record->L2CacheHandle = L2CacheHandle;
- Type4Record->L3CacheHandle = L3CacheHandle;
- Type4Record->CoreCount = MiscProcessorData.CoreCount;
- Type4Record->CoreCount2 = MiscProcessorData.CoreCount;
- Type4Record->EnabledCoreCount = MiscProcessorData.CoresEnabled;
+ *LegacyVoltage = MiscProcessorData.Voltage;
+ Type4Record->CurrentSpeed = MiscProcessorData.CurrentSpeed;
+ Type4Record->MaxSpeed = MiscProcessorData.MaxSpeed;
+ Type4Record->Status = ProcessorStatus.Data;
+ Type4Record->L1CacheHandle = L1CacheHandle;
+ Type4Record->L2CacheHandle = L2CacheHandle;
+ Type4Record->L3CacheHandle = L3CacheHandle;
+
+ if (MiscProcessorData.CoreCount > 255) {
+ Type4Record->CoreCount = 0xFF;
+ } else {
+ Type4Record->CoreCount = MiscProcessorData.CoreCount;
+ }
+
+ Type4Record->CoreCount2 = MiscProcessorData.CoreCount;
+
+ if (MiscProcessorData.CoresEnabled > 255) {
+ Type4Record->EnabledCoreCount = 0xFF;
+ } else {
+ Type4Record->EnabledCoreCount = MiscProcessorData.CoresEnabled;
+ }
+
Type4Record->EnabledCoreCount2 = MiscProcessorData.CoresEnabled;
- Type4Record->ThreadCount = MiscProcessorData.ThreadCount;
- Type4Record->ThreadCount2 = MiscProcessorData.ThreadCount;
+
+ if (MiscProcessorData.ThreadCount > 255) {
+ Type4Record->ThreadCount = 0xFF;
+ } else {
+ Type4Record->ThreadCount = MiscProcessorData.ThreadCount;
+ }
+
+ Type4Record->ThreadCount2 = MiscProcessorData.ThreadCount;
Type4Record->CurrentSpeed = GetCpuFrequency (ProcessorIndex);
Type4Record->ExternalClock =
--
2.34.1
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* Re: [edk2-devel] [PATCH v2] ArmPkg/ProcessorSubClassDxe: Limit counts to 0xFF
2024-02-06 15:24 [edk2-devel] [PATCH v2] ArmPkg/ProcessorSubClassDxe: Limit counts to 0xFF Jeff Brasen via groups.io
@ 2024-02-06 17:24 ` Sami Mujawar
0 siblings, 0 replies; 2+ messages in thread
From: Sami Mujawar @ 2024-02-06 17:24 UTC (permalink / raw)
To: Jeff Brasen (jbrasen@nvidia.com), devel@edk2.groups.io
Cc: ardb+tianocore@kernel.org, quic_llindhol@quicinc.com, nd
Hi Jeff,
Thank you for this patch.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Regards,
Sami Mujawar
On 06/02/2024, 15:25, "Jeff Brasen" <jbrasen@nvidia.com <mailto:jbrasen@nvidia.com>> wrote:
The CoreCount, EnabledCore and ThreadCount counts should be set to 0xFF
if value is greater than 255 per the SMBIOS specification.
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com <mailto:jbrasen@nvidia.com>>
---
.../ProcessorSubClassDxe/ProcessorSubClass.c | 42 +++++++++++++------
1 file changed, 30 insertions(+), 12 deletions(-)
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
index 9050588500..abb4c726de 100644
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
@@ -702,19 +702,37 @@ AddSmbiosProcessorTypeTable (
LegacyVoltage = (UINT8 *)&Type4Record->Voltage;
- *LegacyVoltage = MiscProcessorData.Voltage;
- Type4Record->CurrentSpeed = MiscProcessorData.CurrentSpeed;
- Type4Record->MaxSpeed = MiscProcessorData.MaxSpeed;
- Type4Record->Status = ProcessorStatus.Data;
- Type4Record->L1CacheHandle = L1CacheHandle;
- Type4Record->L2CacheHandle = L2CacheHandle;
- Type4Record->L3CacheHandle = L3CacheHandle;
- Type4Record->CoreCount = MiscProcessorData.CoreCount;
- Type4Record->CoreCount2 = MiscProcessorData.CoreCount;
- Type4Record->EnabledCoreCount = MiscProcessorData.CoresEnabled;
+ *LegacyVoltage = MiscProcessorData.Voltage;
+ Type4Record->CurrentSpeed = MiscProcessorData.CurrentSpeed;
+ Type4Record->MaxSpeed = MiscProcessorData.MaxSpeed;
+ Type4Record->Status = ProcessorStatus.Data;
+ Type4Record->L1CacheHandle = L1CacheHandle;
+ Type4Record->L2CacheHandle = L2CacheHandle;
+ Type4Record->L3CacheHandle = L3CacheHandle;
+
+ if (MiscProcessorData.CoreCount > 255) {
+ Type4Record->CoreCount = 0xFF;
+ } else {
+ Type4Record->CoreCount = MiscProcessorData.CoreCount;
+ }
+
+ Type4Record->CoreCount2 = MiscProcessorData.CoreCount;
+
+ if (MiscProcessorData.CoresEnabled > 255) {
+ Type4Record->EnabledCoreCount = 0xFF;
+ } else {
+ Type4Record->EnabledCoreCount = MiscProcessorData.CoresEnabled;
+ }
+
Type4Record->EnabledCoreCount2 = MiscProcessorData.CoresEnabled;
- Type4Record->ThreadCount = MiscProcessorData.ThreadCount;
- Type4Record->ThreadCount2 = MiscProcessorData.ThreadCount;
+
+ if (MiscProcessorData.ThreadCount > 255) {
+ Type4Record->ThreadCount = 0xFF;
+ } else {
+ Type4Record->ThreadCount = MiscProcessorData.ThreadCount;
+ }
+
+ Type4Record->ThreadCount2 = MiscProcessorData.ThreadCount;
Type4Record->CurrentSpeed = GetCpuFrequency (ProcessorIndex);
Type4Record->ExternalClock =
--
2.34.1
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