From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BD4071A1E2A for ; Wed, 26 Oct 2016 11:38:37 -0700 (PDT) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP; 26 Oct 2016 11:38:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,551,1473145200"; d="scan'208";a="23969621" Received: from mxma-desk2.amr.corp.intel.com ([134.134.155.154]) by fmsmga006.fm.intel.com with ESMTP; 26 Oct 2016 11:38:37 -0700 From: Maurice Ma To: edk2-devel@lists.01.org Cc: Maurice Ma , Prince Agyeman Date: Wed, 26 Oct 2016 11:38:32 -0700 Message-Id: <430a5a6d64bf24652bc077d0ca9c72fbd818b13f.1477507057.git.maurice.ma@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 Subject: [PATCH] CorebootPayloadPkg DSC: Change the section alignment option X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Oct 2016 18:38:37 -0000 The current CorebootPayloadPkg will print the following message "InsertImageRecord - Section Alignment(0x20) is not 4K" during boot. It is caused by the section alignment arranged by the linker. This patch change the alignment to 4K for runtime drivers. Cc: Prince Agyeman Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma --- CorebootPayloadPkg/CorebootPayloadPkg.fdf | 1 + CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 3 +++ CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 3 +++ 3 files changed, 7 insertions(+) diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf index d07fd30a103e..aa50db0e5699 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf +++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf @@ -60,6 +60,7 @@ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf [FV.DXEFV] BlockSize = 0x1000 +FvForceRebase = FALSE FvAlignment = 16 ERASE_POLARITY = 1 MEMORY_MAPPED = TRUE diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc index 435743329674..80d769be24e0 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc @@ -88,6 +88,9 @@ INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + ################################################################################ # # SKU Identification section - list of all SKU IDs supported by this Platform. diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 3ddc81b457ce..dbb8d151d09c 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -90,6 +90,9 @@ INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096 + ################################################################################ # # SKU Identification section - list of all SKU IDs supported by this Platform. -- 1.9.5.msysgit.0