From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 909B6740051 for ; Fri, 22 Sep 2023 08:56:11 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=T4+BzTCSVlxF2JjFkIl6qrqD26h9Mut2eHOIdXkbiPo=; c=relaxed/simple; d=groups.io; h=Message-ID:Date:MIME-Version:User-Agent:Subject:To:Cc:References:From:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1695372970; v=1; b=TXpekbeZVqlxPrEbrQshOZgPqO2rx1UTy8/WXW+P/K4Ks5nUvEB9Lwb7wkwyfcy/8WmPBPl3 CuC8LRaphGAyWIxTvNCgyMwU2G545QClMcaxEZOf60P39l3fsMX2GPzUi7RbPT+UNsDLsfuIQCm pygju3xIaHtxqfSs83Oyi3oU= X-Received: by 127.0.0.2 with SMTP id IIJRYY7687511x68W4K4RwX0; Fri, 22 Sep 2023 01:56:10 -0700 X-Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.16927.1695372969555338764 for ; Fri, 22 Sep 2023 01:56:09 -0700 X-Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 52A85DA7; Fri, 22 Sep 2023 01:56:46 -0700 (PDT) X-Received: from [10.34.100.121] (e126645.nice.arm.com [10.34.100.121]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E2A643F5A1; Fri, 22 Sep 2023 01:56:07 -0700 (PDT) Message-ID: <44022afe-c1bf-30af-cda3-15122dce8090@arm.com> Date: Fri, 22 Sep 2023 10:56:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [edk2-devel] [PATCH edk2-platforms v2 2/3] Platform/ARM: FVP: Specify TRBE interrupt in MADT GICC To: Sami Mujawar , devel@edk2.groups.io Cc: ardb+tianocore@kernel.org, thomas.abraham@arm.com, Anshuman.Khandual@arm.com, Matteo.Carlini@arm.com, Akanksha.Jain2@arm.com, Sibel.Allinson@arm.com, jeshuas@nvidia.com, nd@arm.com References: <20230913125247.34748-1-sami.mujawar@arm.com> <20230913125247.34748-3-sami.mujawar@arm.com> From: "PierreGondois" In-Reply-To: <20230913125247.34748-3-sami.mujawar@arm.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pierre.gondois@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: D359V4xiYwdtkNhLvc3kyKNgx7686176AA= Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=TXpekbeZ; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Hi Sami, On 9/13/23 14:52, Sami Mujawar wrote: > When TRBE is enabled the FVP model uses the PPI 15 > (i.e. INT ID 31) as the TRBE interrupt. > Ref: https://www.kernel.org/doc/Documentation/ > devicetree/bindings/arm/arm,trace-buffer-extension.yaml >=20 > Therefore, check the debug feature register > ID_AA64DFR0_EL1.TraceBuffer field to see if TRBE is > enabled and configure the TRBE interrupt in the GICC > structure in the MADT ACPI table. >=20 > Note: To enable TRBE support in the FVP REvC model > 1. Build TF-A with the CTX_INCLUDE_AARCH32_REGS=3D0 > build flag set, otherwise this results in an > exception when booting TF-A. > 2. Set the model parameters to enable TRBE > -C cluster0.has_trbe=3D1 -C cluster1.has_trbe=3D1 >=20 > Signed-off-by: Sami Mujawar > --- >=20 > Notes: > V2: > - Incorrect comment for TRBE interrupt number [Jeshua] > - Fixed comment to specify TRBE interrupt as [Sami] > PPI 15 > Ref: https://edk2.groups.io/g/devel/message/107426 >=20 > Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/C= onfigurationManager.c | 39 ++++++++++++++++---- > Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/C= onfigurationManagerDxe.inf | 3 +- > 2 files changed, 33 insertions(+), 9 deletions(-) >=20 > diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationM= anagerDxe/ConfigurationManager.c b/Platform/ARM/VExpressPkg/ConfigurationMa= nager/ConfigurationManagerDxe/ConfigurationManager.c > index 4df2d6cdae58df344804a8b41208a3adb8ee0110..221ccd44ca419edf030a0b37a= 6bbe64a1ab11273 100644 > --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerD= xe/ConfigurationManager.c > +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerD= xe/ConfigurationManager.c > @@ -1,7 +1,7 @@ > /** @file > Configuration Manager Dxe > =20 > - Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.
> + Copyright (c) 2017 - 2023, Arm Limited. All rights reserved.
> =20 > SPDX-License-Identifier: BSD-2-Clause-Patent > =20 > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -37,8 +38,8 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryIn= fo =3D { > { > // FADT Table > { > - EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, > - EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, > + EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, > + EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, > CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt), > NULL > }, > @@ -51,8 +52,8 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryIn= fo =3D { > }, > // MADT Table > { > - EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, > - EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, > + EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, > + EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, > CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt), > NULL > }, > @@ -109,15 +110,15 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatReposito= ryInfo =3D { > }, > =20 > // Boot architecture information > - { EFI_ACPI_6_3_ARM_PSCI_COMPLIANT }, // BootArchFlags > + { EFI_ACPI_6_5_ARM_PSCI_COMPLIANT }, // BootArchFlags > =20 > #ifdef HEADLESS_PLATFORM > // Fixed feature flag information > - { EFI_ACPI_6_3_HEADLESS }, // Fixed feature fla= gs > + { EFI_ACPI_6_5_HEADLESS }, // Fixed feature fla= gs > #endif > =20 > // Power management profile information > - { EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement P= rofile > + { EFI_ACPI_6_5_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement P= rofile > =20 > /* GIC CPU Interface information > GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, EnergyEffic= iency) > @@ -474,6 +475,9 @@ InitializePlatformRepository ( > ) > { > EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; > + UINT64 DbgFeatures; > + UINTN Index; > + UINT16 TrbeInterrupt; > =20 > PlatformRepo =3D This->PlatRepoInfo; > =20 > @@ -491,6 +495,25 @@ InitializePlatformRepository ( > PlatformRepo->GicCInfo[6].MPIDR =3D GET_MPID_MT (1, 2, 0); > PlatformRepo->GicCInfo[7].MPIDR =3D GET_MPID_MT (1, 3, 0); > } > + > + TrbeInterrupt =3D 0; > + DbgFeatures =3D ArmReadIdAA64Dfr0 (); > + DEBUG (( > + DEBUG_INFO, > + "Debug Feature Register 0 - ID_AA64DFR0_EL1 =3D 0x%lx\n", > + DbgFeatures > + )); > + > + // The ID_AA64DFR0_EL1.TraceBuffer field identifies support for FEAT_T= RBE. > + if (((DbgFeatures >> 44) & 0xF) !=3D 0) { Ideally I think we should add macros for these register flags instead of ha= rd-coded values like 44/0xF, same comment for: - [PATCH edk2-platforms v2 3/3] Platform/ARM: FVP: Add ETE device if suppor= ted by FVP Regards, Pierre -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108984): https://edk2.groups.io/g/devel/message/108984 Mute This Topic: https://groups.io/mt/101335889/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-