From mboxrd@z Thu Jan 1 00:00:00 1970 Subject: Re: [edk2-devel] MinPlatform Board port (GSoC 2021) To: Nate DeSimone ,devel@edk2.groups.io From: "Benjamin Doron" X-Originating-Location: Thornhill, Ontario, CA (24.52.200.135) X-Originating-Platform: Linux Firefox 87 User-Agent: GROUPS.IO Web Poster MIME-Version: 1.0 Date: Sat, 03 Apr 2021 21:45:12 -0700 References: In-Reply-To: Message-ID: <4406.1617511512854823562@groups.io> Content-Type: multipart/alternative; boundary="hwOoFKPNMN9CSArGB659" --hwOoFKPNMN9CSArGB659 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Wed, Mar 31, 2021 at 07:58 PM, Nate DeSimone wrote: >=20 >=20 >=20 > Hi Benjamin, >=20 >=20 >=20 >=20 >=20 >=20 >=20 > Great to meet you and welcome to the TianoCore project! Glad you hear yo= u > are interested! Doing a board port to the Acer Aspire VN7-572G laptop > sounds like a great GSoC project! I presume that since you already did a > coreboot port that boot guard is disabled on this laptop and you have > figured out how to flash images onto it =F0=9F=98=8A. >=20 >=20 Hi Nate, Nice to meet you too, and thanks! Yes, Boot Guard is disabled on this laptop (and fused, which is a slight s= hame). While SPI PRRs cover most of flash and BIOS control bits are partial= ly enabled by the vendor firmware (perhaps the lock wasn't set by default, = defeating the point), after one modification to the setup's (HII) IFR, thes= e can be disabled. Flashing externally is fairly straightforward - after th= e keyboard comes off the flash chip is visible - but I try to avoid it beca= use I've started having issues with the keyboard connector. It's fine once = it's in and closed again... >=20 >=20 >=20 > The only thing that might be a little challenging is getting a 2 nd copy= of > that laptop for your mentor, so the possibility exists that when it come= s > to debugging problems you might be a little more on your own than you > would be otherwise. I=E2=80=99m not too worried about that looking at yo= ur > CB:35523, it seems like you know what you are doing. >=20 >=20 ...but this might not be relevant to anyone after all. :-) Is that how this normally works? Who would organise it? (It sounds needles= sly expensive, for someone... *shrug*) >=20 >=20 >=20 > For sure our conventions and infrastructure are different, but there are > more parallels between MinPlatform and coreboot than might initially mee= t > the eye. For example: >=20 >=20 >=20 >=20 >=20 >=20 >=20 > BoardInitBeforeMemoryInit() is roughly equivalent to > bootblock_mainboard_init(). >=20 >=20 >=20 > BoardInitBeforeSiliconInit() is roughly equivalent to mainboard_init(). >=20 >=20 >=20 > SiliconPolicyUpdatePreMem() is roughly equivalent to > mainboard_memory_init_params(). >=20 >=20 >=20 >=20 >=20 >=20 >=20 > https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/K= abylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib= .c >=20 >=20 >=20 >=20 > https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/K= abylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPostMemLi= b.c >=20 >=20 >=20 >=20 > FSP Dispatch Mode Policy Init: https://github.com/tianocore/edk2-platfor= ms/blob/master/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Libr= ary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c > ( > https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/K= abylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/P= eiSiliconPolicyUpdateLib.c > ) >=20 >=20 >=20 > FSP API Mode Policy Init: https://github.com/tianocore/edk2-platforms/bl= ob/master/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Libra= ry/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c > ( > https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/K= abylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateL= ibFsp/PeiFspPolicyUpdateLib.c > ) >=20 >=20 >=20 >=20 >=20 >=20 >=20 > I=E2=80=99d recommend only implementing dispatch mode for new boards. We= only had > the API mode version because we were busy making a version of Kaby Lake > FSP that supports dispatch mode (aka AmberLakeFspBinPkg) at the same tim= e > we were developing KabyLakeOpenBoardPkg back in 2019. >=20 >=20 >=20 >=20 >=20 >=20 >=20 > One difference is we group our board ports based on the SOC they use. So > your new board port would go under > Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G for example. >=20 >=20 Thanks for these pointers and references, I will look at them more. As I understand it, the objective of dispatch mode was to remove code dupl= ication in flash and possibly save boot time by minimising phase transition= s. But it makes the PeiCore module non-updateable. From a board initialisat= ion perspective, they're probably the same, so this can be figured out late= r. >=20 >=20 >=20 > I will give you the same caution that I gave Pedro that you will need to > be careful about IP cross-contamination. Since coreboot is a GPL project > and TianoCore is a BSD+Patent project, we can=E2=80=99t use any of their= code. So > you need to be careful to NOT read the coreboot Kaby Lake code (with the > one exception being your patch to add the VN7-572G, since you are the > exclusive author of that work you can choose to re-license it as BSD.) I= n > general, on the days you are doing TianoCore work don=E2=80=99t look at = any > coreboot code. That way the cycle of sleep and dreams clears your head o= f > influence. >=20 >=20 Understood. So, there will be two similar commits of board initialisation?= I doubt I can truly dual-license the code, "BSD+GPL" might be a contradict= ion. However, I'm not a lawyer. >=20 >=20 >=20 > As to your questions: >=20 >=20 >=20 >=20 >=20 > * I wrote the prompt to be a bit more general. I=E2=80=99d recommend tal= king about > your specific project to get MinPlatform working on the Acer Aspire > VN7-572G. What specific additions or changes are you planning to make to > KabylakeOpenBoardPkg to get the VN7-572G working for example? Also, talk= a > bit about timeline. The GSoC program breaks the summer up into two half= =E2=80=99s: > June 7 =E2=80=93 July 16 and July 16 =E2=80=93 August 16. What should yo= ur mentor expect > to be done on July 16th? What should your mentor to expect to be done on > August 16th? > * I=E2=80=99m not 100% sure, but my guess is your email address can be w= hatever > you want. But the application form should contain your full legal name f= or > tax purposes. That doesn=E2=80=99t mean we won=E2=80=99t use your prefer= red nickname when > conversing. >=20 On timeline, I think I'll have more to do in the first half. Because I can= 't solder to the UART pins, I'll need it to boot first. (However, I was ver= y wrong about in this when working on my coreboot port. The OS booted as so= on as, if I understand correctly, FSP-T wasn't misconfigured and I set the = FSP UPD for display correctly. It took a lot more time to improve the port.= ) Sorry, I'll just write something up. >=20 >=20 >=20 > Hope this helps and welcome to the project! >=20 >=20 Yes, thanks! Regarding your second email, yes, that makes sense. I was just nervous abo= ut getting it wrong. Best regards, Benjamin Doron --hwOoFKPNMN9CSArGB659 Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Wed, Mar 31, 2021 at 07:58 PM, Nate DeSimone wrote:

Hi Benjamin,

=C2=A0

Great to meet you and= welcome to the TianoCore project! Glad you hear you are interested! Doing = a board port to the Acer Aspire VN7-572G laptop sounds like a great GSoC pr= oject! I presume that since you already did a coreboot port that boot guard= is disabled on this laptop and you have figured out how to flash images on= to it =F0= = =9F=98=8A.

Hi Nate,
Nice to meet you too, and thanks!

Yes, Boot Guard is= disabled on this laptop (and fused, which is a slight shame). While SPI PR= Rs cover most of flash and BIOS control bits are partially enabled by the v= endor firmware (perhaps the lock wasn't set by default, defeating the p= oint), after one modification to the setup's (HII) IFR, these can be di= sabled. Flashing externally is fairly straightforward - after the keyboard = comes off the flash chip is visible - but I try to avoid it because I'v= e started having issues with the keyboard connector. It's fine once it&= #39;s in and closed again...

The only thing that m= ight be a little challenging is getting a 2nd copy of that lapto= p for your mentor, so the possibility exists that when it comes to debuggin= g problems you might be a little more on your own than you would be otherwi= se. I=E2=80=99m not too worried about that looking at your CB:35523, it see= ms like you know what you are doing.

...but this might not be relevant to anyone after all. :-)

Is tha= t how this normally works? Who would organise it? (It sounds needlessly exp= ensive, for someone... *shrug*)

For sure our conventi= ons and infrastructure are different, but there are more parallels between = MinPlatform and coreboot than might initially meet the eye. For example:

=C2=A0

BoardInitBeforeMemory= Init() is roughly equivalent to bootblock_mainboard_init().

BoardInitBeforeSilico= nInit() is roughly equivalent to mainboard_init().

SiliconPolicyUpdatePr= eMem() is roughly equivalent to mainboard_memory_init_params().

=C2=A0

https://github.com/tianocore/edk2-platfo= rms/blob/master/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Bo= ardInitLib/PeiBoardInitPreMemLib.c

https://github.com/tianocore/edk2-pl= atforms/blob/master/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Librar= y/BoardInitLib/PeiBoardInitPostMemLib.c

FSP Dispatch Mode Pol= icy Init: https://github.com/tianocore/edk2-platforms/blob/master/Pla= tform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPoli= cyUpdateLib/PeiSiliconPolicyUpdateLib.c

FSP API Mode Policy I= nit: https://github.com/tianocore/edk2-platforms/blob/master/Platf= orm/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPo= licyUpdateLibFsp/PeiFspPolicyUpdateLib.c

=C2=A0

I=E2=80=99d recommend= only implementing dispatch mode for new boards. We only had the API mode v= ersion because we were busy making a version of Kaby Lake FSP that supports= dispatch mode (aka AmberLakeFspBinPkg) at the same time we were developing= KabyLakeOpenBoardPkg back in 2019.

=C2=A0

One difference is we = group our board ports based on the SOC they use. So your new board port wou= ld go under Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G for examp= le.

Thanks for these pointers and references, I will look at them more.
As I understand it, the objective of dispatch mode was to remove code du= plication in flash and possibly save boot time by minimising phase transiti= ons. But it makes the PeiCore module non-updateable. From a board initialis= ation perspective, they're probably the same, so this can be figured ou= t later.

I will give you the s= ame caution that I gave Pedro that you will need to be careful about IP cro= ss-contamination. Since coreboot is a GPL project and TianoCore is a BSD+Pa= tent project, we can=E2=80=99t use any of their code. So you need to be car= eful to NOT read the coreboot Kaby Lake code (with the one exception being = your patch to add the VN7-572G, since you are the exclusive author of that = work you can choose to re-license it as BSD.) In general, on the days you a= re doing TianoCore work don=E2=80=99t look at any coreboot code. That way t= he cycle of sleep and dreams clears your head of influence.

Understood. So, there will be two similar commits of board initialisation?= I doubt I can truly dual-license the code, "BSD+GPL" might be a co= ntradiction. However, I'm not a lawyer.

As to your questions:=

=C2=A0

  1. I wrote the pro= mpt to be a bit more general. I=E2=80=99d recommend talking about your spec= ific project to get MinPlatform working on the Acer Aspire VN7-572G. What s= pecific additions or changes are you planning to make to KabylakeOpenBoardP= kg to get the VN7-572G working for example? Also, talk a bit about timeline= . The GSoC program breaks the summer up into two half=E2=80=99s: June 7 =E2= = =80=93 July 16 and July 16 =E2=80=93 August 16. What should your mentor ex= pect to be done on July 16th? What should your mentor to expect to be done = on August 16th?
  2. I=E2=80=99m not= 100% sure, but my guess is your email address can be whatever you want. Bu= t the application form should contain your full legal name for tax purposes= . That doesn=E2=80=99t mean we won=E2=80=99t use your preferred nickname wh= en conversing.
On timeline, I think I'll have more to do in the first half. Because I= can't solder to the UART pins, I'll need it to boot first. (Howeve= r, I was very wrong about in this when working on my coreboot port. The OS = booted as soon as, if I understand correctly, FSP-T wasn't misconfigure= d and I set the FSP UPD for display correctly. It took a lot more time to i= mprove the port.)

Sorry, I'll just write something up.

Hope this helps and w= elcome to the project!

Yes, thanks!

Regarding your second email, yes, that makes sense. = I was just nervous about getting it wrong.

Best regards,
Benja= min Doron --hwOoFKPNMN9CSArGB659--