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* [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib
@ 2023-06-06  6:07 Abdul Lateef Attar
  2023-06-06  6:07 ` [PATCH v14 1/8] MdePkg: Adds AMD SMRAM save state map Abdul Lateef Attar
                   ` (8 more replies)
  0 siblings, 9 replies; 12+ messages in thread
From: Abdul Lateef Attar @ 2023-06-06  6:07 UTC (permalink / raw)
  To: devel
  Cc: Abdul Lateef Attar, Paul Grimes, Abner Chang, Eric Dong, Ray Ni,
	Rahul Kumar, Gerd Hoffmann, Michael D Kinney, Liming Gao,
	Zhiguang Liu, Ard Biesheuvel, Jiewen Yao, Jordan Justen

Backward-compatibility changes:
  This patch series removes the SmmCpuFeaturesReadSaveStateRegister
  and SmmCpuFeaturesWriteSaveStateRegister interface/function.
  SmmReadSaveState() and SmmWriteSaveState() now directly invokes MmSaveStateLib
  routines to save/restore registers.

PR: https://github.com/tianocore/edk2/pull/4519

V14: Delta changes
  Added @note to the MmSaveStateLib.h.
  SaveState(Read/Write) of EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID/EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID
  is handled by PiSmmCpuDxeSmm driver.
  Fixed PatchCheck warnings.
V13: Delta changes
  Address review comments from Ray Ni
  Changed the BASE _NAME of AmdSmmCpuFeaturesLib.
  Removed EFIAPI from local function.
  Removed CpuIndex parameter from MmSaveStateGetRegisterLma
  Modifed MmSaveStateGetRegisterIndex () to accept RegOffset
    as second parameter.
  Removed FILE_GUID library instance for intel implemention from UefiCpuPkg.dsc.
V12:
  Addressed review comments from Michael.
  Added LibraryClasses to .inf file.
  removed duplicate MACRO definations.
  Moved related MACRO defination to respective file.
V11: Delta changes
  Drop the OVMF implementation of MmSaveStateLib
V10: Delta changes:
  Addressed review comments from Abner.
V9: Delta changes:
  Addressed review comments.
  Rename to MmSaveStateLib.
  Also rename SMM_ defines to MM_.
  Implemented OVMF MmSaveStateLib.
  Removes SmmCpuFeaturesReadSaveStateRegister and SmmCpuFeaturesWriteSaveStateRegister
  function interface.
V8 delta changes:
   Addressed review comments from Abner,
   Fix the whitespace error.
   Seperate the Ovmf changes to another patch
V7 delta changes:
   Adds SmmSmramSaveStateLib for Intel processor.
   Integrate SmmSmramSaveStateLib library.
V6 delta changes:
   Addressed review comments for Ray NI.
   removed unnecessary EFIAPI.
V5 delta changes:
   rebase to master branch.
   updated Reviewed-by
V4 delta changes:
  rebase to master branch.
  added reviewed-by.
V3 delta changes:
  Addressed review comments from Abner chang.
  Re-arranged patch order.

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Abdul Lateef Attar <abdattar@amd.com>

Abdul Lateef Attar (8):
  MdePkg: Adds AMD SMRAM save state map
  UefiCpuPkg: Adds MmSaveStateLib library class
  UefiCpuPkg: Implements MmSaveStateLib library instance
  UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code
  UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family
  UefiCpuPkg: Implements MmSaveStateLib for Intel
  UefiCpuPkg: Removes SmmCpuFeaturesReadSaveStateRegister
  OvmfPkg: Uses MmSaveStateLib library

 UefiCpuPkg/UefiCpuPkg.dec                     |   4 +
 OvmfPkg/OvmfPkgIa32.dsc                       |   1 +
 OvmfPkg/OvmfPkgIa32X64.dsc                    |   3 +
 OvmfPkg/OvmfPkgX64.dsc                        |   1 +
 UefiCpuPkg/UefiCpuPkg.dsc                     |  13 +
 .../MmSaveStateLib/AmdMmSaveStateLib.inf      |  34 +
 .../MmSaveStateLib/IntelMmSaveStateLib.inf    |  34 +
 .../AmdSmmCpuFeaturesLib.inf                  |  38 +
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf  |   2 +
 .../Include/Register/Amd/SmramSaveStateMap.h  | 194 +++++
 UefiCpuPkg/Include/Library/MmSaveStateLib.h   |  74 ++
 .../Include/Library/SmmCpuFeaturesLib.h       |  52 --
 .../Library/MmSaveStateLib/MmSaveState.h      |  94 +++
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h    |  56 +-
 .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.c     | 767 ------------------
 .../Library/MmSaveStateLib/AmdMmSaveState.c   | 309 +++++++
 .../Library/MmSaveStateLib/IntelMmSaveState.c | 410 ++++++++++
 .../MmSaveStateLib/MmSaveStateCommon.c        | 132 +++
 .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c  | 387 +++++++++
 .../IntelSmmCpuFeaturesLib.c                  |  70 ++
 .../SmmCpuFeaturesLibCommon.c                 | 128 ---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c    |  11 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c    | 500 +-----------
 MdePkg/MdePkg.ci.yaml                         |   4 +-
 24 files changed, 1810 insertions(+), 1508 deletions(-)
 create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
 create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
 create mode 100644 MdePkg/Include/Register/Amd/SmramSaveStateMap.h
 create mode 100644 UefiCpuPkg/Include/Library/MmSaveStateLib.h
 create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/MmSaveState.h
 create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c
 create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveState.c
 create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/MmSaveStateCommon.c
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c

-- 
2.25.1


^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH v14 1/8] MdePkg: Adds AMD SMRAM save state map
  2023-06-06  6:07 [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Abdul Lateef Attar
@ 2023-06-06  6:07 ` Abdul Lateef Attar
  2023-06-06  6:07 ` [PATCH v14 2/8] UefiCpuPkg: Adds MmSaveStateLib library class Abdul Lateef Attar
                   ` (7 subsequent siblings)
  8 siblings, 0 replies; 12+ messages in thread
From: Abdul Lateef Attar @ 2023-06-06  6:07 UTC (permalink / raw)
  To: devel
  Cc: Abdul Lateef Attar, Paul Grimes, Abner Chang, Michael D Kinney,
	Liming Gao, Zhiguang Liu

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

Adds an SMM SMRAM save-state map for AMD processors.
SMRAM save state maps for the AMD processor family are now supported.

Save state map structure is added based on
AMD64 Architecture Programmer's Manual, Volume 2, Section 10.2.

The AMD legacy save state map for 32-bit architecture is defined.
The AMD64 save state map for 64-bit architecture is defined. 

Also added Amd/SmramSaveStateMap.h to IgnoreFiles of EccCheck,
because structures defined in this file are derived from
Intel/SmramSaveStateMap.h.

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
 .../Include/Register/Amd/SmramSaveStateMap.h  | 194 ++++++++++++++++++
 MdePkg/MdePkg.ci.yaml                         |   4 +-
 2 files changed, 197 insertions(+), 1 deletion(-)
 create mode 100644 MdePkg/Include/Register/Amd/SmramSaveStateMap.h

diff --git a/MdePkg/Include/Register/Amd/SmramSaveStateMap.h b/MdePkg/Include/Register/Amd/SmramSaveStateMap.h
new file mode 100644
index 000000000000..0607d2a19145
--- /dev/null
+++ b/MdePkg/Include/Register/Amd/SmramSaveStateMap.h
@@ -0,0 +1,194 @@
+/** @file
+  AMD SMRAM Save State Map Definitions.
+
+  SMRAM Save State Map definitions based on contents of the
+    AMD64 Architecture Programmer Manual:
+    Volume 2, System Programming, Section 10.2 SMM Resources
+
+  Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
+  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved .<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef AMD_SMRAM_SAVE_STATE_MAP_H_
+#define AMD_SMRAM_SAVE_STATE_MAP_H_
+
+///
+/// Default SMBASE address
+///
+#define SMM_DEFAULT_SMBASE  0x30000
+
+///
+/// Offset of SMM handler from SMBASE
+///
+#define SMM_HANDLER_OFFSET  0x8000
+
+// SMM-Revision Identifier for AMD64 Architecture.
+#define AMD_SMM_MIN_REV_ID_X64  0x30064
+
+#pragma pack (1)
+
+///
+/// 32-bit SMRAM Save State Map
+///
+typedef struct {
+  // Padded an extra 0x200 bytes to match Intel/EDK2
+  UINT8     Reserved[0x200]; // fc00h
+  // AMD Save State area starts @ 0xfe00
+  UINT8     Reserved1[0xf8]; // fe00h
+  UINT32    SMBASE;          // fef8h
+  UINT32    SMMRevId;        // fefch
+  UINT16    IORestart;       // ff00h
+  UINT16    AutoHALTRestart; // ff02h
+  UINT8     Reserved2[0x84]; // ff04h
+  UINT32    GDTBase;         // ff88h
+  UINT64    Reserved3;       // ff8ch
+  UINT32    IDTBase;         // ff94h
+  UINT8     Reserved4[0x10]; // ff98h
+  UINT32    _ES;             // ffa8h
+  UINT32    _CS;             // ffach
+  UINT32    _SS;             // ffb0h
+  UINT32    _DS;             // ffb4h
+  UINT32    _FS;             // ffb8h
+  UINT32    _GS;             // ffbch
+  UINT32    LDTBase;         // ffc0h
+  UINT32    _TR;             // ffc4h
+  UINT32    _DR7;            // ffc8h
+  UINT32    _DR6;            // ffcch
+  UINT32    _EAX;            // ffd0h
+  UINT32    _ECX;            // ffd4h
+  UINT32    _EDX;            // ffd8h
+  UINT32    _EBX;            // ffdch
+  UINT32    _ESP;            // ffe0h
+  UINT32    _EBP;            // ffe4h
+  UINT32    _ESI;            // ffe8h
+  UINT32    _EDI;            // ffech
+  UINT32    _EIP;            // fff0h
+  UINT32    _EFLAGS;         // fff4h
+  UINT32    _CR3;            // fff8h
+  UINT32    _CR0;            // fffch
+} AMD_SMRAM_SAVE_STATE_MAP32;
+
+///
+/// 64-bit SMRAM Save State Map
+///
+typedef struct {
+  // Padded an extra 0x200 bytes to match Intel/EDK2
+  UINT8     Reserved[0x200]; // fc00h
+  // AMD Save State area starts @ 0xfe00
+  UINT16    _ES;              // fe00h
+  UINT16    _ESAttributes;    // fe02h
+  UINT32    _ESLimit;         // fe04h
+  UINT64    _ESBase;          // fe08h
+
+  UINT16    _CS;              // fe10h
+  UINT16    _CSAttributes;    // fe12h
+  UINT32    _CSLimit;         // fe14h
+  UINT64    _CSBase;          // fe18h
+
+  UINT16    _SS;              // fe20h
+  UINT16    _SSAttributes;    // fe22h
+  UINT32    _SSLimit;         // fe24h
+  UINT64    _SSBase;          // fe28h
+
+  UINT16    _DS;              // fe30h
+  UINT16    _DSAttributes;    // fe32h
+  UINT32    _DSLimit;         // fe34h
+  UINT64    _DSBase;          // fe38h
+
+  UINT16    _FS;              // fe40h
+  UINT16    _FSAttributes;    // fe42h
+  UINT32    _FSLimit;         // fe44h
+  UINT64    _FSBase;          // fe48h
+
+  UINT16    _GS;              // fe50h
+  UINT16    _GSAttributes;    // fe52h
+  UINT32    _GSLimit;         // fe54h
+  UINT64    _GSBase;          // fe58h
+
+  UINT32    _GDTRReserved1;   // fe60h
+  UINT16    _GDTRLimit;       // fe64h
+  UINT16    _GDTRReserved2;   // fe66h
+  // UINT64  _GDTRBase;        // fe68h
+  UINT32    _GDTRBaseLoDword;
+  UINT32    _GDTRBaseHiDword;
+
+  UINT16    _LDTR;            // fe70h
+  UINT16    _LDTRAttributes;  // fe72h
+  UINT32    _LDTRLimit;       // fe74h
+  // UINT64  _LDTRBase;        // fe78h
+  UINT32    _LDTRBaseLoDword;
+  UINT32    _LDTRBaseHiDword;
+
+  UINT32    _IDTRReserved1;   // fe80h
+  UINT16    _IDTRLimit;       // fe84h
+  UINT16    _IDTRReserved2;   // fe86h
+  // UINT64  _IDTRBase;        // fe88h
+  UINT32    _IDTRBaseLoDword;
+  UINT32    _IDTRBaseHiDword;
+
+  UINT16    _TR;              // fe90h
+  UINT16    _TRAttributes;    // fe92h
+  UINT32    _TRLimit;         // fe94h
+  UINT64    _TRBase;          // fe98h
+
+  UINT64    IO_RIP;           // fea0h
+  UINT64    IO_RCX;           // fea8h
+  UINT64    IO_RSI;           // feb0h
+  UINT64    IO_RDI;           // feb8h
+  UINT32    IO_DWord;         // fec0h
+  UINT8     Reserved1[0x04];  // fec4h
+  UINT8     IORestart;        // fec8h
+  UINT8     AutoHALTRestart;  // fec9h
+  UINT8     Reserved2[0x06];  // fecah
+  UINT64    EFER;             // fed0h
+  UINT64    SVM_Guest;        // fed8h
+  UINT64    SVM_GuestVMCB;    // fee0h
+  UINT64    SVM_GuestVIntr;   // fee8h
+  UINT8     Reserved3[0x0c];  // fef0h
+  UINT32    SMMRevId;         // fefch
+  UINT32    SMBASE;           // ff00h
+  UINT8     Reserved4[0x14];  // ff04h
+  UINT64    SSP;              // ff18h
+  UINT64    SVM_GuestPAT;     // ff20h
+  UINT64    SVM_HostEFER;     // ff28h
+  UINT64    SVM_HostCR4;      // ff30h
+  UINT64    SVM_HostCR3;      // ff38h
+  UINT64    SVM_HostCR0;      // ff40h
+  UINT64    _CR4;             // ff48h
+  UINT64    _CR3;             // ff50h
+  UINT64    _CR0;             // ff58h
+  UINT64    _DR7;             // ff60h
+  UINT64    _DR6;             // ff68h
+  UINT64    _RFLAGS;          // ff70h
+  UINT64    _RIP;             // ff78h
+  UINT64    _R15;             // ff80h
+  UINT64    _R14;             // ff88h
+  UINT64    _R13;             // ff90h
+  UINT64    _R12;             // ff98h
+  UINT64    _R11;             // ffa0h
+  UINT64    _R10;             // ffa8h
+  UINT64    _R9;              // ffb0h
+  UINT64    _R8;              // ffb8h
+  UINT64    _RDI;             // ffc0h
+  UINT64    _RSI;             // ffc8h
+  UINT64    _RBP;             // ffd0h
+  UINT64    _RSP;             // ffd8h
+  UINT64    _RBX;             // ffe0h
+  UINT64    _RDX;             // ffe8h
+  UINT64    _RCX;             // fff0h
+  UINT64    _RAX;             // fff8h
+} AMD_SMRAM_SAVE_STATE_MAP64;
+
+///
+/// Union of 32-bit and 64-bit SMRAM Save State Maps
+///
+typedef union  {
+  AMD_SMRAM_SAVE_STATE_MAP32    x86;
+  AMD_SMRAM_SAVE_STATE_MAP64    x64;
+} AMD_SMRAM_SAVE_STATE_MAP;
+
+#pragma pack ()
+
+#endif
diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index f024b48685ef..c3faf4913d75 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -5,6 +5,7 @@
 # Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
 # Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
 # Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.<BR>
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 ##
 {
@@ -72,7 +73,8 @@
             "Include/Protocol/DebugSupport.h",
             "Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c",
             "Library/BaseFdtLib",
-            "Library/MipiSysTLib/mipi_syst.h"
+            "Library/MipiSysTLib/mipi_syst.h",
+            "Include/Register/Amd/SmramSaveStateMap.h"
         ]
     },
     ## options defined ci/Plugin/CompilerPlugin
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v14 2/8] UefiCpuPkg: Adds MmSaveStateLib library class
  2023-06-06  6:07 [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Abdul Lateef Attar
  2023-06-06  6:07 ` [PATCH v14 1/8] MdePkg: Adds AMD SMRAM save state map Abdul Lateef Attar
@ 2023-06-06  6:07 ` Abdul Lateef Attar
  2023-06-06  6:07 ` [PATCH v14 3/8] UefiCpuPkg: Implements MmSaveStateLib library instance Abdul Lateef Attar
                   ` (6 subsequent siblings)
  8 siblings, 0 replies; 12+ messages in thread
From: Abdul Lateef Attar @ 2023-06-06  6:07 UTC (permalink / raw)
  To: devel
  Cc: Abdul Lateef Attar, Paul Grimes, Abner Chang, Eric Dong, Ray Ni,
	Rahul Kumar, Gerd Hoffmann

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

Adds MmSaveStateLib Library class in UefiCpuPkg.dec.
Adds function declaration header file.

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>

Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
---
 UefiCpuPkg/UefiCpuPkg.dec                   |  4 ++
 UefiCpuPkg/Include/Library/MmSaveStateLib.h | 74 +++++++++++++++++++++
 2 files changed, 78 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Library/MmSaveStateLib.h

diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index d31c3b127c0b..1f1b10e702bf 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -2,6 +2,7 @@
 # This Package provides UEFI compatible CPU modules and libraries.
 #
 # Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.<BR>
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -60,6 +61,9 @@ [LibraryClasses.IA32, LibraryClasses.X64]
   ##  @libraryclass  Provides function for manipulating x86 paging structures.
   CpuPageTableLib|Include/Library/CpuPageTableLib.h
 
+  ## @libraryclass   Provides functions for manipulating smram savestate registers.
+  MmSaveStateLib|Include/Library/MmSaveStateLib.h
+
 [Guids]
   gUefiCpuPkgTokenSpaceGuid      = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
   gMsegSmramGuid                 = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
diff --git a/UefiCpuPkg/Include/Library/MmSaveStateLib.h b/UefiCpuPkg/Include/Library/MmSaveStateLib.h
new file mode 100644
index 000000000000..db4552e4a809
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/MmSaveStateLib.h
@@ -0,0 +1,74 @@
+/** @file
+Library that provides service to read/write CPU specific smram save state registers.
+
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+
+@note
+  SaveState(Read/Write) of EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID/EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID
+  is handled by PiSmmCpuDxeSmm driver.
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef MM_SAVE_STATE_LIB_H_
+#define MM_SAVE_STATE_LIB_H_
+
+#include <Protocol/MmCpu.h>
+#include <Uefi/UefiBaseType.h>
+
+/**
+  Read a save state register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
+  MM Save State register.
+
+  @param[in]  CpuIndex  The index of the CPU to read the Save State register.
+                        The value must be between 0 and the NumberOfCpus field in
+                        the System Management System Table (SMST).
+  @param[in]  Register  The MM Save State register to read.
+  @param[in]  Width     The number of bytes to read from the CPU save state.
+  @param[out] Buffer    Upon return, this holds the CPU register value read
+                        from the save state.
+
+  @retval EFI_SUCCESS           The register was read from Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support reading Register.
+  @retval EFI_NOT_FOUND         If desired Register not found.
+**/
+EFI_STATUS
+EFIAPI
+MmSaveStateReadRegister (
+  IN  UINTN                       CpuIndex,
+  IN  EFI_MM_SAVE_STATE_REGISTER  Register,
+  IN  UINTN                       Width,
+  OUT VOID                        *Buffer
+  );
+
+/**
+  Writes a save state register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
+  MM save state register.
+
+  @param[in] CpuIndex  The index of the CPU to write the MM Save State.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] Register  The MM Save State register to write.
+  @param[in] Width     The number of bytes to write to the CPU save state.
+  @param[in] Buffer    Upon entry, this holds the new CPU register value.
+
+  @retval EFI_SUCCESS           The register was written to Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support writing Register.
+  @retval EFI_NOT_FOUND         If desired Register not found.
+**/
+EFI_STATUS
+EFIAPI
+MmSaveStateWriteRegister (
+  IN UINTN                       CpuIndex,
+  IN EFI_MM_SAVE_STATE_REGISTER  Register,
+  IN UINTN                       Width,
+  IN CONST VOID                  *Buffer
+  );
+
+#endif
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v14 3/8] UefiCpuPkg: Implements MmSaveStateLib library instance
  2023-06-06  6:07 [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Abdul Lateef Attar
  2023-06-06  6:07 ` [PATCH v14 1/8] MdePkg: Adds AMD SMRAM save state map Abdul Lateef Attar
  2023-06-06  6:07 ` [PATCH v14 2/8] UefiCpuPkg: Adds MmSaveStateLib library class Abdul Lateef Attar
@ 2023-06-06  6:07 ` Abdul Lateef Attar
  2023-06-06  6:07 ` [PATCH v14 4/8] UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code Abdul Lateef Attar
                   ` (5 subsequent siblings)
  8 siblings, 0 replies; 12+ messages in thread
From: Abdul Lateef Attar @ 2023-06-06  6:07 UTC (permalink / raw)
  To: devel
  Cc: Abdul Lateef Attar, Paul Grimes, Abner Chang, Eric Dong, Ray Ni,
	Rahul Kumar, Gerd Hoffmann, Abdul Lateef Attar

From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

Implements MmSaveStateLib Library class for
AMD cpu family.

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>

Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
---
 UefiCpuPkg/UefiCpuPkg.dsc                     |   3 +
 .../MmSaveStateLib/AmdMmSaveStateLib.inf      |  34 ++
 .../Library/MmSaveStateLib/MmSaveState.h      |  94 ++++++
 .../Library/MmSaveStateLib/AmdMmSaveState.c   | 309 ++++++++++++++++++
 .../MmSaveStateLib/MmSaveStateCommon.c        | 132 ++++++++
 5 files changed, 572 insertions(+)
 create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
 create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/MmSaveState.h
 create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c
 create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/MmSaveStateCommon.c

diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 593c11cc7482..8b0cb02a80e8 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -2,6 +2,7 @@
 #  UefiCpuPkg Package
 #
 #  Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
+#  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -99,6 +100,7 @@ [LibraryClasses.common.DXE_SMM_DRIVER]
   MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
   HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
   CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+  MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
 
 [LibraryClasses.common.MM_STANDALONE]
   MmServicesTableLib|MdePkg/Library/StandaloneMmServicesTableLib/StandaloneMmServicesTableLib.inf
@@ -182,6 +184,7 @@ [Components.IA32, Components.X64]
     <LibraryClasses>
       UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestResultReportLibConOut.inf
   }
+  UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
 
 [Components.X64]
   UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHandlerLibUnitTest.inf
diff --git a/UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf b/UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
new file mode 100644
index 000000000000..5c0685f283d3
--- /dev/null
+++ b/UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
@@ -0,0 +1,34 @@
+## @file
+# MM Smram save state service lib.
+#
+# This is MM Smram save state service lib that provide service to read and
+# save savestate area registers.
+#
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 1.29
+  BASE_NAME                      = AmdMmSaveStateLib
+  FILE_GUID                      = FB7D0A60-E8D4-4EFA-90AA-B357BC569879
+  MODULE_TYPE                    = DXE_SMM_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = MmSaveStateLib
+
+[Sources]
+  MmSaveState.h
+  MmSaveStateCommon.c
+  AmdMmSaveState.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  SmmServicesTableLib
diff --git a/UefiCpuPkg/Library/MmSaveStateLib/MmSaveState.h b/UefiCpuPkg/Library/MmSaveStateLib/MmSaveState.h
new file mode 100644
index 000000000000..c3499cbb3b17
--- /dev/null
+++ b/UefiCpuPkg/Library/MmSaveStateLib/MmSaveState.h
@@ -0,0 +1,94 @@
+/** @file
+  SMRAM Save State Map header file.
+
+  Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef MM_SAVESTATE_H_
+#define MM_SAVESTATE_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Protocol/MmCpu.h>
+#include <Library/DebugLib.h>
+#include <Library/MmSaveStateLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+
+// Macro used to simplify the lookup table entries of type CPU_MM_SAVE_STATE_REGISTER_RANGE
+#define MM_REGISTER_RANGE(Start, End)  { Start, End, End - Start + 1 }
+
+// Structure used to describe a range of registers
+typedef struct {
+  EFI_MM_SAVE_STATE_REGISTER    Start;
+  EFI_MM_SAVE_STATE_REGISTER    End;
+  UINTN                         Length;
+} CPU_MM_SAVE_STATE_REGISTER_RANGE;
+
+// Structure used to build a lookup table to retrieve the widths and offsets
+// associated with each supported EFI_MM_SAVE_STATE_REGISTER value
+
+typedef struct {
+  UINT8      Width32;
+  UINT8      Width64;
+  UINT16     Offset32;
+  UINT16     Offset64Lo;
+  UINT16     Offset64Hi;
+  BOOLEAN    Writeable;
+} CPU_MM_SAVE_STATE_LOOKUP_ENTRY;
+
+/**
+  Returns LMA value of the Processor.
+
+  @retval     UINT8     returns LMA bit value.
+**/
+UINT8
+MmSaveStateGetRegisterLma (
+  VOID
+  );
+
+/**
+  Read information from the CPU save state.
+
+  @param  Register  Specifies the CPU register to read form the save state.
+  @param  RegOffset Offset for the next register index.
+
+  @retval 0   Register is not valid
+  @retval >0  Index into mCpuWidthOffset[] associated with Register
+
+**/
+UINTN
+MmSaveStateGetRegisterIndex (
+  IN EFI_MM_SAVE_STATE_REGISTER  Register,
+  IN UINTN                       RegOffset
+  );
+
+/**
+  Read a CPU Save State register on the target processor.
+
+  This function abstracts the differences that whether the CPU Save State register is in the
+  IA32 CPU Save State Map or X64 CPU Save State Map.
+
+  This function supports reading a CPU Save State register in SMBase relocation handler.
+
+  @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
+  @param[in]  RegisterIndex  Index into mCpuWidthOffset[] look up table.
+  @param[in]  Width          The number of bytes to read from the CPU save state.
+  @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
+
+  @retval EFI_SUCCESS           The register was read from Save State.
+  @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
+  @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
+
+**/
+EFI_STATUS
+MmSaveStateReadRegisterByIndex (
+  IN UINTN  CpuIndex,
+  IN UINTN  RegisterIndex,
+  IN UINTN  Width,
+  OUT VOID  *Buffer
+  );
+
+#endif
diff --git a/UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c b/UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c
new file mode 100644
index 000000000000..9fed52896f5c
--- /dev/null
+++ b/UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c
@@ -0,0 +1,309 @@
+/** @file
+Provides services to access SMRAM Save State Map
+
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "MmSaveState.h"
+#include <Register/Amd/SmramSaveStateMap.h>
+#include <Library/BaseLib.h>
+
+// EFER register LMA bit
+#define LMA                                        BIT10
+#define EFER_ADDRESS                               0xC0000080ul
+#define AMD_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX  1
+#define AMD_MM_SAVE_STATE_REGISTER_MAX_INDEX       2
+
+// Macro used to simplify the lookup table entries of type CPU_MM_SAVE_STATE_LOOKUP_ENTRY
+#define MM_CPU_OFFSET(Field)  OFFSET_OF (AMD_SMRAM_SAVE_STATE_MAP, Field)
+
+// Lookup table used to retrieve the widths and offsets associated with each
+// supported EFI_MM_SAVE_STATE_REGISTER value
+CONST CPU_MM_SAVE_STATE_LOOKUP_ENTRY  mCpuWidthOffset[] = {
+  { 0, 0, 0,                            0,                                    FALSE },                                        //  Reserved
+
+  //
+  // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.
+  //
+  { 4, 4, MM_CPU_OFFSET (x86.SMMRevId), MM_CPU_OFFSET (x64.SMMRevId),         0, FALSE},                                      // AMD_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX  = 1
+
+  //
+  // CPU Save State registers defined in PI SMM CPU Protocol.
+  //
+  { 4, 8, MM_CPU_OFFSET (x86.GDTBase),  MM_CPU_OFFSET (x64._GDTRBaseLoDword), MM_CPU_OFFSET (x64._GDTRBaseHiDword), FALSE},   //  EFI_MM_SAVE_STATE_REGISTER_GDTBASE  = 4
+  { 0, 8, 0,                            MM_CPU_OFFSET (x64._IDTRBaseLoDword), MM_CPU_OFFSET (x64._IDTRBaseLoDword), FALSE},   //  EFI_MM_SAVE_STATE_REGISTER_IDTBASE  = 5
+  { 0, 8, 0,                            MM_CPU_OFFSET (x64._LDTRBaseLoDword), MM_CPU_OFFSET (x64._LDTRBaseLoDword), FALSE},   //  EFI_MM_SAVE_STATE_REGISTER_LDTBASE  = 6
+  { 0, 2, 0,                            MM_CPU_OFFSET (x64._GDTRLimit),       0, FALSE},                                      //  EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT = 7
+  { 0, 2, 0,                            MM_CPU_OFFSET (x64._IDTRLimit),       0, FALSE},                                      //  EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT = 8
+  { 0, 4, 0,                            MM_CPU_OFFSET (x64._LDTRLimit),       0, FALSE},                                      //  EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT = 9
+  { 0, 0, 0,                            0,                                    0, FALSE},                                      //  EFI_MM_SAVE_STATE_REGISTER_LDTINFO  = 10
+  { 4, 2, MM_CPU_OFFSET (x86._ES),      MM_CPU_OFFSET (x64._ES),              0, FALSE},                                      //  EFI_MM_SAVE_STATE_REGISTER_ES       = 20
+  { 4, 2, MM_CPU_OFFSET (x86._CS),      MM_CPU_OFFSET (x64._CS),              0, FALSE},                                      //  EFI_MM_SAVE_STATE_REGISTER_CS       = 21
+  { 4, 2, MM_CPU_OFFSET (x86._SS),      MM_CPU_OFFSET (x64._SS),              0, FALSE},                                      //  EFI_MM_SAVE_STATE_REGISTER_SS       = 22
+  { 4, 2, MM_CPU_OFFSET (x86._DS),      MM_CPU_OFFSET (x64._DS),              0, FALSE},                                      //  EFI_MM_SAVE_STATE_REGISTER_DS       = 23
+  { 4, 2, MM_CPU_OFFSET (x86._FS),      MM_CPU_OFFSET (x64._FS),              0, FALSE},                                      //  EFI_MM_SAVE_STATE_REGISTER_FS       = 24
+  { 4, 2, MM_CPU_OFFSET (x86._GS),      MM_CPU_OFFSET (x64._GS),              0, FALSE},                                      //  EFI_MM_SAVE_STATE_REGISTER_GS       = 25
+  { 0, 2, 0,                            MM_CPU_OFFSET (x64._LDTR),            0, FALSE},                                      //  EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL = 26
+  { 0, 2, 0,                            MM_CPU_OFFSET (x64._TR),              0, FALSE},                                      //  EFI_MM_SAVE_STATE_REGISTER_TR_SEL   = 27
+  { 4, 8, MM_CPU_OFFSET (x86._DR7),     MM_CPU_OFFSET (x64._DR7),             MM_CPU_OFFSET (x64._DR7)         + 4, FALSE},   //  EFI_MM_SAVE_STATE_REGISTER_DR7      = 28
+  { 4, 8, MM_CPU_OFFSET (x86._DR6),     MM_CPU_OFFSET (x64._DR6),             MM_CPU_OFFSET (x64._DR6)         + 4, FALSE},   //  EFI_MM_SAVE_STATE_REGISTER_DR6      = 29
+  { 0, 8, 0,                            MM_CPU_OFFSET (x64._R8),              MM_CPU_OFFSET (x64._R8)          + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_R8       = 30
+  { 0, 8, 0,                            MM_CPU_OFFSET (x64._R9),              MM_CPU_OFFSET (x64._R9)          + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_R9       = 31
+  { 0, 8, 0,                            MM_CPU_OFFSET (x64._R10),             MM_CPU_OFFSET (x64._R10)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_R10      = 32
+  { 0, 8, 0,                            MM_CPU_OFFSET (x64._R11),             MM_CPU_OFFSET (x64._R11)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_R11      = 33
+  { 0, 8, 0,                            MM_CPU_OFFSET (x64._R12),             MM_CPU_OFFSET (x64._R12)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_R12      = 34
+  { 0, 8, 0,                            MM_CPU_OFFSET (x64._R13),             MM_CPU_OFFSET (x64._R13)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_R13      = 35
+  { 0, 8, 0,                            MM_CPU_OFFSET (x64._R14),             MM_CPU_OFFSET (x64._R14)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_R14      = 36
+  { 0, 8, 0,                            MM_CPU_OFFSET (x64._R15),             MM_CPU_OFFSET (x64._R15)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_R15      = 37
+  { 4, 8, MM_CPU_OFFSET (x86._EAX),     MM_CPU_OFFSET (x64._RAX),             MM_CPU_OFFSET (x64._RAX)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_RAX      = 38
+  { 4, 8, MM_CPU_OFFSET (x86._EBX),     MM_CPU_OFFSET (x64._RBX),             MM_CPU_OFFSET (x64._RBX)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_RBX      = 39
+  { 4, 8, MM_CPU_OFFSET (x86._ECX),     MM_CPU_OFFSET (x64._RCX),             MM_CPU_OFFSET (x64._RCX)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_RBX      = 39
+  { 4, 8, MM_CPU_OFFSET (x86._EDX),     MM_CPU_OFFSET (x64._RDX),             MM_CPU_OFFSET (x64._RDX)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_RDX      = 41
+  { 4, 8, MM_CPU_OFFSET (x86._ESP),     MM_CPU_OFFSET (x64._RSP),             MM_CPU_OFFSET (x64._RSP)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_RSP      = 42
+  { 4, 8, MM_CPU_OFFSET (x86._EBP),     MM_CPU_OFFSET (x64._RBP),             MM_CPU_OFFSET (x64._RBP)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_RBP      = 43
+  { 4, 8, MM_CPU_OFFSET (x86._ESI),     MM_CPU_OFFSET (x64._RSI),             MM_CPU_OFFSET (x64._RSI)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_RSI      = 44
+  { 4, 8, MM_CPU_OFFSET (x86._EDI),     MM_CPU_OFFSET (x64._RDI),             MM_CPU_OFFSET (x64._RDI)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_RDI      = 45
+  { 4, 8, MM_CPU_OFFSET (x86._EIP),     MM_CPU_OFFSET (x64._RIP),             MM_CPU_OFFSET (x64._RIP)         + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_RIP      = 46
+
+  { 4, 8, MM_CPU_OFFSET (x86._EFLAGS),  MM_CPU_OFFSET (x64._RFLAGS),          MM_CPU_OFFSET (x64._RFLAGS)      + 4, TRUE},    //  EFI_MM_SAVE_STATE_REGISTER_RFLAGS   = 51
+  { 4, 8, MM_CPU_OFFSET (x86._CR0),     MM_CPU_OFFSET (x64._CR0),             MM_CPU_OFFSET (x64._CR0)         + 4, FALSE},   //  EFI_MM_SAVE_STATE_REGISTER_CR0      = 52
+  { 4, 8, MM_CPU_OFFSET (x86._CR3),     MM_CPU_OFFSET (x64._CR3),             MM_CPU_OFFSET (x64._CR3)         + 4, FALSE},   //  EFI_MM_SAVE_STATE_REGISTER_CR3      = 53
+  { 0, 8, 0,                            MM_CPU_OFFSET (x64._CR4),             MM_CPU_OFFSET (x64._CR4)         + 4, FALSE},   //  EFI_MM_SAVE_STATE_REGISTER_CR4      = 54
+  { 0, 0, 0,                            0,                                    0     }
+};
+
+/**
+  Read a save state register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
+  MM Save State register.
+
+  @param[in]  CpuIndex  The index of the CPU to read the Save State register.
+                        The value must be between 0 and the NumberOfCpus field in
+                        the System Management System Table (SMST).
+  @param[in]  Register  The MM Save State register to read.
+  @param[in]  Width     The number of bytes to read from the CPU save state.
+  @param[out] Buffer    Upon return, this holds the CPU register value read
+                        from the save state.
+
+  @retval EFI_SUCCESS           The register was read from Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support reading Register.
+  @retval EFI_NOT_FOUND         If desired Register not found.
+**/
+EFI_STATUS
+EFIAPI
+MmSaveStateReadRegister (
+  IN  UINTN                       CpuIndex,
+  IN  EFI_MM_SAVE_STATE_REGISTER  Register,
+  IN  UINTN                       Width,
+  OUT VOID                        *Buffer
+  )
+{
+  UINT32                     SmmRevId;
+  EFI_MM_SAVE_STATE_IO_INFO  *IoInfo;
+  AMD_SMRAM_SAVE_STATE_MAP   *CpuSaveState;
+  UINT8                      DataWidth;
+
+  // Read CPU State
+  CpuSaveState = (AMD_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
+
+  // Check for special EFI_MM_SAVE_STATE_REGISTER_LMA
+  if (Register == EFI_MM_SAVE_STATE_REGISTER_LMA) {
+    // Only byte access is supported for this register
+    if (Width != 1) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    *(UINT8 *)Buffer = MmSaveStateGetRegisterLma ();
+
+    return EFI_SUCCESS;
+  }
+
+  // Check for special EFI_MM_SAVE_STATE_REGISTER_IO
+  if (Register == EFI_MM_SAVE_STATE_REGISTER_IO) {
+    //
+    // Get SMM Revision ID
+    //
+    MmSaveStateReadRegisterByIndex (CpuIndex, AMD_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);
+
+    //
+    // See if the CPU supports the IOMisc register in the save state
+    //
+    if (SmmRevId < AMD_SMM_MIN_REV_ID_X64) {
+      return EFI_NOT_FOUND;
+    }
+
+    // Check if IO Restart Dword [IO Trap] is valid or not using bit 1.
+    if (!(CpuSaveState->x64.IO_DWord & 0x02u)) {
+      return EFI_NOT_FOUND;
+    }
+
+    // Zero the IoInfo structure that will be returned in Buffer
+    IoInfo = (EFI_MM_SAVE_STATE_IO_INFO *)Buffer;
+    ZeroMem (IoInfo, sizeof (EFI_MM_SAVE_STATE_IO_INFO));
+
+    IoInfo->IoPort = (UINT16)(CpuSaveState->x64.IO_DWord >> 16u);
+
+    if (CpuSaveState->x64.IO_DWord & 0x10u) {
+      IoInfo->IoWidth = EFI_MM_SAVE_STATE_IO_WIDTH_UINT8;
+      DataWidth       = 0x01u;
+    } else if (CpuSaveState->x64.IO_DWord & 0x20u) {
+      IoInfo->IoWidth = EFI_MM_SAVE_STATE_IO_WIDTH_UINT16;
+      DataWidth       = 0x02u;
+    } else {
+      IoInfo->IoWidth = EFI_MM_SAVE_STATE_IO_WIDTH_UINT32;
+      DataWidth       = 0x04u;
+    }
+
+    if (CpuSaveState->x64.IO_DWord & 0x01u) {
+      IoInfo->IoType = EFI_MM_SAVE_STATE_IO_TYPE_INPUT;
+    } else {
+      IoInfo->IoType = EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT;
+    }
+
+    if ((IoInfo->IoType == EFI_MM_SAVE_STATE_IO_TYPE_INPUT) || (IoInfo->IoType == EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT)) {
+      MmSaveStateReadRegister (CpuIndex, EFI_MM_SAVE_STATE_REGISTER_RAX, DataWidth, &IoInfo->IoData);
+    }
+
+    return EFI_SUCCESS;
+  }
+
+  // Convert Register to a register lookup table index
+  return MmSaveStateReadRegisterByIndex (CpuIndex, MmSaveStateGetRegisterIndex (Register, AMD_MM_SAVE_STATE_REGISTER_MAX_INDEX), Width, Buffer);
+}
+
+/**
+  Writes a save state register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
+  MM save state register.
+
+  @param[in] CpuIndex  The index of the CPU to write the MM Save State.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] Register  The MM Save State register to write.
+  @param[in] Width     The number of bytes to write to the CPU save state.
+  @param[in] Buffer    Upon entry, this holds the new CPU register value.
+
+  @retval EFI_SUCCESS           The register was written to Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support writing Register.
+  @retval EFI_NOT_FOUND         If desired Register not found.
+**/
+EFI_STATUS
+EFIAPI
+MmSaveStateWriteRegister (
+  IN UINTN                       CpuIndex,
+  IN EFI_MM_SAVE_STATE_REGISTER  Register,
+  IN UINTN                       Width,
+  IN CONST VOID                  *Buffer
+  )
+{
+  UINTN                     RegisterIndex;
+  AMD_SMRAM_SAVE_STATE_MAP  *CpuSaveState;
+
+  //
+  // Writes to EFI_MM_SAVE_STATE_REGISTER_LMA are ignored
+  //
+  if (Register == EFI_MM_SAVE_STATE_REGISTER_LMA) {
+    return EFI_SUCCESS;
+  }
+
+  //
+  // Writes to EFI_MM_SAVE_STATE_REGISTER_IO are not supported
+  //
+  if (Register == EFI_MM_SAVE_STATE_REGISTER_IO) {
+    return EFI_NOT_FOUND;
+  }
+
+  //
+  // Convert Register to a register lookup table index
+  //
+  RegisterIndex = MmSaveStateGetRegisterIndex (Register, AMD_MM_SAVE_STATE_REGISTER_MAX_INDEX);
+  if (RegisterIndex == 0) {
+    return EFI_NOT_FOUND;
+  }
+
+  CpuSaveState = gSmst->CpuSaveState[CpuIndex];
+
+  //
+  // Do not write non-writable SaveState, because it will cause exception.
+  //
+  if (!mCpuWidthOffset[RegisterIndex].Writeable) {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Check CPU mode
+  //
+  if (MmSaveStateGetRegisterLma () == EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT) {
+    //
+    // If 32-bit mode width is zero, then the specified register can not be accessed
+    //
+    if (mCpuWidthOffset[RegisterIndex].Width32 == 0) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
+    //
+    if (Width > mCpuWidthOffset[RegisterIndex].Width32) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    //
+    // Write SMM State register
+    //
+    ASSERT (CpuSaveState != NULL);
+    CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
+  } else {
+    //
+    // If 64-bit mode width is zero, then the specified register can not be accessed
+    //
+    if (mCpuWidthOffset[RegisterIndex].Width64 == 0) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
+    //
+    if (Width > mCpuWidthOffset[RegisterIndex].Width64) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    //
+    // Write lower 32-bits of SMM State register
+    //
+    CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
+    if (Width >= 4) {
+      //
+      // Write upper 32-bits of SMM State register
+      //
+      CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Returns LMA value of the Processor.
+
+  @retval     UINT8     returns LMA bit value.
+**/
+UINT8
+MmSaveStateGetRegisterLma (
+  VOID
+  )
+{
+  UINT32  LMAValue;
+
+  LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
+  if (LMAValue) {
+    return EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT;
+  }
+
+  return EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT;
+}
diff --git a/UefiCpuPkg/Library/MmSaveStateLib/MmSaveStateCommon.c b/UefiCpuPkg/Library/MmSaveStateLib/MmSaveStateCommon.c
new file mode 100644
index 000000000000..09c6c3f96fed
--- /dev/null
+++ b/UefiCpuPkg/Library/MmSaveStateLib/MmSaveStateCommon.c
@@ -0,0 +1,132 @@
+/** @file
+  Provides common supporting function to access SMRAM Save State Map
+
+  Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "MmSaveState.h"
+
+// Table used by MmSaveStateGetRegisterIndex() to convert an EFI_MM_SAVE_STATE_REGISTER
+// value to an index into a table of type CPU_MM_SAVE_STATE_LOOKUP_ENTRY
+CONST CPU_MM_SAVE_STATE_REGISTER_RANGE  mCpuRegisterRanges[] = {
+  MM_REGISTER_RANGE (EFI_MM_SAVE_STATE_REGISTER_GDTBASE, EFI_MM_SAVE_STATE_REGISTER_LDTINFO),
+  MM_REGISTER_RANGE (EFI_MM_SAVE_STATE_REGISTER_ES,      EFI_MM_SAVE_STATE_REGISTER_RIP),
+  MM_REGISTER_RANGE (EFI_MM_SAVE_STATE_REGISTER_RFLAGS,  EFI_MM_SAVE_STATE_REGISTER_CR4),
+  { (EFI_MM_SAVE_STATE_REGISTER)0,                       (EFI_MM_SAVE_STATE_REGISTER)0,      0}
+};
+
+extern CONST CPU_MM_SAVE_STATE_LOOKUP_ENTRY  mCpuWidthOffset[];
+
+/**
+  Read information from the CPU save state.
+
+  @param  Register  Specifies the CPU register to read form the save state.
+  @param  RegOffset Offset for the next register index.
+
+  @retval 0   Register is not valid
+  @retval >0  Index into mCpuWidthOffset[] associated with Register
+
+**/
+UINTN
+MmSaveStateGetRegisterIndex (
+  IN EFI_MM_SAVE_STATE_REGISTER  Register,
+  IN UINTN                       RegOffset
+  )
+{
+  UINTN  Index;
+  UINTN  Offset;
+
+  for (Index = 0, Offset = RegOffset; mCpuRegisterRanges[Index].Length != 0; Index++) {
+    if ((Register >= mCpuRegisterRanges[Index].Start) && (Register <= mCpuRegisterRanges[Index].End)) {
+      return Register - mCpuRegisterRanges[Index].Start + Offset;
+    }
+
+    Offset += mCpuRegisterRanges[Index].Length;
+  }
+
+  return 0;
+}
+
+/**
+  Read a CPU Save State register on the target processor.
+
+  This function abstracts the differences that whether the CPU Save State register is in the
+  IA32 CPU Save State Map or X64 CPU Save State Map.
+
+  This function supports reading a CPU Save State register in SMBase relocation handler.
+
+  @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
+  @param[in]  RegisterIndex  Index into mCpuWidthOffset[] look up table.
+  @param[in]  Width          The number of bytes to read from the CPU save state.
+  @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
+
+  @retval EFI_SUCCESS           The register was read from Save State.
+  @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
+  @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
+
+**/
+EFI_STATUS
+MmSaveStateReadRegisterByIndex (
+  IN UINTN  CpuIndex,
+  IN UINTN  RegisterIndex,
+  IN UINTN  Width,
+  OUT VOID  *Buffer
+  )
+{
+  if (RegisterIndex == 0) {
+    return EFI_NOT_FOUND;
+  }
+
+  if (MmSaveStateGetRegisterLma () == EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT) {
+    //
+    // If 32-bit mode width is zero, then the specified register can not be accessed
+    //
+    if (mCpuWidthOffset[RegisterIndex].Width32 == 0) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
+    //
+    if (Width > mCpuWidthOffset[RegisterIndex].Width32) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    //
+    // Write return buffer
+    //
+    ASSERT (gSmst->CpuSaveState[CpuIndex] != NULL);
+    CopyMem (Buffer, (UINT8 *)gSmst->CpuSaveState[CpuIndex] + mCpuWidthOffset[RegisterIndex].Offset32, Width);
+  } else {
+    //
+    // If 64-bit mode width is zero, then the specified register can not be accessed
+    //
+    if (mCpuWidthOffset[RegisterIndex].Width64 == 0) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
+    //
+    if (Width > mCpuWidthOffset[RegisterIndex].Width64) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    //
+    // Write lower 32-bits of return buffer
+    //
+    CopyMem (Buffer, (UINT8 *)gSmst->CpuSaveState[CpuIndex] + mCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width));
+    if (Width > 4) {
+      //
+      // Write upper 32-bits of return buffer
+      //
+      CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)gSmst->CpuSaveState[CpuIndex] + mCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v14 4/8] UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code
  2023-06-06  6:07 [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Abdul Lateef Attar
                   ` (2 preceding siblings ...)
  2023-06-06  6:07 ` [PATCH v14 3/8] UefiCpuPkg: Implements MmSaveStateLib library instance Abdul Lateef Attar
@ 2023-06-06  6:07 ` Abdul Lateef Attar
  2023-06-06  6:07 ` [PATCH v14 5/8] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family Abdul Lateef Attar
                   ` (4 subsequent siblings)
  8 siblings, 0 replies; 12+ messages in thread
From: Abdul Lateef Attar @ 2023-06-06  6:07 UTC (permalink / raw)
  To: devel
  Cc: Abdul Lateef Attar, Abner Chang, Paul Grimes, Eric Dong, Ray Ni,
	Rahul Kumar

From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

moves Intel-specific code to the arch-dependent file.
Other processor families might have different
implementation of these functions.
Hence, moving out of the common file.

Cc: Abner Chang <abner.chang@amd.com>
Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
---
 .../IntelSmmCpuFeaturesLib.c                  | 128 ++++++++++++++++++
 .../SmmCpuFeaturesLibCommon.c                 | 128 ------------------
 2 files changed, 128 insertions(+), 128 deletions(-)

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
index 1a2c706fa1f1..8f382b60266c 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
@@ -417,3 +417,131 @@ SmmCpuFeaturesSetSmmRegister (
     AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
   }
 }
+
+/**
+  This function updates the SMRAM save state on the currently executing CPU
+  to resume execution at a specific address after an RSM instruction.  This
+  function must evaluate the SMRAM save state to determine the execution mode
+  the RSM instruction resumes and update the resume execution address with
+  either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart
+  flag in the SMRAM save state must always be cleared.  This function returns
+  the value of the instruction pointer from the SMRAM save state that was
+  replaced.  If this function returns 0, then the SMRAM save state was not
+  modified.
+
+  This function is called during the very first SMI on each CPU after
+  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
+  to signal that the SMBASE of each CPU has been updated before the default
+  SMBASE address is used for the first SMI to the next CPU.
+
+  @param[in] CpuIndex                 The index of the CPU to hook.  The value
+                                      must be between 0 and the NumberOfCpus
+                                      field in the System Management System Table
+                                      (SMST).
+  @param[in] CpuState                 Pointer to SMRAM Save State Map for the
+                                      currently executing CPU.
+  @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
+                                      32-bit execution mode from 64-bit SMM.
+  @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
+                                      same execution mode as SMM.
+
+  @retval 0    This function did modify the SMRAM save state.
+  @retval > 0  The original instruction pointer value from the SMRAM save state
+               before it was replaced.
+**/
+UINT64
+EFIAPI
+SmmCpuFeaturesHookReturnFromSmm (
+  IN UINTN                 CpuIndex,
+  IN SMRAM_SAVE_STATE_MAP  *CpuState,
+  IN UINT64                NewInstructionPointer32,
+  IN UINT64                NewInstructionPointer
+  )
+{
+  return 0;
+}
+
+/**
+  Read an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
+  SMM Save Sate register.
+
+  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
+                        value must be between 0 and the NumberOfCpus field in
+                        the System Management System Table (SMST).
+  @param[in]  Register  The SMM Save State register to read.
+  @param[in]  Width     The number of bytes to read from the CPU save state.
+  @param[out] Buffer    Upon return, this holds the CPU register value read
+                        from the save state.
+
+  @retval EFI_SUCCESS           The register was read from Save State.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support reading Register.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmCpuFeaturesReadSaveStateRegister (
+  IN  UINTN                        CpuIndex,
+  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
+  IN  UINTN                        Width,
+  OUT VOID                         *Buffer
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Writes an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
+  SMM Save Sate register.
+
+  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] Register  The SMM Save State register to write.
+  @param[in] Width     The number of bytes to write to the CPU save state.
+  @param[in] Buffer    Upon entry, this holds the new CPU register value.
+
+  @retval EFI_SUCCESS           The register was written to Save State.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support writing Register.
+**/
+EFI_STATUS
+EFIAPI
+SmmCpuFeaturesWriteSaveStateRegister (
+  IN UINTN                        CpuIndex,
+  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
+  IN UINTN                        Width,
+  IN CONST VOID                   *Buffer
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+/**
+  Check to see if an SMM register is supported by a specified CPU.
+
+  @param[in] CpuIndex  The index of the CPU to check for SMM register support.
+                       The value must be between 0 and the NumberOfCpus field
+                       in the System Management System Table (SMST).
+  @param[in] RegName   Identifies the SMM register to check for support.
+
+  @retval TRUE   The SMM register specified by RegName is supported by the CPU
+                 specified by CpuIndex.
+  @retval FALSE  The SMM register specified by RegName is not supported by the
+                 CPU specified by CpuIndex.
+**/
+BOOLEAN
+EFIAPI
+SmmCpuFeaturesIsSmmRegisterSupported (
+  IN UINTN         CpuIndex,
+  IN SMM_REG_NAME  RegName
+  )
+{
+  if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {
+    return TRUE;
+  }
+
+  return FALSE;
+}
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
index 5498fda38da4..cbf4b495185b 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
@@ -17,49 +17,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 
 #include "CpuFeaturesLib.h"
 
-/**
-  This function updates the SMRAM save state on the currently executing CPU
-  to resume execution at a specific address after an RSM instruction.  This
-  function must evaluate the SMRAM save state to determine the execution mode
-  the RSM instruction resumes and update the resume execution address with
-  either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart
-  flag in the SMRAM save state must always be cleared.  This function returns
-  the value of the instruction pointer from the SMRAM save state that was
-  replaced.  If this function returns 0, then the SMRAM save state was not
-  modified.
-
-  This function is called during the very first SMI on each CPU after
-  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
-  to signal that the SMBASE of each CPU has been updated before the default
-  SMBASE address is used for the first SMI to the next CPU.
-
-  @param[in] CpuIndex                 The index of the CPU to hook.  The value
-                                      must be between 0 and the NumberOfCpus
-                                      field in the System Management System Table
-                                      (SMST).
-  @param[in] CpuState                 Pointer to SMRAM Save State Map for the
-                                      currently executing CPU.
-  @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
-                                      32-bit execution mode from 64-bit SMM.
-  @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
-                                      same execution mode as SMM.
-
-  @retval 0    This function did modify the SMRAM save state.
-  @retval > 0  The original instruction pointer value from the SMRAM save state
-               before it was replaced.
-**/
-UINT64
-EFIAPI
-SmmCpuFeaturesHookReturnFromSmm (
-  IN UINTN                 CpuIndex,
-  IN SMRAM_SAVE_STATE_MAP  *CpuState,
-  IN UINT64                NewInstructionPointer32,
-  IN UINT64                NewInstructionPointer
-  )
-{
-  return 0;
-}
-
 /**
   Hook point in normal execution mode that allows the one CPU that was elected
   as monarch during System Management Mode initialization to perform additional
@@ -90,91 +47,6 @@ SmmCpuFeaturesRendezvousExit (
 {
 }
 
-/**
-  Check to see if an SMM register is supported by a specified CPU.
-
-  @param[in] CpuIndex  The index of the CPU to check for SMM register support.
-                       The value must be between 0 and the NumberOfCpus field
-                       in the System Management System Table (SMST).
-  @param[in] RegName   Identifies the SMM register to check for support.
-
-  @retval TRUE   The SMM register specified by RegName is supported by the CPU
-                 specified by CpuIndex.
-  @retval FALSE  The SMM register specified by RegName is not supported by the
-                 CPU specified by CpuIndex.
-**/
-BOOLEAN
-EFIAPI
-SmmCpuFeaturesIsSmmRegisterSupported (
-  IN UINTN         CpuIndex,
-  IN SMM_REG_NAME  RegName
-  )
-{
-  if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) {
-    return TRUE;
-  }
-
-  return FALSE;
-}
-
-/**
-  Read an SMM Save State register on the target processor.  If this function
-  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
-  SMM Save Sate register.
-
-  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
-                        value must be between 0 and the NumberOfCpus field in
-                        the System Management System Table (SMST).
-  @param[in]  Register  The SMM Save State register to read.
-  @param[in]  Width     The number of bytes to read from the CPU save state.
-  @param[out] Buffer    Upon return, this holds the CPU register value read
-                        from the save state.
-
-  @retval EFI_SUCCESS           The register was read from Save State.
-  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
-  @retval EFI_UNSUPPORTED       This function does not support reading Register.
-
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesReadSaveStateRegister (
-  IN  UINTN                        CpuIndex,
-  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN  UINTN                        Width,
-  OUT VOID                         *Buffer
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-/**
-  Writes an SMM Save State register on the target processor.  If this function
-  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
-  SMM Save Sate register.
-
-  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
-                       value must be between 0 and the NumberOfCpus field in
-                       the System Management System Table (SMST).
-  @param[in] Register  The SMM Save State register to write.
-  @param[in] Width     The number of bytes to write to the CPU save state.
-  @param[in] Buffer    Upon entry, this holds the new CPU register value.
-
-  @retval EFI_SUCCESS           The register was written to Save State.
-  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
-  @retval EFI_UNSUPPORTED       This function does not support writing Register.
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesWriteSaveStateRegister (
-  IN UINTN                        CpuIndex,
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN UINTN                        Width,
-  IN CONST VOID                   *Buffer
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
 /**
   This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
   notification is completely processed.
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v14 5/8] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family
  2023-06-06  6:07 [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Abdul Lateef Attar
                   ` (3 preceding siblings ...)
  2023-06-06  6:07 ` [PATCH v14 4/8] UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code Abdul Lateef Attar
@ 2023-06-06  6:07 ` Abdul Lateef Attar
  2023-06-06  6:07 ` [PATCH v14 6/8] UefiCpuPkg: Implements MmSaveStateLib for Intel Abdul Lateef Attar
                   ` (3 subsequent siblings)
  8 siblings, 0 replies; 12+ messages in thread
From: Abdul Lateef Attar @ 2023-06-06  6:07 UTC (permalink / raw)
  To: devel
  Cc: Abdul Lateef Attar, Paul Grimes, Abner Chang, Eric Dong, Ray Ni,
	Rahul Kumar, Abdul Lateef Attar

From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

Implements interfaces to read and write save state
registers of AMD's processor family.
Initializes processor SMMADDR and MASK depends
on PcdSmrrEnable flag.
Program or corrects the IP once control returns from SMM.

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
---
 UefiCpuPkg/UefiCpuPkg.dsc                     |   7 +
 .../AmdSmmCpuFeaturesLib.inf                  |  38 ++
 .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c  | 445 ++++++++++++++++++
 3 files changed, 490 insertions(+)
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c

diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 8b0cb02a80e8..6e29850bed17 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -169,6 +169,12 @@ [Components.IA32, Components.X64]
     <LibraryClasses>
       SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
   }
+  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {
+    <Defines>
+      FILE_GUID = B7242C74-BD21-49EE-84B4-07162E8C080D
+    <LibraryClasses>
+      SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
+  }
   UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
   UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
   UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
@@ -185,6 +191,7 @@ [Components.IA32, Components.X64]
       UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestResultReportLibConOut.inf
   }
   UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
+  UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
 
 [Components.X64]
   UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHandlerLibUnitTest.inf
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
new file mode 100644
index 000000000000..5ee8a2e720c9
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
@@ -0,0 +1,38 @@
+## @file
+#  The CPU specific programming for PiSmmCpuDxeSmm module.
+#
+#  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+#  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AmdSmmCpuFeaturesLib
+  MODULE_UNI_FILE                = SmmCpuFeaturesLib.uni
+  FILE_GUID                      = 5849E964-78EC-428E-8CBD-848A7E359134
+  MODULE_TYPE                    = DXE_SMM_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SmmCpuFeaturesLib
+  CONSTRUCTOR                    = SmmCpuFeaturesLibConstructor
+
+[Sources]
+  SmmCpuFeaturesLib.c
+  SmmCpuFeaturesLibCommon.c
+  AmdSmmCpuFeaturesLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  PcdLib
+  MemoryAllocationLib
+  DebugLib
+  MmSaveStateLib
+
+[FeaturePcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable               ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable  ## CONSUMES
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c
new file mode 100644
index 000000000000..1473f0a51fe2
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c
@@ -0,0 +1,445 @@
+/** @file
+Implementation specific to the SmmCpuFeatureLib library instance
+for AMD based platforms.
+
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/SmmCpuFeaturesLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Register/Amd/SmramSaveStateMap.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MmSaveStateLib.h>
+
+// EFER register LMA bit
+#define LMA  BIT10
+
+// Machine Specific Registers (MSRs)
+#define SMMADDR_ADDRESS  0xC0010112ul
+#define SMMMASK_ADDRESS  0xC0010113ul
+#define EFER_ADDRESS     0XC0000080ul
+
+// The mode of the CPU at the time an SMI occurs
+STATIC UINT8  mSmmSaveStateRegisterLma;
+
+/**
+  Read an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
+  SMM Save Sate register.
+
+  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
+                        value must be between 0 and the NumberOfCpus field in
+                        the System Management System Table (SMST).
+  @param[in]  Register  The SMM Save State register to read.
+  @param[in]  Width     The number of bytes to read from the CPU save state.
+  @param[out] Buffer    Upon return, this holds the CPU register value read
+                        from the save state.
+
+  @retval EFI_SUCCESS           The register was read from Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support reading Register.
+
+**/
+EFI_STATUS
+EFIAPI
+SmmCpuFeaturesReadSaveStateRegister (
+  IN  UINTN                        CpuIndex,
+  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
+  IN  UINTN                        Width,
+  OUT VOID                         *Buffer
+  )
+{
+  return MmSaveStateReadRegister (CpuIndex, Register, Width, Buffer);
+}
+
+/**
+  Writes an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
+  SMM Save Sate register.
+
+  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] Register  The SMM Save State register to write.
+  @param[in] Width     The number of bytes to write to the CPU save state.
+  @param[in] Buffer    Upon entry, this holds the new CPU register value.
+
+  @retval EFI_SUCCESS           The register was written to Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support writing Register.
+**/
+EFI_STATUS
+EFIAPI
+SmmCpuFeaturesWriteSaveStateRegister (
+  IN UINTN                        CpuIndex,
+  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
+  IN UINTN                        Width,
+  IN CONST VOID                   *Buffer
+  )
+{
+  return MmSaveStateWriteRegister (CpuIndex, Register, Width, Buffer);
+}
+
+/**
+  Performs library initialization.
+
+  This initialization function contains common functionality shared betwen all
+  library instance constructors.
+
+**/
+VOID
+CpuFeaturesLibInitialization (
+  VOID
+  )
+{
+  UINT32  LMAValue;
+
+  LMAValue                 = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
+  mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
+  if (LMAValue) {
+    mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
+  }
+}
+
+/**
+  Called during the very first SMI into System Management Mode to initialize
+  CPU features, including SMBASE, for the currently executing CPU.  Since this
+  is the first SMI, the SMRAM Save State Map is at the default address of
+  AMD_SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET.  The currently executing
+  CPU is specified by CpuIndex and CpuIndex can be used to access information
+  about the currently executing CPU in the ProcessorInfo array and the
+  HotPlugCpuData data structure.
+
+  @param[in] CpuIndex        The index of the CPU to initialize.  The value
+                             must be between 0 and the NumberOfCpus field in
+                             the System Management System Table (SMST).
+  @param[in] IsMonarch       TRUE if the CpuIndex is the index of the CPU that
+                             was elected as monarch during System Management
+                             Mode initialization.
+                             FALSE if the CpuIndex is not the index of the CPU
+                             that was elected as monarch during System
+                             Management Mode initialization.
+  @param[in] ProcessorInfo   Pointer to an array of EFI_PROCESSOR_INFORMATION
+                             structures.  ProcessorInfo[CpuIndex] contains the
+                             information for the currently executing CPU.
+  @param[in] CpuHotPlugData  Pointer to the CPU_HOT_PLUG_DATA structure that
+                             contains the ApidId and SmBase arrays.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesInitializeProcessor (
+  IN UINTN                      CpuIndex,
+  IN BOOLEAN                    IsMonarch,
+  IN EFI_PROCESSOR_INFORMATION  *ProcessorInfo,
+  IN CPU_HOT_PLUG_DATA          *CpuHotPlugData
+  )
+{
+  AMD_SMRAM_SAVE_STATE_MAP  *CpuState;
+  UINT32                    LMAValue;
+
+  //
+  // Configure SMBASE.
+  //
+  CpuState             = (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+  CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
+
+  // Re-initialize the value of mSmmSaveStateRegisterLma flag which might have been changed in PiCpuSmmDxeSmm Driver
+  // Entry point, to make sure correct value on AMD platform is assigned to be used by SmmCpuFeaturesLib.
+  LMAValue                 = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA;
+  mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;
+  if (LMAValue) {
+    mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
+  }
+
+  //
+  // If SMRR is supported, then program SMRR base/mask MSRs.
+  // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.
+  // The code that initializes SMM environment is running in normal mode
+  // from SMRAM region.  If SMRR is enabled here, then the SMRAM region
+  // is protected and the normal mode code execution will fail.
+  //
+  if (FeaturePcdGet (PcdSmrrEnable)) {
+    //
+    // SMRR size cannot be less than 4-KBytes
+    // SMRR size must be of length 2^n
+    // SMRR base alignment cannot be less than SMRR length
+    //
+    if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
+        (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
+        ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))
+    {
+      //
+      // Print message and halt if CPU is Monarch
+      //
+      if (IsMonarch) {
+        DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n"));
+        CpuDeadLoop ();
+      }
+    } else {
+      AsmWriteMsr64 (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase);
+      AsmWriteMsr64 (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData->SmrrSize - 1)) | 0x6600));
+    }
+  }
+}
+
+/**
+  This function updates the SMRAM save state on the currently executing CPU
+  to resume execution at a specific address after an RSM instruction.  This
+  function must evaluate the SMRAM save state to determine the execution mode
+  the RSM instruction resumes and update the resume execution address with
+  either NewInstructionPointer32 or NewInstructionPoint.  The auto HALT restart
+  flag in the SMRAM save state must always be cleared.  This function returns
+  the value of the instruction pointer from the SMRAM save state that was
+  replaced.  If this function returns 0, then the SMRAM save state was not
+  modified.
+
+  This function is called during the very first SMI on each CPU after
+  SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode
+  to signal that the SMBASE of each CPU has been updated before the default
+  SMBASE address is used for the first SMI to the next CPU.
+
+  @param[in] CpuIndex                 The index of the CPU to hook.  The value
+                                      must be between 0 and the NumberOfCpus
+                                      field in the System Management System Table
+                                      (SMST).
+  @param[in] CpuState                 Pointer to SMRAM Save State Map for the
+                                      currently executing CPU.
+  @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
+                                      32-bit execution mode from 64-bit SMM.
+  @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
+                                      same execution mode as SMM.
+
+  @retval 0    This function did modify the SMRAM save state.
+  @retval > 0  The original instruction pointer value from the SMRAM save state
+               before it was replaced.
+**/
+UINT64
+EFIAPI
+SmmCpuFeaturesHookReturnFromSmm (
+  IN UINTN                 CpuIndex,
+  IN SMRAM_SAVE_STATE_MAP  *CpuState,
+  IN UINT64                NewInstructionPointer32,
+  IN UINT64                NewInstructionPointer
+  )
+{
+  UINT64                    OriginalInstructionPointer;
+  AMD_SMRAM_SAVE_STATE_MAP  *AmdCpuState;
+
+  AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState;
+
+  if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
+    OriginalInstructionPointer = (UINT64)AmdCpuState->x86._EIP;
+    AmdCpuState->x86._EIP      = (UINT32)NewInstructionPointer;
+    //
+    // Clear the auto HALT restart flag so the RSM instruction returns
+    // program control to the instruction following the HLT instruction.
+    //
+    if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != 0) {
+      AmdCpuState->x86.AutoHALTRestart &= ~BIT0;
+    }
+  } else {
+    OriginalInstructionPointer = AmdCpuState->x64._RIP;
+    if ((AmdCpuState->x64.EFER & LMA) == 0) {
+      AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer32;
+    } else {
+      AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer;
+    }
+
+    //
+    // Clear the auto HALT restart flag so the RSM instruction returns
+    // program control to the instruction following the HLT instruction.
+    //
+    if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) {
+      AmdCpuState->x64.AutoHALTRestart &= ~BIT0;
+    }
+  }
+
+  return OriginalInstructionPointer;
+}
+
+/**
+  Return the size, in bytes, of a custom SMI Handler in bytes.  If 0 is
+  returned, then a custom SMI handler is not provided by this library,
+  and the default SMI handler must be used.
+
+  @retval 0    Use the default SMI handler.
+  @retval > 0  Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler()
+               The caller is required to allocate enough SMRAM for each CPU to
+               support the size of the custom SMI handler.
+**/
+UINTN
+EFIAPI
+SmmCpuFeaturesGetSmiHandlerSize (
+  VOID
+  )
+{
+  return 0;
+}
+
+/**
+  Install a custom SMI handler for the CPU specified by CpuIndex.  This function
+  is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater
+  than zero and is called by the CPU that was elected as monarch during System
+  Management Mode initialization.
+
+  @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.
+                        The value must be between 0 and the NumberOfCpus field
+                        in the System Management System Table (SMST).
+  @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.
+  @param[in] SmiStack   The stack to use when an SMI is processed by the
+                        the CPU specified by CpuIndex.
+  @param[in] StackSize  The size, in bytes, if the stack used when an SMI is
+                        processed by the CPU specified by CpuIndex.
+  @param[in] GdtBase    The base address of the GDT to use when an SMI is
+                        processed by the CPU specified by CpuIndex.
+  @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is
+                        processed by the CPU specified by CpuIndex.
+  @param[in] IdtBase    The base address of the IDT to use when an SMI is
+                        processed by the CPU specified by CpuIndex.
+  @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is
+                        processed by the CPU specified by CpuIndex.
+  @param[in] Cr3        The base address of the page tables to use when an SMI
+                        is processed by the CPU specified by CpuIndex.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesInstallSmiHandler (
+  IN UINTN   CpuIndex,
+  IN UINT32  SmBase,
+  IN VOID    *SmiStack,
+  IN UINTN   StackSize,
+  IN UINTN   GdtBase,
+  IN UINTN   GdtSize,
+  IN UINTN   IdtBase,
+  IN UINTN   IdtSize,
+  IN UINT32  Cr3
+  )
+{
+}
+
+/**
+  Determines if MTRR registers must be configured to set SMRAM cache-ability
+  when executing in System Management Mode.
+
+  @retval TRUE   MTRR registers must be configured to set SMRAM cache-ability.
+  @retval FALSE  MTRR registers do not need to be configured to set SMRAM
+                 cache-ability.
+**/
+BOOLEAN
+EFIAPI
+SmmCpuFeaturesNeedConfigureMtrrs (
+  VOID
+  )
+{
+  return FALSE;
+}
+
+/**
+  Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
+  returns TRUE.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesDisableSmrr (
+  VOID
+  )
+{
+}
+
+/**
+  Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs()
+  returns TRUE.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesReenableSmrr (
+  VOID
+  )
+{
+}
+
+/**
+  Processor specific hook point each time a CPU enters System Management Mode.
+
+  @param[in] CpuIndex  The index of the CPU that has entered SMM.  The value
+                       must be between 0 and the NumberOfCpus field in the
+                       System Management System Table (SMST).
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesRendezvousEntry (
+  IN UINTN  CpuIndex
+  )
+{
+}
+
+/**
+  Returns the current value of the SMM register for the specified CPU.
+  If the SMM register is not supported, then 0 is returned.
+
+  @param[in] CpuIndex  The index of the CPU to read the SMM register.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] RegName   Identifies the SMM register to read.
+
+  @return  The value of the SMM register specified by RegName from the CPU
+           specified by CpuIndex.
+**/
+UINT64
+EFIAPI
+SmmCpuFeaturesGetSmmRegister (
+  IN UINTN         CpuIndex,
+  IN SMM_REG_NAME  RegName
+  )
+{
+  return 0;
+}
+
+/**
+  Sets the value of an SMM register on a specified CPU.
+  If the SMM register is not supported, then no action is performed.
+
+  @param[in] CpuIndex  The index of the CPU to write the SMM register.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] RegName   Identifies the SMM register to write.
+                       registers are read-only.
+  @param[in] Value     The value to write to the SMM register.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesSetSmmRegister (
+  IN UINTN         CpuIndex,
+  IN SMM_REG_NAME  RegName,
+  IN UINT64        Value
+  )
+{
+}
+
+/**
+  Check to see if an SMM register is supported by a specified CPU.
+
+  @param[in] CpuIndex  The index of the CPU to check for SMM register support.
+                       The value must be between 0 and the NumberOfCpus field
+                       in the System Management System Table (SMST).
+  @param[in] RegName   Identifies the SMM register to check for support.
+
+  @retval TRUE   The SMM register specified by RegName is supported by the CPU
+                 specified by CpuIndex.
+  @retval FALSE  The SMM register specified by RegName is not supported by the
+                 CPU specified by CpuIndex.
+**/
+BOOLEAN
+EFIAPI
+SmmCpuFeaturesIsSmmRegisterSupported (
+  IN UINTN         CpuIndex,
+  IN SMM_REG_NAME  RegName
+  )
+{
+  return FALSE;
+}
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v14 6/8] UefiCpuPkg: Implements MmSaveStateLib for Intel
  2023-06-06  6:07 [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Abdul Lateef Attar
                   ` (4 preceding siblings ...)
  2023-06-06  6:07 ` [PATCH v14 5/8] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family Abdul Lateef Attar
@ 2023-06-06  6:07 ` Abdul Lateef Attar
  2023-06-06  6:07 ` [PATCH v14 7/8] UefiCpuPkg: Removes SmmCpuFeaturesReadSaveStateRegister Abdul Lateef Attar
                   ` (2 subsequent siblings)
  8 siblings, 0 replies; 12+ messages in thread
From: Abdul Lateef Attar @ 2023-06-06  6:07 UTC (permalink / raw)
  To: devel
  Cc: Abdul Lateef Attar, Paul Grimes, Abner Chang, Eric Dong, Ray Ni,
	Rahul Kumar, Gerd Hoffmann

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

Implements MmSaveStateLib library interfaces
to read and write save state
registers for Intel processor family.

Moves Intel and AMD common functionality to common area.

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
---
 UefiCpuPkg/UefiCpuPkg.dsc                     |   3 +
 .../MmSaveStateLib/IntelMmSaveStateLib.inf    |  34 ++
 .../Library/MmSaveStateLib/IntelMmSaveState.c | 410 ++++++++++++++++++
 3 files changed, 447 insertions(+)
 create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
 create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveState.c

diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 6e29850bed17..eb6bdc5bef63 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -101,6 +101,7 @@ [LibraryClasses.common.DXE_SMM_DRIVER]
   HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
   CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
   MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
+  MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
 
 [LibraryClasses.common.MM_STANDALONE]
   MmServicesTableLib|MdePkg/Library/StandaloneMmServicesTableLib/StandaloneMmServicesTableLib.inf
@@ -174,6 +175,7 @@ [Components.IA32, Components.X64]
       FILE_GUID = B7242C74-BD21-49EE-84B4-07162E8C080D
     <LibraryClasses>
       SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
+      MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
   }
   UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
   UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
@@ -191,6 +193,7 @@ [Components.IA32, Components.X64]
       UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestResultReportLibConOut.inf
   }
   UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
+  UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
   UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
 
 [Components.X64]
diff --git a/UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf b/UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
new file mode 100644
index 000000000000..b92dfa643203
--- /dev/null
+++ b/UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
@@ -0,0 +1,34 @@
+## @file
+# SMM Smram save state service lib.
+#
+# This is SMM Smram save state service lib that provide service to read and
+# save savestate area registers.
+#
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 1.29
+  BASE_NAME                      = IntelMmSaveStateLib
+  FILE_GUID                      = 37E8137B-9F74-4250-8951-7A970A3C39C0
+  MODULE_TYPE                    = DXE_SMM_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = MmSaveStateLib
+
+[Sources]
+  MmSaveState.h
+  MmSaveStateCommon.c
+  IntelMmSaveState.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  DebugLib
+  SmmServicesTableLib
diff --git a/UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveState.c b/UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveState.c
new file mode 100644
index 000000000000..fd321bb571d5
--- /dev/null
+++ b/UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveState.c
@@ -0,0 +1,410 @@
+/** @file
+Provides services to access SMRAM Save State Map
+
+Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "MmSaveState.h"
+#include <Register/Intel/SmramSaveStateMap.h>
+#include <Register/Intel/Cpuid.h>
+#include <Library/BaseLib.h>
+
+#define INTEL_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX   1
+#define INTEL_MM_SAVE_STATE_REGISTER_IOMISC_INDEX     2
+#define INTEL_MM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX  3
+#define INTEL_MM_SAVE_STATE_REGISTER_MAX_INDEX        4
+
+///
+/// Macro used to simplify the lookup table entries of type CPU_MM_SAVE_STATE_LOOKUP_ENTRY
+///
+#define MM_CPU_OFFSET(Field)  OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
+
+///
+/// Lookup table used to retrieve the widths and offsets associated with each
+/// supported EFI_MM_SAVE_STATE_REGISTER value
+///
+CONST CPU_MM_SAVE_STATE_LOOKUP_ENTRY  mCpuWidthOffset[] = {
+  { 0, 0, 0,                             0,                                  0,                                  FALSE }, //  Reserved
+
+  //
+  // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.
+  //
+  { 4, 4, MM_CPU_OFFSET (x86.SMMRevId),  MM_CPU_OFFSET (x64.SMMRevId),       0,                                  FALSE }, // INTEL_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX  = 1
+  { 4, 4, MM_CPU_OFFSET (x86.IOMisc),    MM_CPU_OFFSET (x64.IOMisc),         0,                                  FALSE }, // INTEL_MM_SAVE_STATE_REGISTER_IOMISC_INDEX    = 2
+  { 4, 8, MM_CPU_OFFSET (x86.IOMemAddr), MM_CPU_OFFSET (x64.IOMemAddr),      MM_CPU_OFFSET (x64.IOMemAddr) + 4,  FALSE }, // INTEL_MM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3
+
+  //
+  // CPU Save State registers defined in PI SMM CPU Protocol.
+  //
+  { 0, 8, 0,                             MM_CPU_OFFSET (x64.GdtBaseLoDword), MM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_GDTBASE  = 4
+  { 0, 8, 0,                             MM_CPU_OFFSET (x64.IdtBaseLoDword), MM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_IDTBASE  = 5
+  { 0, 8, 0,                             MM_CPU_OFFSET (x64.LdtBaseLoDword), MM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_LDTBASE  = 6
+  { 0, 0, 0,                             0,                                  0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT = 7
+  { 0, 0, 0,                             0,                                  0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT = 8
+  { 0, 0, 0,                             0,                                  0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT = 9
+  { 0, 0, 0,                             0,                                  0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_LDTINFO  = 10
+
+  { 4, 4, MM_CPU_OFFSET (x86._ES),       MM_CPU_OFFSET (x64._ES),            0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_ES       = 20
+  { 4, 4, MM_CPU_OFFSET (x86._CS),       MM_CPU_OFFSET (x64._CS),            0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_CS       = 21
+  { 4, 4, MM_CPU_OFFSET (x86._SS),       MM_CPU_OFFSET (x64._SS),            0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_SS       = 22
+  { 4, 4, MM_CPU_OFFSET (x86._DS),       MM_CPU_OFFSET (x64._DS),            0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_DS       = 23
+  { 4, 4, MM_CPU_OFFSET (x86._FS),       MM_CPU_OFFSET (x64._FS),            0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_FS       = 24
+  { 4, 4, MM_CPU_OFFSET (x86._GS),       MM_CPU_OFFSET (x64._GS),            0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_GS       = 25
+  { 0, 4, 0,                             MM_CPU_OFFSET (x64._LDTR),          0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL = 26
+  { 4, 4, MM_CPU_OFFSET (x86._TR),       MM_CPU_OFFSET (x64._TR),            0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_TR_SEL   = 27
+  { 4, 8, MM_CPU_OFFSET (x86._DR7),      MM_CPU_OFFSET (x64._DR7),           MM_CPU_OFFSET (x64._DR7)    + 4,    FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_DR7      = 28
+  { 4, 8, MM_CPU_OFFSET (x86._DR6),      MM_CPU_OFFSET (x64._DR6),           MM_CPU_OFFSET (x64._DR6)    + 4,    FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_DR6      = 29
+  { 0, 8, 0,                             MM_CPU_OFFSET (x64._R8),            MM_CPU_OFFSET (x64._R8)     + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_R8       = 30
+  { 0, 8, 0,                             MM_CPU_OFFSET (x64._R9),            MM_CPU_OFFSET (x64._R9)     + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_R9       = 31
+  { 0, 8, 0,                             MM_CPU_OFFSET (x64._R10),           MM_CPU_OFFSET (x64._R10)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_R10      = 32
+  { 0, 8, 0,                             MM_CPU_OFFSET (x64._R11),           MM_CPU_OFFSET (x64._R11)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_R11      = 33
+  { 0, 8, 0,                             MM_CPU_OFFSET (x64._R12),           MM_CPU_OFFSET (x64._R12)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_R12      = 34
+  { 0, 8, 0,                             MM_CPU_OFFSET (x64._R13),           MM_CPU_OFFSET (x64._R13)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_R13      = 35
+  { 0, 8, 0,                             MM_CPU_OFFSET (x64._R14),           MM_CPU_OFFSET (x64._R14)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_R14      = 36
+  { 0, 8, 0,                             MM_CPU_OFFSET (x64._R15),           MM_CPU_OFFSET (x64._R15)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_R15      = 37
+  { 4, 8, MM_CPU_OFFSET (x86._EAX),      MM_CPU_OFFSET (x64._RAX),           MM_CPU_OFFSET (x64._RAX)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_RAX      = 38
+  { 4, 8, MM_CPU_OFFSET (x86._EBX),      MM_CPU_OFFSET (x64._RBX),           MM_CPU_OFFSET (x64._RBX)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_RBX      = 39
+  { 4, 8, MM_CPU_OFFSET (x86._ECX),      MM_CPU_OFFSET (x64._RCX),           MM_CPU_OFFSET (x64._RCX)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_RCX      = 40
+  { 4, 8, MM_CPU_OFFSET (x86._EDX),      MM_CPU_OFFSET (x64._RDX),           MM_CPU_OFFSET (x64._RDX)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_RDX      = 41
+  { 4, 8, MM_CPU_OFFSET (x86._ESP),      MM_CPU_OFFSET (x64._RSP),           MM_CPU_OFFSET (x64._RSP)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_RSP      = 42
+  { 4, 8, MM_CPU_OFFSET (x86._EBP),      MM_CPU_OFFSET (x64._RBP),           MM_CPU_OFFSET (x64._RBP)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_RBP      = 43
+  { 4, 8, MM_CPU_OFFSET (x86._ESI),      MM_CPU_OFFSET (x64._RSI),           MM_CPU_OFFSET (x64._RSI)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_RSI      = 44
+  { 4, 8, MM_CPU_OFFSET (x86._EDI),      MM_CPU_OFFSET (x64._RDI),           MM_CPU_OFFSET (x64._RDI)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_RDI      = 45
+  { 4, 8, MM_CPU_OFFSET (x86._EIP),      MM_CPU_OFFSET (x64._RIP),           MM_CPU_OFFSET (x64._RIP)    + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_RIP      = 46
+
+  { 4, 8, MM_CPU_OFFSET (x86._EFLAGS),   MM_CPU_OFFSET (x64._RFLAGS),        MM_CPU_OFFSET (x64._RFLAGS) + 4,    TRUE  }, //  EFI_MM_SAVE_STATE_REGISTER_RFLAGS   = 51
+  { 4, 8, MM_CPU_OFFSET (x86._CR0),      MM_CPU_OFFSET (x64._CR0),           MM_CPU_OFFSET (x64._CR0)    + 4,    FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_CR0      = 52
+  { 4, 8, MM_CPU_OFFSET (x86._CR3),      MM_CPU_OFFSET (x64._CR3),           MM_CPU_OFFSET (x64._CR3)    + 4,    FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_CR3      = 53
+  { 0, 4, 0,                             MM_CPU_OFFSET (x64._CR4),           0,                                  FALSE }, //  EFI_MM_SAVE_STATE_REGISTER_CR4      = 54
+};
+
+///
+/// Structure used to build a lookup table for the IOMisc width information
+///
+typedef struct {
+  UINT8                         Width;
+  EFI_MM_SAVE_STATE_IO_WIDTH    IoWidth;
+} CPU_MM_SAVE_STATE_IO_WIDTH;
+
+///
+/// Lookup table for the IOMisc width information
+///
+STATIC CONST CPU_MM_SAVE_STATE_IO_WIDTH  mSmmCpuIoWidth[] = {
+  { 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8  },  // Undefined           = 0
+  { 1, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8  },  // SMM_IO_LENGTH_BYTE  = 1
+  { 2, EFI_MM_SAVE_STATE_IO_WIDTH_UINT16 },  // SMM_IO_LENGTH_WORD  = 2
+  { 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8  },  // Undefined           = 3
+  { 4, EFI_MM_SAVE_STATE_IO_WIDTH_UINT32 },  // SMM_IO_LENGTH_DWORD = 4
+  { 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8  },  // Undefined           = 5
+  { 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8  },  // Undefined           = 6
+  { 0, EFI_MM_SAVE_STATE_IO_WIDTH_UINT8  }   // Undefined           = 7
+};
+
+///
+/// Lookup table for the IOMisc type information
+///
+STATIC CONST EFI_MM_SAVE_STATE_IO_TYPE  mSmmCpuIoType[] = {
+  EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT,     // SMM_IO_TYPE_OUT_DX        = 0
+  EFI_MM_SAVE_STATE_IO_TYPE_INPUT,      // SMM_IO_TYPE_IN_DX         = 1
+  EFI_MM_SAVE_STATE_IO_TYPE_STRING,     // SMM_IO_TYPE_OUTS          = 2
+  EFI_MM_SAVE_STATE_IO_TYPE_STRING,     // SMM_IO_TYPE_INS           = 3
+  (EFI_MM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 4
+  (EFI_MM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 5
+  EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_OUTS      = 6
+  EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_INS       = 7
+  EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT,     // SMM_IO_TYPE_OUT_IMMEDIATE = 8
+  EFI_MM_SAVE_STATE_IO_TYPE_INPUT,      // SMM_IO_TYPE_OUT_IMMEDIATE = 9
+  (EFI_MM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 10
+  (EFI_MM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 11
+  (EFI_MM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 12
+  (EFI_MM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 13
+  (EFI_MM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 14
+  (EFI_MM_SAVE_STATE_IO_TYPE)0          // Undefined                 = 15
+};
+
+/**
+  Read an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
+  SMM Save Sate register.
+
+  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
+                        value must be between 0 and the NumberOfCpus field in
+                        the System Management System Table (SMST).
+  @param[in]  Register  The SMM Save State register to read.
+  @param[in]  Width     The number of bytes to read from the CPU save state.
+  @param[out] Buffer    Upon return, this holds the CPU register value read
+                        from the save state.
+
+  @retval EFI_SUCCESS           The register was read from Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support reading Register.
+  @retval EFI_NOT_FOUND         If desired Register not found.
+**/
+EFI_STATUS
+EFIAPI
+MmSaveStateReadRegister (
+  IN  UINTN                       CpuIndex,
+  IN  EFI_MM_SAVE_STATE_REGISTER  Register,
+  IN  UINTN                       Width,
+  OUT VOID                        *Buffer
+  )
+{
+  UINT32                     SmmRevId;
+  SMRAM_SAVE_STATE_IOMISC    IoMisc;
+  EFI_MM_SAVE_STATE_IO_INFO  *IoInfo;
+
+  //
+  // Check for special EFI_MM_SAVE_STATE_REGISTER_LMA
+  //
+  if (Register == EFI_MM_SAVE_STATE_REGISTER_LMA) {
+    //
+    // Only byte access is supported for this register
+    //
+    if (Width != 1) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    *(UINT8 *)Buffer = MmSaveStateGetRegisterLma ();
+
+    return EFI_SUCCESS;
+  }
+
+  //
+  // Check for special EFI_MM_SAVE_STATE_REGISTER_IO
+  //
+  if (Register == EFI_MM_SAVE_STATE_REGISTER_IO) {
+    //
+    // Get SMM Revision ID
+    //
+    MmSaveStateReadRegisterByIndex (CpuIndex, INTEL_MM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);
+
+    //
+    // See if the CPU supports the IOMisc register in the save state
+    //
+    if (SmmRevId < SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // Get the IOMisc register value
+    //
+    MmSaveStateReadRegisterByIndex (CpuIndex, INTEL_MM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof (IoMisc.Uint32), &IoMisc.Uint32);
+
+    //
+    // Check for the SMI_FLAG in IOMisc
+    //
+    if (IoMisc.Bits.SmiFlag == 0) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS.
+    //
+    if ((mSmmCpuIoType[IoMisc.Bits.Type] != EFI_MM_SAVE_STATE_IO_TYPE_INPUT) &&
+        (mSmmCpuIoType[IoMisc.Bits.Type] != EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT))
+    {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // Compute index for the I/O Length and I/O Type lookup tables
+    //
+    if ((mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0) || (mSmmCpuIoType[IoMisc.Bits.Type] == 0)) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // Make sure the incoming buffer is large enough to hold IoInfo before accessing
+    //
+    if (Width < sizeof (EFI_MM_SAVE_STATE_IO_INFO)) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    //
+    // Zero the IoInfo structure that will be returned in Buffer
+    //
+    IoInfo = (EFI_MM_SAVE_STATE_IO_INFO *)Buffer;
+    ZeroMem (IoInfo, sizeof (EFI_MM_SAVE_STATE_IO_INFO));
+
+    //
+    // Use lookup tables to help fill in all the fields of the IoInfo structure
+    //
+    IoInfo->IoPort  = (UINT16)IoMisc.Bits.Port;
+    IoInfo->IoWidth = mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth;
+    IoInfo->IoType  = mSmmCpuIoType[IoMisc.Bits.Type];
+    MmSaveStateReadRegister (CpuIndex, EFI_MM_SAVE_STATE_REGISTER_RAX, mSmmCpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData);
+    return EFI_SUCCESS;
+  }
+
+  //
+  // Convert Register to a register lookup table index
+  //
+  return MmSaveStateReadRegisterByIndex (CpuIndex, MmSaveStateGetRegisterIndex (Register, INTEL_MM_SAVE_STATE_REGISTER_MAX_INDEX), Width, Buffer);
+}
+
+/**
+  Writes an SMM Save State register on the target processor.  If this function
+  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
+  SMM Save Sate register.
+
+  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
+                       value must be between 0 and the NumberOfCpus field in
+                       the System Management System Table (SMST).
+  @param[in] Register  The SMM Save State register to write.
+  @param[in] Width     The number of bytes to write to the CPU save state.
+  @param[in] Buffer    Upon entry, this holds the new CPU register value.
+
+  @retval EFI_SUCCESS           The register was written to Save State.
+  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
+  @retval EFI_UNSUPPORTED       This function does not support writing Register.
+  @retval EFI_NOT_FOUND         If desired Register not found.
+**/
+EFI_STATUS
+EFIAPI
+MmSaveStateWriteRegister (
+  IN UINTN                       CpuIndex,
+  IN EFI_MM_SAVE_STATE_REGISTER  Register,
+  IN UINTN                       Width,
+  IN CONST VOID                  *Buffer
+  )
+{
+  UINTN                 RegisterIndex;
+  SMRAM_SAVE_STATE_MAP  *CpuSaveState;
+
+  //
+  // Writes to EFI_MM_SAVE_STATE_REGISTER_LMA are ignored
+  //
+  if (Register == EFI_MM_SAVE_STATE_REGISTER_LMA) {
+    return EFI_SUCCESS;
+  }
+
+  //
+  // Writes to EFI_MM_SAVE_STATE_REGISTER_IO are not supported
+  //
+  if (Register == EFI_MM_SAVE_STATE_REGISTER_IO) {
+    return EFI_NOT_FOUND;
+  }
+
+  //
+  // Convert Register to a register lookup table index
+  //
+  RegisterIndex = MmSaveStateGetRegisterIndex (Register, INTEL_MM_SAVE_STATE_REGISTER_MAX_INDEX);
+  if (RegisterIndex == 0) {
+    return EFI_NOT_FOUND;
+  }
+
+  CpuSaveState = gSmst->CpuSaveState[CpuIndex];
+
+  //
+  // Do not write non-writable SaveState, because it will cause exception.
+  //
+  if (!mCpuWidthOffset[RegisterIndex].Writeable) {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Check CPU mode
+  //
+  if (MmSaveStateGetRegisterLma ()  == EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT) {
+    //
+    // If 32-bit mode width is zero, then the specified register can not be accessed
+    //
+    if (mCpuWidthOffset[RegisterIndex].Width32 == 0) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
+    //
+    if (Width > mCpuWidthOffset[RegisterIndex].Width32) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    //
+    // Write SMM State register
+    //
+    ASSERT (CpuSaveState != NULL);
+    CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
+  } else {
+    //
+    // If 64-bit mode width is zero, then the specified register can not be accessed
+    //
+    if (mCpuWidthOffset[RegisterIndex].Width64 == 0) {
+      return EFI_NOT_FOUND;
+    }
+
+    //
+    // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
+    //
+    if (Width > mCpuWidthOffset[RegisterIndex].Width64) {
+      return EFI_INVALID_PARAMETER;
+    }
+
+    //
+    // Write at most 4 of the lower bytes of SMM State register
+    //
+    CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
+    if (Width > 4) {
+      //
+      // Write at most 4 of the upper bytes of SMM State register
+      //
+      CopyMem ((UINT8 *)CpuSaveState + mCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
+    }
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Returns LMA value of the Processor.
+
+  @retval     UINT8     returns LMA bit value.
+**/
+UINT8
+MmSaveStateGetRegisterLma (
+  VOID
+  )
+{
+  UINT32  RegEax;
+  UINT32  RegEdx;
+  UINTN   FamilyId;
+  UINTN   ModelId;
+  UINT8   SmmSaveStateRegisterLma;
+
+  //
+  // Retrieve CPU Family
+  //
+  AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
+  FamilyId = (RegEax >> 8) & 0xf;
+  ModelId  = (RegEax >> 4) & 0xf;
+  if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
+    ModelId = ModelId | ((RegEax >> 12) & 0xf0);
+  }
+
+  RegEdx = 0;
+  AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
+  if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
+    AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
+  }
+
+  //
+  // Determine the mode of the CPU at the time an SMI occurs
+  //   Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+  //   Volume 3C, Section 34.4.1.1
+  //
+  SmmSaveStateRegisterLma = EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT;
+  if ((RegEdx & BIT29) != 0) {
+    SmmSaveStateRegisterLma = EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT;
+  }
+
+  if (FamilyId == 0x06) {
+    if ((ModelId == 0x17) || (ModelId == 0x0f) || (ModelId == 0x1c)) {
+      SmmSaveStateRegisterLma = EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT;
+    }
+  }
+
+  return SmmSaveStateRegisterLma;
+}
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v14 7/8] UefiCpuPkg: Removes SmmCpuFeaturesReadSaveStateRegister
  2023-06-06  6:07 [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Abdul Lateef Attar
                   ` (5 preceding siblings ...)
  2023-06-06  6:07 ` [PATCH v14 6/8] UefiCpuPkg: Implements MmSaveStateLib for Intel Abdul Lateef Attar
@ 2023-06-06  6:07 ` Abdul Lateef Attar
  2023-06-06  6:07 ` [PATCH v14 8/8] OvmfPkg: Uses MmSaveStateLib library Abdul Lateef Attar
  2023-06-13  7:55 ` [edk2-devel] [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Ni, Ray
  8 siblings, 0 replies; 12+ messages in thread
From: Abdul Lateef Attar @ 2023-06-06  6:07 UTC (permalink / raw)
  To: devel
  Cc: Abdul Lateef Attar, Paul Grimes, Abner Chang, Eric Dong, Ray Ni,
	Rahul Kumar, Gerd Hoffmann, Ard Biesheuvel, Jiewen Yao,
	Jordan Justen

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

Removes SmmCpuFeaturesReadSaveStateRegister and
SmmCpuFeaturesWirteSaveStateRegister function from
SmmCpuFeaturesLib library.

MmSaveStateLib library replaces the functionality of the above
functions.
Platform old/new need to use MmSaveStateLib library to read/write save
state registers.
Current implementation supports Intel and AMD.

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Reviewed-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf  |   2 +
 .../Include/Library/SmmCpuFeaturesLib.h       |  52 --
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h    |  56 +-
 .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c  |  58 --
 .../IntelSmmCpuFeaturesLib.c                  |  58 --
 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c    |  11 +-
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c    | 500 +-----------------
 7 files changed, 9 insertions(+), 728 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
index 158e05e2646c..bd83b4afab26 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
@@ -6,6 +6,7 @@
 #
 # Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.<BR>
 # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -97,6 +98,7 @@ [LibraryClasses]
   ReportStatusCodeLib
   SmmCpuFeaturesLib
   PeCoffGetEntryPointLib
+  MmSaveStateLib
 
 [Protocols]
   gEfiSmmAccess2ProtocolGuid               ## CONSUMES
diff --git a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
index 52160c7145ba..733f0d03ebaa 100644
--- a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
@@ -324,58 +324,6 @@ SmmCpuFeaturesSetSmmRegister (
   IN UINT64        Value
   );
 
-/**
-  Read an SMM Save State register on the target processor.  If this function
-  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
-  SMM Save Sate register.
-
-  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
-                        value must be between 0 and the NumberOfCpus field in
-                        the System Management System Table (SMST).
-  @param[in]  Register  The SMM Save State register to read.
-  @param[in]  Width     The number of bytes to read from the CPU save state.
-  @param[out] Buffer    Upon return, this holds the CPU register value read
-                        from the save state.
-
-  @retval EFI_SUCCESS           The register was read from Save State.
-  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
-  @retval EFI_UNSUPPORTED       This function does not support reading Register.
-
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesReadSaveStateRegister (
-  IN  UINTN                        CpuIndex,
-  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN  UINTN                        Width,
-  OUT VOID                         *Buffer
-  );
-
-/**
-  Writes an SMM Save State register on the target processor.  If this function
-  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
-  SMM Save Sate register.
-
-  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
-                       value must be between 0 and the NumberOfCpus field in
-                       the System Management System Table (SMST).
-  @param[in] Register  The SMM Save State register to write.
-  @param[in] Width     The number of bytes to write to the CPU save state.
-  @param[in] Buffer    Upon entry, this holds the new CPU register value.
-
-  @retval EFI_SUCCESS           The register was written to Save State.
-  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
-  @retval EFI_UNSUPPORTED       This function does not support writing Register.
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesWriteSaveStateRegister (
-  IN UINTN                        CpuIndex,
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN UINTN                        Width,
-  IN CONST VOID                   *Buffer
-  );
-
 /**
   This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
   notification is completely processed.
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index a5c2bdd971ca..106808b08e17 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -3,6 +3,7 @@ Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
 
 Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.<BR>
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
 
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -50,6 +51,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/SmmCpuFeaturesLib.h>
 #include <Library/PeCoffGetEntryPointLib.h>
 #include <Library/RegisterCpuFeaturesLib.h>
+#include <Library/MmSaveStateLib.h>
 
 #include <AcpiCpuData.h>
 #include <CpuHotPlugData.h>
@@ -367,60 +369,6 @@ ExecuteFirstSmiInit (
   VOID
   );
 
-/**
-Read a CPU Save State register on the target processor.
-
-This function abstracts the differences that whether the CPU Save State register is in the
-IA32 CPU Save State Map or X64 CPU Save State Map.
-
-This function supports reading a CPU Save State register in SMBase relocation handler.
-
-@param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
-@param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
-@param[in]  Width          The number of bytes to read from the CPU save state.
-@param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
-
-@retval EFI_SUCCESS           The register was read from Save State.
-@retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
-@retval EFI_INVALID_PARAMETER Buffer is NULL, or Width does not meet requirement per Register type.
-
-**/
-EFI_STATUS
-EFIAPI
-ReadSaveStateRegister (
-  IN UINTN                        CpuIndex,
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN UINTN                        Width,
-  OUT VOID                        *Buffer
-  );
-
-/**
-Write value to a CPU Save State register on the target processor.
-
-This function abstracts the differences that whether the CPU Save State register is in the
-IA32 CPU Save State Map or X64 CPU Save State Map.
-
-This function supports writing a CPU Save State register in SMBase relocation handler.
-
-@param[in] CpuIndex       Specifies the zero-based index of the CPU save state.
-@param[in] RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
-@param[in] Width          The number of bytes to read from the CPU save state.
-@param[in] Buffer         Upon entry, this holds the new CPU register value.
-
-@retval EFI_SUCCESS           The register was written to Save State.
-@retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
-@retval EFI_INVALID_PARAMETER  ProcessorIndex or Width is not correct.
-
-**/
-EFI_STATUS
-EFIAPI
-WriteSaveStateRegister (
-  IN UINTN                        CpuIndex,
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN UINTN                        Width,
-  IN CONST VOID                   *Buffer
-  );
-
 extern BOOLEAN            mSmmRelocated;
 extern volatile  BOOLEAN  *mSmmInitialized;
 extern UINT32             mBspApicId;
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c
index 1473f0a51fe2..e6d1b5010356 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c
@@ -27,64 +27,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 // The mode of the CPU at the time an SMI occurs
 STATIC UINT8  mSmmSaveStateRegisterLma;
 
-/**
-  Read an SMM Save State register on the target processor.  If this function
-  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
-  SMM Save Sate register.
-
-  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
-                        value must be between 0 and the NumberOfCpus field in
-                        the System Management System Table (SMST).
-  @param[in]  Register  The SMM Save State register to read.
-  @param[in]  Width     The number of bytes to read from the CPU save state.
-  @param[out] Buffer    Upon return, this holds the CPU register value read
-                        from the save state.
-
-  @retval EFI_SUCCESS           The register was read from Save State.
-  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
-  @retval EFI_UNSUPPORTED       This function does not support reading Register.
-
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesReadSaveStateRegister (
-  IN  UINTN                        CpuIndex,
-  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN  UINTN                        Width,
-  OUT VOID                         *Buffer
-  )
-{
-  return MmSaveStateReadRegister (CpuIndex, Register, Width, Buffer);
-}
-
-/**
-  Writes an SMM Save State register on the target processor.  If this function
-  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
-  SMM Save Sate register.
-
-  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
-                       value must be between 0 and the NumberOfCpus field in
-                       the System Management System Table (SMST).
-  @param[in] Register  The SMM Save State register to write.
-  @param[in] Width     The number of bytes to write to the CPU save state.
-  @param[in] Buffer    Upon entry, this holds the new CPU register value.
-
-  @retval EFI_SUCCESS           The register was written to Save State.
-  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
-  @retval EFI_UNSUPPORTED       This function does not support writing Register.
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesWriteSaveStateRegister (
-  IN UINTN                        CpuIndex,
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN UINTN                        Width,
-  IN CONST VOID                   *Buffer
-  )
-{
-  return MmSaveStateWriteRegister (CpuIndex, Register, Width, Buffer);
-}
-
 /**
   Performs library initialization.
 
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
index 8f382b60266c..950056a7143d 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c
@@ -461,64 +461,6 @@ SmmCpuFeaturesHookReturnFromSmm (
   return 0;
 }
 
-/**
-  Read an SMM Save State register on the target processor.  If this function
-  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
-  SMM Save Sate register.
-
-  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
-                        value must be between 0 and the NumberOfCpus field in
-                        the System Management System Table (SMST).
-  @param[in]  Register  The SMM Save State register to read.
-  @param[in]  Width     The number of bytes to read from the CPU save state.
-  @param[out] Buffer    Upon return, this holds the CPU register value read
-                        from the save state.
-
-  @retval EFI_SUCCESS           The register was read from Save State.
-  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
-  @retval EFI_UNSUPPORTED       This function does not support reading Register.
-
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesReadSaveStateRegister (
-  IN  UINTN                        CpuIndex,
-  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN  UINTN                        Width,
-  OUT VOID                         *Buffer
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
-/**
-  Writes an SMM Save State register on the target processor.  If this function
-  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
-  SMM Save Sate register.
-
-  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
-                       value must be between 0 and the NumberOfCpus field in
-                       the System Management System Table (SMST).
-  @param[in] Register  The SMM Save State register to write.
-  @param[in] Width     The number of bytes to write to the CPU save state.
-  @param[in] Buffer    Upon entry, this holds the new CPU register value.
-
-  @retval EFI_SUCCESS           The register was written to Save State.
-  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
-  @retval EFI_UNSUPPORTED       This function does not support writing Register.
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesWriteSaveStateRegister (
-  IN UINTN                        CpuIndex,
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN UINTN                        Width,
-  IN CONST VOID                   *Buffer
-  )
-{
-  return EFI_UNSUPPORTED;
-}
-
 /**
   Check to see if an SMM register is supported by a specified CPU.
 
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 2144d6ade853..739164a60089 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -3,6 +3,7 @@ Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
 
 Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.<BR>
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
 
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -276,10 +277,7 @@ SmmReadSaveState (
     return EFI_INVALID_PARAMETER;
   }
 
-  Status = SmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
-  if (Status == EFI_UNSUPPORTED) {
-    Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
-  }
+  Status = MmSaveStateReadRegister (CpuIndex, Register, Width, Buffer);
 
   return Status;
 }
@@ -328,10 +326,7 @@ SmmWriteSaveState (
     return EFI_INVALID_PARAMETER;
   }
 
-  Status = SmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
-  if (Status == EFI_UNSUPPORTED) {
-    Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
-  }
+  Status = MmSaveStateWriteRegister (CpuIndex, Register, Width, Buffer);
 
   return Status;
 }
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
index c8ddc6083df6..1e316ee0acdb 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -2,6 +2,8 @@
 Provides services to access SMRAM Save State Map
 
 Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+
 SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -48,52 +50,6 @@ extern CONST PROCESSOR_SMM_DESCRIPTOR  gcPsd;
 //
 #define LMA  BIT10
 
-///
-/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
-///
-#define SMM_CPU_OFFSET(Field)  OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
-
-///
-/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE
-///
-#define SMM_REGISTER_RANGE(Start, End)  { Start, End, End - Start + 1 }
-
-///
-/// Structure used to describe a range of registers
-///
-typedef struct {
-  EFI_SMM_SAVE_STATE_REGISTER    Start;
-  EFI_SMM_SAVE_STATE_REGISTER    End;
-  UINTN                          Length;
-} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
-
-///
-/// Structure used to build a lookup table to retrieve the widths and offsets
-/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
-///
-
-#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX   1
-#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX     2
-#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX  3
-#define SMM_SAVE_STATE_REGISTER_MAX_INDEX        4
-
-typedef struct {
-  UINT8      Width32;
-  UINT8      Width64;
-  UINT16     Offset32;
-  UINT16     Offset64Lo;
-  UINT16     Offset64Hi;
-  BOOLEAN    Writeable;
-} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
-
-///
-/// Structure used to build a lookup table for the IOMisc width information
-///
-typedef struct {
-  UINT8                          Width;
-  EFI_SMM_SAVE_STATE_IO_WIDTH    IoWidth;
-} CPU_SMM_SAVE_STATE_IO_WIDTH;
-
 ///
 /// Variables from SMI Handler
 ///
@@ -108,463 +64,11 @@ extern CONST UINT16       gcSmiHandlerSize;
 //
 IA32_DESCRIPTOR  gSmiHandlerIdtr;
 
-///
-/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
-/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
-///
-CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE  mSmmCpuRegisterRanges[] = {
-  SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),
-  SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES,      EFI_SMM_SAVE_STATE_REGISTER_RIP),
-  SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,  EFI_SMM_SAVE_STATE_REGISTER_CR4),
-  { (EFI_SMM_SAVE_STATE_REGISTER)0,                        (EFI_SMM_SAVE_STATE_REGISTER)0,      0}
-};
-
-///
-/// Lookup table used to retrieve the widths and offsets associated with each
-/// supported EFI_SMM_SAVE_STATE_REGISTER value
-///
-CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY  mSmmCpuWidthOffset[] = {
-  { 0, 0, 0,                              0,                                   0,                                   FALSE },  //  Reserved
-
-  //
-  // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.
-  //
-  { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId),  SMM_CPU_OFFSET (x64.SMMRevId),       0,                                   FALSE }, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX  = 1
-  { 4, 4, SMM_CPU_OFFSET (x86.IOMisc),    SMM_CPU_OFFSET (x64.IOMisc),         0,                                   FALSE }, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX    = 2
-  { 4, 8, SMM_CPU_OFFSET (x86.IOMemAddr), SMM_CPU_OFFSET (x64.IOMemAddr),      SMM_CPU_OFFSET (x64.IOMemAddr) + 4,  FALSE }, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3
-
-  //
-  // CPU Save State registers defined in PI SMM CPU Protocol.
-  //
-  { 0, 8, 0,                              SMM_CPU_OFFSET (x64.GdtBaseLoDword), SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_GDTBASE  = 4
-  { 0, 8, 0,                              SMM_CPU_OFFSET (x64.IdtBaseLoDword), SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_IDTBASE  = 5
-  { 0, 8, 0,                              SMM_CPU_OFFSET (x64.LdtBaseLoDword), SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_LDTBASE  = 6
-  { 0, 0, 0,                              0,                                   0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
-  { 0, 0, 0,                              0,                                   0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
-  { 0, 0, 0,                              0,                                   0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
-  { 0, 0, 0,                              0,                                   0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_LDTINFO  = 10
-
-  { 4, 4, SMM_CPU_OFFSET (x86._ES),       SMM_CPU_OFFSET (x64._ES),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_ES       = 20
-  { 4, 4, SMM_CPU_OFFSET (x86._CS),       SMM_CPU_OFFSET (x64._CS),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_CS       = 21
-  { 4, 4, SMM_CPU_OFFSET (x86._SS),       SMM_CPU_OFFSET (x64._SS),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_SS       = 22
-  { 4, 4, SMM_CPU_OFFSET (x86._DS),       SMM_CPU_OFFSET (x64._DS),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_DS       = 23
-  { 4, 4, SMM_CPU_OFFSET (x86._FS),       SMM_CPU_OFFSET (x64._FS),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_FS       = 24
-  { 4, 4, SMM_CPU_OFFSET (x86._GS),       SMM_CPU_OFFSET (x64._GS),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_GS       = 25
-  { 0, 4, 0,                              SMM_CPU_OFFSET (x64._LDTR),          0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
-  { 4, 4, SMM_CPU_OFFSET (x86._TR),       SMM_CPU_OFFSET (x64._TR),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_TR_SEL   = 27
-  { 4, 8, SMM_CPU_OFFSET (x86._DR7),      SMM_CPU_OFFSET (x64._DR7),           SMM_CPU_OFFSET (x64._DR7)    + 4,    FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_DR7      = 28
-  { 4, 8, SMM_CPU_OFFSET (x86._DR6),      SMM_CPU_OFFSET (x64._DR6),           SMM_CPU_OFFSET (x64._DR6)    + 4,    FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_DR6      = 29
-  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R8),            SMM_CPU_OFFSET (x64._R8)     + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R8       = 30
-  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R9),            SMM_CPU_OFFSET (x64._R9)     + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R9       = 31
-  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R10),           SMM_CPU_OFFSET (x64._R10)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R10      = 32
-  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R11),           SMM_CPU_OFFSET (x64._R11)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R11      = 33
-  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R12),           SMM_CPU_OFFSET (x64._R12)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R12      = 34
-  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R13),           SMM_CPU_OFFSET (x64._R13)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R13      = 35
-  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R14),           SMM_CPU_OFFSET (x64._R14)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R14      = 36
-  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R15),           SMM_CPU_OFFSET (x64._R15)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R15      = 37
-  { 4, 8, SMM_CPU_OFFSET (x86._EAX),      SMM_CPU_OFFSET (x64._RAX),           SMM_CPU_OFFSET (x64._RAX)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RAX      = 38
-  { 4, 8, SMM_CPU_OFFSET (x86._EBX),      SMM_CPU_OFFSET (x64._RBX),           SMM_CPU_OFFSET (x64._RBX)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RBX      = 39
-  { 4, 8, SMM_CPU_OFFSET (x86._ECX),      SMM_CPU_OFFSET (x64._RCX),           SMM_CPU_OFFSET (x64._RCX)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RCX      = 40
-  { 4, 8, SMM_CPU_OFFSET (x86._EDX),      SMM_CPU_OFFSET (x64._RDX),           SMM_CPU_OFFSET (x64._RDX)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RDX      = 41
-  { 4, 8, SMM_CPU_OFFSET (x86._ESP),      SMM_CPU_OFFSET (x64._RSP),           SMM_CPU_OFFSET (x64._RSP)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RSP      = 42
-  { 4, 8, SMM_CPU_OFFSET (x86._EBP),      SMM_CPU_OFFSET (x64._RBP),           SMM_CPU_OFFSET (x64._RBP)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RBP      = 43
-  { 4, 8, SMM_CPU_OFFSET (x86._ESI),      SMM_CPU_OFFSET (x64._RSI),           SMM_CPU_OFFSET (x64._RSI)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RSI      = 44
-  { 4, 8, SMM_CPU_OFFSET (x86._EDI),      SMM_CPU_OFFSET (x64._RDI),           SMM_CPU_OFFSET (x64._RDI)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RDI      = 45
-  { 4, 8, SMM_CPU_OFFSET (x86._EIP),      SMM_CPU_OFFSET (x64._RIP),           SMM_CPU_OFFSET (x64._RIP)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RIP      = 46
-
-  { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS),   SMM_CPU_OFFSET (x64._RFLAGS),        SMM_CPU_OFFSET (x64._RFLAGS) + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RFLAGS   = 51
-  { 4, 8, SMM_CPU_OFFSET (x86._CR0),      SMM_CPU_OFFSET (x64._CR0),           SMM_CPU_OFFSET (x64._CR0)    + 4,    FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_CR0      = 52
-  { 4, 8, SMM_CPU_OFFSET (x86._CR3),      SMM_CPU_OFFSET (x64._CR3),           SMM_CPU_OFFSET (x64._CR3)    + 4,    FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_CR3      = 53
-  { 0, 4, 0,                              SMM_CPU_OFFSET (x64._CR4),           0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_CR4      = 54
-};
-
-///
-/// Lookup table for the IOMisc width information
-///
-CONST CPU_SMM_SAVE_STATE_IO_WIDTH  mSmmCpuIoWidth[] = {
-  { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8  },  // Undefined           = 0
-  { 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8  },  // SMM_IO_LENGTH_BYTE  = 1
-  { 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 },  // SMM_IO_LENGTH_WORD  = 2
-  { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8  },  // Undefined           = 3
-  { 4, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 },  // SMM_IO_LENGTH_DWORD = 4
-  { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8  },  // Undefined           = 5
-  { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8  },  // Undefined           = 6
-  { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8  }   // Undefined           = 7
-};
-
-///
-/// Lookup table for the IOMisc type information
-///
-CONST EFI_SMM_SAVE_STATE_IO_TYPE  mSmmCpuIoType[] = {
-  EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT,     // SMM_IO_TYPE_OUT_DX        = 0
-  EFI_SMM_SAVE_STATE_IO_TYPE_INPUT,      // SMM_IO_TYPE_IN_DX         = 1
-  EFI_SMM_SAVE_STATE_IO_TYPE_STRING,     // SMM_IO_TYPE_OUTS          = 2
-  EFI_SMM_SAVE_STATE_IO_TYPE_STRING,     // SMM_IO_TYPE_INS           = 3
-  (EFI_SMM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 4
-  (EFI_SMM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 5
-  EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_OUTS      = 6
-  EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_INS       = 7
-  EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT,     // SMM_IO_TYPE_OUT_IMMEDIATE = 8
-  EFI_SMM_SAVE_STATE_IO_TYPE_INPUT,      // SMM_IO_TYPE_OUT_IMMEDIATE = 9
-  (EFI_SMM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 10
-  (EFI_SMM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 11
-  (EFI_SMM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 12
-  (EFI_SMM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 13
-  (EFI_SMM_SAVE_STATE_IO_TYPE)0,         // Undefined                 = 14
-  (EFI_SMM_SAVE_STATE_IO_TYPE)0          // Undefined                 = 15
-};
-
 ///
 /// The mode of the CPU at the time an SMI occurs
 ///
 UINT8  mSmmSaveStateRegisterLma;
 
-/**
-  Read information from the CPU save state.
-
-  @param  Register  Specifies the CPU register to read form the save state.
-
-  @retval 0   Register is not valid
-  @retval >0  Index into mSmmCpuWidthOffset[] associated with Register
-
-**/
-UINTN
-GetRegisterIndex (
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register
-  )
-{
-  UINTN  Index;
-  UINTN  Offset;
-
-  for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {
-    if ((Register >= mSmmCpuRegisterRanges[Index].Start) && (Register <= mSmmCpuRegisterRanges[Index].End)) {
-      return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
-    }
-
-    Offset += mSmmCpuRegisterRanges[Index].Length;
-  }
-
-  return 0;
-}
-
-/**
-  Read a CPU Save State register on the target processor.
-
-  This function abstracts the differences that whether the CPU Save State register is in the
-  IA32 CPU Save State Map or X64 CPU Save State Map.
-
-  This function supports reading a CPU Save State register in SMBase relocation handler.
-
-  @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
-  @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
-  @param[in]  Width          The number of bytes to read from the CPU save state.
-  @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
-
-  @retval EFI_SUCCESS           The register was read from Save State.
-  @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
-  @retval EFI_INVALID_PARAMETER  This or Buffer is NULL.
-
-**/
-EFI_STATUS
-ReadSaveStateRegisterByIndex (
-  IN UINTN  CpuIndex,
-  IN UINTN  RegisterIndex,
-  IN UINTN  Width,
-  OUT VOID  *Buffer
-  )
-{
-  SMRAM_SAVE_STATE_MAP  *CpuSaveState;
-
-  if (RegisterIndex == 0) {
-    return EFI_NOT_FOUND;
-  }
-
-  CpuSaveState = gSmst->CpuSaveState[CpuIndex];
-
-  if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
-    //
-    // If 32-bit mode width is zero, then the specified register can not be accessed
-    //
-    if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
-      return EFI_NOT_FOUND;
-    }
-
-    //
-    // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
-    //
-    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    //
-    // Write return buffer
-    //
-    ASSERT (CpuSaveState != NULL);
-    CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
-  } else {
-    //
-    // If 64-bit mode width is zero, then the specified register can not be accessed
-    //
-    if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
-      return EFI_NOT_FOUND;
-    }
-
-    //
-    // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
-    //
-    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    //
-    // Write at most 4 of the lower bytes of the return buffer
-    //
-    CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width));
-    if (Width > 4) {
-      //
-      // Write at most 4 of the upper bytes of the return buffer
-      //
-      CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
-    }
-  }
-
-  return EFI_SUCCESS;
-}
-
-/**
-  Read a CPU Save State register on the target processor.
-
-  This function abstracts the differences that whether the CPU Save State register is in the
-  IA32 CPU Save State Map or X64 CPU Save State Map.
-
-  This function supports reading a CPU Save State register in SMBase relocation handler.
-
-  @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
-  @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
-  @param[in]  Width          The number of bytes to read from the CPU save state.
-  @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
-
-  @retval EFI_SUCCESS           The register was read from Save State.
-  @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
-  @retval EFI_INVALID_PARAMETER Buffer is NULL, or Width does not meet requirement per Register type.
-
-**/
-EFI_STATUS
-EFIAPI
-ReadSaveStateRegister (
-  IN UINTN                        CpuIndex,
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN UINTN                        Width,
-  OUT VOID                        *Buffer
-  )
-{
-  UINT32                      SmmRevId;
-  SMRAM_SAVE_STATE_IOMISC     IoMisc;
-  EFI_SMM_SAVE_STATE_IO_INFO  *IoInfo;
-
-  //
-  // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
-  //
-  if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
-    //
-    // Only byte access is supported for this register
-    //
-    if (Width != 1) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    *(UINT8 *)Buffer = mSmmSaveStateRegisterLma;
-
-    return EFI_SUCCESS;
-  }
-
-  //
-  // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
-  //
-  if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
-    //
-    // Get SMM Revision ID
-    //
-    ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);
-
-    //
-    // See if the CPU supports the IOMisc register in the save state
-    //
-    if (SmmRevId < SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC) {
-      return EFI_NOT_FOUND;
-    }
-
-    //
-    // Get the IOMisc register value
-    //
-    ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof (IoMisc.Uint32), &IoMisc.Uint32);
-
-    //
-    // Check for the SMI_FLAG in IOMisc
-    //
-    if (IoMisc.Bits.SmiFlag == 0) {
-      return EFI_NOT_FOUND;
-    }
-
-    //
-    // Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS.
-    //
-    if ((mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) &&
-        (mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT))
-    {
-      return EFI_NOT_FOUND;
-    }
-
-    //
-    // Compute index for the I/O Length and I/O Type lookup tables
-    //
-    if ((mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0) || (mSmmCpuIoType[IoMisc.Bits.Type] == 0)) {
-      return EFI_NOT_FOUND;
-    }
-
-    //
-    // Make sure the incoming buffer is large enough to hold IoInfo before accessing
-    //
-    if (Width < sizeof (EFI_SMM_SAVE_STATE_IO_INFO)) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    //
-    // Zero the IoInfo structure that will be returned in Buffer
-    //
-    IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer;
-    ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO));
-
-    //
-    // Use lookup tables to help fill in all the fields of the IoInfo structure
-    //
-    IoInfo->IoPort  = (UINT16)IoMisc.Bits.Port;
-    IoInfo->IoWidth = mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth;
-    IoInfo->IoType  = mSmmCpuIoType[IoMisc.Bits.Type];
-    ReadSaveStateRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX, mSmmCpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData);
-    return EFI_SUCCESS;
-  }
-
-  //
-  // Convert Register to a register lookup table index
-  //
-  return ReadSaveStateRegisterByIndex (CpuIndex, GetRegisterIndex (Register), Width, Buffer);
-}
-
-/**
-  Write value to a CPU Save State register on the target processor.
-
-  This function abstracts the differences that whether the CPU Save State register is in the
-  IA32 CPU Save State Map or X64 CPU Save State Map.
-
-  This function supports writing a CPU Save State register in SMBase relocation handler.
-
-  @param[in] CpuIndex       Specifies the zero-based index of the CPU save state.
-  @param[in] RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
-  @param[in] Width          The number of bytes to read from the CPU save state.
-  @param[in] Buffer         Upon entry, this holds the new CPU register value.
-
-  @retval EFI_SUCCESS           The register was written to Save State.
-  @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
-  @retval EFI_INVALID_PARAMETER  ProcessorIndex or Width is not correct.
-
-**/
-EFI_STATUS
-EFIAPI
-WriteSaveStateRegister (
-  IN UINTN                        CpuIndex,
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN UINTN                        Width,
-  IN CONST VOID                   *Buffer
-  )
-{
-  UINTN                 RegisterIndex;
-  SMRAM_SAVE_STATE_MAP  *CpuSaveState;
-
-  //
-  // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
-  //
-  if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
-    return EFI_SUCCESS;
-  }
-
-  //
-  // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
-  //
-  if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
-    return EFI_NOT_FOUND;
-  }
-
-  //
-  // Convert Register to a register lookup table index
-  //
-  RegisterIndex = GetRegisterIndex (Register);
-  if (RegisterIndex == 0) {
-    return EFI_NOT_FOUND;
-  }
-
-  CpuSaveState = gSmst->CpuSaveState[CpuIndex];
-
-  //
-  // Do not write non-writable SaveState, because it will cause exception.
-  //
-  if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
-    return EFI_UNSUPPORTED;
-  }
-
-  //
-  // Check CPU mode
-  //
-  if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
-    //
-    // If 32-bit mode width is zero, then the specified register can not be accessed
-    //
-    if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
-      return EFI_NOT_FOUND;
-    }
-
-    //
-    // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
-    //
-    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    //
-    // Write SMM State register
-    //
-    ASSERT (CpuSaveState != NULL);
-    CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
-  } else {
-    //
-    // If 64-bit mode width is zero, then the specified register can not be accessed
-    //
-    if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
-      return EFI_NOT_FOUND;
-    }
-
-    //
-    // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
-    //
-    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    //
-    // Write at most 4 of the lower bytes of SMM State register
-    //
-    CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
-    if (Width > 4) {
-      //
-      // Write at most 4 of the upper bytes of SMM State register
-      //
-      CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
-    }
-  }
-
-  return EFI_SUCCESS;
-}
-
 /**
   Hook the code executed immediately after an RSM instruction on the currently
   executing CPU.  The mode of code executed immediately after RSM must be
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH v14 8/8] OvmfPkg: Uses MmSaveStateLib library
  2023-06-06  6:07 [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Abdul Lateef Attar
                   ` (6 preceding siblings ...)
  2023-06-06  6:07 ` [PATCH v14 7/8] UefiCpuPkg: Removes SmmCpuFeaturesReadSaveStateRegister Abdul Lateef Attar
@ 2023-06-06  6:07 ` Abdul Lateef Attar
  2023-06-13  7:55 ` [edk2-devel] [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Ni, Ray
  8 siblings, 0 replies; 12+ messages in thread
From: Abdul Lateef Attar @ 2023-06-06  6:07 UTC (permalink / raw)
  To: devel
  Cc: Abdul Lateef Attar, Paul Grimes, Abner Chang, Eric Dong, Ray Ni,
	Rahul Kumar, Gerd Hoffmann, Ard Biesheuvel, Jiewen Yao,
	Jordan Justen, Abdul Lateef Attar, Jiewen Yao

From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182

Uses new MmSaveStateLib library instance.

Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
---
 OvmfPkg/OvmfPkgIa32.dsc                       |   1 +
 OvmfPkg/OvmfPkgIa32X64.dsc                    |   3 +
 OvmfPkg/OvmfPkgX64.dsc                        |   1 +
 .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.c     | 767 ------------------
 4 files changed, 5 insertions(+), 767 deletions(-)

diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 08b04e65cab7..9185622ae924 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -973,6 +973,7 @@ [Components]
     <LibraryClasses>
       SmmCpuPlatformHookLib|OvmfPkg/Library/SmmCpuPlatformHookLibQemu/SmmCpuPlatformHookLibQemu.inf
       SmmCpuFeaturesLib|OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
+      MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
   }
 
   #
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index d456896a45fb..bad68e997dcc 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -4,6 +4,7 @@
 #  Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.<BR>
 #  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
 #  Copyright (c) Microsoft Corporation.
+#  Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
 #
 #  SPDX-License-Identifier: BSD-2-Clause-Patent
 #
@@ -444,6 +445,7 @@ [LibraryClasses.common.DXE_SMM_DRIVER]
   BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
   PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
   SmmCpuRendezvousLib|UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf
+  MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
 
 [LibraryClasses.common.SMM_CORE]
   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -993,6 +995,7 @@ [Components.X64]
     <LibraryClasses>
       SmmCpuPlatformHookLib|OvmfPkg/Library/SmmCpuPlatformHookLibQemu/SmmCpuPlatformHookLibQemu.inf
       SmmCpuFeaturesLib|OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
+      MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
   }
 
   #
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index e1c0a6fe9ff7..b6de4846cbc8 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -1065,6 +1065,7 @@ [Components]
     <LibraryClasses>
       SmmCpuPlatformHookLib|OvmfPkg/Library/SmmCpuPlatformHookLibQemu/SmmCpuPlatformHookLibQemu.inf
       SmmCpuFeaturesLib|OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
+      MmSaveStateLib|UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
   }
 
   #
diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
index a009123dae88..4c354bafe42f 100644
--- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
+++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
@@ -578,773 +578,6 @@ SmmCpuFeaturesSetSmmRegister (
   ASSERT (FALSE);
 }
 
-///
-/// Macro used to simplify the lookup table entries of type
-/// CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
-///
-#define SMM_CPU_OFFSET(Field)  OFFSET_OF (QEMU_SMRAM_SAVE_STATE_MAP, Field)
-
-///
-/// Macro used to simplify the lookup table entries of type
-/// CPU_SMM_SAVE_STATE_REGISTER_RANGE
-///
-#define SMM_REGISTER_RANGE(Start, End)  { Start, End, End - Start + 1 }
-
-///
-/// Structure used to describe a range of registers
-///
-typedef struct {
-  EFI_SMM_SAVE_STATE_REGISTER    Start;
-  EFI_SMM_SAVE_STATE_REGISTER    End;
-  UINTN                          Length;
-} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
-
-///
-/// Structure used to build a lookup table to retrieve the widths and offsets
-/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
-///
-
-#define SMM_SAVE_STATE_REGISTER_FIRST_INDEX  1
-
-typedef struct {
-  UINT8      Width32;
-  UINT8      Width64;
-  UINT16     Offset32;
-  UINT16     Offset64Lo;
-  UINT16     Offset64Hi;
-  BOOLEAN    Writeable;
-} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
-
-///
-/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
-/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
-///
-STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE  mSmmCpuRegisterRanges[] = {
-  SMM_REGISTER_RANGE (
-    EFI_SMM_SAVE_STATE_REGISTER_GDTBASE,
-    EFI_SMM_SAVE_STATE_REGISTER_LDTINFO
-    ),
-  SMM_REGISTER_RANGE (
-    EFI_SMM_SAVE_STATE_REGISTER_ES,
-    EFI_SMM_SAVE_STATE_REGISTER_RIP
-    ),
-  SMM_REGISTER_RANGE (
-    EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,
-    EFI_SMM_SAVE_STATE_REGISTER_CR4
-    ),
-  { (EFI_SMM_SAVE_STATE_REGISTER)0,     (EFI_SMM_SAVE_STATE_REGISTER)0,0 }
-};
-
-///
-/// Lookup table used to retrieve the widths and offsets associated with each
-/// supported EFI_SMM_SAVE_STATE_REGISTER value
-///
-STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY  mSmmCpuWidthOffset[] = {
-  {
-    0,                                    // Width32
-    0,                                    // Width64
-    0,                                    // Offset32
-    0,                                    // Offset64Lo
-    0,                                    // Offset64Hi
-    FALSE                                 // Writeable
-  }, // Reserved
-
-  //
-  // CPU Save State registers defined in PI SMM CPU Protocol.
-  //
-  {
-    0,                                    // Width32
-    8,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._GDTRBase),       // Offset64Lo
-    SMM_CPU_OFFSET (x64._GDTRBase) + 4,   // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
-
-  {
-    0,                                    // Width32
-    8,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._IDTRBase),       // Offset64Lo
-    SMM_CPU_OFFSET (x64._IDTRBase) + 4,   // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
-
-  {
-    0,                                    // Width32
-    8,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._LDTRBase),       // Offset64Lo
-    SMM_CPU_OFFSET (x64._LDTRBase) + 4,   // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
-
-  {
-    0,                                    // Width32
-    0,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._GDTRLimit),      // Offset64Lo
-    SMM_CPU_OFFSET (x64._GDTRLimit) + 4,  // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
-
-  {
-    0,                                    // Width32
-    0,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._IDTRLimit),      // Offset64Lo
-    SMM_CPU_OFFSET (x64._IDTRLimit) + 4,  // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
-
-  {
-    0,                                    // Width32
-    0,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._LDTRLimit),      // Offset64Lo
-    SMM_CPU_OFFSET (x64._LDTRLimit) + 4,  // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
-
-  {
-    0,                                    // Width32
-    0,                                    // Width64
-    0,                                    // Offset32
-    0,                                    // Offset64Lo
-    0 + 4,                                // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
-
-  {
-    4,                                    // Width32
-    4,                                    // Width64
-    SMM_CPU_OFFSET (x86._ES),             // Offset32
-    SMM_CPU_OFFSET (x64._ES),             // Offset64Lo
-    0,                                    // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
-
-  {
-    4,                                    // Width32
-    4,                                    // Width64
-    SMM_CPU_OFFSET (x86._CS),             // Offset32
-    SMM_CPU_OFFSET (x64._CS),             // Offset64Lo
-    0,                                    // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
-
-  {
-    4,                                    // Width32
-    4,                                    // Width64
-    SMM_CPU_OFFSET (x86._SS),             // Offset32
-    SMM_CPU_OFFSET (x64._SS),             // Offset64Lo
-    0,                                    // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
-
-  {
-    4,                                    // Width32
-    4,                                    // Width64
-    SMM_CPU_OFFSET (x86._DS),             // Offset32
-    SMM_CPU_OFFSET (x64._DS),             // Offset64Lo
-    0,                                    // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
-
-  {
-    4,                                    // Width32
-    4,                                    // Width64
-    SMM_CPU_OFFSET (x86._FS),             // Offset32
-    SMM_CPU_OFFSET (x64._FS),             // Offset64Lo
-    0,                                    // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
-
-  {
-    4,                                    // Width32
-    4,                                    // Width64
-    SMM_CPU_OFFSET (x86._GS),             // Offset32
-    SMM_CPU_OFFSET (x64._GS),             // Offset64Lo
-    0,                                    // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
-
-  {
-    0,                                    // Width32
-    4,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._LDTR),           // Offset64Lo
-    0,                                    // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
-
-  {
-    4,                                    // Width32
-    4,                                    // Width64
-    SMM_CPU_OFFSET (x86._TR),             // Offset32
-    SMM_CPU_OFFSET (x64._TR),             // Offset64Lo
-    0,                                    // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._DR7),            // Offset32
-    SMM_CPU_OFFSET (x64._DR7),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._DR7) + 4,        // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._DR6),            // Offset32
-    SMM_CPU_OFFSET (x64._DR6),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._DR6) + 4,        // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
-
-  {
-    0,                                    // Width32
-    8,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._R8),             // Offset64Lo
-    SMM_CPU_OFFSET (x64._R8) + 4,         // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
-
-  {
-    0,                                    // Width32
-    8,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._R9),             // Offset64Lo
-    SMM_CPU_OFFSET (x64._R9) + 4,         // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
-
-  {
-    0,                                    // Width32
-    8,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._R10),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._R10) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
-
-  {
-    0,                                    // Width32
-    8,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._R11),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._R11) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
-
-  {
-    0,                                    // Width32
-    8,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._R12),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._R12) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
-
-  {
-    0,                                    // Width32
-    8,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._R13),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._R13) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
-
-  {
-    0,                                    // Width32
-    8,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._R14),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._R14) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
-
-  {
-    0,                                    // Width32
-    8,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._R15),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._R15) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._EAX),            // Offset32
-    SMM_CPU_OFFSET (x64._RAX),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._RAX) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._EBX),            // Offset32
-    SMM_CPU_OFFSET (x64._RBX),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._RBX) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._ECX),            // Offset32
-    SMM_CPU_OFFSET (x64._RCX),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._RCX) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._EDX),            // Offset32
-    SMM_CPU_OFFSET (x64._RDX),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._RDX) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._ESP),            // Offset32
-    SMM_CPU_OFFSET (x64._RSP),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._RSP) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._EBP),            // Offset32
-    SMM_CPU_OFFSET (x64._RBP),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._RBP) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._ESI),            // Offset32
-    SMM_CPU_OFFSET (x64._RSI),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._RSI) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._EDI),            // Offset32
-    SMM_CPU_OFFSET (x64._RDI),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._RDI) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._EIP),            // Offset32
-    SMM_CPU_OFFSET (x64._RIP),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._RIP) + 4,        // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._EFLAGS),         // Offset32
-    SMM_CPU_OFFSET (x64._RFLAGS),         // Offset64Lo
-    SMM_CPU_OFFSET (x64._RFLAGS) + 4,     // Offset64Hi
-    TRUE                                  // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._CR0),            // Offset32
-    SMM_CPU_OFFSET (x64._CR0),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._CR0) + 4,        // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
-
-  {
-    4,                                    // Width32
-    8,                                    // Width64
-    SMM_CPU_OFFSET (x86._CR3),            // Offset32
-    SMM_CPU_OFFSET (x64._CR3),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._CR3) + 4,        // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
-
-  {
-    0,                                    // Width32
-    4,                                    // Width64
-    0,                                    // Offset32
-    SMM_CPU_OFFSET (x64._CR4),            // Offset64Lo
-    SMM_CPU_OFFSET (x64._CR4) + 4,        // Offset64Hi
-    FALSE                                 // Writeable
-  }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
-};
-
-//
-// No support for I/O restart
-//
-
-/**
-  Read information from the CPU save state.
-
-  @param  Register  Specifies the CPU register to read form the save state.
-
-  @retval 0   Register is not valid
-  @retval >0  Index into mSmmCpuWidthOffset[] associated with Register
-
-**/
-STATIC
-UINTN
-GetRegisterIndex (
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register
-  )
-{
-  UINTN  Index;
-  UINTN  Offset;
-
-  for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_FIRST_INDEX;
-       mSmmCpuRegisterRanges[Index].Length != 0;
-       Index++)
-  {
-    if ((Register >= mSmmCpuRegisterRanges[Index].Start) &&
-        (Register <= mSmmCpuRegisterRanges[Index].End))
-    {
-      return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
-    }
-
-    Offset += mSmmCpuRegisterRanges[Index].Length;
-  }
-
-  return 0;
-}
-
-/**
-  Read a CPU Save State register on the target processor.
-
-  This function abstracts the differences that whether the CPU Save State
-  register is in the IA32 CPU Save State Map or X64 CPU Save State Map.
-
-  This function supports reading a CPU Save State register in SMBase relocation
-  handler.
-
-  @param[in]  CpuIndex       Specifies the zero-based index of the CPU save
-                             state.
-  @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
-  @param[in]  Width          The number of bytes to read from the CPU save
-                             state.
-  @param[out] Buffer         Upon return, this holds the CPU register value
-                             read from the save state.
-
-  @retval EFI_SUCCESS           The register was read from Save State.
-  @retval EFI_NOT_FOUND         The register is not defined for the Save State
-                                of Processor.
-  @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
-
-**/
-STATIC
-EFI_STATUS
-ReadSaveStateRegisterByIndex (
-  IN UINTN  CpuIndex,
-  IN UINTN  RegisterIndex,
-  IN UINTN  Width,
-  OUT VOID  *Buffer
-  )
-{
-  QEMU_SMRAM_SAVE_STATE_MAP  *CpuSaveState;
-
-  CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
-
-  if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
-    //
-    // If 32-bit mode width is zero, then the specified register can not be
-    // accessed
-    //
-    if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
-      return EFI_NOT_FOUND;
-    }
-
-    //
-    // If Width is bigger than the 32-bit mode width, then the specified
-    // register can not be accessed
-    //
-    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    //
-    // Write return buffer
-    //
-    ASSERT (CpuSaveState != NULL);
-    CopyMem (
-      Buffer,
-      (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
-      Width
-      );
-  } else {
-    //
-    // If 64-bit mode width is zero, then the specified register can not be
-    // accessed
-    //
-    if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
-      return EFI_NOT_FOUND;
-    }
-
-    //
-    // If Width is bigger than the 64-bit mode width, then the specified
-    // register can not be accessed
-    //
-    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    //
-    // Write lower 32-bits of return buffer
-    //
-    CopyMem (
-      Buffer,
-      (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
-      MIN (4, Width)
-      );
-    if (Width >= 4) {
-      //
-      // Write upper 32-bits of return buffer
-      //
-      CopyMem (
-        (UINT8 *)Buffer + 4,
-        (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
-        Width - 4
-        );
-    }
-  }
-
-  return EFI_SUCCESS;
-}
-
-/**
-  Read an SMM Save State register on the target processor.  If this function
-  returns EFI_UNSUPPORTED, then the caller is responsible for reading the
-  SMM Save Sate register.
-
-  @param[in]  CpuIndex  The index of the CPU to read the SMM Save State.  The
-                        value must be between 0 and the NumberOfCpus field in
-                        the System Management System Table (SMST).
-  @param[in]  Register  The SMM Save State register to read.
-  @param[in]  Width     The number of bytes to read from the CPU save state.
-  @param[out] Buffer    Upon return, this holds the CPU register value read
-                        from the save state.
-
-  @retval EFI_SUCCESS           The register was read from Save State.
-  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
-  @retval EFI_UNSUPPORTED       This function does not support reading
-                                Register.
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesReadSaveStateRegister (
-  IN  UINTN                        CpuIndex,
-  IN  EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN  UINTN                        Width,
-  OUT VOID                         *Buffer
-  )
-{
-  UINTN                      RegisterIndex;
-  QEMU_SMRAM_SAVE_STATE_MAP  *CpuSaveState;
-
-  //
-  // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
-  //
-  if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
-    //
-    // Only byte access is supported for this register
-    //
-    if (Width != 1) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
-
-    //
-    // Check CPU mode
-    //
-    if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
-      *(UINT8 *)Buffer = 32;
-    } else {
-      *(UINT8 *)Buffer = 64;
-    }
-
-    return EFI_SUCCESS;
-  }
-
-  //
-  // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
-  //
-  if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
-    return EFI_NOT_FOUND;
-  }
-
-  //
-  // Convert Register to a register lookup table index.  Let
-  // PiSmmCpuDxeSmm implement other special registers (currently
-  // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
-  //
-  RegisterIndex = GetRegisterIndex (Register);
-  if (RegisterIndex == 0) {
-    return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
-            EFI_NOT_FOUND :
-            EFI_UNSUPPORTED);
-  }
-
-  return ReadSaveStateRegisterByIndex (CpuIndex, RegisterIndex, Width, Buffer);
-}
-
-/**
-  Writes an SMM Save State register on the target processor.  If this function
-  returns EFI_UNSUPPORTED, then the caller is responsible for writing the
-  SMM Save Sate register.
-
-  @param[in] CpuIndex  The index of the CPU to write the SMM Save State.  The
-                       value must be between 0 and the NumberOfCpus field in
-                       the System Management System Table (SMST).
-  @param[in] Register  The SMM Save State register to write.
-  @param[in] Width     The number of bytes to write to the CPU save state.
-  @param[in] Buffer    Upon entry, this holds the new CPU register value.
-
-  @retval EFI_SUCCESS           The register was written to Save State.
-  @retval EFI_INVALID_PARAMTER  Buffer is NULL.
-  @retval EFI_UNSUPPORTED       This function does not support writing
-                                Register.
-**/
-EFI_STATUS
-EFIAPI
-SmmCpuFeaturesWriteSaveStateRegister (
-  IN UINTN                        CpuIndex,
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN UINTN                        Width,
-  IN CONST VOID                   *Buffer
-  )
-{
-  UINTN                      RegisterIndex;
-  QEMU_SMRAM_SAVE_STATE_MAP  *CpuSaveState;
-
-  //
-  // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
-  //
-  if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
-    return EFI_SUCCESS;
-  }
-
-  //
-  // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
-  //
-  if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
-    return EFI_NOT_FOUND;
-  }
-
-  //
-  // Convert Register to a register lookup table index.  Let
-  // PiSmmCpuDxeSmm implement other special registers (currently
-  // there is only EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID).
-  //
-  RegisterIndex = GetRegisterIndex (Register);
-  if (RegisterIndex == 0) {
-    return (Register < EFI_SMM_SAVE_STATE_REGISTER_IO ?
-            EFI_NOT_FOUND :
-            EFI_UNSUPPORTED);
-  }
-
-  CpuSaveState = (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];
-
-  //
-  // Do not write non-writable SaveState, because it will cause exception.
-  //
-  if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
-    return EFI_UNSUPPORTED;
-  }
-
-  //
-  // Check CPU mode
-  //
-  if ((CpuSaveState->x86.SMMRevId & 0xFFFF) == 0) {
-    //
-    // If 32-bit mode width is zero, then the specified register can not be
-    // accessed
-    //
-    if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
-      return EFI_NOT_FOUND;
-    }
-
-    //
-    // If Width is bigger than the 32-bit mode width, then the specified
-    // register can not be accessed
-    //
-    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    //
-    // Write SMM State register
-    //
-    ASSERT (CpuSaveState != NULL);
-    CopyMem (
-      (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32,
-      Buffer,
-      Width
-      );
-  } else {
-    //
-    // If 64-bit mode width is zero, then the specified register can not be
-    // accessed
-    //
-    if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
-      return EFI_NOT_FOUND;
-    }
-
-    //
-    // If Width is bigger than the 64-bit mode width, then the specified
-    // register can not be accessed
-    //
-    if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
-      return EFI_INVALID_PARAMETER;
-    }
-
-    //
-    // Write lower 32-bits of SMM State register
-    //
-    CopyMem (
-      (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo,
-      Buffer,
-      MIN (4, Width)
-      );
-    if (Width >= 4) {
-      //
-      // Write upper 32-bits of SMM State register
-      //
-      CopyMem (
-        (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi,
-        (UINT8 *)Buffer + 4,
-        Width - 4
-        );
-    }
-  }
-
-  return EFI_SUCCESS;
-}
-
 /**
   This function is hook point called after the gEfiSmmReadyToLockProtocolGuid
   notification is completely processed.
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [edk2-devel] [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib
  2023-06-06  6:07 [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Abdul Lateef Attar
                   ` (7 preceding siblings ...)
  2023-06-06  6:07 ` [PATCH v14 8/8] OvmfPkg: Uses MmSaveStateLib library Abdul Lateef Attar
@ 2023-06-13  7:55 ` Ni, Ray
  2023-06-16  1:34   ` Ni, Ray
  8 siblings, 1 reply; 12+ messages in thread
From: Ni, Ray @ 2023-06-13  7:55 UTC (permalink / raw)
  To: devel@edk2.groups.io, abdattar@amd.com
  Cc: Paul Grimes, Abner Chang, Dong, Eric, Kumar, Rahul R,
	Gerd Hoffmann, Kinney, Michael D, Gao, Liming, Liu, Zhiguang,
	Ard Biesheuvel, Yao, Jiewen, Justen, Jordan L

Reviewed-by: Ray Ni <ray.ni@intel.com>

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Abdul Lateef
> Attar via groups.io
> Sent: Tuesday, June 6, 2023 2:07 PM
> To: devel@edk2.groups.io
> Cc: Abdul Lateef Attar <abdattar@amd.com>; Paul Grimes
> <paul.grimes@amd.com>; Abner Chang <abner.chang@amd.com>; Dong, Eric
> <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R
> <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>; Kinney,
> Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; Ard
> Biesheuvel <ardb+tianocore@kernel.org>; Yao, Jiewen <jiewen.yao@intel.com>;
> Justen, Jordan L <jordan.l.justen@intel.com>
> Subject: [edk2-devel] [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and
> MmSaveStateLib
> 
> Backward-compatibility changes:
>   This patch series removes the SmmCpuFeaturesReadSaveStateRegister
>   and SmmCpuFeaturesWriteSaveStateRegister interface/function.
>   SmmReadSaveState() and SmmWriteSaveState() now directly invokes
> MmSaveStateLib
>   routines to save/restore registers.
> 
> PR: https://github.com/tianocore/edk2/pull/4519
> 
> V14: Delta changes
>   Added @note to the MmSaveStateLib.h.
>   SaveState(Read/Write) of
> EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID/EFI_MM_SAVE_STATE_REGIS
> TER_PROCESSOR_ID
>   is handled by PiSmmCpuDxeSmm driver.
>   Fixed PatchCheck warnings.
> V13: Delta changes
>   Address review comments from Ray Ni
>   Changed the BASE _NAME of AmdSmmCpuFeaturesLib.
>   Removed EFIAPI from local function.
>   Removed CpuIndex parameter from MmSaveStateGetRegisterLma
>   Modifed MmSaveStateGetRegisterIndex () to accept RegOffset
>     as second parameter.
>   Removed FILE_GUID library instance for intel implemention from
> UefiCpuPkg.dsc.
> V12:
>   Addressed review comments from Michael.
>   Added LibraryClasses to .inf file.
>   removed duplicate MACRO definations.
>   Moved related MACRO defination to respective file.
> V11: Delta changes
>   Drop the OVMF implementation of MmSaveStateLib
> V10: Delta changes:
>   Addressed review comments from Abner.
> V9: Delta changes:
>   Addressed review comments.
>   Rename to MmSaveStateLib.
>   Also rename SMM_ defines to MM_.
>   Implemented OVMF MmSaveStateLib.
>   Removes SmmCpuFeaturesReadSaveStateRegister and
> SmmCpuFeaturesWriteSaveStateRegister
>   function interface.
> V8 delta changes:
>    Addressed review comments from Abner,
>    Fix the whitespace error.
>    Seperate the Ovmf changes to another patch
> V7 delta changes:
>    Adds SmmSmramSaveStateLib for Intel processor.
>    Integrate SmmSmramSaveStateLib library.
> V6 delta changes:
>    Addressed review comments for Ray NI.
>    removed unnecessary EFIAPI.
> V5 delta changes:
>    rebase to master branch.
>    updated Reviewed-by
> V4 delta changes:
>   rebase to master branch.
>   added reviewed-by.
> V3 delta changes:
>   Addressed review comments from Abner chang.
>   Re-arranged patch order.
> 
> Cc: Paul Grimes <paul.grimes@amd.com>
> Cc: Abner Chang <abner.chang@amd.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Abdul Lateef Attar <abdattar@amd.com>
> 
> Abdul Lateef Attar (8):
>   MdePkg: Adds AMD SMRAM save state map
>   UefiCpuPkg: Adds MmSaveStateLib library class
>   UefiCpuPkg: Implements MmSaveStateLib library instance
>   UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code
>   UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family
>   UefiCpuPkg: Implements MmSaveStateLib for Intel
>   UefiCpuPkg: Removes SmmCpuFeaturesReadSaveStateRegister
>   OvmfPkg: Uses MmSaveStateLib library
> 
>  UefiCpuPkg/UefiCpuPkg.dec                     |   4 +
>  OvmfPkg/OvmfPkgIa32.dsc                       |   1 +
>  OvmfPkg/OvmfPkgIa32X64.dsc                    |   3 +
>  OvmfPkg/OvmfPkgX64.dsc                        |   1 +
>  UefiCpuPkg/UefiCpuPkg.dsc                     |  13 +
>  .../MmSaveStateLib/AmdMmSaveStateLib.inf      |  34 +
>  .../MmSaveStateLib/IntelMmSaveStateLib.inf    |  34 +
>  .../AmdSmmCpuFeaturesLib.inf                  |  38 +
>  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf  |   2 +
>  .../Include/Register/Amd/SmramSaveStateMap.h  | 194 +++++
>  UefiCpuPkg/Include/Library/MmSaveStateLib.h   |  74 ++
>  .../Include/Library/SmmCpuFeaturesLib.h       |  52 --
>  .../Library/MmSaveStateLib/MmSaveState.h      |  94 +++
>  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h    |  56 +-
>  .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.c     | 767 ------------------
>  .../Library/MmSaveStateLib/AmdMmSaveState.c   | 309 +++++++
>  .../Library/MmSaveStateLib/IntelMmSaveState.c | 410 ++++++++++
>  .../MmSaveStateLib/MmSaveStateCommon.c        | 132 +++
>  .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c  | 387 +++++++++
>  .../IntelSmmCpuFeaturesLib.c                  |  70 ++
>  .../SmmCpuFeaturesLibCommon.c                 | 128 ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c    |  11 +-
>  UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c    | 500 +-----------
>  MdePkg/MdePkg.ci.yaml                         |   4 +-
>  24 files changed, 1810 insertions(+), 1508 deletions(-)
>  create mode 100644
> UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
>  create mode 100644
> UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
>  create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
>  create mode 100644 MdePkg/Include/Register/Amd/SmramSaveStateMap.h
>  create mode 100644 UefiCpuPkg/Include/Library/MmSaveStateLib.h
>  create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/MmSaveState.h
>  create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c
>  create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveState.c
>  create mode 100644
> UefiCpuPkg/Library/MmSaveStateLib/MmSaveStateCommon.c
>  create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c
> 
> --
> 2.25.1
> 
> 
> 
> 
> 


^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [edk2-devel] [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib
  2023-06-13  7:55 ` [edk2-devel] [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Ni, Ray
@ 2023-06-16  1:34   ` Ni, Ray
  2023-06-19  9:23     ` Gerd Hoffmann
  0 siblings, 1 reply; 12+ messages in thread
From: Ni, Ray @ 2023-06-16  1:34 UTC (permalink / raw)
  To: devel@edk2.groups.io, abdattar@amd.com, Gerd Hoffmann
  Cc: Paul Grimes, Abner Chang, Dong, Eric, Kumar, Rahul R,
	Gerd Hoffmann, Kinney, Michael D, Gao, Liming, Liu, Zhiguang,
	Ard Biesheuvel, Yao, Jiewen, Justen, Jordan L

Gerd,
Can you kindly provide "Reviewed-by" for the patch series?

Thanks,
Ray

> -----Original Message-----
> From: Ni, Ray
> Sent: Tuesday, June 13, 2023 3:56 PM
> To: devel@edk2.groups.io; abdattar@amd.com
> Cc: Paul Grimes <paul.grimes@amd.com>; Abner Chang
> <abner.chang@amd.com>; Dong, Eric <eric.dong@intel.com>; Kumar, Rahul R
> <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>; Kinney,
> Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <gaoliming@byosoft.com.cn>; Liu, Zhiguang <Zhiguang.Liu@intel.com>; Ard
> Biesheuvel <ardb+tianocore@kernel.org>; Yao, Jiewen
> <jiewen.yao@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>
> Subject: RE: [edk2-devel] [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and
> MmSaveStateLib
> 
> Reviewed-by: Ray Ni <ray.ni@intel.com>
> 
> > -----Original Message-----
> > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Abdul
> Lateef
> > Attar via groups.io
> > Sent: Tuesday, June 6, 2023 2:07 PM
> > To: devel@edk2.groups.io
> > Cc: Abdul Lateef Attar <abdattar@amd.com>; Paul Grimes
> > <paul.grimes@amd.com>; Abner Chang <abner.chang@amd.com>; Dong,
> Eric
> > <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R
> > <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com>; Kinney,
> > Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; Ard
> > Biesheuvel <ardb+tianocore@kernel.org>; Yao, Jiewen
> <jiewen.yao@intel.com>;
> > Justen, Jordan L <jordan.l.justen@intel.com>
> > Subject: [edk2-devel] [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and
> > MmSaveStateLib
> >
> > Backward-compatibility changes:
> >   This patch series removes the SmmCpuFeaturesReadSaveStateRegister
> >   and SmmCpuFeaturesWriteSaveStateRegister interface/function.
> >   SmmReadSaveState() and SmmWriteSaveState() now directly invokes
> > MmSaveStateLib
> >   routines to save/restore registers.
> >
> > PR: https://github.com/tianocore/edk2/pull/4519
> >
> > V14: Delta changes
> >   Added @note to the MmSaveStateLib.h.
> >   SaveState(Read/Write) of
> >
> EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID/EFI_MM_SAVE_STATE_REG
> IS
> > TER_PROCESSOR_ID
> >   is handled by PiSmmCpuDxeSmm driver.
> >   Fixed PatchCheck warnings.
> > V13: Delta changes
> >   Address review comments from Ray Ni
> >   Changed the BASE _NAME of AmdSmmCpuFeaturesLib.
> >   Removed EFIAPI from local function.
> >   Removed CpuIndex parameter from MmSaveStateGetRegisterLma
> >   Modifed MmSaveStateGetRegisterIndex () to accept RegOffset
> >     as second parameter.
> >   Removed FILE_GUID library instance for intel implemention from
> > UefiCpuPkg.dsc.
> > V12:
> >   Addressed review comments from Michael.
> >   Added LibraryClasses to .inf file.
> >   removed duplicate MACRO definations.
> >   Moved related MACRO defination to respective file.
> > V11: Delta changes
> >   Drop the OVMF implementation of MmSaveStateLib
> > V10: Delta changes:
> >   Addressed review comments from Abner.
> > V9: Delta changes:
> >   Addressed review comments.
> >   Rename to MmSaveStateLib.
> >   Also rename SMM_ defines to MM_.
> >   Implemented OVMF MmSaveStateLib.
> >   Removes SmmCpuFeaturesReadSaveStateRegister and
> > SmmCpuFeaturesWriteSaveStateRegister
> >   function interface.
> > V8 delta changes:
> >    Addressed review comments from Abner,
> >    Fix the whitespace error.
> >    Seperate the Ovmf changes to another patch
> > V7 delta changes:
> >    Adds SmmSmramSaveStateLib for Intel processor.
> >    Integrate SmmSmramSaveStateLib library.
> > V6 delta changes:
> >    Addressed review comments for Ray NI.
> >    removed unnecessary EFIAPI.
> > V5 delta changes:
> >    rebase to master branch.
> >    updated Reviewed-by
> > V4 delta changes:
> >   rebase to master branch.
> >   added reviewed-by.
> > V3 delta changes:
> >   Addressed review comments from Abner chang.
> >   Re-arranged patch order.
> >
> > Cc: Paul Grimes <paul.grimes@amd.com>
> > Cc: Abner Chang <abner.chang@amd.com>
> > Cc: Eric Dong <eric.dong@intel.com>
> > Cc: Ray Ni <ray.ni@intel.com>
> > Cc: Rahul Kumar <rahul1.kumar@intel.com>
> > Cc: Gerd Hoffmann <kraxel@redhat.com>
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <gaoliming@byosoft.com.cn>
> > Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> > Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > Cc: Jordan Justen <jordan.l.justen@intel.com>
> > Cc: Abdul Lateef Attar <abdattar@amd.com>
> >
> > Abdul Lateef Attar (8):
> >   MdePkg: Adds AMD SMRAM save state map
> >   UefiCpuPkg: Adds MmSaveStateLib library class
> >   UefiCpuPkg: Implements MmSaveStateLib library instance
> >   UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code
> >   UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family
> >   UefiCpuPkg: Implements MmSaveStateLib for Intel
> >   UefiCpuPkg: Removes SmmCpuFeaturesReadSaveStateRegister
> >   OvmfPkg: Uses MmSaveStateLib library
> >
> >  UefiCpuPkg/UefiCpuPkg.dec                     |   4 +
> >  OvmfPkg/OvmfPkgIa32.dsc                       |   1 +
> >  OvmfPkg/OvmfPkgIa32X64.dsc                    |   3 +
> >  OvmfPkg/OvmfPkgX64.dsc                        |   1 +
> >  UefiCpuPkg/UefiCpuPkg.dsc                     |  13 +
> >  .../MmSaveStateLib/AmdMmSaveStateLib.inf      |  34 +
> >  .../MmSaveStateLib/IntelMmSaveStateLib.inf    |  34 +
> >  .../AmdSmmCpuFeaturesLib.inf                  |  38 +
> >  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf  |   2 +
> >  .../Include/Register/Amd/SmramSaveStateMap.h  | 194 +++++
> >  UefiCpuPkg/Include/Library/MmSaveStateLib.h   |  74 ++
> >  .../Include/Library/SmmCpuFeaturesLib.h       |  52 --
> >  .../Library/MmSaveStateLib/MmSaveState.h      |  94 +++
> >  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h    |  56 +-
> >  .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.c     | 767 ------------------
> >  .../Library/MmSaveStateLib/AmdMmSaveState.c   | 309 +++++++
> >  .../Library/MmSaveStateLib/IntelMmSaveState.c | 410 ++++++++++
> >  .../MmSaveStateLib/MmSaveStateCommon.c        | 132 +++
> >  .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c  | 387 +++++++++
> >  .../IntelSmmCpuFeaturesLib.c                  |  70 ++
> >  .../SmmCpuFeaturesLibCommon.c                 | 128 ---
> >  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c    |  11 +-
> >  UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c    | 500 +-----------
> >  MdePkg/MdePkg.ci.yaml                         |   4 +-
> >  24 files changed, 1810 insertions(+), 1508 deletions(-)
> >  create mode 100644
> > UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveStateLib.inf
> >  create mode 100644
> > UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveStateLib.inf
> >  create mode 100644
> > UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
> >  create mode 100644
> MdePkg/Include/Register/Amd/SmramSaveStateMap.h
> >  create mode 100644 UefiCpuPkg/Include/Library/MmSaveStateLib.h
> >  create mode 100644 UefiCpuPkg/Library/MmSaveStateLib/MmSaveState.h
> >  create mode 100644
> UefiCpuPkg/Library/MmSaveStateLib/AmdMmSaveState.c
> >  create mode 100644
> UefiCpuPkg/Library/MmSaveStateLib/IntelMmSaveState.c
> >  create mode 100644
> > UefiCpuPkg/Library/MmSaveStateLib/MmSaveStateCommon.c
> >  create mode 100644
> > UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c
> >
> > --
> > 2.25.1
> >
> >
> >
> > 
> >


^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [edk2-devel] [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib
  2023-06-16  1:34   ` Ni, Ray
@ 2023-06-19  9:23     ` Gerd Hoffmann
  0 siblings, 0 replies; 12+ messages in thread
From: Gerd Hoffmann @ 2023-06-19  9:23 UTC (permalink / raw)
  To: Ni, Ray
  Cc: devel@edk2.groups.io, abdattar@amd.com, Paul Grimes, Abner Chang,
	Dong, Eric, Kumar, Rahul R, Kinney, Michael D, Gao, Liming,
	Liu, Zhiguang, Ard Biesheuvel, Yao, Jiewen, Justen, Jordan L

On Fri, Jun 16, 2023 at 01:34:54AM +0000, Ni, Ray wrote:
> Gerd,
> Can you kindly provide "Reviewed-by" for the patch series?

Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>

take care,
  Gerd


^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2023-06-19  9:23 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-06-06  6:07 [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Abdul Lateef Attar
2023-06-06  6:07 ` [PATCH v14 1/8] MdePkg: Adds AMD SMRAM save state map Abdul Lateef Attar
2023-06-06  6:07 ` [PATCH v14 2/8] UefiCpuPkg: Adds MmSaveStateLib library class Abdul Lateef Attar
2023-06-06  6:07 ` [PATCH v14 3/8] UefiCpuPkg: Implements MmSaveStateLib library instance Abdul Lateef Attar
2023-06-06  6:07 ` [PATCH v14 4/8] UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code Abdul Lateef Attar
2023-06-06  6:07 ` [PATCH v14 5/8] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family Abdul Lateef Attar
2023-06-06  6:07 ` [PATCH v14 6/8] UefiCpuPkg: Implements MmSaveStateLib for Intel Abdul Lateef Attar
2023-06-06  6:07 ` [PATCH v14 7/8] UefiCpuPkg: Removes SmmCpuFeaturesReadSaveStateRegister Abdul Lateef Attar
2023-06-06  6:07 ` [PATCH v14 8/8] OvmfPkg: Uses MmSaveStateLib library Abdul Lateef Attar
2023-06-13  7:55 ` [edk2-devel] [PATCH v14 0/8] Adds AmdSmmCpuFeaturesLib and MmSaveStateLib Ni, Ray
2023-06-16  1:34   ` Ni, Ray
2023-06-19  9:23     ` Gerd Hoffmann

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