* [PATCH v6 0/6] Adds AmdSmmCpuFeaturesLib for AMD Family
@ 2023-03-25 5:38 Abdul Lateef Attar
2023-03-25 5:38 ` [PATCH v6 1/6] MdePkg: Adds AMD SMRAM save state map Abdul Lateef Attar
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Abdul Lateef Attar @ 2023-03-25 5:38 UTC (permalink / raw)
To: devel
Cc: Abdul Lateef Attar, Paul Grimes, Garrett Kirkendall, Abner Chang,
Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann, Michael D Kinney,
Liming Gao, Zhiguang Liu
PR: https://github.com/tianocore/edk2/pull/4173
V6 delta changes:
Addressed review comments for Ray NI,
removed unnecessary EFIAPI.
V5 delta changes:
rebase to master branch.
updated Reviewed-by
V4 delta changes:
rebase to master branch.
added reviewed-by.
V3 delta changes:
Addressed review comments from Abner chang.
Re-arranged patch order.
Cc: Paul Grimes <paul.grimes@amd.com>
Cc: Garrett Kirkendall <garrett.kirkendall@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Abdul Lateef Attar <abdattar@amd.com>
Abdul Lateef Attar (6):
MdePkg: Adds AMD SMRAM save state map
UefiCpuPkg: Adds SmmSmramSaveStateLib library class
UefiCpuPkg: Implements SmmSmramSaveStateLib library class
UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code
UefiCpuPkg: Initial implementation of AMD's SmmCpuFeaturesLib
UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family
UefiCpuPkg/UefiCpuPkg.dec | 4 +
UefiCpuPkg/UefiCpuPkg.dsc | 11 +
.../AmdSmmCpuFeaturesLib.inf | 39 ++
.../AmdSmmSmramSaveStateLib.inf | 28 ++
.../Include/Register/Amd/SmramSaveStateMap.h | 194 ++++++++
.../Include/Library/SmmSmramSaveStateLib.h | 70 +++
.../SmmSmramSaveStateLib/SmramSaveState.h | 101 ++++
.../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c | 445 ++++++++++++++++++
.../IntelSmmCpuFeaturesLib.c | 128 +++++
.../SmmCpuFeaturesLibCommon.c | 128 -----
.../SmmSmramSaveStateLib/AmdSmramSaveState.c | 318 +++++++++++++
.../SmramSaveStateCommon.c | 124 +++++
MdePkg/MdePkg.ci.yaml | 4 +-
13 files changed, 1465 insertions(+), 129 deletions(-)
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf
create mode 100644 UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib.inf
create mode 100644 MdePkg/Include/Register/Amd/SmramSaveStateMap.h
create mode 100644 UefiCpuPkg/Include/Library/SmmSmramSaveStateLib.h
create mode 100644 UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c
create mode 100644 UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmramSaveState.c
create mode 100644 UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v6 1/6] MdePkg: Adds AMD SMRAM save state map 2023-03-25 5:38 [PATCH v6 0/6] Adds AmdSmmCpuFeaturesLib for AMD Family Abdul Lateef Attar @ 2023-03-25 5:38 ` Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 2/6] UefiCpuPkg: Adds SmmSmramSaveStateLib library class Abdul Lateef Attar ` (4 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Abdul Lateef Attar @ 2023-03-25 5:38 UTC (permalink / raw) To: devel Cc: Abdul Lateef Attar, Paul Grimes, Garrett Kirkendall, Abner Chang, Michael D Kinney, Liming Gao, Zhiguang Liu BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Adds an SMM SMRAM save-state map for AMD processors. SMRAM save state maps for the AMD processor family are now supported. Save state map structure is added based on AMD64 Architecture Programmer's Manual, Volume 2, Section 10.2. The AMD legacy save state map for 32-bit architecture is defined. The AMD64 save state map for 64-bit architecture is defined. Also added Amd/SmramSaveStateMap.h to IgnoreFiles of EccCheck, because structures defined in this file are derived from Intel/SmramSaveStateMap.h. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> --- .../Include/Register/Amd/SmramSaveStateMap.h | 194 ++++++++++++++++++ MdePkg/MdePkg.ci.yaml | 4 +- 2 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Include/Register/Amd/SmramSaveStateMap.h diff --git a/MdePkg/Include/Register/Amd/SmramSaveStateMap.h b/MdePkg/Include/Register/Amd/SmramSaveStateMap.h new file mode 100644 index 000000000000..0607d2a19145 --- /dev/null +++ b/MdePkg/Include/Register/Amd/SmramSaveStateMap.h @@ -0,0 +1,194 @@ +/** @file + AMD SMRAM Save State Map Definitions. + + SMRAM Save State Map definitions based on contents of the + AMD64 Architecture Programmer Manual: + Volume 2, System Programming, Section 10.2 SMM Resources + + Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR> + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved .<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef AMD_SMRAM_SAVE_STATE_MAP_H_ +#define AMD_SMRAM_SAVE_STATE_MAP_H_ + +/// +/// Default SMBASE address +/// +#define SMM_DEFAULT_SMBASE 0x30000 + +/// +/// Offset of SMM handler from SMBASE +/// +#define SMM_HANDLER_OFFSET 0x8000 + +// SMM-Revision Identifier for AMD64 Architecture. +#define AMD_SMM_MIN_REV_ID_X64 0x30064 + +#pragma pack (1) + +/// +/// 32-bit SMRAM Save State Map +/// +typedef struct { + // Padded an extra 0x200 bytes to match Intel/EDK2 + UINT8 Reserved[0x200]; // fc00h + // AMD Save State area starts @ 0xfe00 + UINT8 Reserved1[0xf8]; // fe00h + UINT32 SMBASE; // fef8h + UINT32 SMMRevId; // fefch + UINT16 IORestart; // ff00h + UINT16 AutoHALTRestart; // ff02h + UINT8 Reserved2[0x84]; // ff04h + UINT32 GDTBase; // ff88h + UINT64 Reserved3; // ff8ch + UINT32 IDTBase; // ff94h + UINT8 Reserved4[0x10]; // ff98h + UINT32 _ES; // ffa8h + UINT32 _CS; // ffach + UINT32 _SS; // ffb0h + UINT32 _DS; // ffb4h + UINT32 _FS; // ffb8h + UINT32 _GS; // ffbch + UINT32 LDTBase; // ffc0h + UINT32 _TR; // ffc4h + UINT32 _DR7; // ffc8h + UINT32 _DR6; // ffcch + UINT32 _EAX; // ffd0h + UINT32 _ECX; // ffd4h + UINT32 _EDX; // ffd8h + UINT32 _EBX; // ffdch + UINT32 _ESP; // ffe0h + UINT32 _EBP; // ffe4h + UINT32 _ESI; // ffe8h + UINT32 _EDI; // ffech + UINT32 _EIP; // fff0h + UINT32 _EFLAGS; // fff4h + UINT32 _CR3; // fff8h + UINT32 _CR0; // fffch +} AMD_SMRAM_SAVE_STATE_MAP32; + +/// +/// 64-bit SMRAM Save State Map +/// +typedef struct { + // Padded an extra 0x200 bytes to match Intel/EDK2 + UINT8 Reserved[0x200]; // fc00h + // AMD Save State area starts @ 0xfe00 + UINT16 _ES; // fe00h + UINT16 _ESAttributes; // fe02h + UINT32 _ESLimit; // fe04h + UINT64 _ESBase; // fe08h + + UINT16 _CS; // fe10h + UINT16 _CSAttributes; // fe12h + UINT32 _CSLimit; // fe14h + UINT64 _CSBase; // fe18h + + UINT16 _SS; // fe20h + UINT16 _SSAttributes; // fe22h + UINT32 _SSLimit; // fe24h + UINT64 _SSBase; // fe28h + + UINT16 _DS; // fe30h + UINT16 _DSAttributes; // fe32h + UINT32 _DSLimit; // fe34h + UINT64 _DSBase; // fe38h + + UINT16 _FS; // fe40h + UINT16 _FSAttributes; // fe42h + UINT32 _FSLimit; // fe44h + UINT64 _FSBase; // fe48h + + UINT16 _GS; // fe50h + UINT16 _GSAttributes; // fe52h + UINT32 _GSLimit; // fe54h + UINT64 _GSBase; // fe58h + + UINT32 _GDTRReserved1; // fe60h + UINT16 _GDTRLimit; // fe64h + UINT16 _GDTRReserved2; // fe66h + // UINT64 _GDTRBase; // fe68h + UINT32 _GDTRBaseLoDword; + UINT32 _GDTRBaseHiDword; + + UINT16 _LDTR; // fe70h + UINT16 _LDTRAttributes; // fe72h + UINT32 _LDTRLimit; // fe74h + // UINT64 _LDTRBase; // fe78h + UINT32 _LDTRBaseLoDword; + UINT32 _LDTRBaseHiDword; + + UINT32 _IDTRReserved1; // fe80h + UINT16 _IDTRLimit; // fe84h + UINT16 _IDTRReserved2; // fe86h + // UINT64 _IDTRBase; // fe88h + UINT32 _IDTRBaseLoDword; + UINT32 _IDTRBaseHiDword; + + UINT16 _TR; // fe90h + UINT16 _TRAttributes; // fe92h + UINT32 _TRLimit; // fe94h + UINT64 _TRBase; // fe98h + + UINT64 IO_RIP; // fea0h + UINT64 IO_RCX; // fea8h + UINT64 IO_RSI; // feb0h + UINT64 IO_RDI; // feb8h + UINT32 IO_DWord; // fec0h + UINT8 Reserved1[0x04]; // fec4h + UINT8 IORestart; // fec8h + UINT8 AutoHALTRestart; // fec9h + UINT8 Reserved2[0x06]; // fecah + UINT64 EFER; // fed0h + UINT64 SVM_Guest; // fed8h + UINT64 SVM_GuestVMCB; // fee0h + UINT64 SVM_GuestVIntr; // fee8h + UINT8 Reserved3[0x0c]; // fef0h + UINT32 SMMRevId; // fefch + UINT32 SMBASE; // ff00h + UINT8 Reserved4[0x14]; // ff04h + UINT64 SSP; // ff18h + UINT64 SVM_GuestPAT; // ff20h + UINT64 SVM_HostEFER; // ff28h + UINT64 SVM_HostCR4; // ff30h + UINT64 SVM_HostCR3; // ff38h + UINT64 SVM_HostCR0; // ff40h + UINT64 _CR4; // ff48h + UINT64 _CR3; // ff50h + UINT64 _CR0; // ff58h + UINT64 _DR7; // ff60h + UINT64 _DR6; // ff68h + UINT64 _RFLAGS; // ff70h + UINT64 _RIP; // ff78h + UINT64 _R15; // ff80h + UINT64 _R14; // ff88h + UINT64 _R13; // ff90h + UINT64 _R12; // ff98h + UINT64 _R11; // ffa0h + UINT64 _R10; // ffa8h + UINT64 _R9; // ffb0h + UINT64 _R8; // ffb8h + UINT64 _RDI; // ffc0h + UINT64 _RSI; // ffc8h + UINT64 _RBP; // ffd0h + UINT64 _RSP; // ffd8h + UINT64 _RBX; // ffe0h + UINT64 _RDX; // ffe8h + UINT64 _RCX; // fff0h + UINT64 _RAX; // fff8h +} AMD_SMRAM_SAVE_STATE_MAP64; + +/// +/// Union of 32-bit and 64-bit SMRAM Save State Maps +/// +typedef union { + AMD_SMRAM_SAVE_STATE_MAP32 x86; + AMD_SMRAM_SAVE_STATE_MAP64 x64; +} AMD_SMRAM_SAVE_STATE_MAP; + +#pragma pack () + +#endif diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml index 6ba85ebe6186..ac8c93c975ac 100644 --- a/MdePkg/MdePkg.ci.yaml +++ b/MdePkg/MdePkg.ci.yaml @@ -5,6 +5,7 @@ # Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2021, Arm Limited. All rights reserved.<BR> # Copyright (c) 2023, Loongson Technology Corporation Limited. All rights reserved.<BR> +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved .<BR> # SPDX-License-Identifier: BSD-2-Clause-Patent ## { @@ -67,7 +68,8 @@ "Include/Library/PcdLib.h", "Include/Library/SafeIntLib.h", "Include/Protocol/DebugSupport.h", - "Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c" + "Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c", + "Include/Register/Amd/SmramSaveStateMap.h" ] }, ## options defined ci/Plugin/CompilerPlugin -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v6 2/6] UefiCpuPkg: Adds SmmSmramSaveStateLib library class 2023-03-25 5:38 [PATCH v6 0/6] Adds AmdSmmCpuFeaturesLib for AMD Family Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 1/6] MdePkg: Adds AMD SMRAM save state map Abdul Lateef Attar @ 2023-03-25 5:38 ` Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 3/6] UefiCpuPkg: Implements " Abdul Lateef Attar ` (3 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Abdul Lateef Attar @ 2023-03-25 5:38 UTC (permalink / raw) To: devel Cc: Abdul Lateef Attar, Paul Grimes, Garrett Kirkendall, Abner Chang, Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Adds SmmSmramSaveStateLib Library class in UefiCpuPkg.dec. Adds function declaration header file. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> --- UefiCpuPkg/UefiCpuPkg.dec | 4 ++ .../Include/Library/SmmSmramSaveStateLib.h | 70 +++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100644 UefiCpuPkg/Include/Library/SmmSmramSaveStateLib.h diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 2115aa4387a2..8284237511cc 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -2,6 +2,7 @@ # This Package provides UEFI compatible CPU modules and libraries. # # Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.<BR> +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -65,6 +66,9 @@ [LibraryClasses.IA32, LibraryClasses.X64] ## @libraryclass Provides function for manipulating x86 paging structures. CpuPageTableLib|Include/Library/CpuPageTableLib.h + ## @libraryclass Provides functions for manipulating Smram savestate registers. + SmmSmramSaveSateLib|Include/Library/SmmSmramSaveStateLib.h + [Guids] gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }} gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }} diff --git a/UefiCpuPkg/Include/Library/SmmSmramSaveStateLib.h b/UefiCpuPkg/Include/Library/SmmSmramSaveStateLib.h new file mode 100644 index 000000000000..46bc6381bcde --- /dev/null +++ b/UefiCpuPkg/Include/Library/SmmSmramSaveStateLib.h @@ -0,0 +1,70 @@ +/** @file +Library that provides service to read/write CPU specific smram save state registers. + +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR> +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMM_SMRAM_SAVE_STATE_LIB_H_ +#define SMM_SMRAM_SAVE_STATE_LIB_H_ + +#include <Protocol/SmmCpu.h> +#include <Uefi/UefiBaseType.h> + +/** + Read an SMM Save State register on the target processor. If this function + returns EFI_UNSUPPORTED, then the caller is responsible for reading the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to read the SMM Save State. The + value must be between 0 and the NumberOfCpus field in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to read. + @param[in] Width The number of bytes to read from the CPU save state. + @param[out] Buffer Upon return, this holds the CPU register value read + from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support reading Register. + @retval EFI_NOT_FOUND If desired Register not found. +**/ +EFI_STATUS +EFIAPI +SmramSaveStateReadRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + OUT VOID *Buffer + ); + +/** + Writes an SMM Save State register on the target processor. If this function + returns EFI_UNSUPPORTED, then the caller is responsible for writing the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to write the SMM Save State. The + value must be between 0 and the NumberOfCpus field in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to write. + @param[in] Width The number of bytes to write to the CPU save state. + @param[in] Buffer Upon entry, this holds the new CPU register value. + + @retval EFI_SUCCESS The register was written to Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support writing Register. + @retval EFI_NOT_FOUND If desired Register not found. +**/ +EFI_STATUS +EFIAPI +SmramSaveStateWriteRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + IN CONST VOID *Buffer + ); + +#endif -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v6 3/6] UefiCpuPkg: Implements SmmSmramSaveStateLib library class 2023-03-25 5:38 [PATCH v6 0/6] Adds AmdSmmCpuFeaturesLib for AMD Family Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 1/6] MdePkg: Adds AMD SMRAM save state map Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 2/6] UefiCpuPkg: Adds SmmSmramSaveStateLib library class Abdul Lateef Attar @ 2023-03-25 5:38 ` Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 4/6] UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code Abdul Lateef Attar ` (2 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Abdul Lateef Attar @ 2023-03-25 5:38 UTC (permalink / raw) To: devel Cc: Abdul Lateef Attar, Paul Grimes, Garrett Kirkendall, Abner Chang, Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann, Abdul Lateef Attar From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Implements SmmSmramSaveStateLib Library class for AMD cpu family. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> --- UefiCpuPkg/UefiCpuPkg.dsc | 3 + .../AmdSmmSmramSaveStateLib.inf | 28 ++ .../SmmSmramSaveStateLib/SmramSaveState.h | 101 ++++++ .../SmmSmramSaveStateLib/AmdSmramSaveState.c | 318 ++++++++++++++++++ .../SmramSaveStateCommon.c | 124 +++++++ 5 files changed, 574 insertions(+) create mode 100644 UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib.inf create mode 100644 UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h create mode 100644 UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmramSaveState.c create mode 100644 UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index a7318d3fe9db..c9bbff986fbd 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -2,6 +2,7 @@ # UefiCpuPkg Package # # Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR> +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -104,6 +105,7 @@ [LibraryClasses.common.DXE_SMM_DRIVER] MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf + SmmSmramSaveStateLib|UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib.inf [LibraryClasses.common.MM_STANDALONE] MmServicesTableLib|MdePkg/Library/StandaloneMmServicesTableLib/StandaloneMmServicesTableLib.inf @@ -191,6 +193,7 @@ [Components.IA32, Components.X64] <LibraryClasses> UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestResultReportLibConOut.inf } + UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib.inf [Components.X64] UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHandlerLibUnitTest.inf diff --git a/UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib.inf b/UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib.inf new file mode 100644 index 000000000000..91f8927e0419 --- /dev/null +++ b/UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib.inf @@ -0,0 +1,28 @@ +## @file +# SMM Smram save state service lib. +# +# This is SMM Smram save state service lib that provide service to read and +# save savestate area registers. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 1.29 + BASE_NAME = AmdSmmSmramSaveStateLib + FILE_GUID = FB7D0A60-E8D4-4EFA-90AA-B357BC569879 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = SmmSmramSaveStateLib + +[Sources] + SmramSaveState.h + SmramSaveStateCommon.c + AmdSmramSaveState.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec diff --git a/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h b/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h new file mode 100644 index 000000000000..6c424e3e36e9 --- /dev/null +++ b/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveState.h @@ -0,0 +1,101 @@ +/** @file + SMRAM Save State Map header file. + + Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR> + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SMRAM_SAVESTATE_H_ +#define SMRAM_SAVESTATE_H_ + +#include <Uefi/UefiBaseType.h> +#include <Protocol/SmmCpu.h> +#include <Library/DebugLib.h> +#include <Library/SmmSmramSaveStateLib.h> +#include <Library/SmmServicesTableLib.h> +#include <Library/BaseMemoryLib.h> + +// EFER register LMA bit +#define LMA BIT10 + +// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE +#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 } + +#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 2 + +// Structure used to describe a range of registers +typedef struct { + EFI_SMM_SAVE_STATE_REGISTER Start; + EFI_SMM_SAVE_STATE_REGISTER End; + UINTN Length; +} CPU_SMM_SAVE_STATE_REGISTER_RANGE; + +// Structure used to build a lookup table to retrieve the widths and offsets +// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value + +typedef struct { + UINT8 Width32; + UINT8 Width64; + UINT16 Offset32; + UINT16 Offset64Lo; + UINT16 Offset64Hi; + BOOLEAN Writeable; +} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY; + +/** + Returns LMA value of the Processor. + + @param[in] VOID + + @retval UINT8 returns LMA bit value. +**/ +UINT8 +SmramSaveStateGetRegisterLma ( + VOID + ); + +/** + Read information from the CPU save state. + + @param Register Specifies the CPU register to read form the save state. + + @retval 0 Register is not valid + @retval >0 Index into mSmmSmramCpuWidthOffset[] associated with Register + +**/ +UINTN +EFIAPI +SmramSaveStateGetRegisterIndex ( + IN EFI_SMM_SAVE_STATE_REGISTER Register + ); + +/** + Read a CPU Save State register on the target processor. + + This function abstracts the differences that whether the CPU Save State register is in the + IA32 CPU Save State Map or X64 CPU Save State Map. + + This function supports reading a CPU Save State register in SMBase relocation handler. + + @param[in] CpuIndex Specifies the zero-based index of the CPU save state. + @param[in] RegisterIndex Index into mSmmSmramCpuWidthOffset[] look up table. + @param[in] Width The number of bytes to read from the CPU save state. + @param[out] Buffer Upon return, this holds the CPU register value read from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor. + @retval EFI_INVALID_PARAMTER This or Buffer is NULL. + +**/ +EFI_STATUS +EFIAPI +SmramSaveStateReadRegisterByIndex ( + IN UINTN CpuIndex, + IN UINTN RegisterIndex, + IN UINTN Width, + OUT VOID *Buffer + ); + +#endif diff --git a/UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmramSaveState.c b/UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmramSaveState.c new file mode 100644 index 000000000000..8fc4466f473e --- /dev/null +++ b/UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmramSaveState.c @@ -0,0 +1,318 @@ +/** @file +Provides services to access SMRAM Save State Map + +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR> +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmramSaveState.h" +#include <Register/Amd/SmramSaveStateMap.h> +#include <Library/BaseLib.h> + +#define EFER_ADDRESS 0XC0000080ul +#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1 + +// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY +#define SMM_CPU_OFFSET(Field) OFFSET_OF (AMD_SMRAM_SAVE_STATE_MAP, Field) + +// Table used by SmramSaveStateGetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER +// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY +CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmSmramCpuRegisterRanges[] = { + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO), + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP), + SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4), + { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0} +}; + +// Lookup table used to retrieve the widths and offsets associated with each +// supported EFI_SMM_SAVE_STATE_REGISTER value +CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmSmramCpuWidthOffset[] = { + { 0, 0, 0, 0, FALSE }, // Reserved + + // + // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol. + // + { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId), SMM_CPU_OFFSET (x64.SMMRevId), 0, FALSE}, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1 + + // + // CPU Save State registers defined in PI SMM CPU Protocol. + // + { 4, 8, SMM_CPU_OFFSET (x86.GDTBase), SMM_CPU_OFFSET (x64._GDTRBaseLoDword), SMM_CPU_OFFSET (x64._GDTRBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4 + { 0, 8, 0, SMM_CPU_OFFSET (x64._IDTRBaseLoDword), SMM_CPU_OFFSET (x64._IDTRBaseLoDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5 + { 0, 8, 0, SMM_CPU_OFFSET (x64._LDTRBaseLoDword), SMM_CPU_OFFSET (x64._LDTRBaseLoDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6 + { 0, 2, 0, SMM_CPU_OFFSET (x64._GDTRLimit), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7 + { 0, 2, 0, SMM_CPU_OFFSET (x64._IDTRLimit), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8 + { 0, 4, 0, SMM_CPU_OFFSET (x64._LDTRLimit), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9 + { 0, 0, 0, 0, 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10 + { 4, 2, SMM_CPU_OFFSET (x86._ES), SMM_CPU_OFFSET (x64._ES), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20 + { 4, 2, SMM_CPU_OFFSET (x86._CS), SMM_CPU_OFFSET (x64._CS), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21 + { 4, 2, SMM_CPU_OFFSET (x86._SS), SMM_CPU_OFFSET (x64._SS), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22 + { 4, 2, SMM_CPU_OFFSET (x86._DS), SMM_CPU_OFFSET (x64._DS), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23 + { 4, 2, SMM_CPU_OFFSET (x86._FS), SMM_CPU_OFFSET (x64._FS), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24 + { 4, 2, SMM_CPU_OFFSET (x86._GS), SMM_CPU_OFFSET (x64._GS), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25 + { 0, 2, 0, SMM_CPU_OFFSET (x64._LDTR), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26 + { 0, 2, 0, SMM_CPU_OFFSET (x64._TR), 0, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27 + { 4, 8, SMM_CPU_OFFSET (x86._DR7), SMM_CPU_OFFSET (x64._DR7), SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28 + { 4, 8, SMM_CPU_OFFSET (x86._DR6), SMM_CPU_OFFSET (x64._DR6), SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R8), SMM_CPU_OFFSET (x64._R8) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R9), SMM_CPU_OFFSET (x64._R9) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R10), SMM_CPU_OFFSET (x64._R10) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R11), SMM_CPU_OFFSET (x64._R11) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R12), SMM_CPU_OFFSET (x64._R12) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R13), SMM_CPU_OFFSET (x64._R13) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R14), SMM_CPU_OFFSET (x64._R14) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36 + { 0, 8, 0, SMM_CPU_OFFSET (x64._R15), SMM_CPU_OFFSET (x64._R15) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37 + { 4, 8, SMM_CPU_OFFSET (x86._EAX), SMM_CPU_OFFSET (x64._RAX), SMM_CPU_OFFSET (x64._RAX) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38 + { 4, 8, SMM_CPU_OFFSET (x86._EBX), SMM_CPU_OFFSET (x64._RBX), SMM_CPU_OFFSET (x64._RBX) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39 + { 4, 8, SMM_CPU_OFFSET (x86._ECX), SMM_CPU_OFFSET (x64._RCX), SMM_CPU_OFFSET (x64._RCX) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39 + { 4, 8, SMM_CPU_OFFSET (x86._EDX), SMM_CPU_OFFSET (x64._RDX), SMM_CPU_OFFSET (x64._RDX) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41 + { 4, 8, SMM_CPU_OFFSET (x86._ESP), SMM_CPU_OFFSET (x64._RSP), SMM_CPU_OFFSET (x64._RSP) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42 + { 4, 8, SMM_CPU_OFFSET (x86._EBP), SMM_CPU_OFFSET (x64._RBP), SMM_CPU_OFFSET (x64._RBP) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43 + { 4, 8, SMM_CPU_OFFSET (x86._ESI), SMM_CPU_OFFSET (x64._RSI), SMM_CPU_OFFSET (x64._RSI) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44 + { 4, 8, SMM_CPU_OFFSET (x86._EDI), SMM_CPU_OFFSET (x64._RDI), SMM_CPU_OFFSET (x64._RDI) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45 + { 4, 8, SMM_CPU_OFFSET (x86._EIP), SMM_CPU_OFFSET (x64._RIP), SMM_CPU_OFFSET (x64._RIP) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46 + + { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS), SMM_CPU_OFFSET (x64._RFLAGS), SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE}, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51 + { 4, 8, SMM_CPU_OFFSET (x86._CR0), SMM_CPU_OFFSET (x64._CR0), SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52 + { 4, 8, SMM_CPU_OFFSET (x86._CR3), SMM_CPU_OFFSET (x64._CR3), SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53 + { 0, 8, 0, SMM_CPU_OFFSET (x64._CR4), SMM_CPU_OFFSET (x64._CR4) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54 + { 0, 0, 0, 0, 0 } +}; + +/** + Read an SMM Save State register on the target processor. If this function + returns EFI_UNSUPPORTED, then the caller is responsible for reading the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to read the SMM Save State. The + value must be between 0 and the NumberOfCpus field in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to read. + @param[in] Width The number of bytes to read from the CPU save state. + @param[out] Buffer Upon return, this holds the CPU register value read + from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support reading Register. + @retval EFI_NOT_FOUND If desired Register not found. +**/ +EFI_STATUS +EFIAPI +SmramSaveStateReadRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + OUT VOID *Buffer + ) +{ + UINT32 SmmRevId; + EFI_SMM_SAVE_STATE_IO_INFO *IoInfo; + AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState; + UINT8 DataWidth; + + // Read CPU State + CpuSaveState = (AMD_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex]; + + // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA + if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) { + // Only byte access is supported for this register + if (Width != 1) { + return EFI_INVALID_PARAMETER; + } + + *(UINT8 *)Buffer = SmramSaveStateGetRegisterLma (); + + return EFI_SUCCESS; + } + + // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO + + if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) { + // + // Get SMM Revision ID + // + SmramSaveStateReadRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId); + + // + // See if the CPU supports the IOMisc register in the save state + // + if (SmmRevId < AMD_SMM_MIN_REV_ID_X64) { + return EFI_NOT_FOUND; + } + + // Check if IO Restart Dword [IO Trap] is valid or not using bit 1. + if (!(CpuSaveState->x64.IO_DWord & 0x02u)) { + return EFI_NOT_FOUND; + } + + // Zero the IoInfo structure that will be returned in Buffer + IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer; + ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO)); + + IoInfo->IoPort = (UINT16)(CpuSaveState->x64.IO_DWord >> 16u); + + if (CpuSaveState->x64.IO_DWord & 0x10u) { + IoInfo->IoWidth = EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8; + DataWidth = 0x01u; + } else if (CpuSaveState->x64.IO_DWord & 0x20u) { + IoInfo->IoWidth = EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16; + DataWidth = 0x02u; + } else { + IoInfo->IoWidth = EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32; + DataWidth = 0x04u; + } + + if (CpuSaveState->x64.IO_DWord & 0x01u) { + IoInfo->IoType = EFI_SMM_SAVE_STATE_IO_TYPE_INPUT; + } else { + IoInfo->IoType = EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT; + } + + if ((IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) || (IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT)) { + SmramSaveStateReadRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX, DataWidth, &IoInfo->IoData); + } + + return EFI_SUCCESS; + } + + // Convert Register to a register lookup table index + return SmramSaveStateReadRegisterByIndex (CpuIndex, SmramSaveStateGetRegisterIndex (Register), Width, Buffer); +} + +/** + Writes an SMM Save State register on the target processor. If this function + returns EFI_UNSUPPORTED, then the caller is responsible for writing the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to write the SMM Save State. The + value must be between 0 and the NumberOfCpus field in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to write. + @param[in] Width The number of bytes to write to the CPU save state. + @param[in] Buffer Upon entry, this holds the new CPU register value. + + @retval EFI_SUCCESS The register was written to Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support writing Register. + @retval EFI_NOT_FOUND If desired Register not found. +**/ +EFI_STATUS +EFIAPI +SmramSaveStateWriteRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + IN CONST VOID *Buffer + ) +{ + UINTN RegisterIndex; + AMD_SMRAM_SAVE_STATE_MAP *CpuSaveState; + + // + // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored + // + if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) { + return EFI_SUCCESS; + } + + // + // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported + // + if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) { + return EFI_NOT_FOUND; + } + + // + // Convert Register to a register lookup table index + // + RegisterIndex = SmramSaveStateGetRegisterIndex (Register); + if (RegisterIndex == 0) { + return EFI_NOT_FOUND; + } + + CpuSaveState = gSmst->CpuSaveState[CpuIndex]; + + // + // Do not write non-writable SaveState, because it will cause exception. + // + if (!mSmmSmramCpuWidthOffset[RegisterIndex].Writeable) { + return EFI_UNSUPPORTED; + } + + // + // Check CPU mode + // + if (SmramSaveStateGetRegisterLma () == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { + // + // If 32-bit mode width is zero, then the specified register can not be accessed + // + if (mSmmSmramCpuWidthOffset[RegisterIndex].Width32 == 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed + // + if (Width > mSmmSmramCpuWidthOffset[RegisterIndex].Width32) { + return EFI_INVALID_PARAMETER; + } + + // + // Write SMM State register + // + ASSERT (CpuSaveState != NULL); + CopyMem ((UINT8 *)CpuSaveState + mSmmSmramCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width); + } else { + // + // If 64-bit mode width is zero, then the specified register can not be accessed + // + if (mSmmSmramCpuWidthOffset[RegisterIndex].Width64 == 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed + // + if (Width > mSmmSmramCpuWidthOffset[RegisterIndex].Width64) { + return EFI_INVALID_PARAMETER; + } + + // + // Write lower 32-bits of SMM State register + // + CopyMem ((UINT8 *)CpuSaveState + mSmmSmramCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width)); + if (Width >= 4) { + // + // Write upper 32-bits of SMM State register + // + CopyMem ((UINT8 *)CpuSaveState + mSmmSmramCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4); + } + } + + return EFI_SUCCESS; +} + +/** + Returns LMA value of the Processor. + + @param[in] VOID + + @retval UINT8 returns LMA bit value. +**/ +UINT8 +SmramSaveStateGetRegisterLma ( + VOID + ) +{ + UINT32 LMAValue; + + LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; + if (LMAValue) { + return EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; + } + + return EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; +} diff --git a/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c b/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c new file mode 100644 index 000000000000..98e89f9eec3f --- /dev/null +++ b/UefiCpuPkg/Library/SmmSmramSaveStateLib/SmramSaveStateCommon.c @@ -0,0 +1,124 @@ +/** @file + Provides common supporting function to access SMRAM Save State Map + + Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR> + Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SmramSaveState.h" + +extern CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmSmramCpuRegisterRanges[]; +extern CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmSmramCpuWidthOffset[]; + +/** + Read information from the CPU save state. + + @param Register Specifies the CPU register to read form the save state. + + @retval 0 Register is not valid + @retval >0 Index into mSmmSmramCpuWidthOffset[] associated with Register + +**/ +UINTN +EFIAPI +SmramSaveStateGetRegisterIndex ( + IN EFI_SMM_SAVE_STATE_REGISTER Register + ) +{ + UINTN Index; + UINTN Offset; + + for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmSmramCpuRegisterRanges[Index].Length != 0; Index++) { + if ((Register >= mSmmSmramCpuRegisterRanges[Index].Start) && (Register <= mSmmSmramCpuRegisterRanges[Index].End)) { + return Register - mSmmSmramCpuRegisterRanges[Index].Start + Offset; + } + + Offset += mSmmSmramCpuRegisterRanges[Index].Length; + } + + return 0; +} + +/** + Read a CPU Save State register on the target processor. + + This function abstracts the differences that whether the CPU Save State register is in the + IA32 CPU Save State Map or X64 CPU Save State Map. + + This function supports reading a CPU Save State register in SMBase relocation handler. + + @param[in] CpuIndex Specifies the zero-based index of the CPU save state. + @param[in] RegisterIndex Index into mSmmSmramCpuWidthOffset[] look up table. + @param[in] Width The number of bytes to read from the CPU save state. + @param[out] Buffer Upon return, this holds the CPU register value read from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor. + @retval EFI_INVALID_PARAMTER This or Buffer is NULL. + +**/ +EFI_STATUS +EFIAPI +SmramSaveStateReadRegisterByIndex ( + IN UINTN CpuIndex, + IN UINTN RegisterIndex, + IN UINTN Width, + OUT VOID *Buffer + ) +{ + if (RegisterIndex == 0) { + return EFI_NOT_FOUND; + } + + if (SmramSaveStateGetRegisterLma () == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { + // + // If 32-bit mode width is zero, then the specified register can not be accessed + // + if (mSmmSmramCpuWidthOffset[RegisterIndex].Width32 == 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 32-bit mode width, then the specified register can not be accessed + // + if (Width > mSmmSmramCpuWidthOffset[RegisterIndex].Width32) { + return EFI_INVALID_PARAMETER; + } + + // + // Write return buffer + // + ASSERT (gSmst->CpuSaveState[CpuIndex] != NULL); + CopyMem (Buffer, (UINT8 *)gSmst->CpuSaveState[CpuIndex] + mSmmSmramCpuWidthOffset[RegisterIndex].Offset32, Width); + } else { + // + // If 64-bit mode width is zero, then the specified register can not be accessed + // + if (mSmmSmramCpuWidthOffset[RegisterIndex].Width64 == 0) { + return EFI_NOT_FOUND; + } + + // + // If Width is bigger than the 64-bit mode width, then the specified register can not be accessed + // + if (Width > mSmmSmramCpuWidthOffset[RegisterIndex].Width64) { + return EFI_INVALID_PARAMETER; + } + + // + // Write lower 32-bits of return buffer + // + CopyMem (Buffer, (UINT8 *)gSmst->CpuSaveState[CpuIndex] + mSmmSmramCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width)); + if (Width >= 4) { + // + // Write upper 32-bits of return buffer + // + CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)gSmst->CpuSaveState[CpuIndex] + mSmmSmramCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4); + } + } + + return EFI_SUCCESS; +} -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v6 4/6] UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code 2023-03-25 5:38 [PATCH v6 0/6] Adds AmdSmmCpuFeaturesLib for AMD Family Abdul Lateef Attar ` (2 preceding siblings ...) 2023-03-25 5:38 ` [PATCH v6 3/6] UefiCpuPkg: Implements " Abdul Lateef Attar @ 2023-03-25 5:38 ` Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 5/6] UefiCpuPkg: Initial implementation of AMD's SmmCpuFeaturesLib Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 6/6] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family Abdul Lateef Attar 5 siblings, 0 replies; 9+ messages in thread From: Abdul Lateef Attar @ 2023-03-25 5:38 UTC (permalink / raw) To: devel Cc: Abdul Lateef Attar, Abner Chang, Garrett Kirkendall, Paul Grimes, Eric Dong, Ray Ni, Rahul Kumar From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 moves Intel-specific code to the arch-dependent file. Other processor families might have different implementation of these functions. Hence, moving out of the common file. Cc: Abner Chang <abner.chang@amd.com> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> Cc: Paul Grimes <paul.grimes@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> --- .../IntelSmmCpuFeaturesLib.c | 128 ++++++++++++++++++ .../SmmCpuFeaturesLibCommon.c | 128 ------------------ 2 files changed, 128 insertions(+), 128 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c index 1a2c706fa1f1..8f382b60266c 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/IntelSmmCpuFeaturesLib.c @@ -417,3 +417,131 @@ SmmCpuFeaturesSetSmmRegister ( AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value); } } + +/** + This function updates the SMRAM save state on the currently executing CPU + to resume execution at a specific address after an RSM instruction. This + function must evaluate the SMRAM save state to determine the execution mode + the RSM instruction resumes and update the resume execution address with + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart + flag in the SMRAM save state must always be cleared. This function returns + the value of the instruction pointer from the SMRAM save state that was + replaced. If this function returns 0, then the SMRAM save state was not + modified. + + This function is called during the very first SMI on each CPU after + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode + to signal that the SMBASE of each CPU has been updated before the default + SMBASE address is used for the first SMI to the next CPU. + + @param[in] CpuIndex The index of the CPU to hook. The value + must be between 0 and the NumberOfCpus + field in the System Management System Table + (SMST). + @param[in] CpuState Pointer to SMRAM Save State Map for the + currently executing CPU. + @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to + 32-bit execution mode from 64-bit SMM. + @param[in] NewInstructionPointer Instruction pointer to use if resuming to + same execution mode as SMM. + + @retval 0 This function did modify the SMRAM save state. + @retval > 0 The original instruction pointer value from the SMRAM save state + before it was replaced. +**/ +UINT64 +EFIAPI +SmmCpuFeaturesHookReturnFromSmm ( + IN UINTN CpuIndex, + IN SMRAM_SAVE_STATE_MAP *CpuState, + IN UINT64 NewInstructionPointer32, + IN UINT64 NewInstructionPointer + ) +{ + return 0; +} + +/** + Read an SMM Save State register on the target processor. If this function + returns EFI_UNSUPPORTED, then the caller is responsible for reading the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to read the SMM Save State. The + value must be between 0 and the NumberOfCpus field in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to read. + @param[in] Width The number of bytes to read from the CPU save state. + @param[out] Buffer Upon return, this holds the CPU register value read + from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support reading Register. + +**/ +EFI_STATUS +EFIAPI +SmmCpuFeaturesReadSaveStateRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + OUT VOID *Buffer + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Writes an SMM Save State register on the target processor. If this function + returns EFI_UNSUPPORTED, then the caller is responsible for writing the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to write the SMM Save State. The + value must be between 0 and the NumberOfCpus field in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to write. + @param[in] Width The number of bytes to write to the CPU save state. + @param[in] Buffer Upon entry, this holds the new CPU register value. + + @retval EFI_SUCCESS The register was written to Save State. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support writing Register. +**/ +EFI_STATUS +EFIAPI +SmmCpuFeaturesWriteSaveStateRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + IN CONST VOID *Buffer + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Check to see if an SMM register is supported by a specified CPU. + + @param[in] CpuIndex The index of the CPU to check for SMM register support. + The value must be between 0 and the NumberOfCpus field + in the System Management System Table (SMST). + @param[in] RegName Identifies the SMM register to check for support. + + @retval TRUE The SMM register specified by RegName is supported by the CPU + specified by CpuIndex. + @retval FALSE The SMM register specified by RegName is not supported by the + CPU specified by CpuIndex. +**/ +BOOLEAN +EFIAPI +SmmCpuFeaturesIsSmmRegisterSupported ( + IN UINTN CpuIndex, + IN SMM_REG_NAME RegName + ) +{ + if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) { + return TRUE; + } + + return FALSE; +} diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c index 5498fda38da4..cbf4b495185b 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c @@ -17,49 +17,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "CpuFeaturesLib.h" -/** - This function updates the SMRAM save state on the currently executing CPU - to resume execution at a specific address after an RSM instruction. This - function must evaluate the SMRAM save state to determine the execution mode - the RSM instruction resumes and update the resume execution address with - either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart - flag in the SMRAM save state must always be cleared. This function returns - the value of the instruction pointer from the SMRAM save state that was - replaced. If this function returns 0, then the SMRAM save state was not - modified. - - This function is called during the very first SMI on each CPU after - SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode - to signal that the SMBASE of each CPU has been updated before the default - SMBASE address is used for the first SMI to the next CPU. - - @param[in] CpuIndex The index of the CPU to hook. The value - must be between 0 and the NumberOfCpus - field in the System Management System Table - (SMST). - @param[in] CpuState Pointer to SMRAM Save State Map for the - currently executing CPU. - @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to - 32-bit execution mode from 64-bit SMM. - @param[in] NewInstructionPointer Instruction pointer to use if resuming to - same execution mode as SMM. - - @retval 0 This function did modify the SMRAM save state. - @retval > 0 The original instruction pointer value from the SMRAM save state - before it was replaced. -**/ -UINT64 -EFIAPI -SmmCpuFeaturesHookReturnFromSmm ( - IN UINTN CpuIndex, - IN SMRAM_SAVE_STATE_MAP *CpuState, - IN UINT64 NewInstructionPointer32, - IN UINT64 NewInstructionPointer - ) -{ - return 0; -} - /** Hook point in normal execution mode that allows the one CPU that was elected as monarch during System Management Mode initialization to perform additional @@ -90,91 +47,6 @@ SmmCpuFeaturesRendezvousExit ( { } -/** - Check to see if an SMM register is supported by a specified CPU. - - @param[in] CpuIndex The index of the CPU to check for SMM register support. - The value must be between 0 and the NumberOfCpus field - in the System Management System Table (SMST). - @param[in] RegName Identifies the SMM register to check for support. - - @retval TRUE The SMM register specified by RegName is supported by the CPU - specified by CpuIndex. - @retval FALSE The SMM register specified by RegName is not supported by the - CPU specified by CpuIndex. -**/ -BOOLEAN -EFIAPI -SmmCpuFeaturesIsSmmRegisterSupported ( - IN UINTN CpuIndex, - IN SMM_REG_NAME RegName - ) -{ - if (FeaturePcdGet (PcdSmmFeatureControlEnable) && (RegName == SmmRegFeatureControl)) { - return TRUE; - } - - return FALSE; -} - -/** - Read an SMM Save State register on the target processor. If this function - returns EFI_UNSUPPORTED, then the caller is responsible for reading the - SMM Save Sate register. - - @param[in] CpuIndex The index of the CPU to read the SMM Save State. The - value must be between 0 and the NumberOfCpus field in - the System Management System Table (SMST). - @param[in] Register The SMM Save State register to read. - @param[in] Width The number of bytes to read from the CPU save state. - @param[out] Buffer Upon return, this holds the CPU register value read - from the save state. - - @retval EFI_SUCCESS The register was read from Save State. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_UNSUPPORTED This function does not support reading Register. - -**/ -EFI_STATUS -EFIAPI -SmmCpuFeaturesReadSaveStateRegister ( - IN UINTN CpuIndex, - IN EFI_SMM_SAVE_STATE_REGISTER Register, - IN UINTN Width, - OUT VOID *Buffer - ) -{ - return EFI_UNSUPPORTED; -} - -/** - Writes an SMM Save State register on the target processor. If this function - returns EFI_UNSUPPORTED, then the caller is responsible for writing the - SMM Save Sate register. - - @param[in] CpuIndex The index of the CPU to write the SMM Save State. The - value must be between 0 and the NumberOfCpus field in - the System Management System Table (SMST). - @param[in] Register The SMM Save State register to write. - @param[in] Width The number of bytes to write to the CPU save state. - @param[in] Buffer Upon entry, this holds the new CPU register value. - - @retval EFI_SUCCESS The register was written to Save State. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_UNSUPPORTED This function does not support writing Register. -**/ -EFI_STATUS -EFIAPI -SmmCpuFeaturesWriteSaveStateRegister ( - IN UINTN CpuIndex, - IN EFI_SMM_SAVE_STATE_REGISTER Register, - IN UINTN Width, - IN CONST VOID *Buffer - ) -{ - return EFI_UNSUPPORTED; -} - /** This function is hook point called after the gEfiSmmReadyToLockProtocolGuid notification is completely processed. -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v6 5/6] UefiCpuPkg: Initial implementation of AMD's SmmCpuFeaturesLib 2023-03-25 5:38 [PATCH v6 0/6] Adds AmdSmmCpuFeaturesLib for AMD Family Abdul Lateef Attar ` (3 preceding siblings ...) 2023-03-25 5:38 ` [PATCH v6 4/6] UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code Abdul Lateef Attar @ 2023-03-25 5:38 ` Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 6/6] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family Abdul Lateef Attar 5 siblings, 0 replies; 9+ messages in thread From: Abdul Lateef Attar @ 2023-03-25 5:38 UTC (permalink / raw) To: devel Cc: Abdul Lateef Attar, Paul Grimes, Garrett Kirkendall, Abner Chang, Eric Dong, Ray Ni, Rahul Kumar From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Adds initial defination for AMD's SmmCpuFeaturesLib library implementation. All function's body either empty or just returns value. Its initial skeleton of library implementation. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> --- UefiCpuPkg/UefiCpuPkg.dsc | 8 + .../AmdSmmCpuFeaturesLib.inf | 33 ++ .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c | 345 ++++++++++++++++++ 3 files changed, 386 insertions(+) create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index c9bbff986fbd..5e1060a35b1e 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -178,6 +178,13 @@ [Components.IA32, Components.X64] <LibraryClasses> SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf } + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { + <Defines> + FILE_GUID = B7242C74-BD21-49EE-84B4-07162E8C080D + <LibraryClasses> + SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf + SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf + } UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf @@ -194,6 +201,7 @@ [Components.IA32, Components.X64] UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultReportLib/UnitTestResultReportLibConOut.inf } UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib.inf + UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf [Components.X64] UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHandlerLibUnitTest.inf diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf new file mode 100644 index 000000000000..4c77efc64462 --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf @@ -0,0 +1,33 @@ +## @file +# The CPU specific programming for PiSmmCpuDxeSmm module. +# +# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR> +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SmmCpuFeaturesLib + MODULE_UNI_FILE = SmmCpuFeaturesLib.uni + FILE_GUID = 5849E964-78EC-428E-8CBD-848A7E359134 + MODULE_TYPE = DXE_SMM_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = SmmCpuFeaturesLib + CONSTRUCTOR = SmmCpuFeaturesLibConstructor + +[Sources] + SmmCpuFeaturesLib.c + SmmCpuFeaturesLibCommon.c + AmdSmmCpuFeaturesLib.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + DebugLib diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c new file mode 100644 index 000000000000..c74e1a0c0c5b --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c @@ -0,0 +1,345 @@ +/** @file +Implementation specific to the SmmCpuFeatureLib library instance +for AMD based platforms. + +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR> +Copyright (c) Microsoft Corporation.<BR> +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Library/SmmCpuFeaturesLib.h> +#include <Uefi/UefiBaseType.h> + +/** + Read an SMM Save State register on the target processor. If this function + returns EFI_UNSUPPORTED, then the caller is responsible for reading the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to read the SMM Save State. The + value must be between 0 and the NumberOfCpus field in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to read. + @param[in] Width The number of bytes to read from the CPU save state. + @param[out] Buffer Upon return, this holds the CPU register value read + from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support reading Register. + +**/ +EFI_STATUS +EFIAPI +SmmCpuFeaturesReadSaveStateRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + OUT VOID *Buffer + ) +{ + return EFI_SUCCESS; +} + +/** + Writes an SMM Save State register on the target processor. If this function + returns EFI_UNSUPPORTED, then the caller is responsible for writing the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to write the SMM Save State. The + value must be between 0 and the NumberOfCpus field in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to write. + @param[in] Width The number of bytes to write to the CPU save state. + @param[in] Buffer Upon entry, this holds the new CPU register value. + + @retval EFI_SUCCESS The register was written to Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support writing Register. +**/ +EFI_STATUS +EFIAPI +SmmCpuFeaturesWriteSaveStateRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + IN CONST VOID *Buffer + ) +{ + return EFI_SUCCESS; +} + +/** + Performs library initialization. + + This initialization function contains common functionality shared betwen all + library instance constructors. + +**/ +VOID +CpuFeaturesLibInitialization ( + VOID + ) +{ +} + +/** + Called during the very first SMI into System Management Mode to initialize + CPU features, including SMBASE, for the currently executing CPU. Since this + is the first SMI, the SMRAM Save State Map is at the default address of + AMD_SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing + CPU is specified by CpuIndex and CpuIndex can be used to access information + about the currently executing CPU in the ProcessorInfo array and the + HotPlugCpuData data structure. + + @param[in] CpuIndex The index of the CPU to initialize. The value + must be between 0 and the NumberOfCpus field in + the System Management System Table (SMST). + @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU that + was elected as monarch during System Management + Mode initialization. + FALSE if the CpuIndex is not the index of the CPU + that was elected as monarch during System + Management Mode initialization. + @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMATION + structures. ProcessorInfo[CpuIndex] contains the + information for the currently executing CPU. + @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure that + contains the ApidId and SmBase arrays. +**/ +VOID +EFIAPI +SmmCpuFeaturesInitializeProcessor ( + IN UINTN CpuIndex, + IN BOOLEAN IsMonarch, + IN EFI_PROCESSOR_INFORMATION *ProcessorInfo, + IN CPU_HOT_PLUG_DATA *CpuHotPlugData + ) +{ +} + +/** + This function updates the SMRAM save state on the currently executing CPU + to resume execution at a specific address after an RSM instruction. This + function must evaluate the SMRAM save state to determine the execution mode + the RSM instruction resumes and update the resume execution address with + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart + flag in the SMRAM save state must always be cleared. This function returns + the value of the instruction pointer from the SMRAM save state that was + replaced. If this function returns 0, then the SMRAM save state was not + modified. + + This function is called during the very first SMI on each CPU after + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode + to signal that the SMBASE of each CPU has been updated before the default + SMBASE address is used for the first SMI to the next CPU. + + @param[in] CpuIndex The index of the CPU to hook. The value + must be between 0 and the NumberOfCpus + field in the System Management System Table + (SMST). + @param[in] CpuState Pointer to SMRAM Save State Map for the + currently executing CPU. + @param[in] NewInstructionPointer32 Instruction pointer to use if resuming to + 32-bit execution mode from 64-bit SMM. + @param[in] NewInstructionPointer Instruction pointer to use if resuming to + same execution mode as SMM. + + @retval 0 This function did modify the SMRAM save state. + @retval > 0 The original instruction pointer value from the SMRAM save state + before it was replaced. +**/ +UINT64 +EFIAPI +SmmCpuFeaturesHookReturnFromSmm ( + IN UINTN CpuIndex, + IN SMRAM_SAVE_STATE_MAP *CpuState, + IN UINT64 NewInstructionPointer32, + IN UINT64 NewInstructionPointer + ) +{ + return 0; +} + +/** + Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is + returned, then a custom SMI handler is not provided by this library, + and the default SMI handler must be used. + + @retval 0 Use the default SMI handler. + @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler() + The caller is required to allocate enough SMRAM for each CPU to + support the size of the custom SMI handler. +**/ +UINTN +EFIAPI +SmmCpuFeaturesGetSmiHandlerSize ( + VOID + ) +{ + return 0; +} + +/** + Install a custom SMI handler for the CPU specified by CpuIndex. This function + is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater + than zero and is called by the CPU that was elected as monarch during System + Management Mode initialization. + + @param[in] CpuIndex The index of the CPU to install the custom SMI handler. + The value must be between 0 and the NumberOfCpus field + in the System Management System Table (SMST). + @param[in] SmBase The SMBASE address for the CPU specified by CpuIndex. + @param[in] SmiStack The stack to use when an SMI is processed by the + the CPU specified by CpuIndex. + @param[in] StackSize The size, in bytes, if the stack used when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] GdtBase The base address of the GDT to use when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] IdtBase The base address of the IDT to use when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] Cr3 The base address of the page tables to use when an SMI + is processed by the CPU specified by CpuIndex. +**/ +VOID +EFIAPI +SmmCpuFeaturesInstallSmiHandler ( + IN UINTN CpuIndex, + IN UINT32 SmBase, + IN VOID *SmiStack, + IN UINTN StackSize, + IN UINTN GdtBase, + IN UINTN GdtSize, + IN UINTN IdtBase, + IN UINTN IdtSize, + IN UINT32 Cr3 + ) +{ +} + +/** + Determines if MTRR registers must be configured to set SMRAM cache-ability + when executing in System Management Mode. + + @retval TRUE MTRR registers must be configured to set SMRAM cache-ability. + @retval FALSE MTRR registers do not need to be configured to set SMRAM + cache-ability. +**/ +BOOLEAN +EFIAPI +SmmCpuFeaturesNeedConfigureMtrrs ( + VOID + ) +{ + return FALSE; +} + +/** + Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs() + returns TRUE. +**/ +VOID +EFIAPI +SmmCpuFeaturesDisableSmrr ( + VOID + ) +{ +} + +/** + Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs() + returns TRUE. +**/ +VOID +EFIAPI +SmmCpuFeaturesReenableSmrr ( + VOID + ) +{ +} + +/** + Processor specific hook point each time a CPU enters System Management Mode. + + @param[in] CpuIndex The index of the CPU that has entered SMM. The value + must be between 0 and the NumberOfCpus field in the + System Management System Table (SMST). +**/ +VOID +EFIAPI +SmmCpuFeaturesRendezvousEntry ( + IN UINTN CpuIndex + ) +{ +} + +/** + Returns the current value of the SMM register for the specified CPU. + If the SMM register is not supported, then 0 is returned. + + @param[in] CpuIndex The index of the CPU to read the SMM register. The + value must be between 0 and the NumberOfCpus field in + the System Management System Table (SMST). + @param[in] RegName Identifies the SMM register to read. + + @return The value of the SMM register specified by RegName from the CPU + specified by CpuIndex. +**/ +UINT64 +EFIAPI +SmmCpuFeaturesGetSmmRegister ( + IN UINTN CpuIndex, + IN SMM_REG_NAME RegName + ) +{ + return 0; +} + +/** + Sets the value of an SMM register on a specified CPU. + If the SMM register is not supported, then no action is performed. + + @param[in] CpuIndex The index of the CPU to write the SMM register. The + value must be between 0 and the NumberOfCpus field in + the System Management System Table (SMST). + @param[in] RegName Identifies the SMM register to write. + registers are read-only. + @param[in] Value The value to write to the SMM register. +**/ +VOID +EFIAPI +SmmCpuFeaturesSetSmmRegister ( + IN UINTN CpuIndex, + IN SMM_REG_NAME RegName, + IN UINT64 Value + ) +{ +} + +/** + Check to see if an SMM register is supported by a specified CPU. + + @param[in] CpuIndex The index of the CPU to check for SMM register support. + The value must be between 0 and the NumberOfCpus field + in the System Management System Table (SMST). + @param[in] RegName Identifies the SMM register to check for support. + + @retval TRUE The SMM register specified by RegName is supported by the CPU + specified by CpuIndex. + @retval FALSE The SMM register specified by RegName is not supported by the + CPU specified by CpuIndex. +**/ +BOOLEAN +EFIAPI +SmmCpuFeaturesIsSmmRegisterSupported ( + IN UINTN CpuIndex, + IN SMM_REG_NAME RegName + ) +{ + return FALSE; +} -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v6 6/6] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family 2023-03-25 5:38 [PATCH v6 0/6] Adds AmdSmmCpuFeaturesLib for AMD Family Abdul Lateef Attar ` (4 preceding siblings ...) 2023-03-25 5:38 ` [PATCH v6 5/6] UefiCpuPkg: Initial implementation of AMD's SmmCpuFeaturesLib Abdul Lateef Attar @ 2023-03-25 5:38 ` Abdul Lateef Attar 2023-03-31 7:59 ` [edk2-devel] " Ni, Ray 5 siblings, 1 reply; 9+ messages in thread From: Abdul Lateef Attar @ 2023-03-25 5:38 UTC (permalink / raw) To: devel Cc: Abdul Lateef Attar, Paul Grimes, Garrett Kirkendall, Abner Chang, Eric Dong, Ray Ni, Rahul Kumar, Abdul Lateef Attar From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 Implements interfaces to read and write save state registers of AMD's processor family. Initializes processor SMMADDR and MASK depends on PcdSmrrEnable flag. Program or corrects the IP once control returns from SMM. Cc: Paul Grimes <paul.grimes@amd.com> Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> Reviewed-by: Abner Chang <abner.chang@amd.com> --- .../AmdSmmCpuFeaturesLib.inf | 6 + .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c | 106 +++++++++++++++++- 2 files changed, 109 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf index 4c77efc64462..9d5b8c2e972d 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf @@ -31,3 +31,9 @@ [LibraryClasses] PcdLib MemoryAllocationLib DebugLib + SmmSmramSaveStateLib + +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable ## CONSUMES + diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c index c74e1a0c0c5b..af45be3e265a 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c @@ -11,6 +11,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/SmmCpuFeaturesLib.h> #include <Uefi/UefiBaseType.h> +#include <Register/Amd/SmramSaveStateMap.h> +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/SmmSmramSaveStateLib.h> + +// EFER register LMA bit +#define LMA BIT10 + +// Machine Specific Registers (MSRs) +#define SMMADDR_ADDRESS 0xC0010112ul +#define SMMMASK_ADDRESS 0xC0010113ul +#define EFER_ADDRESS 0XC0000080ul + +// The mode of the CPU at the time an SMI occurs +STATIC UINT8 mSmmSaveStateRegisterLma; /** Read an SMM Save State register on the target processor. If this function @@ -39,7 +54,7 @@ SmmCpuFeaturesReadSaveStateRegister ( OUT VOID *Buffer ) { - return EFI_SUCCESS; + return SmramSaveStateReadRegister (CpuIndex, Register, Width, Buffer); } /** @@ -67,7 +82,7 @@ SmmCpuFeaturesWriteSaveStateRegister ( IN CONST VOID *Buffer ) { - return EFI_SUCCESS; + return SmramSaveStateWriteRegister (CpuIndex, Register, Width, Buffer); } /** @@ -82,6 +97,13 @@ CpuFeaturesLibInitialization ( VOID ) { + UINT32 LMAValue; + + LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; + mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; + if (LMAValue) { + mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; + } } /** @@ -117,6 +139,52 @@ SmmCpuFeaturesInitializeProcessor ( IN CPU_HOT_PLUG_DATA *CpuHotPlugData ) { + AMD_SMRAM_SAVE_STATE_MAP *CpuState; + UINT32 LMAValue; + + // + // Configure SMBASE. + // + CpuState = (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + + // Re-initialize the value of mSmmSaveStateRegisterLma flag which might have been changed in PiCpuSmmDxeSmm Driver + // Entry point, to make sure correct value on AMD platform is assigned to be used by SmmCpuFeaturesLib. + LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; + mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; + if (LMAValue) { + mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; + } + + // + // If SMRR is supported, then program SMRR base/mask MSRs. + // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI. + // The code that initializes SMM environment is running in normal mode + // from SMRAM region. If SMRR is enabled here, then the SMRAM region + // is protected and the normal mode code execution will fail. + // + if (FeaturePcdGet (PcdSmrrEnable)) { + // + // SMRR size cannot be less than 4-KBytes + // SMRR size must be of length 2^n + // SMRR base alignment cannot be less than SMRR length + // + if ((CpuHotPlugData->SmrrSize < SIZE_4KB) || + (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) || + ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) + { + // + // Print message and halt if CPU is Monarch + // + if (IsMonarch) { + DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size requirement!\n")); + CpuDeadLoop (); + } + } else { + AsmWriteMsr64 (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase); + AsmWriteMsr64 (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData->SmrrSize - 1)) | 0x6600)); + } + } } /** @@ -159,7 +227,39 @@ SmmCpuFeaturesHookReturnFromSmm ( IN UINT64 NewInstructionPointer ) { - return 0; + UINT64 OriginalInstructionPointer; + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState; + + AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; + + if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { + OriginalInstructionPointer = (UINT64)AmdCpuState->x86._EIP; + AmdCpuState->x86._EIP = (UINT32)NewInstructionPointer; + // + // Clear the auto HALT restart flag so the RSM instruction returns + // program control to the instruction following the HLT instruction. + // + if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != 0) { + AmdCpuState->x86.AutoHALTRestart &= ~BIT0; + } + } else { + OriginalInstructionPointer = AmdCpuState->x64._RIP; + if ((AmdCpuState->x64.EFER & LMA) == 0) { + AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer32; + } else { + AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer; + } + + // + // Clear the auto HALT restart flag so the RSM instruction returns + // program control to the instruction following the HLT instruction. + // + if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) { + AmdCpuState->x64.AutoHALTRestart &= ~BIT0; + } + } + + return OriginalInstructionPointer; } /** -- 2.25.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [edk2-devel] [PATCH v6 6/6] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family 2023-03-25 5:38 ` [PATCH v6 6/6] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family Abdul Lateef Attar @ 2023-03-31 7:59 ` Ni, Ray 2023-04-07 6:09 ` Attar, AbdulLateef (Abdul Lateef) 0 siblings, 1 reply; 9+ messages in thread From: Ni, Ray @ 2023-03-31 7:59 UTC (permalink / raw) To: devel@edk2.groups.io, abdattar@amd.com Cc: Abdul Lateef Attar, Paul Grimes, Garrett Kirkendall, Abner Chang, Dong, Eric, Kumar, Rahul R It's a bit wired that AMD version of SmmCpuFeaturesLib calls AMD version of SmmSmramSaveStateLib. The question naturally becomes: why not integrate the two lib implementations together to avoid creating the SmmSmramSaveStateLib library class? Because I cannot imagine AmdSmmCpuFeaturesLib calls to IntelSmmSmramSaveStateLib. But I like the idea of separating the SMM save state access logic out of the SmmCpuFeaturesLib. Do you think CpuSmm driver calling the SmmSmramSaveStateLib is better? > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Abdul > Lateef Attar via groups.io > Sent: Saturday, March 25, 2023 1:39 PM > To: devel@edk2.groups.io > Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>; Paul Grimes > <paul.grimes@amd.com>; Garrett Kirkendall <garrett.kirkendall@amd.com>; > Abner Chang <abner.chang@amd.com>; Dong, Eric <eric.dong@intel.com>; > Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; > Abdul Lateef Attar <abdattar@amd.com> > Subject: [edk2-devel] [PATCH v6 6/6] UefiCpuPkg: Implements > SmmCpuFeaturesLib for AMD Family > > From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 > > Implements interfaces to read and write save state > registers of AMD's processor family. > Initializes processor SMMADDR and MASK depends > on PcdSmrrEnable flag. > Program or corrects the IP once control returns from SMM. > > Cc: Paul Grimes <paul.grimes@amd.com> > Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> > Cc: Abner Chang <abner.chang@amd.com> > Cc: Eric Dong <eric.dong@intel.com> > Cc: Ray Ni <ray.ni@intel.com> > Cc: Rahul Kumar <rahul1.kumar@intel.com> > Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> > Reviewed-by: Abner Chang <abner.chang@amd.com> > --- > .../AmdSmmCpuFeaturesLib.inf | 6 + > .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c | 106 > +++++++++++++++++- > 2 files changed, 109 insertions(+), 3 deletions(-) > > diff --git > a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > index 4c77efc64462..9d5b8c2e972d 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > +++ > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > @@ -31,3 +31,9 @@ [LibraryClasses] > PcdLib > MemoryAllocationLib > DebugLib > + SmmSmramSaveStateLib > + > +[FeaturePcd] > + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable ## CONSUMES > + gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable ## > CONSUMES > + > diff --git > a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c > index c74e1a0c0c5b..af45be3e265a 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c > @@ -11,6 +11,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #include <Library/SmmCpuFeaturesLib.h> > #include <Uefi/UefiBaseType.h> > +#include <Register/Amd/SmramSaveStateMap.h> > +#include <Library/BaseLib.h> > +#include <Library/DebugLib.h> > +#include <Library/SmmSmramSaveStateLib.h> > + > +// EFER register LMA bit > +#define LMA BIT10 > + > +// Machine Specific Registers (MSRs) > +#define SMMADDR_ADDRESS 0xC0010112ul > +#define SMMMASK_ADDRESS 0xC0010113ul > +#define EFER_ADDRESS 0XC0000080ul > + > +// The mode of the CPU at the time an SMI occurs > +STATIC UINT8 mSmmSaveStateRegisterLma; > > /** > Read an SMM Save State register on the target processor. If this function > @@ -39,7 +54,7 @@ SmmCpuFeaturesReadSaveStateRegister ( > OUT VOID *Buffer > ) > { > - return EFI_SUCCESS; > + return SmramSaveStateReadRegister (CpuIndex, Register, Width, Buffer); > } > > /** > @@ -67,7 +82,7 @@ SmmCpuFeaturesWriteSaveStateRegister ( > IN CONST VOID *Buffer > ) > { > - return EFI_SUCCESS; > + return SmramSaveStateWriteRegister (CpuIndex, Register, Width, Buffer); > } > > /** > @@ -82,6 +97,13 @@ CpuFeaturesLibInitialization ( > VOID > ) > { > + UINT32 LMAValue; > + > + LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; > + mSmmSaveStateRegisterLma = > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; > + if (LMAValue) { > + mSmmSaveStateRegisterLma = > EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; > + } > } > > /** > @@ -117,6 +139,52 @@ SmmCpuFeaturesInitializeProcessor ( > IN CPU_HOT_PLUG_DATA *CpuHotPlugData > ) > { > + AMD_SMRAM_SAVE_STATE_MAP *CpuState; > + UINT32 LMAValue; > + > + // > + // Configure SMBASE. > + // > + CpuState = (AMD_SMRAM_SAVE_STATE_MAP > *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); > + CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex]; > + > + // Re-initialize the value of mSmmSaveStateRegisterLma flag which might > have been changed in PiCpuSmmDxeSmm Driver > + // Entry point, to make sure correct value on AMD platform is assigned to > be used by SmmCpuFeaturesLib. > + LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; > + mSmmSaveStateRegisterLma = > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; > + if (LMAValue) { > + mSmmSaveStateRegisterLma = > EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; > + } > + > + // > + // If SMRR is supported, then program SMRR base/mask MSRs. > + // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first > normal SMI. > + // The code that initializes SMM environment is running in normal mode > + // from SMRAM region. If SMRR is enabled here, then the SMRAM region > + // is protected and the normal mode code execution will fail. > + // > + if (FeaturePcdGet (PcdSmrrEnable)) { > + // > + // SMRR size cannot be less than 4-KBytes > + // SMRR size must be of length 2^n > + // SMRR base alignment cannot be less than SMRR length > + // > + if ((CpuHotPlugData->SmrrSize < SIZE_4KB) || > + (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData- > >SmrrSize)) || > + ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != > CpuHotPlugData->SmrrBase)) > + { > + // > + // Print message and halt if CPU is Monarch > + // > + if (IsMonarch) { > + DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet > alignment/size requirement!\n")); > + CpuDeadLoop (); > + } > + } else { > + AsmWriteMsr64 (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase); > + AsmWriteMsr64 (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData- > >SmrrSize - 1)) | 0x6600)); > + } > + } > } > > /** > @@ -159,7 +227,39 @@ SmmCpuFeaturesHookReturnFromSmm ( > IN UINT64 NewInstructionPointer > ) > { > - return 0; > + UINT64 OriginalInstructionPointer; > + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState; > + > + AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; > + > + if (mSmmSaveStateRegisterLma == > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { > + OriginalInstructionPointer = (UINT64)AmdCpuState->x86._EIP; > + AmdCpuState->x86._EIP = (UINT32)NewInstructionPointer; > + // > + // Clear the auto HALT restart flag so the RSM instruction returns > + // program control to the instruction following the HLT instruction. > + // > + if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != 0) { > + AmdCpuState->x86.AutoHALTRestart &= ~BIT0; > + } > + } else { > + OriginalInstructionPointer = AmdCpuState->x64._RIP; > + if ((AmdCpuState->x64.EFER & LMA) == 0) { > + AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer32; > + } else { > + AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer; > + } > + > + // > + // Clear the auto HALT restart flag so the RSM instruction returns > + // program control to the instruction following the HLT instruction. > + // > + if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) { > + AmdCpuState->x64.AutoHALTRestart &= ~BIT0; > + } > + } > + > + return OriginalInstructionPointer; > } > > /** > -- > 2.25.1 > > > > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [edk2-devel] [PATCH v6 6/6] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family 2023-03-31 7:59 ` [edk2-devel] " Ni, Ray @ 2023-04-07 6:09 ` Attar, AbdulLateef (Abdul Lateef) 0 siblings, 0 replies; 9+ messages in thread From: Attar, AbdulLateef (Abdul Lateef) @ 2023-04-07 6:09 UTC (permalink / raw) To: Ni, Ray, devel@edk2.groups.io Cc: Grimes, Paul, Kirkendall, Garrett, Chang, Abner, Dong, Eric, Kumar, Rahul R [AMD Official Use Only - General] Hi Ray, Please see inline. Thanks AbduL -----Original Message----- From: Ni, Ray <ray.ni@intel.com> Sent: 31 March 2023 13:29 To: devel@edk2.groups.io; Attar, AbdulLateef (Abdul Lateef) <AbdulLateef.Attar@amd.com> Cc: Attar, AbdulLateef (Abdul Lateef) <AbdulLateef.Attar@amd.com>; Grimes, Paul <Paul.Grimes@amd.com>; Kirkendall, Garrett <Garrett.Kirkendall@amd.com>; Chang, Abner <Abner.Chang@amd.com>; Dong, Eric <eric.dong@intel.com>; Kumar, Rahul R <rahul.r.kumar@intel.com> Subject: RE: [edk2-devel] [PATCH v6 6/6] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding. It's a bit wired that AMD version of SmmCpuFeaturesLib calls AMD version of SmmSmramSaveStateLib. The question naturally becomes: why not integrate the two lib implementations together to avoid creating the SmmSmramSaveStateLib library class? Because I cannot imagine AmdSmmCpuFeaturesLib calls to IntelSmmSmramSaveStateLib. [Abdul] Initial version of this patch series has combined implementation of SmmSmramSaveStateLib and AmdSmmCpuFeaturesLib, but reviewers (Abner) suggested to separate the save state library; So that we can implement generic library for both AMD and Intel. But I like the idea of separating the SMM save state access logic out of the SmmCpuFeaturesLib. Do you think CpuSmm driver calling the SmmSmramSaveStateLib is better? [Abdul] I'll make the changes and submit the patch for the same. > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Abdul > Lateef Attar via groups.io > Sent: Saturday, March 25, 2023 1:39 PM > To: devel@edk2.groups.io > Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>; Paul Grimes > <paul.grimes@amd.com>; Garrett Kirkendall > <garrett.kirkendall@amd.com>; Abner Chang <abner.chang@amd.com>; Dong, > Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R > <rahul.r.kumar@intel.com>; Abdul Lateef Attar <abdattar@amd.com> > Subject: [edk2-devel] [PATCH v6 6/6] UefiCpuPkg: Implements > SmmCpuFeaturesLib for AMD Family > > From: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4182 > > Implements interfaces to read and write save state registers of AMD's > processor family. > Initializes processor SMMADDR and MASK depends on PcdSmrrEnable flag. > Program or corrects the IP once control returns from SMM. > > Cc: Paul Grimes <paul.grimes@amd.com> > Cc: Garrett Kirkendall <garrett.kirkendall@amd.com> > Cc: Abner Chang <abner.chang@amd.com> > Cc: Eric Dong <eric.dong@intel.com> > Cc: Ray Ni <ray.ni@intel.com> > Cc: Rahul Kumar <rahul1.kumar@intel.com> > Signed-off-by: Abdul Lateef Attar <abdattar@amd.com> > Reviewed-by: Abner Chang <abner.chang@amd.com> > --- > .../AmdSmmCpuFeaturesLib.inf | 6 + > .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c | 106 > +++++++++++++++++- > 2 files changed, 109 insertions(+), 3 deletions(-) > > diff --git > a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > index 4c77efc64462..9d5b8c2e972d 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > +++ > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf > @@ -31,3 +31,9 @@ [LibraryClasses] > PcdLib > MemoryAllocationLib > DebugLib > + SmmSmramSaveStateLib > + > +[FeaturePcd] > + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable ## CONSUMES > + gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable ## > CONSUMES > + > diff --git > a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c > index c74e1a0c0c5b..af45be3e265a 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c > @@ -11,6 +11,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #include <Library/SmmCpuFeaturesLib.h> #include > <Uefi/UefiBaseType.h> > +#include <Register/Amd/SmramSaveStateMap.h> > +#include <Library/BaseLib.h> > +#include <Library/DebugLib.h> > +#include <Library/SmmSmramSaveStateLib.h> > + > +// EFER register LMA bit > +#define LMA BIT10 > + > +// Machine Specific Registers (MSRs) > +#define SMMADDR_ADDRESS 0xC0010112ul #define SMMMASK_ADDRESS > +0xC0010113ul > +#define EFER_ADDRESS 0XC0000080ul > + > +// The mode of the CPU at the time an SMI occurs STATIC UINT8 > +mSmmSaveStateRegisterLma; > > /** > Read an SMM Save State register on the target processor. If this > function @@ -39,7 +54,7 @@ SmmCpuFeaturesReadSaveStateRegister ( > OUT VOID *Buffer > ) > { > - return EFI_SUCCESS; > + return SmramSaveStateReadRegister (CpuIndex, Register, Width, > + Buffer); > } > > /** > @@ -67,7 +82,7 @@ SmmCpuFeaturesWriteSaveStateRegister ( > IN CONST VOID *Buffer > ) > { > - return EFI_SUCCESS; > + return SmramSaveStateWriteRegister (CpuIndex, Register, Width, > + Buffer); > } > > /** > @@ -82,6 +97,13 @@ CpuFeaturesLibInitialization ( > VOID > ) > { > + UINT32 LMAValue; > + > + LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; > + mSmmSaveStateRegisterLma = > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; > + if (LMAValue) { > + mSmmSaveStateRegisterLma = > EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; > + } > } > > /** > @@ -117,6 +139,52 @@ SmmCpuFeaturesInitializeProcessor ( > IN CPU_HOT_PLUG_DATA *CpuHotPlugData > ) > { > + AMD_SMRAM_SAVE_STATE_MAP *CpuState; > + UINT32 LMAValue; > + > + // > + // Configure SMBASE. > + // > + CpuState = (AMD_SMRAM_SAVE_STATE_MAP > *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); > + CpuState->x64.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex]; > + > + // Re-initialize the value of mSmmSaveStateRegisterLma flag which > + might > have been changed in PiCpuSmmDxeSmm Driver > + // Entry point, to make sure correct value on AMD platform is > + assigned to > be used by SmmCpuFeaturesLib. > + LMAValue = (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; > + mSmmSaveStateRegisterLma = > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; > + if (LMAValue) { > + mSmmSaveStateRegisterLma = > EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; > + } > + > + // > + // If SMRR is supported, then program SMRR base/mask MSRs. > + // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first > normal SMI. > + // The code that initializes SMM environment is running in normal > + mode // from SMRAM region. If SMRR is enabled here, then the SMRAM > + region // is protected and the normal mode code execution will fail. > + // > + if (FeaturePcdGet (PcdSmrrEnable)) { > + // > + // SMRR size cannot be less than 4-KBytes > + // SMRR size must be of length 2^n > + // SMRR base alignment cannot be less than SMRR length > + // > + if ((CpuHotPlugData->SmrrSize < SIZE_4KB) || > + (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData- > >SmrrSize)) || > + ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) > + != > CpuHotPlugData->SmrrBase)) > + { > + // > + // Print message and halt if CPU is Monarch > + // > + if (IsMonarch) { > + DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet > alignment/size requirement!\n")); > + CpuDeadLoop (); > + } > + } else { > + AsmWriteMsr64 (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase); > + AsmWriteMsr64 (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData- > >SmrrSize - 1)) | 0x6600)); > + } > + } > } > > /** > @@ -159,7 +227,39 @@ SmmCpuFeaturesHookReturnFromSmm ( > IN UINT64 NewInstructionPointer > ) > { > - return 0; > + UINT64 OriginalInstructionPointer; > + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState; > + > + AmdCpuState = (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; > + > + if (mSmmSaveStateRegisterLma == > EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { > + OriginalInstructionPointer = (UINT64)AmdCpuState->x86._EIP; > + AmdCpuState->x86._EIP = (UINT32)NewInstructionPointer; > + // > + // Clear the auto HALT restart flag so the RSM instruction returns > + // program control to the instruction following the HLT instruction. > + // > + if ((AmdCpuState->x86.AutoHALTRestart & BIT0) != 0) { > + AmdCpuState->x86.AutoHALTRestart &= ~BIT0; > + } > + } else { > + OriginalInstructionPointer = AmdCpuState->x64._RIP; > + if ((AmdCpuState->x64.EFER & LMA) == 0) { > + AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer32; > + } else { > + AmdCpuState->x64._RIP = (UINT32)NewInstructionPointer; > + } > + > + // > + // Clear the auto HALT restart flag so the RSM instruction returns > + // program control to the instruction following the HLT instruction. > + // > + if ((AmdCpuState->x64.AutoHALTRestart & BIT0) != 0) { > + AmdCpuState->x64.AutoHALTRestart &= ~BIT0; > + } > + } > + > + return OriginalInstructionPointer; > } > > /** > -- > 2.25.1 > > > > > ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-04-07 6:09 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-03-25 5:38 [PATCH v6 0/6] Adds AmdSmmCpuFeaturesLib for AMD Family Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 1/6] MdePkg: Adds AMD SMRAM save state map Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 2/6] UefiCpuPkg: Adds SmmSmramSaveStateLib library class Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 3/6] UefiCpuPkg: Implements " Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 4/6] UefiCpuPkg/SmmCpuFeaturesLib: Restructure arch-dependent code Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 5/6] UefiCpuPkg: Initial implementation of AMD's SmmCpuFeaturesLib Abdul Lateef Attar 2023-03-25 5:38 ` [PATCH v6 6/6] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family Abdul Lateef Attar 2023-03-31 7:59 ` [edk2-devel] " Ni, Ray 2023-04-07 6:09 ` Attar, AbdulLateef (Abdul Lateef)
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