From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 622991A1E69 for ; Tue, 6 Sep 2016 10:27:33 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP; 06 Sep 2016 10:27:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,292,1470726000"; d="scan'208";a="165064033" Received: from orsmsx106.amr.corp.intel.com ([10.22.225.133]) by fmsmga004.fm.intel.com with ESMTP; 06 Sep 2016 10:27:32 -0700 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.118]) by ORSMSX106.amr.corp.intel.com ([169.254.1.199]) with mapi id 14.03.0248.002; Tue, 6 Sep 2016 10:27:32 -0700 From: "Mudusuru, Giri P" To: "Fan, Jeff" , "edk2-devel@lists.01.org" CC: "Kinney, Michael D" , "Tian, Feng" Thread-Topic: [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment Thread-Index: AQHSCDNj+oPGH5CJcEewofp3FzYchqBstyzQ Date: Tue, 6 Sep 2016 17:27:32 +0000 Message-ID: <4666AEFED60F8E4198B42BB01DCEABDF76ECF2A7@ORSMSX113.amr.corp.intel.com> References: <20160906113852.11408-1-jeff.fan@intel.com> <20160906113852.11408-21-jeff.fan@intel.com> In-Reply-To: <20160906113852.11408-21-jeff.fan@intel.com> Accept-Language: en-US, hi-IN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Subject: Re: [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Sep 2016 17:27:33 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks Jeff for adding comments to refer the SDM naming. Reviewed series of patches. Reviewed-by: Giri P Mudusuru =20 > -----Original Message----- > From: Fan, Jeff > Sent: Tuesday, September 6, 2016 4:39 AM > To: edk2-devel@lists.01.org > Cc: Kinney, Michael D ; Tian, Feng > ; Mudusuru, Giri P > Subject: [Patch 20/20] UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SD= M > in comment >=20 > Cc: Michael Kinney > Cc: Feng Tian > Cc: Giri P Mudusuru > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jeff Fan > --- > UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 51 > ++++++++++++++++++++++++++++ > 1 file changed, 51 insertions(+) >=20 > diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h > b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h > index 6695b69..75f2dce 100644 > --- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h > +++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h > @@ -41,6 +41,7 @@ >=20 > Msr.Uint64 =3D AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT); > @endcode > + @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM. > **/ > #define MSR_XEON_PHI_SMI_COUNT 0x00000034 >=20 > @@ -85,6 +86,7 @@ typedef union { > Msr.Uint64 =3D AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO); > AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64); > @endcode > + @note MSR_XEON_PHI_PLATFORM_INFO is defined as > MSR_PLATFORM_INFO in SDM. > **/ > #define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE >=20 > @@ -151,6 +153,7 @@ typedef union { > Msr.Uint64 =3D AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL); > AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64); > @endcode > + @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as > MSR_PKG_CST_CONFIG_CONTROL in SDM. > **/ > #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2 >=20 > @@ -208,6 +211,7 @@ typedef union { > Msr.Uint64 =3D AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE); > AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64); > @endcode > + @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as > MSR_PMG_IO_CAPTURE_BASE in SDM. > **/ > #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4 >=20 > @@ -261,6 +265,7 @@ typedef union { > Msr.Uint64 =3D AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG); > AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64); > @endcode > + @note MSR_XEON_PHI_FEATURE_CONFIG is defined as > MSR_FEATURE_CONFIG in SDM. > **/ > #define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C >=20 > @@ -313,6 +318,7 @@ typedef union { > Msr.Uint64 =3D AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE); > AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64); > @endcode > + @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as > IA32_MISC_ENABLE in SDM. > **/ > #define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0 >=20 > @@ -402,6 +408,7 @@ typedef union { > Msr.Uint64 =3D AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET); > AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64); > @endcode > + @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as > MSR_TEMPERATURE_TARGET in SDM. > **/ > #define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2 >=20 > @@ -450,6 +457,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0); > AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr); > @endcode > + @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 > in SDM. > **/ > #define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6 >=20 > @@ -468,6 +476,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1); > AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr); > @endcode > + @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 > in SDM. > **/ > #define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7 >=20 > @@ -488,6 +497,7 @@ typedef union { > Msr.Uint64 =3D AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT); > AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64); > @endcode > + @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as > MSR_TURBO_RATIO_LIMIT in SDM. > **/ > #define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD >=20 > @@ -612,6 +622,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT); > AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr); > @endcode > + @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM. > **/ > #define MSR_XEON_PHI_LBR_SELECT 0x000001C8 >=20 > @@ -630,6 +641,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS); > AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr); > @endcode > + @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as > MSR_LASTBRANCH_TOS in SDM. > **/ > #define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9 >=20 > @@ -647,6 +659,7 @@ typedef union { >=20 > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP); > @endcode > + @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in > SDM. > **/ > #define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD >=20 > @@ -664,6 +677,7 @@ typedef union { >=20 > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP); > @endcode > + @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. > **/ > #define MSR_XEON_PHI_LER_TO_LIP 0x000001DE >=20 > @@ -682,6 +696,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS); > AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr); > @endcode > + @note MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS is defined as > IA32_PERF_GLOBAL_STAUS in SDM. > **/ > #define MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS 0x0000038E >=20 > @@ -700,6 +715,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE); > AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr); > @endcode > + @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in > SDM. > **/ > #define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1 >=20 > @@ -720,6 +736,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY); > AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr); > @endcode > + @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as > MSR_PKG_C3_RESIDENCY in SDM. > **/ > #define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8 >=20 > @@ -738,6 +755,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY); > AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr); > @endcode > + @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as > MSR_PKG_C6_RESIDENCY in SDM. > **/ > #define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9 >=20 > @@ -756,6 +774,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY); > AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr); > @endcode > + @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as > MSR_PKG_C7_RESIDENCY in SDM. > **/ > #define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA >=20 > @@ -776,6 +795,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY); > AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr); > @endcode > + @note MSR_XEON_PHI_MC0_RESIDENCY is defined as > MSR_MC0_RESIDENCY in SDM. > **/ > #define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC >=20 > @@ -794,6 +814,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY); > AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr); > @endcode > + @note MSR_XEON_PHI_MC6_RESIDENCY is defined as > MSR_MC6_RESIDENCY in SDM. > **/ > #define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD >=20 > @@ -814,6 +835,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY); > AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr); > @endcode > + @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as > MSR_CORE_C6_RESIDENCY in SDM. > **/ > #define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF >=20 > @@ -832,6 +854,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_MC3_CTL); > AsmWriteMsr64 (MSR_XEON_PHI_MC3_CTL, Msr); > @endcode > + @note MSR_XEON_PHI_MC3_CTL is defined as MSR_MC3_CTL in SDM. > **/ > #define MSR_XEON_PHI_MC3_CTL 0x0000040C >=20 > @@ -850,6 +873,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_MC3_STATUS); > AsmWriteMsr64 (MSR_XEON_PHI_MC3_STATUS, Msr); > @endcode > + @note MSR_XEON_PHI_MC3_STATUS is defined as MSR_MC3_STATUS in > SDM. > **/ > #define MSR_XEON_PHI_MC3_STATUS 0x0000040D >=20 > @@ -868,6 +892,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_MC3_ADDR); > AsmWriteMsr64 (MSR_XEON_PHI_MC3_ADDR, Msr); > @endcode > + @note MSR_XEON_PHI_MC3_ADDR is defined as MSR_MC3_ADDR in SDM. > **/ > #define MSR_XEON_PHI_MC3_ADDR 0x0000040E >=20 > @@ -886,6 +911,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_MC4_CTL); > AsmWriteMsr64 (MSR_XEON_PHI_MC4_CTL, Msr); > @endcode > + @note MSR_XEON_PHI_MC4_CTL is defined as MSR_MC4_CTL in SDM. > **/ > #define MSR_XEON_PHI_MC4_CTL 0x00000410 >=20 > @@ -904,6 +930,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_MC4_STATUS); > AsmWriteMsr64 (MSR_XEON_PHI_MC4_STATUS, Msr); > @endcode > + @note MSR_XEON_PHI_MC4_STATUS is defined as MSR_MC4_STATUS in > SDM. > **/ > #define MSR_XEON_PHI_MC4_STATUS 0x00000411 >=20 > @@ -925,6 +952,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_MC4_ADDR); > AsmWriteMsr64 (MSR_XEON_PHI_MC4_ADDR, Msr); > @endcode > + @note MSR_XEON_PHI_MC4_ADDR is defined as MSR_MC4_ADDR in SDM. > **/ > #define MSR_XEON_PHI_MC4_ADDR 0x00000412 >=20 > @@ -943,6 +971,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_MC5_CTL); > AsmWriteMsr64 (MSR_XEON_PHI_MC5_CTL, Msr); > @endcode > + @note MSR_XEON_PHI_MC5_CTL is defined as MSR_MC5_CTL in SDM. > **/ > #define MSR_XEON_PHI_MC5_CTL 0x00000414 >=20 > @@ -961,6 +990,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_MC5_STATUS); > AsmWriteMsr64 (MSR_XEON_PHI_MC5_STATUS, Msr); > @endcode > + @note MSR_XEON_PHI_MC5_STATUS is defined as MSR_MC5_STATUS in > SDM. > **/ > #define MSR_XEON_PHI_MC5_STATUS 0x00000415 >=20 > @@ -979,6 +1009,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_MC5_ADDR); > AsmWriteMsr64 (MSR_XEON_PHI_MC5_ADDR, Msr); > @endcode > + @note MSR_XEON_PHI_MC5_ADDR is defined as MSR_MC5_ADDR in SDM. > **/ > #define MSR_XEON_PHI_MC5_ADDR 0x00000416 >=20 > @@ -996,6 +1027,7 @@ typedef union { >=20 > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM); > @endcode > + @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as > IA32_VMX_EPT_VPID_ENUM in SDM. > **/ > #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C >=20 > @@ -1014,6 +1046,7 @@ typedef union { >=20 > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC); > @endcode > + @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as > IA32_VMX_FMFUNC in SDM. > **/ > #define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491 >=20 > @@ -1033,6 +1066,7 @@ typedef union { >=20 > Msr.Uint64 =3D AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT); > @endcode > + @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as > MSR_RAPL_POWER_UNIT in SDM. > **/ > #define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606 >=20 > @@ -1092,6 +1126,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY); > AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr); > @endcode > + @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as > MSR_PKG_C2_RESIDENCY in SDM. > **/ > #define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D >=20 > @@ -1111,6 +1146,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT); > AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr); > @endcode > + @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as > MSR_PKG_POWER_LIMIT in SDM. > **/ > #define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610 >=20 > @@ -1128,6 +1164,7 @@ typedef union { >=20 > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS); > @endcode > + @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as > MSR_PKG_ENERGY_STATUS in SDM. > **/ > #define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611 >=20 > @@ -1145,6 +1182,7 @@ typedef union { >=20 > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS); > @endcode > + @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as > MSR_PKG_PERF_STATUS in SDM. > **/ > #define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613 >=20 > @@ -1164,6 +1202,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO); > AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr); > @endcode > + @note MSR_XEON_PHI_PKG_POWER_INFO is defined as > MSR_PKG_POWER_INFO in SDM. > **/ > #define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614 >=20 > @@ -1183,6 +1222,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT); > AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr); > @endcode > + @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as > MSR_DRAM_POWER_LIMIT in SDM. > **/ > #define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618 >=20 > @@ -1200,6 +1240,7 @@ typedef union { >=20 > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS); > @endcode > + @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as > MSR_DRAM_ENERGY_STATUS in SDM. > **/ > #define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619 >=20 > @@ -1218,6 +1259,7 @@ typedef union { >=20 > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS); > @endcode > + @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as > MSR_DRAM_PERF_STATUS in SDM. > **/ > #define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B >=20 > @@ -1236,6 +1278,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO); > AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr); > @endcode > + @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as > MSR_DRAM_POWER_INFO in SDM. > **/ > #define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C >=20 > @@ -1255,6 +1298,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT); > AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr); > @endcode > + @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as > MSR_PP0_POWER_LIMIT in SDM. > **/ > #define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638 >=20 > @@ -1273,6 +1317,7 @@ typedef union { >=20 > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS); > @endcode > + @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as > MSR_PP0_ENERGY_STATUS in SDM. > **/ > #define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639 >=20 > @@ -1290,6 +1335,7 @@ typedef union { >=20 > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL); > @endcode > + @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as > MSR_CONFIG_TDP_NOMINAL in SDM. > **/ > #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648 >=20 > @@ -1307,6 +1353,7 @@ typedef union { >=20 > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1); > @endcode > + @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as > MSR_CONFIG_TDP_LEVEL1 in SDM. > **/ > #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649 >=20 > @@ -1324,6 +1371,7 @@ typedef union { >=20 > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2); > @endcode > + @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as > MSR_CONFIG_TDP_LEVEL2 in SDM. > **/ > #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A >=20 > @@ -1342,6 +1390,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL); > AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr); > @endcode > + @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as > MSR_CONFIG_TDP_CONTROL in SDM. > **/ > #define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B >=20 > @@ -1360,6 +1409,7 @@ typedef union { > Msr =3D AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO); > AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr); > @endcode > + @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as > MSR_TURBO_ACTIVATION_RATIO in SDM. > **/ > #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C >=20 > @@ -1381,6 +1431,7 @@ typedef union { > Msr.Uint64 =3D AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS); > AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64); > @endcode > + @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as > MSR_CORE_PERF_LIMIT_REASONS in SDM. > **/ > #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690 >=20 > -- > 2.9.3.windows.2