From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.8487.1648455017030517745 for ; Mon, 28 Mar 2022 01:10:43 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=Gb9iUpC2; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648455043; x=1679991043; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7ly7YQ7Ppk7ltwscECjDcuYdBG6/KhrcV4BHSl4Lnfg=; b=Gb9iUpC28fwdSodImbQpWwTZKEGVXpEqZTXNPDH3/ULkhBwNm1AhsO6o PH2yUqs40gj9ojxlCnKsfCNOusG+B8IXrBMqF73gi3758jZ6UecxrsH1W 32moNJBN6Nt9F4hAk2oOC5on+kE07HVNwSwB8NTJgURHqiyU31TYkGVXY aXLPB5bGqmBlLhdhg/2zNwsfWOlXV7wX/8knHIrq6UlaYAV6snbF8TFya I68Mr9j3jA2VjPzCvanUQ4XtyI76t/Defb9E+jzz/XkEXusJvvXA+HopJ xwo+qY6e6bFl5TNSe6kg2yAflQgyYQ90VSLpwitJxHKKdm9riC8IXlp4V w==; X-IronPort-AV: E=McAfee;i="6200,9189,10299"; a="257771443" X-IronPort-AV: E=Sophos;i="5.90,216,1643702400"; d="scan'208";a="257771443" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2022 01:10:42 -0700 X-IronPort-AV: E=Sophos;i="5.90,216,1643702400"; d="scan'208";a="563428645" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.167]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2022 01:10:40 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [PATCH V11 39/47] OvmfPkg: Update PlatformPei to support Tdx guest Date: Mon, 28 Mar 2022 16:08:18 +0800 Message-Id: <469c5004be8e82af61741638542cab11e95254f6.1648454441.git.min.m.xu@intel.com> X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 OvmfPkg/PlatformPei is updated to support Tdx guest. There are below major changes. - Set Tdx related PCDs - Publish Tdx RamRegions In this patch there is another new function BuildPlatformInfoHob (). This function builds EFI_HOB_PLATFORM_INFO which contains the HostBridgeDevId. The hob is built in both Td guest and Non-Td guest. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/OvmfPkg.dec | 1 + OvmfPkg/PlatformPei/FeatureControl.c | 7 +++- OvmfPkg/PlatformPei/IntelTdx.c | 51 ++++++++++++++++++++++++++++ OvmfPkg/PlatformPei/MemDetect.c | 13 +++++-- OvmfPkg/PlatformPei/Platform.c | 13 +++++++ OvmfPkg/PlatformPei/Platform.h | 19 +++++++++++ OvmfPkg/PlatformPei/PlatformPei.inf | 3 ++ 7 files changed, 104 insertions(+), 3 deletions(-) create mode 100644 OvmfPkg/PlatformPei/IntelTdx.c diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index f3d06411b51b..746050d64ba7 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -133,6 +133,7 @@ gGrubFileGuid = {0xb5ae312c, 0xbc8a, 0x43b1, {0x9c, 0x62, 0xeb, 0xb8, 0x26, 0xdd, 0x5d, 0x07}} gConfidentialComputingSecretGuid = {0xadf956ad, 0xe98c, 0x484c, {0xae, 0x11, 0xb5, 0x1c, 0x7d, 0x33, 0x64, 0x47}} gConfidentialComputingSevSnpBlobGuid = {0x067b1f5f, 0xcf26, 0x44c5, {0x85, 0x54, 0x93, 0xd7, 0x77, 0x91, 0x2d, 0x42}} + gUefiOvmfPkgPlatformInfoGuid = {0xdec9b486, 0x1f16, 0x47c7, {0x8f, 0x68, 0xdf, 0x1a, 0x41, 0x88, 0x8b, 0xa5}} [Ppis] # PPI whose presence in the PPI database signals that the TPM base address diff --git a/OvmfPkg/PlatformPei/FeatureControl.c b/OvmfPkg/PlatformPei/FeatureControl.c index 9af58c2655f8..5864ee0c214d 100644 --- a/OvmfPkg/PlatformPei/FeatureControl.c +++ b/OvmfPkg/PlatformPei/FeatureControl.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "Platform.h" @@ -37,7 +38,11 @@ WriteFeatureControl ( IN OUT VOID *WorkSpace ) { - AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, mFeatureControlValue); + if (TdIsEnabled ()) { + TdVmCall (TDVMCALL_WRMSR, (UINT64)MSR_IA32_FEATURE_CONTROL, mFeatureControlValue, 0, 0, 0); + } else { + AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, mFeatureControlValue); + } } /** diff --git a/OvmfPkg/PlatformPei/IntelTdx.c b/OvmfPkg/PlatformPei/IntelTdx.c new file mode 100644 index 000000000000..3c1ddbfafd80 --- /dev/null +++ b/OvmfPkg/PlatformPei/IntelTdx.c @@ -0,0 +1,51 @@ +/** @file + Initialize Intel TDX support. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "Platform.h" + +/** + This Function checks if TDX is available, if present then it sets + the dynamic PCDs for Tdx guest. + **/ +VOID +IntelTdxInitialize ( + VOID + ) +{ + #ifdef MDE_CPU_X64 + RETURN_STATUS PcdStatus; + + if (!TdIsEnabled ()) { + return; + } + + PcdStatus = PcdSet64S (PcdConfidentialComputingGuestAttr, CCAttrIntelTdx); + ASSERT_RETURN_ERROR (PcdStatus); + + PcdStatus = PcdSet64S (PcdTdxSharedBitMask, TdSharedPageMask ()); + ASSERT_RETURN_ERROR (PcdStatus); + + PcdStatus = PcdSetBoolS (PcdSetNxForStack, TRUE); + ASSERT_RETURN_ERROR (PcdStatus); + #endif +} diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index 61d7d3059f7b..2e47b1322990 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -37,7 +37,6 @@ Module Name: #include #include - #include "Platform.h" VOID @@ -231,7 +230,12 @@ GetPeiMemoryCap ( PdpEntries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 30); ASSERT (PdpEntries <= 0x200); } else { - Pml4Entries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39); + if (mPlatformInfoHob.PhysMemAddressWidth > 48) { + Pml4Entries = 0x200; + } else { + Pml4Entries = 1 << (mPlatformInfoHob.PhysMemAddressWidth - 39); + } + ASSERT (Pml4Entries <= 0x200); PdpEntries = 512; } @@ -354,6 +358,11 @@ InitializeRamRegions ( IN EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { + if (TdIsEnabled ()) { + PlatformTdxPublishRamRegions (); + return; + } + PlatformQemuInitializeRam (PlatformInfoHob); SevInitializeRam (); diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index f05aec599fcb..f006755d5fdb 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -310,6 +310,17 @@ MaxCpuCountInitialization ( ASSERT_RETURN_ERROR (PcdStatus); } +/** + * @brief Builds PlatformInfo Hob + */ +VOID +BuildPlatformInfoHob ( + VOID + ) +{ + BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid, &mPlatformInfoHob, sizeof (EFI_HOB_PLATFORM_INFO)); +} + /** Perform Platform PEI initialization. @@ -386,7 +397,9 @@ InitializePlatform ( MiscInitialization (&mPlatformInfoHob); } + IntelTdxInitialize (); InstallFeatureControlCallback (); + BuildPlatformInfoHob (); return EFI_SUCCESS; } diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 3d148893401a..29b51b2debd8 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -11,6 +11,7 @@ #include #include +#include extern EFI_HOB_PLATFORM_INFO mPlatformInfoHob; @@ -84,6 +85,24 @@ AmdSevInitialize ( VOID ); +/** + This Function checks if TDX is available, if present then it sets + the dynamic PCDs for Tdx guest. It also builds Guid hob which contains + the Host Bridge DevId. + **/ +VOID +IntelTdxInitialize ( + VOID + ); + +/** + * @brief Builds PlatformInfo Hob + */ +VOID +BuildPlatformInfoHob ( + VOID + ); + VOID SevInitializeRam ( VOID diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf index f6bfc09c2dd5..00372fa0ebb5 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -31,6 +31,7 @@ MemTypeInfo.c Platform.c Platform.h + IntelTdx.c [Packages] EmbeddedPkg/EmbeddedPkg.dec @@ -43,6 +44,7 @@ [Guids] gEfiMemoryTypeInformationGuid gFdtHobGuid + gUefiOvmfPkgPlatformInfoGuid [LibraryClasses] BaseLib @@ -111,6 +113,7 @@ gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures + gEfiMdeModulePkgTokenSpaceGuid.PcdTdxSharedBitMask [FixedPcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase -- 2.29.2.windows.2