From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.435.1644260572851807004 for ; Mon, 07 Feb 2022 11:02:53 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=OqHhXEr3; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: isaac.w.oram@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644260572; x=1675796572; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4EZGWWhM0UBigIWCEx9Wcw6v0heTee5ghzQYS+26zWI=; b=OqHhXEr30+cyjStNnvU08nP2TUwfhJBmMZMnref07AWAf/A/fO3vUsbx PB1IizxzvTwuQ6LitzbsvgQ4AI/Nznw3QqcglssZm0hhgwbOIyuPc0K3a PqbuUPFifBbTc5tfA4KVA2iYkM6xGazD34f/yVIeIufmEimaZjr/qEPaf UjKXPJRXgY9In/vzqkQLsRJOxAPoi0a1fGxM2ZpN8EOzbYffL0Vwvn0OQ dzpBkBvERHBVmtk1dB2oGH40VSIequc4vA2L2QWcSO/57T2N75On70VVy btSWdeZ1c3n2CNnTXpks3U+nYkYPMsLZ0A8yrF+ER9A8Svdb4MzkBZIRK g==; X-IronPort-AV: E=McAfee;i="6200,9189,10250"; a="309532836" X-IronPort-AV: E=Sophos;i="5.88,350,1635231600"; d="scan'208";a="309532836" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2022 11:02:50 -0800 X-IronPort-AV: E=Sophos;i="5.88,350,1635231600"; d="scan'208";a="567583940" Received: from iworam-desk.amr.corp.intel.com ([10.7.150.79]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2022 11:02:50 -0800 From: "Oram, Isaac W" To: devel@edk2.groups.io Cc: Nate DeSimone , Chasel Chiu Subject: [edk2-devel][edk2-platforms][PATCH V1 2/8] WhitleyOpenBoardPkg/AcpiTables: Add ACPI Table definitions Date: Mon, 7 Feb 2022 11:02:39 -0800 Message-Id: <46abc027d4f33cce1da11cff8a8c5269f838cef0.1644259969.git.isaac.w.oram@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Header files for C structures used to build ACPI tables Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram --- Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h | 91 +++++++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h | 30 +++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h | 37 ++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h | 206 ++++++++++++++++++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h | 88 +++++++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h | 43 ++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h | 58 ++++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h | 57 ++++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h | 56 ++++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h | 84 ++++++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h | 58 ++++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h | 50 +++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h | 45 +++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h | 120 ++++++++++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h | 87 +++++++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h | 48 +++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h | 59 ++++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTable.h | 82 ++++++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h | 53 +++++ Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h | 67 +++++++ Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 7 +- Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h | 8 + 22 files changed, 1430 insertions(+), 4 deletions(-) diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h new file mode 100644 index 0000000000..0fb913a6a8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Bdat.h @@ -0,0 +1,91 @@ +/** @file + This file describes the contents of the BDAT ACPI. + + @copyright + Copyright 1999 - 2019 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _BDAT_H_ +#define _BDAT_H_ + +// +// Statements that include other files +// +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) + +#define EFI_BDAT_TABLE_SIGNATURE SIGNATURE_32('B','D','A','T') + +#define BDAT_PRIMARY_VER 0x0004 +#define BDAT_SECONDARY_VER 0x0000 + +typedef struct { + UINT8 BiosDataSignature[8]; // "BDATHEAD" + UINT32 BiosDataStructSize; // sizeof BDAT_STRUCTURE + sizeof BDAT_MEMORY_DATA_STRUCTURE + sizeof BDAT_RMT_STRUCTURE + UINT16 Crc16; // 16-bit CRC of BDAT_STRUCTURE (calculated with 0 in this field) + UINT16 Reserved; + UINT16 PrimaryVersion; // Primary version + UINT16 SecondaryVersion; // Secondary version + UINT32 OemOffset; // Optional offset to OEM-defined structure + UINT32 Reserved1; + UINT32 Reserved2; +} BDAT_HEADER_STRUCTURE; + +typedef struct bdatSchemaList { + UINT16 SchemaListLength; //Number of Schemas present + UINT16 Reserved; + UINT16 Year; + UINT8 Month; + UINT8 Day; + UINT8 Hour; + UINT8 Minute; + UINT8 Second; + UINT8 Reserved1; + // + // This is a dynamic region, where Schema list address is filled out. + // Each schema location is 32 bits long and complies with BDAT 4.0 version. + // +} BDAT_SCHEMA_LIST_STRUCTURE; + +//BDAT Header Struct which contains information all exisitng BDAT Schemas +typedef struct bdatStruct { + BDAT_HEADER_STRUCTURE BdatHeader; + BDAT_SCHEMA_LIST_STRUCTURE BdatSchemas; +} BDAT_STRUCTURE; + +// +// BIOS Data ACPI structure +// +typedef struct { + + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BdatGas; + +} EFI_BDAT_ACPI_DESCRIPTION_TABLE; + +// +// BIOS Data Parameter Region Generic Address +// Information +// +#define EFI_BDAT_ACPI_POINTER 0x0 + +#define ___INTERNAL_CONVERT_TO_STRING___(a) #a +#define CONVERT_TO_STRING(a) ___INTERNAL_CONVERT_TO_STRING___(a) + +// +// This is copied from Include\Acpi.h +// +#define CREATOR_ID_INTEL 0x4C544E49 //"LTNI""INTL"(Intel) +#define CREATOR_REV_INTEL 0x20090903 + +#define EFI_ACPI_TABLE_VERSION_ALL (EFI_ACPI_TABLE_VERSION_1_0B|EFI_ACPI_TABLE_VERSION_2_0|EFI_ACPI_TABLE_VERSION_3_0) + +#pragma pack() + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h new file mode 100644 index 0000000000..cfaa9247d8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Dbg2.h @@ -0,0 +1,30 @@ +/** @file + + @copyright + Copyright 2019 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DBG2_H_ +#define _DBG2_H_ + +// +// Statements that include other files +// +#include + +#pragma pack(1) +typedef +struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Table; + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Entry; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAdressRegister; + UINT32 AddressSize; + CHAR8 NamespaceString[2]; + +} DBG2_DEBUG_TABLE; +#pragma pack() + + +#endif //_DBG2_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h new file mode 100644 index 0000000000..56e32c41f5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Facs.h @@ -0,0 +1,37 @@ +/** @file + This file describes the contents of the ACPI Firmware ACPI Control + Structure (FACS). Some additional ACPI values are defined in Acpi1_0.h and + Acpi2_0.h + All changes to the FACS contents should be done in this file. + + @copyright + Copyright 1996 - 2015 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _FACS_H +#define _FACS_H + +// +// Statements that include other files +// +#include + +// +// FACS Definitions +// +#define EFI_ACPI_FIRMWARE_WAKING_VECTOR 0x00000000 +#define EFI_ACPI_GLOBAL_LOCK 0x00000000 + +// +// Firmware Control Structure Feature Flags are defined in AcpiX.0.h +// +#define EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS 0x00000000 + +#define EFI_ACPI_X_FIRMWARE_WAKING_VECTOR 0x0000000000000000 + +#define EFI_ACPI_OSPM_FLAGS 0x00000000 + + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h new file mode 100644 index 0000000000..004aac350d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Fadt.h @@ -0,0 +1,206 @@ +/** @file + This file describes the contents of the ACPI Fixed ACPI Description Table + FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h. + All changes to the FADT contents should be done in this file. + + @copyright + Copyright 1996 - 2020 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _FADT_H_ +#define _FADT_H_ + +// +// Statements that include other files +// +#include +#include "Platform.h" +#include + +// +// FADT Definitions +// +#define EFI_ACPI_OEM_FADT_REVISION 0x00000000 +// +// For ACPI 1.0 supprt +// Harwich sets this to #define EFI_ACPI_INT_MODEL 0x01 +// + +/* +INT_MODEL Field +The FADT defines the fixed ACPI information that is needed by the operating system as +defined in section 5.2.5 of the ACPI 1.0 specification. Currently, this table provides a field +for INT_MODEL, which was intended to be used to report the interrupt mode of the machine. +This field is ignored by the Microsoft?Windows?2000 and later operating system because the +Microsoft Windows 98 operating system only supports programmable interrupt controller (PIC) mode. +This forces system manufacturers (OEMs) who want to support Windows 98 to enter a "0" in the INT_MODEL field. +This would then preclude using multiple processors on Windows 2000 and later versions. +Because the INT_MODEL field in the FADT cannot be dynamically updated while the machine is running, +it cannot be used to report the interrupt mode, and therefore it is ignored by Windows 98, +and Windows 2000 and later versions. +http://www.microsoft.com/whdc/system/CEC/ACPI-MP.mspx +For Watson Creek we set this to 0 and then dynamically update this to 1 in the DSDT tables _PIC method and GPIC field. +*/ +#define EFI_ACPI_INT_MODEL 0x0 + +#define EFI_ACPI_PREFERRED_PM_PROFILE 0x04 + +#define EFI_ACPI_SCI_INT 0x0009 +#define EFI_ACPI_SMI_CMD 0x0 + +#define EFI_ACPI_ACPI_ENABLE 0x00 +#define EFI_ACPI_ACPI_DISABLE 0x00 +#define EFI_ACPI_S4_BIOS_REQ 0x00 +#define EFI_ACPI_CST_CNT 0x00 + +#define EFI_ACPI_PSTATE_CNT 0x00 +#define EFI_ACPI_GPE1_BASE (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 2) +#define EFI_ACPI_P_LVL2_LAT 0x0065 +#define EFI_ACPI_P_LVL3_LAT 0x03E9 +// +// #define EFI_ACPI_FLUSH_SIZE 0x0400 +// +#define EFI_ACPI_FLUSH_SIZE 0x0000 +// +// #define EFI_ACPI_FLUSH_STRIDE 0x0010 +// +#define EFI_ACPI_FLUSH_STRIDE 0x0000 +#define EFI_ACPI_DUTY_OFFSET 0x01 +// +// #define EFI_ACPI_DUTY_OFFSET 0x00 +// +#define EFI_ACPI_DUTY_WIDTH 0x00 + +#define EFI_ACPI_DAY_ALRM 0x0D +#define EFI_ACPI_MON_ALRM 0x00 +#define EFI_ACPI_CENTURY 0x32 + +// +// IA-PC Boot Architecture Flags, see ACPI 2.0 table specification and Acpi6_2.h +// No legacy KBC and legcay devices other reported in ASL code +// +// #define EFI_ACPI_IAPC_BOOT_ARCH (EFI_ACPI_6_2_LEGACY_DEVICES | EFI_ACPI_6_2_8042) +// +//#define EFI_ACPI_IAPC_BOOT_ARCH EFI_ACPI_6_2_8042 +#define EFI_ACPI_OS_ASPM_DISABLE (1 << 4) + +#define EFI_ACPI_IAPC_BOOT_ARCH EFI_ACPI_6_2_8042 | EFI_ACPI_OS_ASPM_DISABLE + +// +// Fixed Feature Flags, see ACPI 6.2 table specification and Acpi6_2.h +// +#define EFI_ACPI_FIXED_FEATURE_FLAGS (EFI_ACPI_6_2_RESET_REG_SUP | \ + EFI_ACPI_6_2_RTC_S4 | \ + EFI_ACPI_6_2_SLP_BUTTON | \ + EFI_ACPI_6_2_WBINVD | \ + EFI_ACPI_6_2_PROC_C1 \ + ) + +// +// PM1A Event Register Block Generic Address Information +// +#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO +#define EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH 0x20 +#define EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET 0x00 +#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS (FixedPcdGet32 (PcdEfiAcpiPm1aEvtBlkAddress)) + +// +// PM1B Event Register Block Generic Address Information +// +#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO +#define EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH 0x00 +#define EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET 0x00 +#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS 0x00000000 + +// +// PM1A Control Register Block Generic Address Information +// +#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO +#define EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH 0x10 +#define EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET 0x00 +#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x04) + +// +// PM1B Control Register Block Generic Address Information +// +#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO +#define EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH 0x00 +#define EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET 0x00 +#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS 0x00 + +// +// PM2 Control Register Block Generic Address Information +// +#define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO +#define EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH 0x08 +#define EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET 0x00 +#define EFI_ACPI_PM2_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x50) + +// +// Power Management Timer Control Register Block Generic Address +// Information +// +#define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO +#define EFI_ACPI_PM_TMR_BLK_BIT_WIDTH 0x20 +#define EFI_ACPI_PM_TMR_BLK_BIT_OFFSET 0x00 +#define EFI_ACPI_PM_TMR_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x08) + +// +// General Purpose Event 0 Register Block Generic Address +// Information +// +#define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO +#define EFI_ACPI_GPE0_BLK_BIT_WIDTH 0x100 // size of R_PCH_ACPI_GPE0_STS_127_96 + R_PCH_ACPI_GPE0_EN_127_96 (2*0x80 = 0x100) +#define EFI_ACPI_GPE0_BLK_BIT_OFFSET 0x00 +#define EFI_ACPI_GPE0_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x80) + +// +// General Purpose Event 1 Register Block Generic Address +// Information +// +#define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO +#define EFI_ACPI_GPE1_BLK_BIT_WIDTH 0x0 +#define EFI_ACPI_GPE1_BLK_BIT_OFFSET 0x0 +#define EFI_ACPI_GPE1_BLK_ADDRESS 0x0 +// +// Reset Register Generic Address Information +// +#define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO +#define EFI_ACPI_RESET_REG_BIT_WIDTH 0x08 +#define EFI_ACPI_RESET_REG_BIT_OFFSET 0x00 +#define EFI_ACPI_RESET_REG_ADDRESS 0x00000CF9 +#define EFI_ACPI_RESET_VALUE 0x06 + +// +// Number of bytes decoded by PM1 event blocks (a and b) +// +#define EFI_ACPI_PM1_EVT_LEN ((EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH) / 8) + +// +// Number of bytes decoded by PM1 control blocks (a and b) +// +#define EFI_ACPI_PM1_CNT_LEN ((EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH) / 8) + +// +// Number of bytes decoded by PM2 control block +// +#define EFI_ACPI_PM2_CNT_LEN (EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH / 8) + +// +// Number of bytes decoded by PM timer block +// +#define EFI_ACPI_PM_TMR_LEN (EFI_ACPI_PM_TMR_BLK_BIT_WIDTH / 8) + +// +// Number of bytes decoded by GPE0 block +// +#define EFI_ACPI_GPE0_BLK_LEN (EFI_ACPI_GPE0_BLK_BIT_WIDTH / 8) + +// +// Number of bytes decoded by GPE1 block +// +#define EFI_ACPI_GPE1_BLK_LEN (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 8) + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h new file mode 100644 index 0000000000..ad6684acce --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hmat.h @@ -0,0 +1,88 @@ +/** @file + + @copyright + Copyright 2016 - 2020 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _HMAT_HMAT_H_ +#define _HMAT_HMAT_H_ + +#include +#include +#include "Platform.h" +#include "Msars.h" +#include "Sllbis.h" +#include "Mscis.h" + +#define EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01 +#define EFI_ACPI_OEM_HMAT_REVISION 0x00000001 + +#define EFI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('H', 'M', 'A', 'T') +#define MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE_TYPE 0 +#define SYSTEM_LOCALITY_LATENCY_BANDWIDTH_INFORMATION_STRUCTURE_TYPE 1 +#define MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE_TYPE 2 + +#define EFI_ACPI_HMAT_MSARS_COUNT (MC_MAX_NODE * MAX_CRS_ENTRIES_PER_NODE) +#define EFI_ACPI_HMAT_LBIS_COUNT (EFI_ACPI_HMAT_MAX_SLLBIS_DATA_TYPES * MAX_HMAT_MEMORY_HIERACHY_LEVELS) +#define EFI_ACPI_HMAT_MSCIS_COUNT (MC_MAX_NODE * MAX_CRS_ENTRIES_PER_NODE) + + +#define HMAT_BW_BASE_UNIT 1024 // 1024 MB/S +#define HMAT_LATENCY_BASE_UNIT 1 // 1ns + +#define HBM_4_NODES_CASE 4 +#define HBM_2_NODES_CASE 2 +#define HBM_1_NODE_CASE 1 + +// +// In HBM as Cache mode, Cache Flags are only for Last Level of Cache (Flags = 1), and 1st Level of Cache (Flags = 2). +// So Flag = 0 should be skipped. +// +#define HMAT_HBM_CACHE_FLAG_OFFSET 1 + +#pragma pack(1) +typedef enum { + TypeFlatMemoryMode = 1, + TypeCacheMemoryMode = 2, + TypeHybridMemoryMode = 3, +} LBIS_MEMORY_FLAGS_TYPE; + +typedef struct { + UINT8 Valid; + UINT32 ElementId; + UINT64 MemMapIndexMap; + UINT8 Cacheable; + UINT64 MemorySideCacheSize; + UINT16 NumSmbiosHandles; + UINT16 SmbiosHandles[MAX_TYPE17_CACHE_DEVICES]; + UINT8 PhysicalSocketId; +} MEMORY_DOMAIN_LIST_INFO; + +typedef struct { + UINT32 ProcessorDomainNumber; + UINT32 MemoryDomainNumber; + UINT16 ProcessorDomainList [EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS]; + MEMORY_DOMAIN_LIST_INFO MemoryDomainList [EFI_ACPI_HMAT_NUMBER_OF_MEMORY_DOMAINS]; + UINT8 SncEnabled; + UINT8 SncNumOfCluster; + UINT8 VirtualNumaEnabled; + UINT8 VirtualNumOfCluster; + UINT8 ProcessorDomainSocketIdList [EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS]; +} HMAT_PROXIMITY_DOMAIN_DATA_STRUCTURE; + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved; // To make the structures 8 byte aligned +} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER; + +typedef struct { + EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER HmatHeader; + MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE Msars[EFI_ACPI_HMAT_MSARS_COUNT]; + LATENCY_BANDWIDTH_INFO_STRUCTURE Lbis[EFI_ACPI_HMAT_LBIS_COUNT]; + MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE MemSideCache[EFI_ACPI_HMAT_MSCIS_COUNT]; +} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE; +#pragma pack() + +#endif /* _HMAT_H_ */ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h new file mode 100644 index 0000000000..a3b9ef256a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Hpet.h @@ -0,0 +1,43 @@ +/** @file + This file describes the contents of the ACPI High Precision Event Timer Description Table + HPET). Some additional ACPI values are defined in Acpi1_0.h, Acpi2_0.h, and Acpi3_0.h + All changes to the HPET contents should be done in this file. + + @copyright + Copyright 1999 - 2019 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _HPET_H_ +#define _HPET_H_ + +// +// Statements that include other files +// +#include +#include + +// +// HPET Definitions +// +#define EFI_ACPI_OEM_HPET_REVISION 0x00000001 + +#define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A701 + +// +// Event Timer Block Base Address Information +// +#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_MEMORY +#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH 0x00 +#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET 0x00 +#define EFI_ACPI_EVENT_TIMER_ACCESS_SIZE 0x00 +#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS 0x00000000FED00000 + +#define EFI_ACPI_HPET_NUMBER 0x00 + +#define EFI_ACPI_MIN_CLOCK_TICK 0x0080 + +#define EFI_ACPI_HPET_ATTRIBUTES 0x00 + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h new file mode 100644 index 0000000000..7277961baa --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mcfg.h @@ -0,0 +1,58 @@ +/** @file + ACPI Memory mapped configuration space base address Description Table + implementation, based on PCI Firmware Specification Revision 3.0 final draft, + downloadable at http://www.pcisig.com/home + + @copyright + Copyright 1999 - 2019 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MCFG_H_ +#define _MCFG_H_ + +// +// Statements that include other files +// +#include +#include +#include "Platform.h" +// +// "MCFG" Static Resource Affinity Table +// +#define EFI_ACPI_6_2_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE 0x4746434D + +// +// MCFG Definitions, see specification for details. +// +#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001 + +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT MAX_SOCKET + +// +// MCFG Table definition. The table must be defined in a platform +// specific manner. +// +// +// Ensure proper structure formats +// +#pragma pack(1) + +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + +#if EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT > 0 + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Segment[ + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT]; +#endif + +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE; + +#pragma pack() + +#endif // _MCFG_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h new file mode 100644 index 0000000000..058ae67717 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Migt.h @@ -0,0 +1,57 @@ +/** @file + This file describes the contents of the MIGT ACPI table. + + @copyright + Copyright 1999 - 2019 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MIGT_H_ +#define _MIGT_H_ + +// +// Statements that include other files +// +#include + +// +// MIGT ACPI structure +// +typedef struct { + + EFI_ACPI_DESCRIPTION_HEADER Header; + // MIGT Specific Entries + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ControlRegister; + UINT32 ControlRegisterValue; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ActionRegion; + +} EFI_MIGT_ACPI_DESCRIPTION_TABLE; + + +// +// MIGT ACPI Definitions +// +#define MIGT_SMI_SERVICE_ID 0xFD // Door Bell + +#define EFI_MIGT_ACPI_TABLE_SIGNATURE SIGNATURE_32('M','I','G','T') +#define EFI_MIGT_ACPI_DESCRIPTION_TABLE_REVISION 0x01 +#define EFI_MIGT_ACPI_OEM_REVISION 0x00000000 + +// +// MIGT Control Register Generic Address Information +// +#define EFI_MIGT_CR_ACPI_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO +#define EFI_MIGT_CR_ACPI_REGISTER_BIT_WIDTH 0x8 +#define EFI_MIGT_CR_ACPI_REGISTER_BIT_OFFSET 0x0 +#define EFI_MIGT_CR_ACPI_SMI_ADDRESS 0xB2 + +// +// MIGT Action Region Generic Address Information +// +#define EFI_MIGT_AR_ACPI_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_MEMORY +#define EFI_MIGT_AR_ACPI_REGISTER_BIT_WIDTH 64 +#define EFI_MIGT_AR_ACPI_REGISTER_BIT_OFFSET 0x0 +#define EFI_MIGT_AR_ACPI_MEMORY_ADDRESS 0x0 + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h new file mode 100644 index 0000000000..a088d66ea5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msars.h @@ -0,0 +1,56 @@ +/** @file + + @copyright + Copyright 2016 - 2018 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MSARS_H_ +#define _MSARS_H_ + +#include + +#pragma pack(1) +typedef struct { + UINT16 ProcessorDomainValid:1; + UINT16 MemoryDomainValid:1; + UINT16 ReservationHint:1; + UINT16 Reserved_15_3:13; +} MSARS_FLAGS_BITS; + +typedef union { + UINT16 Value; + MSARS_FLAGS_BITS Bits; +} MSARS_FLAGS; + +typedef struct { + UINT16 Type; + UINT16 Reserved_2_4; + UINT32 Length; + MSARS_FLAGS Flags; + UINT16 Reserved_10_12; + UINT32 ProcessorProximityDomain; + UINT32 MemoryProximityDomain; + UINT32 Reserved_20_24; + UINT64 AddrBase; //System Physical Address Range Base + UINT64 AddrLength; //System Physical Address Range Length +} MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE; +#pragma pack() + +// MSARS_INIT Macro +// Used to initialize MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE +#define MSARS_INIT() { \ + (UINT16) MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE_TYPE, \ + (UINT16) 0, \ + (UINT32) sizeof(MEMORY_SUBSYSTEM_ADDRESS_RANGE_STRUCTURE), \ + {(UINT16) 0}, \ + (UINT16) 0, \ + (UINT32) 0, \ + (UINT32) 0, \ + (UINT32) 0, \ + (UINT64) 0, \ + (UINT64) 0, \ + }, + +#endif /* _MSARS_H_ */ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h new file mode 100644 index 0000000000..44d80910e2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Mscis.h @@ -0,0 +1,84 @@ +/** @file + + @copyright + Copyright 2016 - 2018 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MSCIS_H_ +#define _MSCIS_H_ + +#include + +#define EFI_ACPI_HMAT_CACHE_LEVEL_NONE 0 +#define EFI_ACPI_HMAT_ONE_LEVEL_CACHE 1 +#define EFI_ACPI_HMAT_TWO_LEVEL_CACHE 2 +#define EFI_ACPI_HMAT_THREE_LEVEL_CACHE 3 + +#define EFI_ACPI_HMAT_CACHE_ASSOCIATIVITY_NONE 0 +#define EFI_ACPI_HMAT_CACHE_ASSOCIATIVITY_DIRECT_MAPPED 1 +#define EFI_ACPI_HMAT_CACHE_ASSOCIATIVITY_COIMPLEX_CACHE_INDEXING 2 + +#define EFI_ACPI_HMAT_WRITE_POLICY_NONE 0 +#define EFI_ACPI_HMAT_WRITE_POLICY_WB 1 +#define EFI_ACPI_HMAT_WRITE_POLICY_WT 2 + +#define HBM_CACHE_LINE_SIZE 72 +#define DDR4_CACHE_LINE_SIZE 64 + +// +// MAX_CH = MAX_IMC * MAX_MC_CH +// MAX_IMC = Maximum memory controllers per socket +// MAX_MC_CH = Max number of channels per MC +// For each channel, 1 DDR can act as 2LM cache. This is the maximum number of cache devices per memory domain +// +#define MAX_TYPE17_CACHE_DEVICES MAX_CH + +#pragma pack(1) +typedef struct { + UINT32 TotalCacheLevels:4; + UINT32 CacheLevel:4; + UINT32 CacheAssociativity:4; + UINT32 WritePolicy:4; + UINT32 CacheLineSize:16; +} CACHE_ATTRIBUTES_BITS; + +typedef union { + UINT32 Data; + CACHE_ATTRIBUTES_BITS Bits; +} CACHE_ATTRIBUTES; + +typedef struct { + UINT16 Type; + UINT16 Reserved_2_4; + UINT32 Length; + UINT32 MemoryProximityDomain; + UINT32 Reserved_12_16; + UINT64 MemorySideCacheSize; + CACHE_ATTRIBUTES CacheAttributes; + UINT16 Reserved_28_30; + UINT16 NumSmbiosHandles; + UINT16 SmbiosHandles [MAX_TYPE17_CACHE_DEVICES]; +} MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE; +#pragma pack() + +// MSCIS_INIT Macro +// Used to initialize MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE +#define MSCIS_INIT() { \ + (UINT16) MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE_TYPE, \ + (UINT16) 0, \ + (UINT32) sizeof(MEMORY_SIDE_CACHE_INFORMATION_STRUCTURE), \ + (UINT32) 0, \ + (UINT32) 0, \ + (UINT64) 0, \ + {(UINT32) 0}, \ + (UINT16) 0, \ + (UINT16) 0, \ + }, +/* + SMBIOS handles not used for 2LM. Will be added for HBM + {(UINT16) 0}, \ + }, +*/ +#endif /* _MSCIS_H_ */ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h new file mode 100644 index 0000000000..31c6e0f580 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Msct.h @@ -0,0 +1,58 @@ +/** @file + This file describes the contents of the ACPI Maximum System Characteristics Table (MSCT). + Some additional ACPI values are defined in Acpi1_0.h, Acpi2_0.h, and Acpi3_0.h. + All changes to the MSCT contents should be done in this file. + + @copyright + Copyright 2019 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MSCT_H_ +#define _MSCT_H_ + +// +// Statements that include other files +// +#include +#include +#include + +// +// MSCT Definitions, see specification for details. +// +#ifndef EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE +#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE 0x5443534D +#endif +#define EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01 +#define EFI_ACPI_OEM_MSCT_REVISION 0x00000001 +#define EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE_REVISION 0x01 + + +// +// MSCT Table definition +// +#pragma pack(1) + +typedef struct { + UINT8 Revision; + UINT8 Length; + UINT32 ProxDomRangeLow; + UINT32 ProxDomRangeHigh; + UINT32 MaxProcessorCapacity; + UINT64 MaxMemoryCapacity; +} EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE; + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 OffsetProxDomInfo; + UINT32 MaxNumProxDom; + UINT32 MaxNumClockDom; + UINT64 MaxPhysicalAddress; + EFI_ACPI_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE ProxDomInfoStructure[MAX_SOCKET]; +} EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE; + +#pragma pack() + +#endif //_MSCT_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h new file mode 100644 index 0000000000..5ea51b6d59 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Nfit.h @@ -0,0 +1,50 @@ +/** @file + + @copyright + Copyright 1999 - 2019 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// The version of NvDimm F/W Interface Table (Nfit) supported has been updated to ASWG-ECR-Draft4-RC6_93.doc +// This file contains definitions for Acpi side for the Nfit creation and publication of Nfit tables. +// A BIG NOTE: When ever the NVDIMM_FW_INTERFACE_TABLE defined either here or what is in Nfit.h of CrystalRidge Protocol driver +// changes, the same changes need to relect in both the files. + +#ifndef _NFIT_DEFS_H_ +#define _NFIT_DEFS_H_ + +#include + +#define NVDIMM_FW_INTERFACE_TABLE_SIGNATURE EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE +#define NVDIMM_FW_INTERFACE_TABLE_REVISION EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION + +#define MAX_NFIT_SIZE 0x18000 + + +// +// NVDIMM Firmware Interface Table struct +// IMPORTANT NOTE: Num of various sub-table fields of the Nfit has been eliminated in the latest Nfit Spec (0.8k) +// And also since there is NO memory allocation scheme for Nfit (all globals), Adding a buffer NfitTables with the, +// max nfit size currently set to 4k. Will need to watch if we will ever overrun this buffer. It is expected that +// Nfit parser will need to parse the NfitTables field to understand the various other Nfit Tables in this buffer +// based on the Type and Length field of these tables. +// +#pragma pack(1) +typedef struct _NVDIMM_FW_INT_TBL { + UINT32 Signature; // 'NFIT' should be the signature for this table + UINT32 Length; // Length in bytes fir the entire table + UINT8 Revision; // Revision # of this table, initial is '1' + UINT8 Checksum; // Entire Table Checksum must sum to 0 + UINT8 OemID[6]; // OemID + UINT8 OemTblID[8]; // Should be Manufacturer's Model # + UINT32 OemRevision; // Oem Revision of for Supplied OEM Table ID + UINT32 CreatorID; // Vendor ID of the utility that is creating this table + UINT32 CreatorRev; // Revision of utility that is creating this table + UINT32 Reserved; + UINT8 NfitTables[MAX_NFIT_SIZE]; // See Description above (IMPORTANT). +} NVDIMM_FW_INTERFACE_TABLE; +#pragma pack() + +#endif // _NFIT_DEFS_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h new file mode 100644 index 0000000000..ceb0684f17 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pcat.h @@ -0,0 +1,45 @@ +/** @file + Pcat.h + + @copyright + Copyright 2014 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCAT_DEFS_H_ +#define _PCAT_DEFS_H_ + +#include + +/// @brief PCAT Signature to put in table header +#define NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE_SIGNATURE SIGNATURE_32('P', 'C', 'A', 'T') + +#define NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE_REVISION 0x11 + +#define MAX_PCAT_SIZE 0x200 + +typedef struct { + UINT32 Signature; // 'PCAT' should be the signature for this table + UINT32 Length; // Length in bytes for the entire table + UINT8 Revision; // Revision # of this table, initial is '1' + UINT8 Checksum; // Entire Table Checksum must sum to 0 + UINT8 OemID[6]; // OemID + UINT8 OemTblID[8]; // Should be Manufacturer's Model # + UINT32 OemRevision; // Oem Revision of for Supplied OEM Table ID + UINT32 CreatorID; // Vendor ID of the utility that is creating this table + UINT32 CreatorRev; // Revision of utility that is creating this table + UINT32 Reserved; // Alignement for size modulo 8 = 0 + UINT8 PCATTables[MAX_PCAT_SIZE]; +} NVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE, *PNVDIMM_PLATFORM_CONFIG_ATTRIBUTE_TABLE; + +/// @brief Layout of SSKU Attribute Extension Table header +typedef struct { + UINT16 Type; // Type for Mgmt Info Struct, type should be 3 + UINT16 Length; // Length in Bytes for Entire SSKU Attribute Extension Table size. + UINT16 Rsvd; + UINT16 VendorID; // Vendor ID + EFI_GUID Guid; // Intel defined SSKU Attribute Extension Table. guid: F93032E5-B045-40ef-91C8-F02B06AD948D +} NVDIMM_SSKU_ATTR_EXT_TABLE, *PNVDIMM_SSKU_ATTR_EXT_TABLE; + +#endif //_PCAT_DEFS_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h new file mode 100644 index 0000000000..923483f2da --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Pmtt.h @@ -0,0 +1,120 @@ +/** @file + + @copyright + Copyright 2016 - 2018 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_PMTT_H_ +#define _ACPI_PMTT_H_ + +// +// Includes +// +#include +#include +#include +#include + +// +// PMTT Definitions +// +#define ACPI_PMTT_TABLE_SIGNATURE 0x54544D50 +#define ACPI_PMTT_TABLE_REVISION 0x02 +#define ACPI_PMTT_OEM_REVISION 1 + +#define PMTT_TOP_LEVEL_AGGREGATOR_DEVICE 0x0001 +#define PMTT_PHYSICAL_ELEMENT_OF_TOPOLOGY 0x0002 +#define PMTT_AEP_DIMM 0x0004 + +#define ACPI_TOP_LEVEL_SOCKET 0x00 +#define ACPI_TOP_LEVEL_IMC 0x01 +#define PHYSICAL_COMPONENT_IDENTIFIER_TYPE_DIMM 0x02 +#define ACPI_TOP_LEVEL_VENDOR_SPECIFIC_DEVICE 0xFF + +// PMTT GUID variables +#define PMTT_TYPE_DIE_GUID { 0xA2555053, 0xCDE4, 0x40A5, {0x80, 0x76, 0x00, 0xE3, 0xAB, 0xA6, 0xCA, 0xA7} } +#define PMTT_TYPE_CHANNEL_GUID { 0x23BF9281, 0xE69c, 0x471F, {0xB2, 0x99, 0xB0, 0x98, 0x2B, 0x2F, 0x55, 0xF9} } +#define PMTT_TYPE_SLOT_GUID { 0xFDCB2a68, 0xC203, 0x4312, {0xB2, 0x91, 0xB8, 0xE8, 0x62, 0x86, 0xC2, 0xC1} } + +typedef struct { + UINT8 Type; + UINT8 Rsvd; + UINT16 Length; + UINT16 Flag; + UINT16 Rsvd1; + UINT32 NumOfMemoryDevices; + UINT32 SmbiosHandle; +} ACPI_PMTT_DIMM_DEVICE; + +typedef struct { + UINT8 Type; + UINT8 Rsvd; + UINT16 Length; + UINT16 Flag; + UINT16 Rsvd1; + UINT32 NumOfMemoryDevices; + GUID TypeUuid; + UINT16 SlotId; + UINT16 Rsvd2; + ACPI_PMTT_DIMM_DEVICE Dimm; +} ACPI_PMTT_SLOT_DEVICE; + +typedef struct { + UINT8 Type; + UINT8 Rsvd; + UINT16 Length; + UINT16 Flag; + UINT16 Rsvd1; + UINT32 NumOfMemoryDevices; + GUID TypeUuid; + UINT16 ChannelId; + UINT16 Rsvd2; + ACPI_PMTT_SLOT_DEVICE Slot[MAX_DIMM]; +} ACPI_PMTT_CHANNEL_DEVICE; + +typedef struct { + UINT8 Type; + UINT8 Rsvd; + UINT16 Length; + UINT16 Flag; + UINT16 Rsvd1; + UINT32 NumOfMemoryDevices; + UINT16 ImcId; + UINT16 Rsvd2; + ACPI_PMTT_CHANNEL_DEVICE Channel[MAX_MC_CH]; +} ACPI_PMTT_IMC_DEVICE; + +typedef struct { + UINT8 Type; + UINT8 Rsvd; + UINT16 Length; + UINT16 Flag; + UINT16 Rsvd1; + UINT32 NumOfMemoryDevices; + GUID TypeUuid; + UINT16 DieId; + UINT16 Rsvd2; + ACPI_PMTT_IMC_DEVICE Imc[MAX_IMC]; +} ACPI_PMTT_DIE_DEVICE; + +typedef struct { + UINT8 Type; + UINT8 Rsvd; + UINT16 Length; + UINT16 Flag; + UINT16 Rsvd1; + UINT32 NumOfMemoryDevices; + UINT16 SckIdent; + UINT16 Rsvd2; + ACPI_PMTT_DIE_DEVICE Die[MAX_DIE]; +} ACPI_PMTT_SOCKET_DEVICE; + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 NumOfMemoryDevices; + ACPI_PMTT_SOCKET_DEVICE Socket[MAX_SOCKET]; +} ACPI_PLATFORM_MEMORY_TOPOLOGY_TABLE; + +#endif // _ACPI_PMTT_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h new file mode 100644 index 0000000000..c119a0f712 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Sllbis.h @@ -0,0 +1,87 @@ +/** @file + + @copyright + Copyright 2016 - 2017 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SLLBIS_H_ +#define _SLLBIS_H_ + +#include + +#define EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS MC_MAX_NODE +#define EFI_ACPI_HMAT_NUMBER_OF_MEMORY_DOMAINS (MC_MAX_NODE * MAX_CRS_ENTRIES_PER_NODE) + +#define EFI_ACPI_HMAT_MEMORY_HIERACHY_MEMORY 0 +#define EFI_ACPI_HMAT_MEMORY_HIERACHY_LAST_LEVEL_MEMORY 1 +#define EFI_ACPI_HMAT_MEMORY_HIERACHY_FIRST_LEVEL_MEMORY 2 +#define EFI_ACPI_HMAT_MEMORY_HIERACHY_SECOND_LEVEL_MEMORY 3 +#define EFI_ACPI_HMAT_MEMORY_HIERACHY_THIRD_LEVEL_MEMORY 4 + + +#define EFI_ACPI_HMAT_ACCESS_LATENCY 0 +#define EFI_ACPI_HMAT_READ_LATENCY 1 +#define EFI_ACPI_HMAT_WRITE_LATENCY 2 +#define EFI_ACPI_HMAT_ACCESS_BANDWIDTH 3 +#define EFI_ACPI_HMAT_READ_BANDWIDTH 4 +#define EFI_ACPI_HMAT_WRITE_BANDWIDTH 5 + +#define EFI_ACPI_HMAT_MAX_SLLBIS_DATA_TYPES 4 +#define EFI_ACPI_HMAT_NUMBER_SLLBIS_DATA_TYPES 6 + +#define EFI_ACPI_HMAT_ELEMENT_BASE_UNIT_VALUE 10 + +#define MAX_HMAT_MEMORY_HIERACHY_LEVELS 3 // Flat, Cache, and Hybrid +#define HMAT_PERFORMANCE_UNIFORM_ACCESS 1 +#define HMAT_PERFORMANCE_NONUNIFORM_ACCESS 0 + +#define EFI_ACPI_HMAT_MEMORY_BW_LATENCY_ATTRIBUTE_LENGTH 4 +#define EFI_ACPI_HMAT_MEMORY_BW_LATENCY_ATTRIBUTE_START_BIT 4 + + +#pragma pack(1) + +typedef struct { + UINT16 Type; + UINT16 Reserved_2_4; + UINT32 Length; + UINT8 Flags; + UINT8 DataType; + UINT16 Reserved_10_12; + UINT32 InitiatorProximityDomainsNumber; + UINT32 TargetProximityDomainsNumber; + UINT32 Reserved_20_24; + UINT64 EntryBaseUnit; + UINT32 InitiatorProximityDomainList[EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS]; + UINT32 TargetProximityDomainList[EFI_ACPI_HMAT_NUMBER_OF_MEMORY_DOMAINS]; + UINT16 RelativeDistanceEntry[EFI_ACPI_HMAT_NUMBER_OF_PROCESSOR_DOMAINS][EFI_ACPI_HMAT_NUMBER_OF_MEMORY_DOMAINS]; +} LATENCY_BANDWIDTH_INFO_STRUCTURE; +#pragma pack() + +// LBIS Macros +// Used to initialize LATENCY_BANDWIDTH_INFO_STRUCTURE +#define LBIS_START() { \ + (UINT16) SYSTEM_LOCALITY_LATENCY_BANDWIDTH_INFORMATION_STRUCTURE_TYPE, \ + (UINT16) 0, \ + (UINT32) sizeof(LATENCY_BANDWIDTH_INFO_STRUCTURE), \ + (UINT8) 0, \ + (UINT8) 0, \ + (UINT16) 0, \ + (UINT32) 0, \ + (UINT32) 0, \ + (UINT32) 0, \ + (UINT64) 0, \ + {(UINT32) 0}, \ + {(UINT32) 0}, \ + { + +#define RELATIVE_DISTANCE() \ + {(UINT16) 0}, + +#define LBIS_END() \ + }, \ +}, + +#endif /* _SLLBIS_H_ */ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h new file mode 100644 index 0000000000..90ea2c24cb --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spcr.h @@ -0,0 +1,48 @@ +/** @file + This file describes the contents of the ACPI Serial Port Console Redirection + Table (SPCR). Some additional ACPI 2.0 values are defined in Acpi2_0.h. + All changes to the Spcr contents should be done in this file. + + @copyright + Copyright 1999 - 2002 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SPCR_H_ +#define _SPCR_H_ + +// +// SPCR Definitions, see TBD specification for details. +// + +#define EFI_ACPI_OEM_SPCR_REVISION 0x00000000 // TBD + +#define EFI_ACPI_INTERFACE_TYPE 0x00 // full 16550 interface. + +// +// Base Address +// +#define EFI_ACPI_BASE_ADDRESS_ADDRESS_SPACE_ID EFI_ACPI_6_2_SYSTEM_IO +#define EFI_ACPI_BASE_ADDRESS_BIT_WIDTH 0x08 +#define EFI_ACPI_BASE_ADDRESS_BIT_OFFSET 0x00 +#define EFI_ACPI_BASE_ADDRESS_ADDRESS 0x0000000000000000 // Updated at run time + +#define EFI_ACPI_INTERRUPT_TYPE 0x03 // Dual-8259 and IOAPIC +#define EFI_ACPI_IRQ 0x04 // Updated at run time +#define EFI_ACPI_GLOBAL_SYSTEM_INTERRUPT 0x04 // Updated at run time +#define EFI_ACPI_BAUD_RATE 0x07 // 115200 +#define EFI_ACPI_PARITY 0x00 // No parity +#define EFI_ACPI_STOP_BITS 0x00 // 0 stop bit +#define EFI_ACPI_FLOW_CONTROL 0x00 // No flow control +#define EFI_ACPI_TERMINAL_TYPE 0x03 // ANSI +#define EFI_ACPI_LANGUAGE 0x00 // Reserved +#define EFI_ACPI_PCI_DEVICE_ID 0xFFFF +#define EFI_ACPI_PCI_VENDOR_ID 0xFFFF +#define EFI_ACPI_PCI_BUS_NUMBER 0x00 +#define EFI_ACPI_PCI_DEVICE_NUMBER 0x00 +#define EFI_ACPI_PCI_FUNCTION_NUMBER 0x00 +#define EFI_ACPI_PCI_FLAGS 0x00000000 +#define EFI_ACPI_PCI_SEGMENT 0x00 + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h new file mode 100644 index 0000000000..576c390bd6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Spmi.h @@ -0,0 +1,59 @@ +/** @file + + @copyright + Copyright 2019 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SPMI_H_ +#define _SPMI_H_ + +// +// Statements that include other files +// +#include + +// +// Spmi Definitions, see specification for details. +// +#ifndef EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE +#define EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE 0x494D5053 +#endif + +#define EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_REVISION 0x05 +#define EFI_ACPI_OEM_SPMI_REVISION 0x00000001 +#define EFI_ACPI_SPMI_SPECIFICATION_REVISION 0x0200 + + +// +// SPMI Table definition +// +#pragma pack(1) + +#define KEYBOARD_CONTROLLER_STYLE 0x01 +#define SYSTEM_IO 0x01 +#define IPMI_DEFAULT_IO_BASE 0xCA2 + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT8 InterfaceType; // 36 + UINT8 Reserved37; // 37 + UINT16 SpecificationRevision; // 38 - 39 + UINT8 InterruptType; // 40 + UINT8 GPE; // 41 + UINT8 Reserved42; // 42 + UINT8 PciDeviceFlag; // 43 + UINT32 GlobalSystemInterrupt; // 44 - 47 + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddress; // 48 - 59 + UINT8 UidByte1; // 60 LSB + UINT8 UidByte2; // 61 + UINT8 UidByte3; // 62 + UINT8 UidByte4; // 63 MSB + UINT8 Reserved64; // 64 +} EFI_ACPI_SERVER_PROCESSOR_MANAGEMENT_INTERFACE_TABLE; + + +#pragma pack() + +#endif //_SPMI_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTable.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTable.h new file mode 100644 index 0000000000..fe25f5b4e3 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/WatchdogDescriptionTable.h @@ -0,0 +1,82 @@ +/** @file + ACPI Watchdog Description Table as defined in Intel + ICH Family Watchdog Timer (WDT) Application Note (AP-725) + + @copyright + Copyright 2019 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _WATCH_DOG_DESCRIPTION_TABLE_H_ +#define _WATCH_DOG_DESCRIPTION_TABLE_H_ + +// +// Include files +// +#include + +// +// Ensure proper structure formats +// +#pragma pack(1) +// +// WDDT structure ACPI 6.2 compliant +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT16 SpecVersion; + UINT16 TableVersion; + UINT16 Vid; + EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE BaseAddress; + UINT16 TimerMaxCount; + UINT16 TimerMinCount; + UINT16 TimerCountPeriod; + UINT16 Status; + UINT16 Capability; +} EFI_ACPI_WATCH_DOG_DESCRIPTION_TABLE; + +// +// "WDDT" Watchdog Description Table signatures +// +#define EFI_ACPI_WDDT_SIGNATURE 0x54444457 + +#pragma pack() + +// +// WDDT Revision +// +#define EFI_ACPI_WATCHDOG_DESCRIPTION_1_0_TABLE_REVISION 0x01 + +// +// WDDT Spec Version +// +#define EFI_ACPI_WDDT_SPEC_1_0_VERSION 0x01 + +// +// WDDT Description Table Version +// +#define EFI_ACPI_WDDT_TABLE_1_0_VERSION 0x01 + +// +// WDT Status +// +#define EFI_ACPI_WDDT_STATUS_AVAILABLE 0x0001 +#define EFI_ACPI_WDDT_STATUS_ACTIVE 0x0002 +#define EFI_ACPI_WDDT_STATUS_OWNED_BY_BIOS 0x0000 +#define EFI_ACPI_WDDT_STATUS_OWNED_BY_OS 0x0004 +#define EFI_ACPI_WDDT_STATUS_USER_RESET_EVENT 0x0800 +#define EFI_ACPI_WDDT_STATUS_WDT_EVENT 0x1000 +#define EFI_ACPI_WDDT_STATUS_POWER_FAIL_EVENT 0x2000 +#define EFI_ACPI_WDDT_STATUS_UNKNOWN_RESET_EVENT 0x4000 + +// +// WDT Capability +// +#define EFI_ACPI_WDDT_CAPABILITY_AUTO_RESET 0x0001 +#define EFI_ACPI_WDDT_CAPABILITY_ALERT_SUPPORT 0x0002 +#define EFI_ACPI_WDDT_CAPABILITY_PLATFORM_SHUTDOWN 0x0004 +#define EFI_ACPI_WDDT_CAPABILITY_IMMEDIATE_SHUTDOWN 0x0008 +#define EFI_ACPI_WDDT_CAPABILITY_BIOS_HANDOFF_SUPPORT 0x0010 + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h new file mode 100644 index 0000000000..9ffe2c6e89 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wddt.h @@ -0,0 +1,53 @@ +/** @file + This file describes the contents of the ACPI Watchdog Description + Table (WDDT). Some additional ACPI values are defined in Acpi1_0.h and + Acpi2_0.h. + + @copyright + Copyright 1999 - 2019 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _WDDT_H +#define _WDDT_H + +// +// Statements that include other files +// +#include + +// +// WDDT Definitions, ACPI 6.2 +// +#define EFI_ACPI_WDDT_DESCRIPTION_TABLE_REVISION 1 +#define EFI_ACPI_OEM_WDDT_REVISION 0x00000001 +#define EFI_ACPI_WDDT_SPEC_VERSION 0x0100 +#define EFI_ACPI_WDDT_TABLE_VERSION 0x0100 +#define EFI_ACPI_WDDT_TIMER_MAX_COUNT 0x003f +#define EFI_ACPI_WDDT_TIMER_MIN_VALUE 0x0004 +#define EFI_ACPI_WDDT_TIMER_PERIOD_COUNT 600 +// +// WDDT_STATUS bits +// +#define EFI_ACPI_WDDT_STATUS_AVAILABLE 0x0001 +#define EFI_ACPI_WDDT_STATUS_ACTIVE 0x0002 +#define EFI_ACPI_WDDT_STATUS_OWNED_BY_BIOS 0x0000 +#define EFI_ACPI_WDDT_STATUS_OWNED_BY_OS 0x0004 +#define EFI_ACPI_WDDT_STATUS_USER_RESET_EVENT 0x0800 +#define EFI_ACPI_WDDT_STATUS_WDT_EVENT 0x1000 +#define EFI_ACPI_WDDT_STATUS_POWER_FAIL_EVENT 0x2000 +#define EFI_ACPI_WDDT_STATUS_UNKNOWN_RESET_EVENT 0x4000 + +// +// WDDT Capability bits +// +#define EFI_ACPI_WDDT_CAPABILITY_AUTO_RESET 0x0001 +#define EFI_ACPI_WDDT_CAPABILITY_ALERT_SUPPORT 0x0002 +#define EFI_ACPI_WDDT_CAPABILITY_PLATFORM_SHUTDOWN 0x0004 +#define EFI_ACPI_WDDT_CAPABILITY_IMMEDIATE_SHUTDOWN 0x0008 +#define EFI_ACPI_WDDT_CAPABILITY_BIOS_HANDOFF_SUPPORT 0x0010 + +#pragma pack() + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h new file mode 100644 index 0000000000..112e162931 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Acpi/Wsmt.h @@ -0,0 +1,67 @@ +/** @file + + @copyright + Copyright 2017 - 2020 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +#ifndef _WSMT_H_ +#define _WSMT_H_ + +// +// Statements that include other files +// + +#include + +// +// signature "WSMT" +// + +#define ACPI_WSMT_SIGNATURE 0x544D5357 +#define ACPI_WSMT_LENGTH 40 +#define ACPI_OEM_WSMT_REVISION 0x00000000 +#define EFI_ACPI_WSMT_REVISION 0x00000001 +#define WSMT_PROTECTION_FLAG (BIT0 | BIT1 | BIT2 ) + + +#pragma pack(1) + +typedef union { + struct { + // + //BIT0: + //If set, expresses that for all synchronous SMM entries, + //SMM will validate that input and output buffers lie entirely within the expected fixed memory regions. + // + UINT32 FixedCommBuffers:1; + // + //BIT1: COMM_BUFFER_NESTED_PTR_PROTECTION + //If set, expresses that for all synchronous SMM entries, SMM will validate that input and + //output pointers embedded within the fixed communication buffer only refer to address ranges + //that lie entirely within the expected fixed memory regions. + // + UINT32 CommBufferNestedPointerProtection:1; + // + //BIT2: SYSTEM_RESOURCE_PROTECTION + //Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms. + // + UINT32 SystemResourceProtection:1; + UINT32 Reserved:29; + } Bits; + UINT32 Flags; +} EFI_ACPI_WSMT_PROTECTION_FLAGS; + +// +// WSMT ACPI table +// +typedef struct _ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_TABLE { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_WSMT_PROTECTION_FLAGS ProtectionFlags; +} ACPI_WINDOWS_SMM_SECURITY_MITIGATIONS_TABLE; + +#pragma pack() + +#endif //_WSMT_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec index 5e27d9beb4..4d416325ae 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec @@ -16,8 +16,8 @@ PACKAGE_VERSION = 0.91 [Includes] - Include - Include/Protocol + Include + Include/Protocol #TODO: Move these generated temp files into include. Uba/BoardInit/Dxe @@ -159,8 +159,7 @@ [PcdsFixedAtBuild] -#SKX_TODO: add a new GUID, and replace the 'gPlatformTokenSpaceGuid' used here to it, or move these values to the SocketPkg where the GUID is defined -# Using a GUID defined in another .DEC file is a violation of the UEFI packaging standards. + gPlatformTokenSpaceGuid.PcdEfiAcpiPm1aEvtBlkAddress|0x00000500|UINT32|0x00000031 gCpPlatFlashTokenSpaceGuid.PcdFlashBase|0x00000000 |UINT32|0x3000000E gCpPlatFlashTokenSpaceGuid.PcdFlashSize|0x00000000 |UINT32|0x3000000F diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h b/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h index 0ea93e9a78..7af4eb72f6 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/UncoreCommonIncludes.h @@ -80,6 +80,8 @@ #define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes #endif +#define MAX_CRS_ENTRIES_PER_NODE 8 // Max number of ranges allowed on a memory node + #ifndef TOTAL_CB3_DEVICES #define TOTAL_CB3_DEVICES 64 // IOAT_TOTAL_FUNCS * MAX_SOCKET. Note: this covers up to 8S. #endif @@ -108,4 +110,10 @@ #define MAX_B2P_MAILBOX_GROUPS 32 #endif // !MAX_B2P_MAILBOX_GROUPS +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_CREATOR_ID 0x4C544E49 // "INTL" +#define EFI_ACPI_CREATOR_REVISION 0x20091013 // Oct 13 2009 + #endif -- 2.27.0.windows.1