From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.85.128.45, mailfrom: philmd@redhat.com) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by groups.io with SMTP; Wed, 08 May 2019 00:33:46 -0700 Received: by mail-wm1-f45.google.com with SMTP id o189so1893031wmb.1 for ; Wed, 08 May 2019 00:33:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:openpgp:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=1+lDgDBMJHdwTzmaCuQn89i8uTGrd4VWUUS1bsB/L9M=; b=JUj928Pv/p5B6bENqQtXgDURqQIe4eV/ofGFUAoomu6gU/pdtoqUPfqfxAkjNOHxmj AWM405iIUFWy2FwtiUSsBQtymf3B71AKCT1mzVDCUfUUbSrJX0F/3NleMeVj+taUmsjw O+exUyCzBHUYSV/I2l81slUpkSfoVFFZ5TJ0fQ2D8XgA2z2PriGNW6ukKYqguAevSm8z 8vUZr1tj5eG8gTibU1wy6N2wesEOC9qb9Y2XaJuD0afhz9glDK6XW7wjUjP95UjgQQol rPt+PKnONHiG85P5wngIavMCV9bnqGLIgEJJinVG0wW+afzxRi3RusZcjhrdc7cIUDfP e1qQ== X-Gm-Message-State: APjAAAU+7h5bKCmsXM0egKui0murQ9PzCUgWhBUpPqxjTXOK5mAiaZMO t7UuHPIfFHHjbndNKyfX2ER83g== X-Google-Smtp-Source: APXvYqzUkjIFaADGgHJxH/60cnUPfYNWpDCtQo5dP6o4fIFb4VkBxRf4HjwbUsfQkJyKt74NYtjlLQ== X-Received: by 2002:a1c:1f92:: with SMTP id f140mr1734664wmf.132.1557300824720; Wed, 08 May 2019 00:33:44 -0700 (PDT) Return-Path: Received: from [192.168.1.37] (193.red-88-21-103.staticip.rima-tde.net. [88.21.103.193]) by smtp.gmail.com with ESMTPSA id s124sm1791775wmf.42.2019.05.08.00.33.42 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Wed, 08 May 2019 00:33:43 -0700 (PDT) Subject: Re: [edk2-devel] [PATCH 4/4] OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear To: devel@edk2.groups.io, lersek@redhat.com Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen References: <20190504000716.7525-1-lersek@redhat.com> <20190504000716.7525-5-lersek@redhat.com> From: =?UTF-8?B?UGhpbGlwcGUgTWF0aGlldS1EYXVkw6k=?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: <46dccf0d-6ab6-11e6-d473-187cf8ce7114@redhat.com> Date: Wed, 8 May 2019 09:33:42 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190504000716.7525-5-lersek@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 5/4/19 2:07 AM, Laszlo Ersek wrote: > Assume that we boot OVMF in a QEMU guest with 1025 MB of RAM. The > following assertion will fire: > >> ASSERT_EFI_ERROR (Status = Out of Resources) >> ASSERT OvmfPkg/PlatformPei/MemDetect.c(696): !EFI_ERROR (Status) > > That's because the range [1025 MB, 4 GB) that we try to mark as > uncacheable with MTRRs has size 3071 MB: > > 0x1_0000_0000 > -0x0_4010_0000 > -------------- > 0x0_BFF0_0000 > > The integer that stands for the uncacheable area size has 11 (eleven) bits > set to 1. As a result, covering this size requires 11 variable MTRRs (each > MTRR must cover a naturally aligned, power-of-two sized area). But, if we > need more variable MTRRs than the CPU can muster (such as 8), then > MtrrSetMemoryAttribute() fails, and we refuse to continue booting (which > is justified, in itself). > > Unfortunately, this is not difficult to trigger, and the error message is > well-hidden from end-users, in the OVMF debug log. The following > mitigation is inspired by SeaBIOS: > > Truncate the uncacheable area size to a power-of-two, while keeping the > end fixed at 4 GB. Such an interval can be covered by just one variable > MTRR. > > This may leave such an MMIO gap, between the end of low-RAM and the start > of the uncacheable area, that is marked as WB (through the MTRR default). > Raise the base of the 32-bit PCI MMIO aperture accordingly -- the gap will > not be used for anything. I had to draw it to be sure I understood correctly: +-------------+ +-------------+ <-- 4GB | | | | | | | | | | | PCI MMIO | | | | | | | | uncacheable | | uncacheable | | | | | | | | | ----> +-------------+ <-- mQemuUc32Base | | | | | (pow2 aligned) | | | | GAP | | | | | (cacheable) | +-------------+ ---- +-------------+ <-- TopOfLowRam | | | | (not pow2 aligned) | | | | | | | | | | | | | LowerMemory | | LowerMemory | | (cacheable) | | (cacheable) | | | | | | | | | | | | | +-------------+ +-------------+ > On Q35, the minimal 32-bit PCI MMIO aperture (triggered by RAM size 2815 > MB) shrinks from > > 0xE000_0000 - 0xAFF0_0000 = 769 MB > > to > > 0xE000_0000 - 0xC000_0000 = 512 MB > > On i440fx, the minimal 32-bit PCI MMIO aperture (triggered by RAM size > 3583 MB) shrinks from > > 0xFC00_0000 - 0xDFF0_0000 = 449 MB > > to > > 0xFC00_0000 - 0xE000_0000 = 448 MB > > Cc: Ard Biesheuvel > Cc: Gerd Hoffmann > Cc: Jordan Justen > Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1666941 > Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1701710 > Signed-off-by: Laszlo Ersek > --- > OvmfPkg/PlatformPei/Platform.h | 2 ++ > OvmfPkg/PlatformPei/MemDetect.c | 23 +++++++++++++++++--- > OvmfPkg/PlatformPei/Platform.c | 4 +--- > 3 files changed, 23 insertions(+), 6 deletions(-) > > diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h > index 81af8b71480f..4476ddd871cd 100644 > --- a/OvmfPkg/PlatformPei/Platform.h > +++ b/OvmfPkg/PlatformPei/Platform.h > @@ -114,4 +114,6 @@ extern UINT32 mMaxCpuCount; > > extern UINT16 mHostBridgeDevId; > > +extern UINT32 mQemuUc32Base; > + > #endif // _PLATFORM_PEI_H_INCLUDED_ > diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c > index e890e36408a6..ae73c63d27d5 100644 > --- a/OvmfPkg/PlatformPei/MemDetect.c > +++ b/OvmfPkg/PlatformPei/MemDetect.c > @@ -42,6 +42,8 @@ STATIC UINT32 mS3AcpiReservedMemorySize; > > STATIC UINT16 mQ35TsegMbytes; > > +UINT32 mQemuUc32Base; > + > VOID > Q35TsegMbytesInitialization ( > VOID > @@ -663,6 +665,8 @@ QemuInitializeRam ( > // cover it exactly. > // > if (IsMtrrSupported ()) { > + UINT32 Uc32Size; > + > MtrrGetAllMtrrs (&MtrrSettings); > > // > @@ -689,11 +693,24 @@ QemuInitializeRam ( > > // > // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as > - // uncacheable > + // uncacheable. Make sure one variable MTRR suffices by truncating the size > + // to a whole power of two. This will round the base *up*, and a gap (not > + // used for either RAM or MMIO) may stay in the middle, marked as > + // cacheable-by-default. > // > - Status = MtrrSetMemoryAttribute (LowerMemorySize, > - SIZE_4GB - LowerMemorySize, CacheUncacheable); > + Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize)); > + mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size); > + if (mQemuUc32Base != LowerMemorySize) { > + DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for " > + "an UC32 size of 0x%x\n", __FUNCTION__, (UINT32)LowerMemorySize, > + mQemuUc32Base, Uc32Size)); > + } > + > + Status = MtrrSetMemoryAttribute (mQemuUc32Base, Uc32Size, > + CacheUncacheable); > ASSERT_EFI_ERROR (Status); > + } else { > + mQemuUc32Base = (UINT32)LowerMemorySize; > } > } > > diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c > index fd8eccaf3e50..c064b4ed9b8f 100644 > --- a/OvmfPkg/PlatformPei/Platform.c > +++ b/OvmfPkg/PlatformPei/Platform.c > @@ -174,14 +174,12 @@ MemMapInitialization ( > AddIoMemoryRangeHob (0x0A0000, BASE_1MB); > > if (!mXen) { > - UINT32 TopOfLowRam; > UINT64 PciExBarBase; > UINT32 PciBase; > UINT32 PciSize; > > - TopOfLowRam = GetSystemMemorySizeBelow4gb (); > PciExBarBase = 0; > - PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; > + PciBase = (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base; > if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { > // > // The 32-bit PCI host aperture is expected to fall between the top of > Reviewed-by: Philippe Mathieu-Daude