From: "zhoucheng" <zhoucheng@phytium.com.cn>
To: Pedro Falcato <pedro.falcato@gmail.com>,devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH v1 1/1] MdeModulePkg:Add Warm Reset for Xhc
Date: Thu, 03 Nov 2022 20:15:35 -0700 [thread overview]
Message-ID: <4722.1667531735089236658@groups.io> (raw)
In-Reply-To: <CAKbZUD3LLw4UYZe7SVs2LVR8C7aqi-d0adHVQ+b3aC6jjv70ww@mail.gmail.com>
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Hi Pedro:
// The description here is the judgment state,we can watch to XHC PORTSC register.
// according to Xhc Spec 5.4.8 chapter Table39.we can knowleadge more information.
// We need to pay attention to the PED CCS and PLS bits of the PORTSC register.
+ State = XhcReadOpReg (Xhc, Offset);
+ if ((( (State & 0x1e0) >> 5) == 6) && ( (State & 3) == 0)) {
↓ ↓
PLS bit PED and CCS bit
// PLS: Port Link State PED: Port Enabled/Disabled CCS: Current Connect Status
// If the CCS bit and PED are 0, the device is disconnected and the port is not enabled.
// If PLS is 6, the controller state machine is abnormal and software intervention is required.
// According to Usb3.2 spec 7.5.2 chapter.Inactive is a state where a link has failed Enhanced SuperSpeed operation.
// The software is required to perform a warm reset operation.
// Therefore, according to the Xhc1.1 spec 5.8 chapter Table39, we can write 1 to its highest bit and perform a hot reset operation to restore the controller.
+ State |= 0x80000000;
For the value of this block, the above explanation has been made, and the discussion can be continued at the same time.
Thanks!
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next prev parent reply other threads:[~2022-11-04 3:15 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-03 15:53 [PATCH v1 0/1] MdeModulePkg:Add Warm Reset for Xhc zhoucheng
2022-11-03 15:53 ` [PATCH v1 1/1] " zhoucheng
2022-11-03 18:28 ` [edk2-devel] " Pedro Falcato
2022-11-04 3:15 ` zhoucheng [this message]
2022-11-16 6:55 ` Wu, Hao A
2022-11-16 11:36 ` zhoucheng
2022-11-17 1:48 ` Wu, Hao A
2022-11-17 10:23 ` zhoucheng
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