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dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=amd.com; Received: from DM5PR12MB1355.namprd12.prod.outlook.com (2603:10b6:3:6e::7) by DM5PR12MB1354.namprd12.prod.outlook.com (2603:10b6:3:7a::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3066.20; Fri, 5 Jun 2020 13:28:05 +0000 Received: from DM5PR12MB1355.namprd12.prod.outlook.com ([fe80::4ce1:9947:9681:c8b1]) by DM5PR12MB1355.namprd12.prod.outlook.com ([fe80::4ce1:9947:9681:c8b1%10]) with mapi id 15.20.3066.019; Fri, 5 Jun 2020 13:28:05 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Brijesh Singh , Ard Biesheuvel , Eric Dong , Jordan Justen , Laszlo Ersek , Liming Gao , Michael D Kinney , Ray Ni Subject: [PATCH v9 16/46] OvmfPkg/VmgExitLib: Add support for MSR_PROT NAE events Date: Fri, 5 Jun 2020 08:27:07 -0500 Message-Id: <4755705446e2be236ec262cc47ed59d5fdc112ba.1591363657.git.thomas.lendacky@amd.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: X-ClientProxiedBy: DM5PR19CA0060.namprd19.prod.outlook.com (2603:10b6:3:116::22) To DM5PR12MB1355.namprd12.prod.outlook.com (2603:10b6:3:6e::7) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR19CA0060.namprd19.prod.outlook.com (2603:10b6:3:116::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3066.18 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: B8dIoauKMEeUR7/FXvd+6k41u4kZJctMvurWhUdgUweOXO5qZ4pWAw6Dfp23LOSNS+UnDQ0CFs6w4rl7iR1OnY43oHeumdqFqdJPSq6C0H8uNEUMwrXLRLrt/PqMF86q9p9iFrGSSR5Ue51oji/MWUX+aIIu9HeUa4qr9lnvllc3rMgH+NrrsjfiJRBMNj3jiZWyY2IlTmwomDpsjpq19cp7h/EUJYgLwkQH4yFPsoHM6+CT0peFdyALZ8LuJH1dNzrIHoRt9p1x+63fN1xK02qcTa8vCnW7OoUx/KOJ2o5BumLKCw0N+243GStEnnGC3Ji1aHwZPXJtPJTtQ+vhD30PfD3LkN2//KhG5NawO0Bg3WpZwUDllfmhuwgokrMPh4THfijY2+cY8AM0ZJUw8qnjc9cVVsHHvbN53sgduUYeFKoeKvGVlv6ZX1199G6srGbYDyy2F2w5HZlFhelMrty6k2dD/3Chf4xaJY6xU6g= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 81abcec6-9155-4498-91bd-08d80954472a X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jun 2020 13:28:05.1009 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kLYV1nkyRL7ozzNjTRs5yromzcaRjIN5L29CVOvhpUPUhr5ILhbhNmQiN0/4bLVLJPcLP+r9qnF0rWoh/2vfbQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1354 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a MSR_PROT intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support an MSR_PROT NAE event. Parse the instruction that generated the #VC exception to determine whether it is RDMSR or WRMSR, setting the required register register values in the GHCB and creating the proper SW_EXIT_INFO1 value in the GHCB. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 65 ++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index 1e0b2bf399da..009eb48cd468 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -374,6 +374,67 @@ UnsupportedExit ( return Status;=0D }=0D =0D +/**=0D + Handle an MSR event.=0D +=0D + Use the VMGEXIT instruction to handle either a RDMSR or WRMSR event.=0D +=0D + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation=0D + Block=0D + @param[in, out] Regs x64 processor context=0D + @param[in] InstructionData Instruction parsing context=0D +=0D + @return 0 Event handled successfully=0D + @return Others New exception value to propagate=0D +=0D +**/=0D +STATIC=0D +UINT64=0D +MsrExit (=0D + IN OUT GHCB *Ghcb,=0D + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs,=0D + IN SEV_ES_INSTRUCTION_DATA *InstructionData=0D + )=0D +{=0D + UINT64 ExitInfo1, Status;=0D +=0D + ExitInfo1 =3D 0;=0D +=0D + switch (*(InstructionData->OpCodes + 1)) {=0D + case 0x30: // WRMSR=0D + ExitInfo1 =3D 1;=0D + Ghcb->SaveArea.Rax =3D Regs->Rax;=0D + GhcbSetRegValid (Ghcb, GhcbRax);=0D + Ghcb->SaveArea.Rdx =3D Regs->Rdx;=0D + GhcbSetRegValid (Ghcb, GhcbRdx);=0D + //=0D + // fall through=0D + //=0D + case 0x32: // RDMSR=0D + Ghcb->SaveArea.Rcx =3D Regs->Rcx;=0D + GhcbSetRegValid (Ghcb, GhcbRcx);=0D + break;=0D + default:=0D + return UnsupportedExit (Ghcb, Regs, InstructionData);=0D + }=0D +=0D + Status =3D VmgExit (Ghcb, SVM_EXIT_MSR, ExitInfo1, 0);=0D + if (Status !=3D 0) {=0D + return Status;=0D + }=0D +=0D + if (ExitInfo1 =3D=3D 0) {=0D + if (!GhcbIsRegValid (Ghcb, GhcbRax) ||=0D + !GhcbIsRegValid (Ghcb, GhcbRdx)) {=0D + return UnsupportedExit (Ghcb, Regs, InstructionData);=0D + }=0D + Regs->Rax =3D Ghcb->SaveArea.Rax;=0D + Regs->Rdx =3D Ghcb->SaveArea.Rdx;=0D + }=0D +=0D + return 0;=0D +}=0D +=0D /**=0D Build the IOIO event information.=0D =0D @@ -705,6 +766,10 @@ VmgExitHandleVc ( NaeExit =3D IoioExit;=0D break;=0D =0D + case SVM_EXIT_MSR:=0D + NaeExit =3D MsrExit;=0D + break;=0D +=0D default:=0D NaeExit =3D UnsupportedExit;=0D }=0D --=20 2.27.0