Re: [edk2-devel] [Question] How do you set PCIe host bridge address space granularity for a PCI host bridge defined with PciHostBridgeLib?

["Arminder Singh" <arminders208@outlook.com>]

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Hello, thanks for the clarification! Couple of questions.

1) when implementing PciHostBridgeLib, are we supposed to put host addresses (address the CPU uses after translation) in the Mem/MemAbove4G apertures or PCI/device addresses? (address the device uses before translation)
2) Does the 'Mem' aperture have to be a 32 bit address/limit from host perspective?
3) Does translation have to be 0 for Mem/MemAbove4G apertures in the PCI_ROOT_BRIDGE struct? Most example platforms do that, but I'm not sure if that's a requirement for PciHostBridgeLib or just convention.


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